2 * Driver for the NVIDIA Tegra pinmux
4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
7 * Copyright (C) 2010 Google, Inc.
8 * Copyright (C) 2010 NVIDIA Corporation
9 * Copyright (C) 2009-2011 ST-Ericsson AB
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms and conditions of the GNU General Public License,
13 * version 2, as published by the Free Software Foundation.
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 #include <linux/err.h>
22 #include <linux/init.h>
24 #include <linux/module.h>
26 #include <linux/platform_device.h>
27 #include <linux/pinctrl/machine.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/pinctrl/pinconf.h>
31 #include <linux/slab.h>
34 #include "pinctrl-tegra.h"
38 struct pinctrl_dev *pctl;
40 const struct tegra_pinctrl_soc_data *soc;
46 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
48 return readl(pmx->regs[bank] + reg);
51 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
53 writel(val, pmx->regs[bank] + reg);
56 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
58 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
60 return pmx->soc->ngroups;
63 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
66 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
68 return pmx->soc->groups[group].name;
71 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
73 const unsigned **pins,
76 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
78 *pins = pmx->soc->groups[group].pins;
79 *num_pins = pmx->soc->groups[group].npins;
84 #ifdef CONFIG_DEBUG_FS
85 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
89 seq_printf(s, " %s", dev_name(pctldev->dev));
93 static int reserve_map(struct device *dev, struct pinctrl_map **map,
94 unsigned *reserved_maps, unsigned *num_maps,
97 unsigned old_num = *reserved_maps;
98 unsigned new_num = *num_maps + reserve;
99 struct pinctrl_map *new_map;
101 if (old_num >= new_num)
104 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
106 dev_err(dev, "krealloc(map) failed\n");
110 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
113 *reserved_maps = new_num;
118 static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
119 unsigned *num_maps, const char *group,
120 const char *function)
122 if (WARN_ON(*num_maps == *reserved_maps))
125 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
126 (*map)[*num_maps].data.mux.group = group;
127 (*map)[*num_maps].data.mux.function = function;
133 static int add_map_configs(struct device *dev, struct pinctrl_map **map,
134 unsigned *reserved_maps, unsigned *num_maps,
135 const char *group, unsigned long *configs,
136 unsigned num_configs)
138 unsigned long *dup_configs;
140 if (WARN_ON(*num_maps == *reserved_maps))
143 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
146 dev_err(dev, "kmemdup(configs) failed\n");
150 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
151 (*map)[*num_maps].data.configs.group_or_pin = group;
152 (*map)[*num_maps].data.configs.configs = dup_configs;
153 (*map)[*num_maps].data.configs.num_configs = num_configs;
159 static int add_config(struct device *dev, unsigned long **configs,
160 unsigned *num_configs, unsigned long config)
162 unsigned old_num = *num_configs;
163 unsigned new_num = old_num + 1;
164 unsigned long *new_configs;
166 new_configs = krealloc(*configs, sizeof(*new_configs) * new_num,
169 dev_err(dev, "krealloc(configs) failed\n");
173 new_configs[old_num] = config;
175 *configs = new_configs;
176 *num_configs = new_num;
181 void tegra_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
182 struct pinctrl_map *map, unsigned num_maps)
186 for (i = 0; i < num_maps; i++)
187 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
188 kfree(map[i].data.configs.configs);
193 static const struct cfg_param {
194 const char *property;
195 enum tegra_pinconf_param param;
197 {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL},
198 {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE},
199 {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT},
200 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
201 {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
202 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
203 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
204 {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT},
205 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
206 {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
207 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
208 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
209 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
212 int tegra_pinctrl_dt_subnode_to_map(struct device *dev,
213 struct device_node *np,
214 struct pinctrl_map **map,
215 unsigned *reserved_maps,
219 const char *function;
221 unsigned long config;
222 unsigned long *configs = NULL;
223 unsigned num_configs = 0;
225 struct property *prop;
228 ret = of_property_read_string(np, "nvidia,function", &function);
230 /* EINVAL=missing, which is fine since it's optional */
233 "could not parse property nvidia,function\n");
237 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
238 ret = of_property_read_u32(np, cfg_params[i].property, &val);
240 config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
241 ret = add_config(dev, &configs, &num_configs, config);
244 /* EINVAL=missing, which is fine since it's optional */
245 } else if (ret != -EINVAL) {
246 dev_err(dev, "could not parse property %s\n",
247 cfg_params[i].property);
252 if (function != NULL)
256 ret = of_property_count_strings(np, "nvidia,pins");
258 dev_err(dev, "could not parse property nvidia,pins\n");
263 ret = reserve_map(dev, map, reserved_maps, num_maps, reserve);
267 of_property_for_each_string(np, "nvidia,pins", prop, group) {
269 ret = add_map_mux(map, reserved_maps, num_maps,
276 ret = add_map_configs(dev, map, reserved_maps,
277 num_maps, group, configs,
291 int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
292 struct device_node *np_config,
293 struct pinctrl_map **map, unsigned *num_maps)
295 unsigned reserved_maps;
296 struct device_node *np;
303 for_each_child_of_node(np_config, np) {
304 ret = tegra_pinctrl_dt_subnode_to_map(pctldev->dev, np, map,
305 &reserved_maps, num_maps);
307 tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps);
315 static struct pinctrl_ops tegra_pinctrl_ops = {
316 .get_groups_count = tegra_pinctrl_get_groups_count,
317 .get_group_name = tegra_pinctrl_get_group_name,
318 .get_group_pins = tegra_pinctrl_get_group_pins,
319 #ifdef CONFIG_DEBUG_FS
320 .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
322 .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
323 .dt_free_map = tegra_pinctrl_dt_free_map,
326 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
328 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
330 return pmx->soc->nfunctions;
333 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
336 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
338 return pmx->soc->functions[function].name;
341 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
343 const char * const **groups,
344 unsigned * const num_groups)
346 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
348 *groups = pmx->soc->functions[function].groups;
349 *num_groups = pmx->soc->functions[function].ngroups;
354 static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
357 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
358 const struct tegra_pingroup *g;
362 g = &pmx->soc->groups[group];
364 if (WARN_ON(g->mux_reg < 0))
367 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
368 if (g->funcs[i] == function)
371 if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
374 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
375 val &= ~(0x3 << g->mux_bit);
376 val |= i << g->mux_bit;
377 pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
382 static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
383 unsigned function, unsigned group)
385 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
386 const struct tegra_pingroup *g;
389 g = &pmx->soc->groups[group];
391 if (WARN_ON(g->mux_reg < 0))
394 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
395 val &= ~(0x3 << g->mux_bit);
396 val |= g->func_safe << g->mux_bit;
397 pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
400 static struct pinmux_ops tegra_pinmux_ops = {
401 .get_functions_count = tegra_pinctrl_get_funcs_count,
402 .get_function_name = tegra_pinctrl_get_func_name,
403 .get_function_groups = tegra_pinctrl_get_func_groups,
404 .enable = tegra_pinctrl_enable,
405 .disable = tegra_pinctrl_disable,
408 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
409 const struct tegra_pingroup *g,
410 enum tegra_pinconf_param param,
412 s8 *bank, s16 *reg, s8 *bit, s8 *width)
415 case TEGRA_PINCONF_PARAM_PULL:
416 *bank = g->pupd_bank;
421 case TEGRA_PINCONF_PARAM_TRISTATE:
427 case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
428 *bank = g->einput_bank;
429 *reg = g->einput_reg;
430 *bit = g->einput_bit;
433 case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
434 *bank = g->odrain_bank;
435 *reg = g->odrain_reg;
436 *bit = g->odrain_bit;
439 case TEGRA_PINCONF_PARAM_LOCK:
440 *bank = g->lock_bank;
445 case TEGRA_PINCONF_PARAM_IORESET:
446 *bank = g->ioreset_bank;
447 *reg = g->ioreset_reg;
448 *bit = g->ioreset_bit;
451 case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
457 case TEGRA_PINCONF_PARAM_SCHMITT:
460 *bit = g->schmitt_bit;
463 case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
469 case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
473 *width = g->drvdn_width;
475 case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
479 *width = g->drvup_width;
481 case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
485 *width = g->slwf_width;
487 case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
491 *width = g->slwr_width;
494 dev_err(pmx->dev, "Invalid config param %04x\n", param);
501 "Config param %04x not supported on group %s\n",
509 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
510 unsigned pin, unsigned long *config)
512 dev_err(pctldev->dev, "pin_config_get op not supported\n");
516 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
517 unsigned pin, unsigned long config)
519 dev_err(pctldev->dev, "pin_config_set op not supported\n");
523 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
524 unsigned group, unsigned long *config)
526 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
527 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
529 const struct tegra_pingroup *g;
535 g = &pmx->soc->groups[group];
537 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
542 val = pmx_readl(pmx, bank, reg);
543 mask = (1 << width) - 1;
544 arg = (val >> bit) & mask;
546 *config = TEGRA_PINCONF_PACK(param, arg);
551 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
552 unsigned group, unsigned long config)
554 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
555 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
556 u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
557 const struct tegra_pingroup *g;
563 g = &pmx->soc->groups[group];
565 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
570 val = pmx_readl(pmx, bank, reg);
572 /* LOCK can't be cleared */
573 if (param == TEGRA_PINCONF_PARAM_LOCK) {
574 if ((val & BIT(bit)) && !arg) {
575 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
580 /* Special-case Boolean values; allow any non-zero as true */
584 /* Range-check user-supplied value */
585 mask = (1 << width) - 1;
587 dev_err(pctldev->dev,
588 "config %lx: %x too big for %d bit register\n",
593 /* Update register */
594 val &= ~(mask << bit);
596 pmx_writel(pmx, val, bank, reg);
601 #ifdef CONFIG_DEBUG_FS
602 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
603 struct seq_file *s, unsigned offset)
607 static const char *strip_prefix(const char *s)
609 const char *comma = strchr(s, ',');
616 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
617 struct seq_file *s, unsigned group)
619 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
620 const struct tegra_pingroup *g;
626 g = &pmx->soc->groups[group];
628 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
629 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
630 &bank, ®, &bit, &width);
634 val = pmx_readl(pmx, bank, reg);
636 val &= (1 << width) - 1;
638 seq_printf(s, "\n\t%s=%u",
639 strip_prefix(cfg_params[i].property), val);
643 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
645 unsigned long config)
647 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
648 u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
649 const char *pname = "unknown";
652 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
653 if (cfg_params[i].param == param) {
654 pname = cfg_params[i].property;
659 seq_printf(s, "%s=%d", strip_prefix(pname), arg);
663 struct pinconf_ops tegra_pinconf_ops = {
664 .pin_config_get = tegra_pinconf_get,
665 .pin_config_set = tegra_pinconf_set,
666 .pin_config_group_get = tegra_pinconf_group_get,
667 .pin_config_group_set = tegra_pinconf_group_set,
668 #ifdef CONFIG_DEBUG_FS
669 .pin_config_dbg_show = tegra_pinconf_dbg_show,
670 .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
671 .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
675 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
676 .name = "Tegra GPIOs",
681 static struct pinctrl_desc tegra_pinctrl_desc = {
682 .pctlops = &tegra_pinctrl_ops,
683 .pmxops = &tegra_pinmux_ops,
684 .confops = &tegra_pinconf_ops,
685 .owner = THIS_MODULE,
688 int __devinit tegra_pinctrl_probe(struct platform_device *pdev,
689 const struct tegra_pinctrl_soc_data *soc_data)
691 struct tegra_pmx *pmx;
692 struct resource *res;
695 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
697 dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
700 pmx->dev = &pdev->dev;
703 tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
704 tegra_pinctrl_desc.name = dev_name(&pdev->dev);
705 tegra_pinctrl_desc.pins = pmx->soc->pins;
706 tegra_pinctrl_desc.npins = pmx->soc->npins;
709 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
715 pmx->regs = devm_kzalloc(&pdev->dev, pmx->nbanks * sizeof(*pmx->regs),
718 dev_err(&pdev->dev, "Can't alloc regs pointer\n");
722 for (i = 0; i < pmx->nbanks; i++) {
723 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
725 dev_err(&pdev->dev, "Missing MEM resource\n");
729 if (!devm_request_mem_region(&pdev->dev, res->start,
731 dev_name(&pdev->dev))) {
733 "Couldn't request MEM resource %d\n", i);
737 pmx->regs[i] = devm_ioremap(&pdev->dev, res->start,
740 dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
745 pmx->pctl = pinctrl_register(&tegra_pinctrl_desc, &pdev->dev, pmx);
747 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
751 pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
753 platform_set_drvdata(pdev, pmx);
755 dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
759 EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);
761 int __devexit tegra_pinctrl_remove(struct platform_device *pdev)
763 struct tegra_pmx *pmx = platform_get_drvdata(pdev);
765 pinctrl_unregister(pmx->pctl);
769 EXPORT_SYMBOL_GPL(tegra_pinctrl_remove);