drivers/pinctrl/pinctrl-single.c

   1 /*
   2  * Generic device tree based pinctrl driver for one register per pin
   3  * type pinmux controllers
   4  *
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2. This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/io.h>
  15 #include <linux/slab.h>
  16 #include <linux/err.h>
  17 #include <linux/list.h>
  18 #include <linux/interrupt.h>
  19
  20 #include <linux/irqchip/chained_irq.h>
  21
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26
  27 #include <linux/pinctrl/pinctrl.h>
  28 #include <linux/pinctrl/pinmux.h>
  29 #include <linux/pinctrl/pinconf-generic.h>
  30
  31 #include <linux/platform_data/pinctrl-single.h>
  32
  33 #include "core.h"
  34 #include "devicetree.h"
  35 #include "pinconf.h"
  36
  37 #define DRIVER_NAME                     "pinctrl-single"
  38 #define PCS_OFF_DISABLED                ~0U
  39
  40 /**
  41  * struct pcs_pingroup - pingroups for a function
  42  * @np:         pingroup device node pointer
  43  * @name:       pingroup name
  44  * @gpins:      array of the pins in the group
  45  * @ngpins:     number of pins in the group
  46  * @node:       list node
  47  */
  48 struct pcs_pingroup {
  49         struct device_node *np;
  50         const char *name;
  51         int *gpins;
  52         int ngpins;
  53         struct list_head node;
  54 };
  55
  56 /**
  57  * struct pcs_func_vals - mux function register offset and value pair
  58  * @reg:        register virtual address
  59  * @val:        register value
  60  */
  61 struct pcs_func_vals {
  62         void __iomem *reg;
  63         unsigned val;
  64         unsigned mask;
  65 };
  66
  67 /**
  68  * struct pcs_conf_vals - pinconf parameter, pinconf register offset
  69  * and value, enable, disable, mask
  70  * @param:      config parameter
  71  * @val:        user input bits in the pinconf register
  72  * @enable:     enable bits in the pinconf register
  73  * @disable:    disable bits in the pinconf register
  74  * @mask:       mask bits in the register value
  75  */
  76 struct pcs_conf_vals {
  77         enum pin_config_param param;
  78         unsigned val;
  79         unsigned enable;
  80         unsigned disable;
  81         unsigned mask;
  82 };
  83
  84 /**
  85  * struct pcs_conf_type - pinconf property name, pinconf param pair
  86  * @name:       property name in DTS file
  87  * @param:      config parameter
  88  */
  89 struct pcs_conf_type {
  90         const char *name;
  91         enum pin_config_param param;
  92 };
  93
  94 /**
  95  * struct pcs_function - pinctrl function
  96  * @name:       pinctrl function name
  97  * @vals:       register and vals array
  98  * @nvals:      number of entries in vals array
  99  * @pgnames:    array of pingroup names the function uses
 100  * @npgnames:   number of pingroup names the function uses
 101  * @node:       list node
 102  */
 103 struct pcs_function {
 104         const char *name;
 105         struct pcs_func_vals *vals;
 106         unsigned nvals;
 107         const char **pgnames;
 108         int npgnames;
 109         struct pcs_conf_vals *conf;
 110         int nconfs;
 111         struct list_head node;
 112 };
 113
 114 /**
 115  * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
 116  * @offset:     offset base of pins
 117  * @npins:      number pins with the same mux value of gpio function
 118  * @gpiofunc:   mux value of gpio function
 119  * @node:       list node
 120  */
 121 struct pcs_gpiofunc_range {
 122         unsigned offset;
 123         unsigned npins;
 124         unsigned gpiofunc;
 125         struct list_head node;
 126 };
 127
 128 /**
 129  * struct pcs_data - wrapper for data needed by pinctrl framework
 130  * @pa:         pindesc array
 131  * @cur:        index to current element
 132  *
 133  * REVISIT: We should be able to drop this eventually by adding
 134  * support for registering pins individually in the pinctrl
 135  * framework for those drivers that don't need a static array.
 136  */
 137 struct pcs_data {
 138         struct pinctrl_pin_desc *pa;
 139         int cur;
 140 };
 141
 142 /**
 143  * struct pcs_soc_data - SoC specific settings
 144  * @flags:      initial SoC specific PCS_FEAT_xxx values
 145  * @irq:        optional interrupt for the controller
 146  * @irq_enable_mask:    optional SoC specific interrupt enable mask
 147  * @irq_status_mask:    optional SoC specific interrupt status mask
 148  * @rearm:      optional SoC specific wake-up rearm function
 149  */
 150 struct pcs_soc_data {
 151         unsigned flags;
 152         int irq;
 153         unsigned irq_enable_mask;
 154         unsigned irq_status_mask;
 155         void (*rearm)(void);
 156 };
 157
 158 /**
 159  * struct pcs_device - pinctrl device instance
 160  * @res:        resources
 161  * @base:       virtual address of the controller
 162  * @size:       size of the ioremapped area
 163  * @dev:        device entry
 164  * @np:         device tree node
 165  * @pctl:       pin controller device
 166  * @flags:      mask of PCS_FEAT_xxx values
 167  * @missing_nr_pinctrl_cells: for legacy binding, may go away
 168  * @socdata:    soc specific data
 169  * @lock:       spinlock for register access
 170  * @mutex:      mutex protecting the lists
 171  * @width:      bits per mux register
 172  * @fmask:      function register mask
 173  * @fshift:     function register shift
 174  * @foff:       value to turn mux off
 175  * @fmax:       max number of functions in fmask
 176  * @bits_per_mux: number of bits per mux
 177  * @bits_per_pin: number of bits per pin
 178  * @pins:       physical pins on the SoC
 179  * @pgtree:     pingroup index radix tree
 180  * @ftree:      function index radix tree
 181  * @pingroups:  list of pingroups
 182  * @functions:  list of functions
 183  * @gpiofuncs:  list of gpio functions
 184  * @irqs:       list of interrupt registers
 185  * @chip:       chip container for this instance
 186  * @domain:     IRQ domain for this instance
 187  * @ngroups:    number of pingroups
 188  * @nfuncs:     number of functions
 189  * @desc:       pin controller descriptor
 190  * @read:       register read function to use
 191  * @write:      register write function to use
 192  */
 193 struct pcs_device {
 194         struct resource *res;
 195         void __iomem *base;
 196         unsigned size;
 197         struct device *dev;
 198         struct device_node *np;
 199         struct pinctrl_dev *pctl;
 200         unsigned flags;
 201 #define PCS_QUIRK_SHARED_IRQ    (1 << 2)
 202 #define PCS_FEAT_IRQ            (1 << 1)
 203 #define PCS_FEAT_PINCONF        (1 << 0)
 204         struct property *missing_nr_pinctrl_cells;
 205         struct pcs_soc_data socdata;
 206         raw_spinlock_t lock;
 207         struct mutex mutex;
 208         unsigned width;
 209         unsigned fmask;
 210         unsigned fshift;
 211         unsigned foff;
 212         unsigned fmax;
 213         bool bits_per_mux;
 214         unsigned bits_per_pin;
 215         struct pcs_data pins;
 216         struct radix_tree_root pgtree;
 217         struct radix_tree_root ftree;
 218         struct list_head pingroups;
 219         struct list_head functions;
 220         struct list_head gpiofuncs;
 221         struct list_head irqs;
 222         struct irq_chip chip;
 223         struct irq_domain *domain;
 224         unsigned ngroups;
 225         unsigned nfuncs;
 226         struct pinctrl_desc desc;
 227         unsigned (*read)(void __iomem *reg);
 228         void (*write)(unsigned val, void __iomem *reg);
 229 };
 230
 231 #define PCS_QUIRK_HAS_SHARED_IRQ        (pcs->flags & PCS_QUIRK_SHARED_IRQ)
 232 #define PCS_HAS_IRQ             (pcs->flags & PCS_FEAT_IRQ)
 233 #define PCS_HAS_PINCONF         (pcs->flags & PCS_FEAT_PINCONF)
 234
 235 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
 236                            unsigned long *config);
 237 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
 238                            unsigned long *configs, unsigned num_configs);
 239
 240 static enum pin_config_param pcs_bias[] = {
 241         PIN_CONFIG_BIAS_PULL_DOWN,
 242         PIN_CONFIG_BIAS_PULL_UP,
 243 };
 244
 245 /*
 246  * This lock class tells lockdep that irqchip core that this single
 247  * pinctrl can be in a different category than its parents, so it won't
 248  * report false recursion.
 249  */
 250 static struct lock_class_key pcs_lock_class;
 251
 252 /*
 253  * REVISIT: Reads and writes could eventually use regmap or something
 254  * generic. But at least on omaps, some mux registers are performance
 255  * critical as they may need to be remuxed every time before and after
 256  * idle. Adding tests for register access width for every read and
 257  * write like regmap is doing is not desired, and caching the registers
 258  * does not help in this case.
 259  */
 260
 261 static unsigned __maybe_unused pcs_readb(void __iomem *reg)
 262 {
 263         return readb(reg);
 264 }
 265
 266 static unsigned __maybe_unused pcs_readw(void __iomem *reg)
 267 {
 268         return readw(reg);
 269 }
 270
 271 static unsigned __maybe_unused pcs_readl(void __iomem *reg)
 272 {
 273         return readl(reg);
 274 }
 275
 276 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
 277 {
 278         writeb(val, reg);
 279 }
 280
 281 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
 282 {
 283         writew(val, reg);
 284 }
 285
 286 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
 287 {
 288         writel(val, reg);
 289 }
 290
 291 static int pcs_get_groups_count(struct pinctrl_dev *pctldev)
 292 {
 293         struct pcs_device *pcs;
 294
 295         pcs = pinctrl_dev_get_drvdata(pctldev);
 296
 297         return pcs->ngroups;
 298 }
 299
 300 static const char *pcs_get_group_name(struct pinctrl_dev *pctldev,
 301                                         unsigned gselector)
 302 {
 303         struct pcs_device *pcs;
 304         struct pcs_pingroup *group;
 305
 306         pcs = pinctrl_dev_get_drvdata(pctldev);
 307         group = radix_tree_lookup(&pcs->pgtree, gselector);
 308         if (!group) {
 309                 dev_err(pcs->dev, "%s could not find pingroup%i\n",
 310                         __func__, gselector);
 311                 return NULL;
 312         }
 313
 314         return group->name;
 315 }
 316
 317 static int pcs_get_group_pins(struct pinctrl_dev *pctldev,
 318                                         unsigned gselector,
 319                                         const unsigned **pins,
 320                                         unsigned *npins)
 321 {
 322         struct pcs_device *pcs;
 323         struct pcs_pingroup *group;
 324
 325         pcs = pinctrl_dev_get_drvdata(pctldev);
 326         group = radix_tree_lookup(&pcs->pgtree, gselector);
 327         if (!group) {
 328                 dev_err(pcs->dev, "%s could not find pingroup%i\n",
 329                         __func__, gselector);
 330                 return -EINVAL;
 331         }
 332
 333         *pins = group->gpins;
 334         *npins = group->ngpins;
 335
 336         return 0;
 337 }
 338
 339 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
 340                                         struct seq_file *s,
 341                                         unsigned pin)
 342 {
 343         struct pcs_device *pcs;
 344         unsigned val, mux_bytes;
 345         unsigned long offset;
 346         size_t pa;
 347
 348         pcs = pinctrl_dev_get_drvdata(pctldev);
 349
 350         mux_bytes = pcs->width / BITS_PER_BYTE;
 351         offset = pin * mux_bytes;
 352         val = pcs->read(pcs->base + offset);
 353         pa = pcs->res->start + offset;
 354
 355         seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
 356 }
 357
 358 static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
 359                                 struct pinctrl_map *map, unsigned num_maps)
 360 {
 361         struct pcs_device *pcs;
 362
 363         pcs = pinctrl_dev_get_drvdata(pctldev);
 364         devm_kfree(pcs->dev, map);
 365 }
 366
 367 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
 368                                 struct device_node *np_config,
 369                                 struct pinctrl_map **map, unsigned *num_maps);
 370
 371 static const struct pinctrl_ops pcs_pinctrl_ops = {
 372         .get_groups_count = pcs_get_groups_count,
 373         .get_group_name = pcs_get_group_name,
 374         .get_group_pins = pcs_get_group_pins,
 375         .pin_dbg_show = pcs_pin_dbg_show,
 376         .dt_node_to_map = pcs_dt_node_to_map,
 377         .dt_free_map = pcs_dt_free_map,
 378 };
 379
 380 static int pcs_get_functions_count(struct pinctrl_dev *pctldev)
 381 {
 382         struct pcs_device *pcs;
 383
 384         pcs = pinctrl_dev_get_drvdata(pctldev);
 385
 386         return pcs->nfuncs;
 387 }
 388
 389 static const char *pcs_get_function_name(struct pinctrl_dev *pctldev,
 390                                                 unsigned fselector)
 391 {
 392         struct pcs_device *pcs;
 393         struct pcs_function *func;
 394
 395         pcs = pinctrl_dev_get_drvdata(pctldev);
 396         func = radix_tree_lookup(&pcs->ftree, fselector);
 397         if (!func) {
 398                 dev_err(pcs->dev, "%s could not find function%i\n",
 399                         __func__, fselector);
 400                 return NULL;
 401         }
 402
 403         return func->name;
 404 }
 405
 406 static int pcs_get_function_groups(struct pinctrl_dev *pctldev,
 407                                         unsigned fselector,
 408                                         const char * const **groups,
 409                                         unsigned * const ngroups)
 410 {
 411         struct pcs_device *pcs;
 412         struct pcs_function *func;
 413
 414         pcs = pinctrl_dev_get_drvdata(pctldev);
 415         func = radix_tree_lookup(&pcs->ftree, fselector);
 416         if (!func) {
 417                 dev_err(pcs->dev, "%s could not find function%i\n",
 418                         __func__, fselector);
 419                 return -EINVAL;
 420         }
 421         *groups = func->pgnames;
 422         *ngroups = func->npgnames;
 423
 424         return 0;
 425 }
 426
 427 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
 428                             struct pcs_function **func)
 429 {
 430         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 431         struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
 432         const struct pinctrl_setting_mux *setting;
 433         unsigned fselector;
 434
 435         /* If pin is not described in DTS & enabled, mux_setting is NULL. */
 436         setting = pdesc->mux_setting;
 437         if (!setting)
 438                 return -ENOTSUPP;
 439         fselector = setting->func;
 440         *func = radix_tree_lookup(&pcs->ftree, fselector);
 441         if (!(*func)) {
 442                 dev_err(pcs->dev, "%s could not find function%i\n",
 443                         __func__, fselector);
 444                 return -ENOTSUPP;
 445         }
 446         return 0;
 447 }
 448
 449 static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
 450         unsigned group)
 451 {
 452         struct pcs_device *pcs;
 453         struct pcs_function *func;
 454         int i;
 455
 456         pcs = pinctrl_dev_get_drvdata(pctldev);
 457         /* If function mask is null, needn't enable it. */
 458         if (!pcs->fmask)
 459                 return 0;
 460         func = radix_tree_lookup(&pcs->ftree, fselector);
 461         if (!func)
 462                 return -EINVAL;
 463
 464         dev_dbg(pcs->dev, "enabling %s function%i\n",
 465                 func->name, fselector);
 466
 467         for (i = 0; i < func->nvals; i++) {
 468                 struct pcs_func_vals *vals;
 469                 unsigned long flags;
 470                 unsigned val, mask;
 471
 472                 vals = &func->vals[i];
 473                 raw_spin_lock_irqsave(&pcs->lock, flags);
 474                 val = pcs->read(vals->reg);
 475
 476                 if (pcs->bits_per_mux)
 477                         mask = vals->mask;
 478                 else
 479                         mask = pcs->fmask;
 480
 481                 val &= ~mask;
 482                 val |= (vals->val & mask);
 483                 pcs->write(val, vals->reg);
 484                 raw_spin_unlock_irqrestore(&pcs->lock, flags);
 485         }
 486
 487         return 0;
 488 }
 489
 490 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
 491                             struct pinctrl_gpio_range *range, unsigned pin)
 492 {
 493         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 494         struct pcs_gpiofunc_range *frange = NULL;
 495         struct list_head *pos, *tmp;
 496         int mux_bytes = 0;
 497         unsigned data;
 498
 499         /* If function mask is null, return directly. */
 500         if (!pcs->fmask)
 501                 return -ENOTSUPP;
 502
 503         list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
 504                 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
 505                 if (pin >= frange->offset + frange->npins
 506                         || pin < frange->offset)
 507                         continue;
 508                 mux_bytes = pcs->width / BITS_PER_BYTE;
 509                 data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask;
 510                 data |= frange->gpiofunc;
 511                 pcs->write(data, pcs->base + pin * mux_bytes);
 512                 break;
 513         }
 514         return 0;
 515 }
 516
 517 static const struct pinmux_ops pcs_pinmux_ops = {
 518         .get_functions_count = pcs_get_functions_count,
 519         .get_function_name = pcs_get_function_name,
 520         .get_function_groups = pcs_get_function_groups,
 521         .set_mux = pcs_set_mux,
 522         .gpio_request_enable = pcs_request_gpio,
 523 };
 524
 525 /* Clear BIAS value */
 526 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
 527 {
 528         unsigned long config;
 529         int i;
 530         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 531                 config = pinconf_to_config_packed(pcs_bias[i], 0);
 532                 pcs_pinconf_set(pctldev, pin, &config, 1);
 533         }
 534 }
 535
 536 /*
 537  * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
 538  * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
 539  */
 540 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
 541 {
 542         unsigned long config;
 543         int i;
 544
 545         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 546                 config = pinconf_to_config_packed(pcs_bias[i], 0);
 547                 if (!pcs_pinconf_get(pctldev, pin, &config))
 548                         goto out;
 549         }
 550         return true;
 551 out:
 552         return false;
 553 }
 554
 555 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
 556                                 unsigned pin, unsigned long *config)
 557 {
 558         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 559         struct pcs_function *func;
 560         enum pin_config_param param;
 561         unsigned offset = 0, data = 0, i, j, ret;
 562
 563         ret = pcs_get_function(pctldev, pin, &func);
 564         if (ret)
 565                 return ret;
 566
 567         for (i = 0; i < func->nconfs; i++) {
 568                 param = pinconf_to_config_param(*config);
 569                 if (param == PIN_CONFIG_BIAS_DISABLE) {
 570                         if (pcs_pinconf_bias_disable(pctldev, pin)) {
 571                                 *config = 0;
 572                                 return 0;
 573                         } else {
 574                                 return -ENOTSUPP;
 575                         }
 576                 } else if (param != func->conf[i].param) {
 577                         continue;
 578                 }
 579
 580                 offset = pin * (pcs->width / BITS_PER_BYTE);
 581                 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
 582                 switch (func->conf[i].param) {
 583                 /* 4 parameters */
 584                 case PIN_CONFIG_BIAS_PULL_DOWN:
 585                 case PIN_CONFIG_BIAS_PULL_UP:
 586                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 587                         if ((data != func->conf[i].enable) ||
 588                             (data == func->conf[i].disable))
 589                                 return -ENOTSUPP;
 590                         *config = 0;
 591                         break;
 592                 /* 2 parameters */
 593                 case PIN_CONFIG_INPUT_SCHMITT:
 594                         for (j = 0; j < func->nconfs; j++) {
 595                                 switch (func->conf[j].param) {
 596                                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 597                                         if (data != func->conf[j].enable)
 598                                                 return -ENOTSUPP;
 599                                         break;
 600                                 default:
 601                                         break;
 602                                 }
 603                         }
 604                         *config = data;
 605                         break;
 606                 case PIN_CONFIG_DRIVE_STRENGTH:
 607                 case PIN_CONFIG_SLEW_RATE:
 608                 case PIN_CONFIG_LOW_POWER_MODE:
 609                 default:
 610                         *config = data;
 611                         break;
 612                 }
 613                 return 0;
 614         }
 615         return -ENOTSUPP;
 616 }
 617
 618 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
 619                                 unsigned pin, unsigned long *configs,
 620                                 unsigned num_configs)
 621 {
 622         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 623         struct pcs_function *func;
 624         unsigned offset = 0, shift = 0, i, data, ret;
 625         u16 arg;
 626         int j;
 627
 628         ret = pcs_get_function(pctldev, pin, &func);
 629         if (ret)
 630                 return ret;
 631
 632         for (j = 0; j < num_configs; j++) {
 633                 for (i = 0; i < func->nconfs; i++) {
 634                         if (pinconf_to_config_param(configs[j])
 635                                 != func->conf[i].param)
 636                                 continue;
 637
 638                         offset = pin * (pcs->width / BITS_PER_BYTE);
 639                         data = pcs->read(pcs->base + offset);
 640                         arg = pinconf_to_config_argument(configs[j]);
 641                         switch (func->conf[i].param) {
 642                         /* 2 parameters */
 643                         case PIN_CONFIG_INPUT_SCHMITT:
 644                         case PIN_CONFIG_DRIVE_STRENGTH:
 645                         case PIN_CONFIG_SLEW_RATE:
 646                         case PIN_CONFIG_LOW_POWER_MODE:
 647                                 shift = ffs(func->conf[i].mask) - 1;
 648                                 data &= ~func->conf[i].mask;
 649                                 data |= (arg << shift) & func->conf[i].mask;
 650                                 break;
 651                         /* 4 parameters */
 652                         case PIN_CONFIG_BIAS_DISABLE:
 653                                 pcs_pinconf_clear_bias(pctldev, pin);
 654                                 break;
 655                         case PIN_CONFIG_BIAS_PULL_DOWN:
 656                         case PIN_CONFIG_BIAS_PULL_UP:
 657                                 if (arg)
 658                                         pcs_pinconf_clear_bias(pctldev, pin);
 659                                 /* fall through */
 660                         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 661                                 data &= ~func->conf[i].mask;
 662                                 if (arg)
 663                                         data |= func->conf[i].enable;
 664                                 else
 665                                         data |= func->conf[i].disable;
 666                                 break;
 667                         default:
 668                                 return -ENOTSUPP;
 669                         }
 670                         pcs->write(data, pcs->base + offset);
 671
 672                         break;
 673                 }
 674                 if (i >= func->nconfs)
 675                         return -ENOTSUPP;
 676         } /* for each config */
 677
 678         return 0;
 679 }
 680
 681 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
 682                                 unsigned group, unsigned long *config)
 683 {
 684         const unsigned *pins;
 685         unsigned npins, old = 0;
 686         int i, ret;
 687
 688         ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
 689         if (ret)
 690                 return ret;
 691         for (i = 0; i < npins; i++) {
 692                 if (pcs_pinconf_get(pctldev, pins[i], config))
 693                         return -ENOTSUPP;
 694                 /* configs do not match between two pins */
 695                 if (i && (old != *config))
 696                         return -ENOTSUPP;
 697                 old = *config;
 698         }
 699         return 0;
 700 }
 701
 702 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
 703                                 unsigned group, unsigned long *configs,
 704                                 unsigned num_configs)
 705 {
 706         const unsigned *pins;
 707         unsigned npins;
 708         int i, ret;
 709
 710         ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
 711         if (ret)
 712                 return ret;
 713         for (i = 0; i < npins; i++) {
 714                 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
 715                         return -ENOTSUPP;
 716         }
 717         return 0;
 718 }
 719
 720 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 721                                 struct seq_file *s, unsigned pin)
 722 {
 723 }
 724
 725 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 726                                 struct seq_file *s, unsigned selector)
 727 {
 728 }
 729
 730 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
 731                                         struct seq_file *s,
 732                                         unsigned long config)
 733 {
 734         pinconf_generic_dump_config(pctldev, s, config);
 735 }
 736
 737 static const struct pinconf_ops pcs_pinconf_ops = {
 738         .pin_config_get = pcs_pinconf_get,
 739         .pin_config_set = pcs_pinconf_set,
 740         .pin_config_group_get = pcs_pinconf_group_get,
 741         .pin_config_group_set = pcs_pinconf_group_set,
 742         .pin_config_dbg_show = pcs_pinconf_dbg_show,
 743         .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
 744         .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
 745         .is_generic = true,
 746 };
 747
 748 /**
 749  * pcs_add_pin() - add a pin to the static per controller pin array
 750  * @pcs: pcs driver instance
 751  * @offset: register offset from base
 752  */
 753 static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
 754                 unsigned pin_pos)
 755 {
 756         struct pcs_soc_data *pcs_soc = &pcs->socdata;
 757         struct pinctrl_pin_desc *pin;
 758         int i;
 759
 760         i = pcs->pins.cur;
 761         if (i >= pcs->desc.npins) {
 762                 dev_err(pcs->dev, "too many pins, max %i\n",
 763                         pcs->desc.npins);
 764                 return -ENOMEM;
 765         }
 766
 767         if (pcs_soc->irq_enable_mask) {
 768                 unsigned val;
 769
 770                 val = pcs->read(pcs->base + offset);
 771                 if (val & pcs_soc->irq_enable_mask) {
 772                         dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
 773                                 (unsigned long)pcs->res->start + offset, val);
 774                         val &= ~pcs_soc->irq_enable_mask;
 775                         pcs->write(val, pcs->base + offset);
 776                 }
 777         }
 778
 779         pin = &pcs->pins.pa[i];
 780         pin->number = i;
 781         pcs->pins.cur++;
 782
 783         return i;
 784 }
 785
 786 /**
 787  * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
 788  * @pcs: pcs driver instance
 789  *
 790  * In case of errors, resources are freed in pcs_free_resources.
 791  *
 792  * If your hardware needs holes in the address space, then just set
 793  * up multiple driver instances.
 794  */
 795 static int pcs_allocate_pin_table(struct pcs_device *pcs)
 796 {
 797         int mux_bytes, nr_pins, i;
 798         int num_pins_in_register = 0;
 799
 800         mux_bytes = pcs->width / BITS_PER_BYTE;
 801
 802         if (pcs->bits_per_mux) {
 803                 pcs->bits_per_pin = fls(pcs->fmask);
 804                 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
 805                 num_pins_in_register = pcs->width / pcs->bits_per_pin;
 806         } else {
 807                 nr_pins = pcs->size / mux_bytes;
 808         }
 809
 810         dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
 811         pcs->pins.pa = devm_kzalloc(pcs->dev,
 812                                 sizeof(*pcs->pins.pa) * nr_pins,
 813                                 GFP_KERNEL);
 814         if (!pcs->pins.pa)
 815                 return -ENOMEM;
 816
 817         pcs->desc.pins = pcs->pins.pa;
 818         pcs->desc.npins = nr_pins;
 819
 820         for (i = 0; i < pcs->desc.npins; i++) {
 821                 unsigned offset;
 822                 int res;
 823                 int byte_num;
 824                 int pin_pos = 0;
 825
 826                 if (pcs->bits_per_mux) {
 827                         byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
 828                         offset = (byte_num / mux_bytes) * mux_bytes;
 829                         pin_pos = i % num_pins_in_register;
 830                 } else {
 831                         offset = i * mux_bytes;
 832                 }
 833                 res = pcs_add_pin(pcs, offset, pin_pos);
 834                 if (res < 0) {
 835                         dev_err(pcs->dev, "error adding pins: %i\n", res);
 836                         return res;
 837                 }
 838         }
 839
 840         return 0;
 841 }
 842
 843 /**
 844  * pcs_add_function() - adds a new function to the function list
 845  * @pcs: pcs driver instance
 846  * @np: device node of the mux entry
 847  * @name: name of the function
 848  * @vals: array of mux register value pairs used by the function
 849  * @nvals: number of mux register value pairs
 850  * @pgnames: array of pingroup names for the function
 851  * @npgnames: number of pingroup names
 852  */
 853 static struct pcs_function *pcs_add_function(struct pcs_device *pcs,
 854                                         struct device_node *np,
 855                                         const char *name,
 856                                         struct pcs_func_vals *vals,
 857                                         unsigned nvals,
 858                                         const char **pgnames,
 859                                         unsigned npgnames)
 860 {
 861         struct pcs_function *function;
 862
 863         function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
 864         if (!function)
 865                 return NULL;
 866
 867         function->name = name;
 868         function->vals = vals;
 869         function->nvals = nvals;
 870         function->pgnames = pgnames;
 871         function->npgnames = npgnames;
 872
 873         mutex_lock(&pcs->mutex);
 874         list_add_tail(&function->node, &pcs->functions);
 875         radix_tree_insert(&pcs->ftree, pcs->nfuncs, function);
 876         pcs->nfuncs++;
 877         mutex_unlock(&pcs->mutex);
 878
 879         return function;
 880 }
 881
 882 static void pcs_remove_function(struct pcs_device *pcs,
 883                                 struct pcs_function *function)
 884 {
 885         int i;
 886
 887         mutex_lock(&pcs->mutex);
 888         for (i = 0; i < pcs->nfuncs; i++) {
 889                 struct pcs_function *found;
 890
 891                 found = radix_tree_lookup(&pcs->ftree, i);
 892                 if (found == function)
 893                         radix_tree_delete(&pcs->ftree, i);
 894         }
 895         list_del(&function->node);
 896         mutex_unlock(&pcs->mutex);
 897 }
 898
 899 /**
 900  * pcs_add_pingroup() - add a pingroup to the pingroup list
 901  * @pcs: pcs driver instance
 902  * @np: device node of the mux entry
 903  * @name: name of the pingroup
 904  * @gpins: array of the pins that belong to the group
 905  * @ngpins: number of pins in the group
 906  */
 907 static int pcs_add_pingroup(struct pcs_device *pcs,
 908                                         struct device_node *np,
 909                                         const char *name,
 910                                         int *gpins,
 911                                         int ngpins)
 912 {
 913         struct pcs_pingroup *pingroup;
 914
 915         pingroup = devm_kzalloc(pcs->dev, sizeof(*pingroup), GFP_KERNEL);
 916         if (!pingroup)
 917                 return -ENOMEM;
 918
 919         pingroup->name = name;
 920         pingroup->np = np;
 921         pingroup->gpins = gpins;
 922         pingroup->ngpins = ngpins;
 923
 924         mutex_lock(&pcs->mutex);
 925         list_add_tail(&pingroup->node, &pcs->pingroups);
 926         radix_tree_insert(&pcs->pgtree, pcs->ngroups, pingroup);
 927         pcs->ngroups++;
 928         mutex_unlock(&pcs->mutex);
 929
 930         return 0;
 931 }
 932
 933 /**
 934  * pcs_get_pin_by_offset() - get a pin index based on the register offset
 935  * @pcs: pcs driver instance
 936  * @offset: register offset from the base
 937  *
 938  * Note that this is OK as long as the pins are in a static array.
 939  */
 940 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
 941 {
 942         unsigned index;
 943
 944         if (offset >= pcs->size) {
 945                 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
 946                         offset, pcs->size);
 947                 return -EINVAL;
 948         }
 949
 950         if (pcs->bits_per_mux)
 951                 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
 952         else
 953                 index = offset / (pcs->width / BITS_PER_BYTE);
 954
 955         return index;
 956 }
 957
 958 /*
 959  * check whether data matches enable bits or disable bits
 960  * Return value: 1 for matching enable bits, 0 for matching disable bits,
 961  *               and negative value for matching failure.
 962  */
 963 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
 964 {
 965         int ret = -EINVAL;
 966
 967         if (data == enable)
 968                 ret = 1;
 969         else if (data == disable)
 970                 ret = 0;
 971         return ret;
 972 }
 973
 974 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
 975                        unsigned value, unsigned enable, unsigned disable,
 976                        unsigned mask)
 977 {
 978         (*conf)->param = param;
 979         (*conf)->val = value;
 980         (*conf)->enable = enable;
 981         (*conf)->disable = disable;
 982         (*conf)->mask = mask;
 983         (*conf)++;
 984 }
 985
 986 static void add_setting(unsigned long **setting, enum pin_config_param param,
 987                         unsigned arg)
 988 {
 989         **setting = pinconf_to_config_packed(param, arg);
 990         (*setting)++;
 991 }
 992
 993 /* add pinconf setting with 2 parameters */
 994 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
 995                           const char *name, enum pin_config_param param,
 996                           struct pcs_conf_vals **conf, unsigned long **settings)
 997 {
 998         unsigned value[2], shift;
 999         int ret;
1000
1001         ret = of_property_read_u32_array(np, name, value, 2);
1002         if (ret)
1003                 return;
1004         /* set value & mask */
1005         value[0] &= value[1];
1006         shift = ffs(value[1]) - 1;
1007         /* skip enable & disable */
1008         add_config(conf, param, value[0], 0, 0, value[1]);
1009         add_setting(settings, param, value[0] >> shift);
1010 }
1011
1012 /* add pinconf setting with 4 parameters */
1013 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
1014                           const char *name, enum pin_config_param param,
1015                           struct pcs_conf_vals **conf, unsigned long **settings)
1016 {
1017         unsigned value[4];
1018         int ret;
1019
1020         /* value to set, enable, disable, mask */
1021         ret = of_property_read_u32_array(np, name, value, 4);
1022         if (ret)
1023                 return;
1024         if (!value[3]) {
1025                 dev_err(pcs->dev, "mask field of the property can't be 0\n");
1026                 return;
1027         }
1028         value[0] &= value[3];
1029         value[1] &= value[3];
1030         value[2] &= value[3];
1031         ret = pcs_config_match(value[0], value[1], value[2]);
1032         if (ret < 0)
1033                 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
1034         add_config(conf, param, value[0], value[1], value[2], value[3]);
1035         add_setting(settings, param, ret);
1036 }
1037
1038 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
1039                              struct pcs_function *func,
1040                              struct pinctrl_map **map)
1041
1042 {
1043         struct pinctrl_map *m = *map;
1044         int i = 0, nconfs = 0;
1045         unsigned long *settings = NULL, *s = NULL;
1046         struct pcs_conf_vals *conf = NULL;
1047         struct pcs_conf_type prop2[] = {
1048                 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
1049                 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
1050                 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
1051                 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
1052         };
1053         struct pcs_conf_type prop4[] = {
1054                 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
1055                 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
1056                 { "pinctrl-single,input-schmitt-enable",
1057                         PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
1058         };
1059
1060         /* If pinconf isn't supported, don't parse properties in below. */
1061         if (!PCS_HAS_PINCONF)
1062                 return 0;
1063
1064         /* cacluate how much properties are supported in current node */
1065         for (i = 0; i < ARRAY_SIZE(prop2); i++) {
1066                 if (of_find_property(np, prop2[i].name, NULL))
1067                         nconfs++;
1068         }
1069         for (i = 0; i < ARRAY_SIZE(prop4); i++) {
1070                 if (of_find_property(np, prop4[i].name, NULL))
1071                         nconfs++;
1072         }
1073         if (!nconfs)
1074                 return 0;
1075
1076         func->conf = devm_kzalloc(pcs->dev,
1077                                   sizeof(struct pcs_conf_vals) * nconfs,
1078                                   GFP_KERNEL);
1079         if (!func->conf)
1080                 return -ENOMEM;
1081         func->nconfs = nconfs;
1082         conf = &(func->conf[0]);
1083         m++;
1084         settings = devm_kzalloc(pcs->dev, sizeof(unsigned long) * nconfs,
1085                                 GFP_KERNEL);
1086         if (!settings)
1087                 return -ENOMEM;
1088         s = &settings[0];
1089
1090         for (i = 0; i < ARRAY_SIZE(prop2); i++)
1091                 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
1092                               &conf, &s);
1093         for (i = 0; i < ARRAY_SIZE(prop4); i++)
1094                 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
1095                               &conf, &s);
1096         m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
1097         m->data.configs.group_or_pin = np->name;
1098         m->data.configs.configs = settings;
1099         m->data.configs.num_configs = nconfs;
1100         return 0;
1101 }
1102
1103 static void pcs_free_pingroups(struct pcs_device *pcs);
1104
1105 /**
1106  * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
1107  * @pcs: pinctrl driver instance
1108  * @np: device node of the mux entry
1109  * @map: map entry
1110  * @num_maps: number of map
1111  * @pgnames: pingroup names
1112  *
1113  * Note that this binding currently supports only sets of one register + value.
1114  *
1115  * Also note that this driver tries to avoid understanding pin and function
1116  * names because of the extra bloat they would cause especially in the case of
1117  * a large number of pins. This driver just sets what is specified for the board
1118  * in the .dts file. Further user space debugging tools can be developed to
1119  * decipher the pin and function names using debugfs.
1120  *
1121  * If you are concerned about the boot time, set up the static pins in
1122  * the bootloader, and only set up selected pins as device tree entries.
1123  */
1124 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
1125                                                 struct device_node *np,
1126                                                 struct pinctrl_map **map,
1127                                                 unsigned *num_maps,
1128                                                 const char **pgnames)
1129 {
1130         const char *name = "pinctrl-single,pins";
1131         struct pcs_func_vals *vals;
1132         int rows, *pins, found = 0, res = -ENOMEM, i;
1133         struct pcs_function *function;
1134
1135         rows = pinctrl_count_index_with_args(np, name);
1136         if (rows <= 0) {
1137                 dev_err(pcs->dev, "Ivalid number of rows: %d\n", rows);
1138                 return -EINVAL;
1139         }
1140
1141         vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL);
1142         if (!vals)
1143                 return -ENOMEM;
1144
1145         pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows, GFP_KERNEL);
1146         if (!pins)
1147                 goto free_vals;
1148
1149         for (i = 0; i < rows; i++) {
1150                 struct of_phandle_args pinctrl_spec;
1151                 unsigned int offset;
1152                 int pin;
1153
1154                 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1155                 if (res)
1156                         return res;
1157
1158                 if (pinctrl_spec.args_count < 2) {
1159                         dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1160                                 pinctrl_spec.args_count);
1161                         break;
1162                 }
1163
1164                 /* Index plus one value cell */
1165                 offset = pinctrl_spec.args[0];
1166                 vals[found].reg = pcs->base + offset;
1167                 vals[found].val = pinctrl_spec.args[1];
1168
1169                 dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x\n",
1170                         pinctrl_spec.np->name, offset, pinctrl_spec.args[1]);
1171
1172                 pin = pcs_get_pin_by_offset(pcs, offset);
1173                 if (pin < 0) {
1174                         dev_err(pcs->dev,
1175                                 "could not add functions for %s %ux\n",
1176                                 np->name, offset);
1177                         break;
1178                 }
1179                 pins[found++] = pin;
1180         }
1181
1182         pgnames[0] = np->name;
1183         function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1184         if (!function) {
1185                 res = -ENOMEM;
1186                 goto free_pins;
1187         }
1188
1189         res = pcs_add_pingroup(pcs, np, np->name, pins, found);
1190         if (res < 0)
1191                 goto free_function;
1192
1193         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1194         (*map)->data.mux.group = np->name;
1195         (*map)->data.mux.function = np->name;
1196
1197         if (PCS_HAS_PINCONF) {
1198                 res = pcs_parse_pinconf(pcs, np, function, map);
1199                 if (res)
1200                         goto free_pingroups;
1201                 *num_maps = 2;
1202         } else {
1203                 *num_maps = 1;
1204         }
1205         return 0;
1206
1207 free_pingroups:
1208         pcs_free_pingroups(pcs);
1209         *num_maps = 1;
1210 free_function:
1211         pcs_remove_function(pcs, function);
1212
1213 free_pins:
1214         devm_kfree(pcs->dev, pins);
1215
1216 free_vals:
1217         devm_kfree(pcs->dev, vals);
1218
1219         return res;
1220 }
1221
1222 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1223                                                 struct device_node *np,
1224                                                 struct pinctrl_map **map,
1225                                                 unsigned *num_maps,
1226                                                 const char **pgnames)
1227 {
1228         const char *name = "pinctrl-single,bits";
1229         struct pcs_func_vals *vals;
1230         int rows, *pins, found = 0, res = -ENOMEM, i;
1231         int npins_in_row;
1232         struct pcs_function *function;
1233
1234         rows = pinctrl_count_index_with_args(np, name);
1235         if (rows <= 0) {
1236                 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1237                 return -EINVAL;
1238         }
1239
1240         npins_in_row = pcs->width / pcs->bits_per_pin;
1241
1242         vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row,
1243                         GFP_KERNEL);
1244         if (!vals)
1245                 return -ENOMEM;
1246
1247         pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows * npins_in_row,
1248                         GFP_KERNEL);
1249         if (!pins)
1250                 goto free_vals;
1251
1252         for (i = 0; i < rows; i++) {
1253                 struct of_phandle_args pinctrl_spec;
1254                 unsigned offset, val;
1255                 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1256                 unsigned pin_num_from_lsb;
1257                 int pin;
1258
1259                 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1260                 if (res)
1261                         return res;
1262
1263                 if (pinctrl_spec.args_count < 3) {
1264                         dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1265                                 pinctrl_spec.args_count);
1266                         break;
1267                 }
1268
1269                 /* Index plus two value cells */
1270                 offset = pinctrl_spec.args[0];
1271                 val = pinctrl_spec.args[1];
1272                 mask = pinctrl_spec.args[2];
1273
1274                 dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x mask: 0x%x\n",
1275                         pinctrl_spec.np->name, offset, val, mask);
1276
1277                 /* Parse pins in each row from LSB */
1278                 while (mask) {
1279                         bit_pos = __ffs(mask);
1280                         pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1281                         mask_pos = ((pcs->fmask) << bit_pos);
1282                         val_pos = val & mask_pos;
1283                         submask = mask & mask_pos;
1284
1285                         if ((mask & mask_pos) == 0) {
1286                                 dev_err(pcs->dev,
1287                                         "Invalid mask for %s at 0x%x\n",
1288                                         np->name, offset);
1289                                 break;
1290                         }
1291
1292                         mask &= ~mask_pos;
1293
1294                         if (submask != mask_pos) {
1295                                 dev_warn(pcs->dev,
1296                                                 "Invalid submask 0x%x for %s at 0x%x\n",
1297                                                 submask, np->name, offset);
1298                                 continue;
1299                         }
1300
1301                         vals[found].mask = submask;
1302                         vals[found].reg = pcs->base + offset;
1303                         vals[found].val = val_pos;
1304
1305                         pin = pcs_get_pin_by_offset(pcs, offset);
1306                         if (pin < 0) {
1307                                 dev_err(pcs->dev,
1308                                         "could not add functions for %s %ux\n",
1309                                         np->name, offset);
1310                                 break;
1311                         }
1312                         pins[found++] = pin + pin_num_from_lsb;
1313                 }
1314         }
1315
1316         pgnames[0] = np->name;
1317         function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1318         if (!function) {
1319                 res = -ENOMEM;
1320                 goto free_pins;
1321         }
1322
1323         res = pcs_add_pingroup(pcs, np, np->name, pins, found);
1324         if (res < 0)
1325                 goto free_function;
1326
1327         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1328         (*map)->data.mux.group = np->name;
1329         (*map)->data.mux.function = np->name;
1330
1331         if (PCS_HAS_PINCONF) {
1332                 dev_err(pcs->dev, "pinconf not supported\n");
1333                 goto free_pingroups;
1334         }
1335
1336         *num_maps = 1;
1337         return 0;
1338
1339 free_pingroups:
1340         pcs_free_pingroups(pcs);
1341         *num_maps = 1;
1342 free_function:
1343         pcs_remove_function(pcs, function);
1344
1345 free_pins:
1346         devm_kfree(pcs->dev, pins);
1347
1348 free_vals:
1349         devm_kfree(pcs->dev, vals);
1350
1351         return res;
1352 }
1353 /**
1354  * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1355  * @pctldev: pinctrl instance
1356  * @np_config: device tree pinmux entry
1357  * @map: array of map entries
1358  * @num_maps: number of maps
1359  */
1360 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1361                                 struct device_node *np_config,
1362                                 struct pinctrl_map **map, unsigned *num_maps)
1363 {
1364         struct pcs_device *pcs;
1365         const char **pgnames;
1366         int ret;
1367
1368         pcs = pinctrl_dev_get_drvdata(pctldev);
1369
1370         /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1371         *map = devm_kzalloc(pcs->dev, sizeof(**map) * 2, GFP_KERNEL);
1372         if (!*map)
1373                 return -ENOMEM;
1374
1375         *num_maps = 0;
1376
1377         pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1378         if (!pgnames) {
1379                 ret = -ENOMEM;
1380                 goto free_map;
1381         }
1382
1383         if (pcs->bits_per_mux) {
1384                 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1385                                 num_maps, pgnames);
1386                 if (ret < 0) {
1387                         dev_err(pcs->dev, "no pins entries for %s\n",
1388                                 np_config->name);
1389                         goto free_pgnames;
1390                 }
1391         } else {
1392                 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1393                                 num_maps, pgnames);
1394                 if (ret < 0) {
1395                         dev_err(pcs->dev, "no pins entries for %s\n",
1396                                 np_config->name);
1397                         goto free_pgnames;
1398                 }
1399         }
1400
1401         return 0;
1402
1403 free_pgnames:
1404         devm_kfree(pcs->dev, pgnames);
1405 free_map:
1406         devm_kfree(pcs->dev, *map);
1407
1408         return ret;
1409 }
1410
1411 /**
1412  * pcs_free_funcs() - free memory used by functions
1413  * @pcs: pcs driver instance
1414  */
1415 static void pcs_free_funcs(struct pcs_device *pcs)
1416 {
1417         struct list_head *pos, *tmp;
1418         int i;
1419
1420         mutex_lock(&pcs->mutex);
1421         for (i = 0; i < pcs->nfuncs; i++) {
1422                 struct pcs_function *func;
1423
1424                 func = radix_tree_lookup(&pcs->ftree, i);
1425                 if (!func)
1426                         continue;
1427                 radix_tree_delete(&pcs->ftree, i);
1428         }
1429         list_for_each_safe(pos, tmp, &pcs->functions) {
1430                 struct pcs_function *function;
1431
1432                 function = list_entry(pos, struct pcs_function, node);
1433                 list_del(&function->node);
1434         }
1435         mutex_unlock(&pcs->mutex);
1436 }
1437
1438 /**
1439  * pcs_free_pingroups() - free memory used by pingroups
1440  * @pcs: pcs driver instance
1441  */
1442 static void pcs_free_pingroups(struct pcs_device *pcs)
1443 {
1444         struct list_head *pos, *tmp;
1445         int i;
1446
1447         mutex_lock(&pcs->mutex);
1448         for (i = 0; i < pcs->ngroups; i++) {
1449                 struct pcs_pingroup *pingroup;
1450
1451                 pingroup = radix_tree_lookup(&pcs->pgtree, i);
1452                 if (!pingroup)
1453                         continue;
1454                 radix_tree_delete(&pcs->pgtree, i);
1455         }
1456         list_for_each_safe(pos, tmp, &pcs->pingroups) {
1457                 struct pcs_pingroup *pingroup;
1458
1459                 pingroup = list_entry(pos, struct pcs_pingroup, node);
1460                 list_del(&pingroup->node);
1461         }
1462         mutex_unlock(&pcs->mutex);
1463 }
1464
1465 /**
1466  * pcs_irq_free() - free interrupt
1467  * @pcs: pcs driver instance
1468  */
1469 static void pcs_irq_free(struct pcs_device *pcs)
1470 {
1471         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1472
1473         if (pcs_soc->irq < 0)
1474                 return;
1475
1476         if (pcs->domain)
1477                 irq_domain_remove(pcs->domain);
1478
1479         if (PCS_QUIRK_HAS_SHARED_IRQ)
1480                 free_irq(pcs_soc->irq, pcs_soc);
1481         else
1482                 irq_set_chained_handler(pcs_soc->irq, NULL);
1483 }
1484
1485 /**
1486  * pcs_free_resources() - free memory used by this driver
1487  * @pcs: pcs driver instance
1488  */
1489 static void pcs_free_resources(struct pcs_device *pcs)
1490 {
1491         pcs_irq_free(pcs);
1492         pinctrl_unregister(pcs->pctl);
1493         pcs_free_funcs(pcs);
1494         pcs_free_pingroups(pcs);
1495 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1496         if (pcs->missing_nr_pinctrl_cells)
1497                 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
1498 #endif
1499 }
1500
1501 static const struct of_device_id pcs_of_match[];
1502
1503 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1504 {
1505         const char *propname = "pinctrl-single,gpio-range";
1506         const char *cellname = "#pinctrl-single,gpio-range-cells";
1507         struct of_phandle_args gpiospec;
1508         struct pcs_gpiofunc_range *range;
1509         int ret, i;
1510
1511         for (i = 0; ; i++) {
1512                 ret = of_parse_phandle_with_args(node, propname, cellname,
1513                                                  i, &gpiospec);
1514                 /* Do not treat it as error. Only treat it as end condition. */
1515                 if (ret) {
1516                         ret = 0;
1517                         break;
1518                 }
1519                 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1520                 if (!range) {
1521                         ret = -ENOMEM;
1522                         break;
1523                 }
1524                 range->offset = gpiospec.args[0];
1525                 range->npins = gpiospec.args[1];
1526                 range->gpiofunc = gpiospec.args[2];
1527                 mutex_lock(&pcs->mutex);
1528                 list_add_tail(&range->node, &pcs->gpiofuncs);
1529                 mutex_unlock(&pcs->mutex);
1530         }
1531         return ret;
1532 }
1533 /**
1534  * @reg:        virtual address of interrupt register
1535  * @hwirq:      hardware irq number
1536  * @irq:        virtual irq number
1537  * @node:       list node
1538  */
1539 struct pcs_interrupt {
1540         void __iomem *reg;
1541         irq_hw_number_t hwirq;
1542         unsigned int irq;
1543         struct list_head node;
1544 };
1545
1546 /**
1547  * pcs_irq_set() - enables or disables an interrupt
1548  *
1549  * Note that this currently assumes one interrupt per pinctrl
1550  * register that is typically used for wake-up events.
1551  */
1552 static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1553                                int irq, const bool enable)
1554 {
1555         struct pcs_device *pcs;
1556         struct list_head *pos;
1557         unsigned mask;
1558
1559         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1560         list_for_each(pos, &pcs->irqs) {
1561                 struct pcs_interrupt *pcswi;
1562                 unsigned soc_mask;
1563
1564                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1565                 if (irq != pcswi->irq)
1566                         continue;
1567
1568                 soc_mask = pcs_soc->irq_enable_mask;
1569                 raw_spin_lock(&pcs->lock);
1570                 mask = pcs->read(pcswi->reg);
1571                 if (enable)
1572                         mask |= soc_mask;
1573                 else
1574                         mask &= ~soc_mask;
1575                 pcs->write(mask, pcswi->reg);
1576
1577                 /* flush posted write */
1578                 mask = pcs->read(pcswi->reg);
1579                 raw_spin_unlock(&pcs->lock);
1580         }
1581
1582         if (pcs_soc->rearm)
1583                 pcs_soc->rearm();
1584 }
1585
1586 /**
1587  * pcs_irq_mask() - mask pinctrl interrupt
1588  * @d: interrupt data
1589  */
1590 static void pcs_irq_mask(struct irq_data *d)
1591 {
1592         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1593
1594         pcs_irq_set(pcs_soc, d->irq, false);
1595 }
1596
1597 /**
1598  * pcs_irq_unmask() - unmask pinctrl interrupt
1599  * @d: interrupt data
1600  */
1601 static void pcs_irq_unmask(struct irq_data *d)
1602 {
1603         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1604
1605         pcs_irq_set(pcs_soc, d->irq, true);
1606 }
1607
1608 /**
1609  * pcs_irq_set_wake() - toggle the suspend and resume wake up
1610  * @d: interrupt data
1611  * @state: wake-up state
1612  *
1613  * Note that this should be called only for suspend and resume.
1614  * For runtime PM, the wake-up events should be enabled by default.
1615  */
1616 static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1617 {
1618         if (state)
1619                 pcs_irq_unmask(d);
1620         else
1621                 pcs_irq_mask(d);
1622
1623         return 0;
1624 }
1625
1626 /**
1627  * pcs_irq_handle() - common interrupt handler
1628  * @pcs_irq: interrupt data
1629  *
1630  * Note that this currently assumes we have one interrupt bit per
1631  * mux register. This interrupt is typically used for wake-up events.
1632  * For more complex interrupts different handlers can be specified.
1633  */
1634 static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1635 {
1636         struct pcs_device *pcs;
1637         struct list_head *pos;
1638         int count = 0;
1639
1640         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1641         list_for_each(pos, &pcs->irqs) {
1642                 struct pcs_interrupt *pcswi;
1643                 unsigned mask;
1644
1645                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1646                 raw_spin_lock(&pcs->lock);
1647                 mask = pcs->read(pcswi->reg);
1648                 raw_spin_unlock(&pcs->lock);
1649                 if (mask & pcs_soc->irq_status_mask) {
1650                         generic_handle_irq(irq_find_mapping(pcs->domain,
1651                                                             pcswi->hwirq));
1652                         count++;
1653                 }
1654         }
1655
1656         return count;
1657 }
1658
1659 /**
1660  * pcs_irq_handler() - handler for the shared interrupt case
1661  * @irq: interrupt
1662  * @d: data
1663  *
1664  * Use this for cases where multiple instances of
1665  * pinctrl-single share a single interrupt like on omaps.
1666  */
1667 static irqreturn_t pcs_irq_handler(int irq, void *d)
1668 {
1669         struct pcs_soc_data *pcs_soc = d;
1670
1671         return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1672 }
1673
1674 /**
1675  * pcs_irq_handle() - handler for the dedicated chained interrupt case
1676  * @irq: interrupt
1677  * @desc: interrupt descriptor
1678  *
1679  * Use this if you have a separate interrupt for each
1680  * pinctrl-single instance.
1681  */
1682 static void pcs_irq_chain_handler(struct irq_desc *desc)
1683 {
1684         struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1685         struct irq_chip *chip;
1686
1687         chip = irq_desc_get_chip(desc);
1688         chained_irq_enter(chip, desc);
1689         pcs_irq_handle(pcs_soc);
1690         /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1691         chained_irq_exit(chip, desc);
1692
1693         return;
1694 }
1695
1696 static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1697                              irq_hw_number_t hwirq)
1698 {
1699         struct pcs_soc_data *pcs_soc = d->host_data;
1700         struct pcs_device *pcs;
1701         struct pcs_interrupt *pcswi;
1702
1703         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1704         pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1705         if (!pcswi)
1706                 return -ENOMEM;
1707
1708         pcswi->reg = pcs->base + hwirq;
1709         pcswi->hwirq = hwirq;
1710         pcswi->irq = irq;
1711
1712         mutex_lock(&pcs->mutex);
1713         list_add_tail(&pcswi->node, &pcs->irqs);
1714         mutex_unlock(&pcs->mutex);
1715
1716         irq_set_chip_data(irq, pcs_soc);
1717         irq_set_chip_and_handler(irq, &pcs->chip,
1718                                  handle_level_irq);
1719         irq_set_lockdep_class(irq, &pcs_lock_class);
1720         irq_set_noprobe(irq);
1721
1722         return 0;
1723 }
1724
1725 static const struct irq_domain_ops pcs_irqdomain_ops = {
1726         .map = pcs_irqdomain_map,
1727         .xlate = irq_domain_xlate_onecell,
1728 };
1729
1730 /**
1731  * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1732  * @pcs: pcs driver instance
1733  * @np: device node pointer
1734  */
1735 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1736                                         struct device_node *np)
1737 {
1738         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1739         const char *name = "pinctrl";
1740         int num_irqs;
1741
1742         if (!pcs_soc->irq_enable_mask ||
1743             !pcs_soc->irq_status_mask) {
1744                 pcs_soc->irq = -1;
1745                 return -EINVAL;
1746         }
1747
1748         INIT_LIST_HEAD(&pcs->irqs);
1749         pcs->chip.name = name;
1750         pcs->chip.irq_ack = pcs_irq_mask;
1751         pcs->chip.irq_mask = pcs_irq_mask;
1752         pcs->chip.irq_unmask = pcs_irq_unmask;
1753         pcs->chip.irq_set_wake = pcs_irq_set_wake;
1754
1755         if (PCS_QUIRK_HAS_SHARED_IRQ) {
1756                 int res;
1757
1758                 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1759                                   IRQF_SHARED | IRQF_NO_SUSPEND |
1760                                   IRQF_NO_THREAD,
1761                                   name, pcs_soc);
1762                 if (res) {
1763                         pcs_soc->irq = -1;
1764                         return res;
1765                 }
1766         } else {
1767                 irq_set_chained_handler_and_data(pcs_soc->irq,
1768                                                  pcs_irq_chain_handler,
1769                                                  pcs_soc);
1770         }
1771
1772         /*
1773          * We can use the register offset as the hardirq
1774          * number as irq_domain_add_simple maps them lazily.
1775          * This way we can easily support more than one
1776          * interrupt per function if needed.
1777          */
1778         num_irqs = pcs->size;
1779
1780         pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1781                                             &pcs_irqdomain_ops,
1782                                             pcs_soc);
1783         if (!pcs->domain) {
1784                 irq_set_chained_handler(pcs_soc->irq, NULL);
1785                 return -EINVAL;
1786         }
1787
1788         return 0;
1789 }
1790
1791 #ifdef CONFIG_PM
1792 static int pinctrl_single_suspend(struct platform_device *pdev,
1793                                         pm_message_t state)
1794 {
1795         struct pcs_device *pcs;
1796
1797         pcs = platform_get_drvdata(pdev);
1798         if (!pcs)
1799                 return -EINVAL;
1800
1801         return pinctrl_force_sleep(pcs->pctl);
1802 }
1803
1804 static int pinctrl_single_resume(struct platform_device *pdev)
1805 {
1806         struct pcs_device *pcs;
1807
1808         pcs = platform_get_drvdata(pdev);
1809         if (!pcs)
1810                 return -EINVAL;
1811
1812         return pinctrl_force_default(pcs->pctl);
1813 }
1814 #endif
1815
1816 /**
1817  * pcs_quirk_missing_pinctrl_cells - handle legacy binding
1818  * @pcs: pinctrl driver instance
1819  * @np: device tree node
1820  * @cells: number of cells
1821  *
1822  * Handle legacy binding with no #pinctrl-cells. This should be
1823  * always two pinctrl-single,bit-per-mux and one for others.
1824  * At some point we may want to consider removing this.
1825  */
1826 static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
1827                                            struct device_node *np,
1828                                            int cells)
1829 {
1830         struct property *p;
1831         const char *name = "#pinctrl-cells";
1832         int error;
1833         u32 val;
1834
1835         error = of_property_read_u32(np, name, &val);
1836         if (!error)
1837                 return 0;
1838
1839         dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
1840                  name, cells);
1841
1842         p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
1843         if (!p)
1844                 return -ENOMEM;
1845
1846         p->length = sizeof(__be32);
1847         p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
1848         if (!p->value)
1849                 return -ENOMEM;
1850         *(__be32 *)p->value = cpu_to_be32(cells);
1851
1852         p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
1853         if (!p->name)
1854                 return -ENOMEM;
1855
1856         pcs->missing_nr_pinctrl_cells = p;
1857
1858 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1859         error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
1860 #endif
1861
1862         return error;
1863 }
1864
1865 static int pcs_probe(struct platform_device *pdev)
1866 {
1867         struct device_node *np = pdev->dev.of_node;
1868         const struct of_device_id *match;
1869         struct pcs_pdata *pdata;
1870         struct resource *res;
1871         struct pcs_device *pcs;
1872         const struct pcs_soc_data *soc;
1873         int ret;
1874
1875         match = of_match_device(pcs_of_match, &pdev->dev);
1876         if (!match)
1877                 return -EINVAL;
1878
1879         pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1880         if (!pcs) {
1881                 dev_err(&pdev->dev, "could not allocate\n");
1882                 return -ENOMEM;
1883         }
1884         pcs->dev = &pdev->dev;
1885         pcs->np = np;
1886         raw_spin_lock_init(&pcs->lock);
1887         mutex_init(&pcs->mutex);
1888         INIT_LIST_HEAD(&pcs->pingroups);
1889         INIT_LIST_HEAD(&pcs->functions);
1890         INIT_LIST_HEAD(&pcs->gpiofuncs);
1891         soc = match->data;
1892         pcs->flags = soc->flags;
1893         memcpy(&pcs->socdata, soc, sizeof(*soc));
1894
1895         ret = of_property_read_u32(np, "pinctrl-single,register-width",
1896                                    &pcs->width);
1897         if (ret) {
1898                 dev_err(pcs->dev, "register width not specified\n");
1899
1900                 return ret;
1901         }
1902
1903         ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1904                                    &pcs->fmask);
1905         if (!ret) {
1906                 pcs->fshift = __ffs(pcs->fmask);
1907                 pcs->fmax = pcs->fmask >> pcs->fshift;
1908         } else {
1909                 /* If mask property doesn't exist, function mux is invalid. */
1910                 pcs->fmask = 0;
1911                 pcs->fshift = 0;
1912                 pcs->fmax = 0;
1913         }
1914
1915         ret = of_property_read_u32(np, "pinctrl-single,function-off",
1916                                         &pcs->foff);
1917         if (ret)
1918                 pcs->foff = PCS_OFF_DISABLED;
1919
1920         pcs->bits_per_mux = of_property_read_bool(np,
1921                                                   "pinctrl-single,bit-per-mux");
1922         ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
1923                                               pcs->bits_per_mux ? 2 : 1);
1924         if (ret) {
1925                 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");
1926
1927                 return ret;
1928         }
1929
1930         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1931         if (!res) {
1932                 dev_err(pcs->dev, "could not get resource\n");
1933                 return -ENODEV;
1934         }
1935
1936         pcs->res = devm_request_mem_region(pcs->dev, res->start,
1937                         resource_size(res), DRIVER_NAME);
1938         if (!pcs->res) {
1939                 dev_err(pcs->dev, "could not get mem_region\n");
1940                 return -EBUSY;
1941         }
1942
1943         pcs->size = resource_size(pcs->res);
1944         pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1945         if (!pcs->base) {
1946                 dev_err(pcs->dev, "could not ioremap\n");
1947                 return -ENODEV;
1948         }
1949
1950         INIT_RADIX_TREE(&pcs->pgtree, GFP_KERNEL);
1951         INIT_RADIX_TREE(&pcs->ftree, GFP_KERNEL);
1952         platform_set_drvdata(pdev, pcs);
1953
1954         switch (pcs->width) {
1955         case 8:
1956                 pcs->read = pcs_readb;
1957                 pcs->write = pcs_writeb;
1958                 break;
1959         case 16:
1960                 pcs->read = pcs_readw;
1961                 pcs->write = pcs_writew;
1962                 break;
1963         case 32:
1964                 pcs->read = pcs_readl;
1965                 pcs->write = pcs_writel;
1966                 break;
1967         default:
1968                 break;
1969         }
1970
1971         pcs->desc.name = DRIVER_NAME;
1972         pcs->desc.pctlops = &pcs_pinctrl_ops;
1973         pcs->desc.pmxops = &pcs_pinmux_ops;
1974         if (PCS_HAS_PINCONF)
1975                 pcs->desc.confops = &pcs_pinconf_ops;
1976         pcs->desc.owner = THIS_MODULE;
1977
1978         ret = pcs_allocate_pin_table(pcs);
1979         if (ret < 0)
1980                 goto free;
1981
1982         pcs->pctl = pinctrl_register(&pcs->desc, pcs->dev, pcs);
1983         if (IS_ERR(pcs->pctl)) {
1984                 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1985                 ret = PTR_ERR(pcs->pctl);
1986                 goto free;
1987         }
1988
1989         ret = pcs_add_gpio_func(np, pcs);
1990         if (ret < 0)
1991                 goto free;
1992
1993         pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1994         if (pcs->socdata.irq)
1995                 pcs->flags |= PCS_FEAT_IRQ;
1996
1997         /* We still need auxdata for some omaps for PRM interrupts */
1998         pdata = dev_get_platdata(&pdev->dev);
1999         if (pdata) {
2000                 if (pdata->rearm)
2001                         pcs->socdata.rearm = pdata->rearm;
2002                 if (pdata->irq) {
2003                         pcs->socdata.irq = pdata->irq;
2004                         pcs->flags |= PCS_FEAT_IRQ;
2005                 }
2006         }
2007
2008         if (PCS_HAS_IRQ) {
2009                 ret = pcs_irq_init_chained_handler(pcs, np);
2010                 if (ret < 0)
2011                         dev_warn(pcs->dev, "initialized with no interrupts\n");
2012         }
2013
2014         dev_info(pcs->dev, "%i pins at pa %p size %u\n",
2015                  pcs->desc.npins, pcs->base, pcs->size);
2016
2017         return 0;
2018
2019 free:
2020         pcs_free_resources(pcs);
2021
2022         return ret;
2023 }
2024
2025 static int pcs_remove(struct platform_device *pdev)
2026 {
2027         struct pcs_device *pcs = platform_get_drvdata(pdev);
2028
2029         if (!pcs)
2030                 return 0;
2031
2032         pcs_free_resources(pcs);
2033
2034         return 0;
2035 }
2036
2037 static const struct pcs_soc_data pinctrl_single_omap_wkup = {
2038         .flags = PCS_QUIRK_SHARED_IRQ,
2039         .irq_enable_mask = (1 << 14),   /* OMAP_WAKEUP_EN */
2040         .irq_status_mask = (1 << 15),   /* OMAP_WAKEUP_EVENT */
2041 };
2042
2043 static const struct pcs_soc_data pinctrl_single_dra7 = {
2044         .irq_enable_mask = (1 << 24),   /* WAKEUPENABLE */
2045         .irq_status_mask = (1 << 25),   /* WAKEUPEVENT */
2046 };
2047
2048 static const struct pcs_soc_data pinctrl_single_am437x = {
2049         .flags = PCS_QUIRK_SHARED_IRQ,
2050         .irq_enable_mask = (1 << 29),   /* OMAP_WAKEUP_EN */
2051         .irq_status_mask = (1 << 30),   /* OMAP_WAKEUP_EVENT */
2052 };
2053
2054 static const struct pcs_soc_data pinctrl_single = {
2055 };
2056
2057 static const struct pcs_soc_data pinconf_single = {
2058         .flags = PCS_FEAT_PINCONF,
2059 };
2060
2061 static const struct of_device_id pcs_of_match[] = {
2062         { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
2063         { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
2064         { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
2065         { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
2066         { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
2067         { .compatible = "pinctrl-single", .data = &pinctrl_single },
2068         { .compatible = "pinconf-single", .data = &pinconf_single },
2069         { },
2070 };
2071 MODULE_DEVICE_TABLE(of, pcs_of_match);
2072
2073 static struct platform_driver pcs_driver = {
2074         .probe          = pcs_probe,
2075         .remove         = pcs_remove,
2076         .driver = {
2077                 .name           = DRIVER_NAME,
2078                 .of_match_table = pcs_of_match,
2079         },
2080 #ifdef CONFIG_PM
2081         .suspend = pinctrl_single_suspend,
2082         .resume = pinctrl_single_resume,
2083 #endif
2084 };
2085
2086 module_platform_driver(pcs_driver);
2087
2088 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
2089 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
2090 MODULE_LICENSE("GPL v2");