1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd.
5 * Copyright (c) 2013 MundoReader S.L.
6 * Author: Heiko Stuebner <heiko@sntech.de>
8 * With some ideas taken from pinctrl-samsung:
9 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
10 * http://www.samsung.com
11 * Copyright (c) 2012 Linaro Ltd
12 * https://www.linaro.org
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
18 #ifndef _PINCTRL_ROCKCHIP_H
19 #define _PINCTRL_ROCKCHIP_H
31 #define RK_GPIO0_B2 10
32 #define RK_GPIO0_B3 11
33 #define RK_GPIO0_B4 12
34 #define RK_GPIO0_B5 13
35 #define RK_GPIO0_B6 14
36 #define RK_GPIO0_B7 15
37 #define RK_GPIO0_C0 16
38 #define RK_GPIO0_C1 17
39 #define RK_GPIO0_C2 18
40 #define RK_GPIO0_C3 19
41 #define RK_GPIO0_C4 20
42 #define RK_GPIO0_C5 21
43 #define RK_GPIO0_C6 22
44 #define RK_GPIO0_C7 23
45 #define RK_GPIO0_D0 24
46 #define RK_GPIO0_D1 25
47 #define RK_GPIO0_D2 26
48 #define RK_GPIO0_D3 27
49 #define RK_GPIO0_D4 28
50 #define RK_GPIO0_D5 29
51 #define RK_GPIO0_D6 30
52 #define RK_GPIO0_D7 31
54 #define RK_GPIO1_A0 32
55 #define RK_GPIO1_A1 33
56 #define RK_GPIO1_A2 34
57 #define RK_GPIO1_A3 35
58 #define RK_GPIO1_A4 36
59 #define RK_GPIO1_A5 37
60 #define RK_GPIO1_A6 38
61 #define RK_GPIO1_A7 39
62 #define RK_GPIO1_B0 40
63 #define RK_GPIO1_B1 41
64 #define RK_GPIO1_B2 42
65 #define RK_GPIO1_B3 43
66 #define RK_GPIO1_B4 44
67 #define RK_GPIO1_B5 45
68 #define RK_GPIO1_B6 46
69 #define RK_GPIO1_B7 47
70 #define RK_GPIO1_C0 48
71 #define RK_GPIO1_C1 49
72 #define RK_GPIO1_C2 50
73 #define RK_GPIO1_C3 51
74 #define RK_GPIO1_C4 52
75 #define RK_GPIO1_C5 53
76 #define RK_GPIO1_C6 54
77 #define RK_GPIO1_C7 55
78 #define RK_GPIO1_D0 56
79 #define RK_GPIO1_D1 57
80 #define RK_GPIO1_D2 58
81 #define RK_GPIO1_D3 59
82 #define RK_GPIO1_D4 60
83 #define RK_GPIO1_D5 61
84 #define RK_GPIO1_D6 62
85 #define RK_GPIO1_D7 63
87 #define RK_GPIO2_A0 64
88 #define RK_GPIO2_A1 65
89 #define RK_GPIO2_A2 66
90 #define RK_GPIO2_A3 67
91 #define RK_GPIO2_A4 68
92 #define RK_GPIO2_A5 69
93 #define RK_GPIO2_A6 70
94 #define RK_GPIO2_A7 71
95 #define RK_GPIO2_B0 72
96 #define RK_GPIO2_B1 73
97 #define RK_GPIO2_B2 74
98 #define RK_GPIO2_B3 75
99 #define RK_GPIO2_B4 76
100 #define RK_GPIO2_B5 77
101 #define RK_GPIO2_B6 78
102 #define RK_GPIO2_B7 79
103 #define RK_GPIO2_C0 80
104 #define RK_GPIO2_C1 81
105 #define RK_GPIO2_C2 82
106 #define RK_GPIO2_C3 83
107 #define RK_GPIO2_C4 84
108 #define RK_GPIO2_C5 85
109 #define RK_GPIO2_C6 86
110 #define RK_GPIO2_C7 87
111 #define RK_GPIO2_D0 88
112 #define RK_GPIO2_D1 89
113 #define RK_GPIO2_D2 90
114 #define RK_GPIO2_D3 91
115 #define RK_GPIO2_D4 92
116 #define RK_GPIO2_D5 93
117 #define RK_GPIO2_D6 94
118 #define RK_GPIO2_D7 95
120 #define RK_GPIO3_A0 96
121 #define RK_GPIO3_A1 97
122 #define RK_GPIO3_A2 98
123 #define RK_GPIO3_A3 99
124 #define RK_GPIO3_A4 100
125 #define RK_GPIO3_A5 101
126 #define RK_GPIO3_A6 102
127 #define RK_GPIO3_A7 103
128 #define RK_GPIO3_B0 104
129 #define RK_GPIO3_B1 105
130 #define RK_GPIO3_B2 106
131 #define RK_GPIO3_B3 107
132 #define RK_GPIO3_B4 108
133 #define RK_GPIO3_B5 109
134 #define RK_GPIO3_B6 110
135 #define RK_GPIO3_B7 111
136 #define RK_GPIO3_C0 112
137 #define RK_GPIO3_C1 113
138 #define RK_GPIO3_C2 114
139 #define RK_GPIO3_C3 115
140 #define RK_GPIO3_C4 116
141 #define RK_GPIO3_C5 117
142 #define RK_GPIO3_C6 118
143 #define RK_GPIO3_C7 119
144 #define RK_GPIO3_D0 120
145 #define RK_GPIO3_D1 121
146 #define RK_GPIO3_D2 122
147 #define RK_GPIO3_D3 123
148 #define RK_GPIO3_D4 124
149 #define RK_GPIO3_D5 125
150 #define RK_GPIO3_D6 126
151 #define RK_GPIO3_D7 127
153 #define RK_GPIO4_A0 128
154 #define RK_GPIO4_A1 129
155 #define RK_GPIO4_A2 130
156 #define RK_GPIO4_A3 131
157 #define RK_GPIO4_A4 132
158 #define RK_GPIO4_A5 133
159 #define RK_GPIO4_A6 134
160 #define RK_GPIO4_A7 135
161 #define RK_GPIO4_B0 136
162 #define RK_GPIO4_B1 137
163 #define RK_GPIO4_B2 138
164 #define RK_GPIO4_B3 139
165 #define RK_GPIO4_B4 140
166 #define RK_GPIO4_B5 141
167 #define RK_GPIO4_B6 142
168 #define RK_GPIO4_B7 143
169 #define RK_GPIO4_C0 144
170 #define RK_GPIO4_C1 145
171 #define RK_GPIO4_C2 146
172 #define RK_GPIO4_C3 147
173 #define RK_GPIO4_C4 148
174 #define RK_GPIO4_C5 149
175 #define RK_GPIO4_C6 150
176 #define RK_GPIO4_C7 151
177 #define RK_GPIO4_D0 152
178 #define RK_GPIO4_D1 153
179 #define RK_GPIO4_D2 154
180 #define RK_GPIO4_D3 155
181 #define RK_GPIO4_D4 156
182 #define RK_GPIO4_D5 157
183 #define RK_GPIO4_D6 158
184 #define RK_GPIO4_D7 159
186 enum rockchip_pinctrl_type {
202 * struct rockchip_gpio_regs
203 * @port_dr: data register
204 * @port_ddr: data direction register
205 * @int_en: interrupt enable
206 * @int_mask: interrupt mask
207 * @int_type: interrupt trigger type, such as high, low, edge trriger type.
208 * @int_polarity: interrupt polarity enable register
209 * @int_bothedge: interrupt bothedge enable register
210 * @int_status: interrupt status register
211 * @int_rawstatus: int_status = int_rawstatus & int_mask
212 * @debounce: enable debounce for interrupt signal
213 * @dbclk_div_en: enable divider for debounce clock
214 * @dbclk_div_con: setting for divider of debounce clock
215 * @port_eoi: end of interrupt of the port
216 * @ext_port: port data from external
217 * @version_id: controller version register
219 struct rockchip_gpio_regs {
238 * struct rockchip_iomux
239 * @type: iomux variant using IOMUX_* constants
240 * @offset: if initialized to -1 it will be autocalculated, by specifying
241 * an initial offset value the relevant source offset can be reset
242 * to a new value for autocalculating the following iomux registers.
244 struct rockchip_iomux {
250 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
252 enum rockchip_pin_drv_type {
253 DRV_TYPE_IO_DEFAULT = 0,
254 DRV_TYPE_IO_1V8_OR_3V0,
255 DRV_TYPE_IO_1V8_ONLY,
256 DRV_TYPE_IO_1V8_3V0_AUTO,
257 DRV_TYPE_IO_3V3_ONLY,
262 * enum type index corresponding to rockchip_pull_list arrays index.
264 enum rockchip_pin_pull_type {
265 PULL_TYPE_IO_DEFAULT = 0,
266 PULL_TYPE_IO_1V8_ONLY,
271 * struct rockchip_drv
272 * @drv_type: drive strength variant using rockchip_perpin_drv_type
273 * @offset: if initialized to -1 it will be autocalculated, by specifying
274 * an initial offset value the relevant source offset can be reset
275 * to a new value for autocalculating the following drive strength
276 * registers. if used chips own cal_drv func instead to calculate
277 * registers offset, the variant could be ignored.
279 struct rockchip_drv {
280 enum rockchip_pin_drv_type drv_type;
285 * struct rockchip_pin_bank
286 * @dev: the pinctrl device bind to the bank
287 * @reg_base: register base of the gpio bank
288 * @regmap_pull: optional separate register for additional pull settings
289 * @clk: clock of the gpio bank
290 * @db_clk: clock of the gpio debounce
291 * @irq: interrupt of the gpio bank
292 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
293 * @pin_base: first pin number
294 * @nr_pins: number of pins in this bank
295 * @name: name of the bank
296 * @bank_num: number of the bank, to account for holes
297 * @iomux: array describing the 4 iomux sources of the bank
298 * @drv: array describing the 4 drive strength sources of the bank
299 * @pull_type: array describing the 4 pull type sources of the bank
300 * @valid: is all necessary information present
301 * @of_node: dt node of this bank
302 * @drvdata: common pinctrl basedata
303 * @domain: irqdomain of the gpio bank
304 * @gpio_chip: gpiolib chip
305 * @grange: gpio range
306 * @slock: spinlock for the gpio bank
307 * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
308 * @recalced_mask: bit mask to indicate a need to recalulate the mask
309 * @route_mask: bits describing the routing pins of per bank
310 * @deferred_output: gpio output settings to be done after gpio bank probed
311 * @deferred_lock: mutex for the deferred_output shared btw gpio and pinctrl
313 struct rockchip_pin_bank {
315 void __iomem *reg_base;
316 struct regmap *regmap_pull;
325 struct rockchip_iomux iomux[4];
326 struct rockchip_drv drv[4];
327 enum rockchip_pin_pull_type pull_type[4];
329 struct device_node *of_node;
330 struct rockchip_pinctrl *drvdata;
331 struct irq_domain *domain;
332 struct gpio_chip gpio_chip;
333 struct pinctrl_gpio_range grange;
334 raw_spinlock_t slock;
335 const struct rockchip_gpio_regs *gpio_regs;
337 u32 toggle_edge_mode;
340 struct list_head deferred_pins;
341 struct mutex deferred_lock;
345 * struct rockchip_mux_recalced_data: represent a pin iomux data.
348 * @bit: index at register.
349 * @reg: register offset.
352 struct rockchip_mux_recalced_data {
360 enum rockchip_mux_route_location {
361 ROCKCHIP_ROUTE_SAME = 0,
367 * struct rockchip_mux_recalced_data: represent a pin iomux data.
368 * @bank_num: bank number.
369 * @pin: index at register or used to calc index.
370 * @func: the min pin.
371 * @route_location: the mux route location (same, pmu, grf).
372 * @route_offset: the max pin.
373 * @route_val: the register offset.
375 struct rockchip_mux_route_data {
379 enum rockchip_mux_route_location route_location;
384 struct rockchip_pin_ctrl {
385 struct rockchip_pin_bank *pin_banks;
389 enum rockchip_pinctrl_type type;
394 struct rockchip_mux_recalced_data *iomux_recalced;
396 struct rockchip_mux_route_data *iomux_routes;
399 int (*pull_calc_reg)(struct rockchip_pin_bank *bank,
400 int pin_num, struct regmap **regmap,
402 int (*drv_calc_reg)(struct rockchip_pin_bank *bank,
403 int pin_num, struct regmap **regmap,
405 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
406 int pin_num, struct regmap **regmap,
410 struct rockchip_pin_config {
412 unsigned long *configs;
413 unsigned int nconfigs;
416 enum pin_config_param;
418 struct rockchip_pin_deferred {
419 struct list_head head;
421 enum pin_config_param param;
426 * struct rockchip_pin_group: represent group of pins of a pinmux function.
427 * @name: name of the pin group, used to lookup the group.
428 * @pins: the pins included in this group.
429 * @npins: number of pins included in this group.
430 * @data: local pin configuration
432 struct rockchip_pin_group {
436 struct rockchip_pin_config *data;
440 * struct rockchip_pmx_func: represent a pin function.
441 * @name: name of the pin function, used to lookup the function.
442 * @groups: one or more names of pin groups that provide this function.
443 * @ngroups: number of groups included in @groups.
445 struct rockchip_pmx_func {
451 struct rockchip_pinctrl {
452 struct regmap *regmap_base;
454 struct regmap *regmap_pull;
455 struct regmap *regmap_pmu;
457 struct rockchip_pin_ctrl *ctrl;
458 struct pinctrl_desc pctl;
459 struct pinctrl_dev *pctl_dev;
460 struct rockchip_pin_group *groups;
461 unsigned int ngroups;
462 struct rockchip_pmx_func *functions;
463 unsigned int nfunctions;