drivers/pinctrl/pinctrl-rockchip.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2013 MundoReader S.L.
   5  * Author: Heiko Stuebner <heiko@sntech.de>
   6  *
   7  * With some ideas taken from pinctrl-samsung:
   8  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9  *              http://www.samsung.com
  10  * Copyright (c) 2012 Linaro Ltd
  11  *              http://www.linaro.org
  12  *
  13  * and pinctrl-at91:
  14  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as published
  18  * by the Free Software Foundation.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #include <linux/init.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/bitops.h>
  30 #include <linux/gpio.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/pinctrl/machine.h>
  34 #include <linux/pinctrl/pinconf.h>
  35 #include <linux/pinctrl/pinctrl.h>
  36 #include <linux/pinctrl/pinmux.h>
  37 #include <linux/pinctrl/pinconf-generic.h>
  38 #include <linux/irqchip/chained_irq.h>
  39 #include <linux/clk.h>
  40 #include <linux/regmap.h>
  41 #include <linux/mfd/syscon.h>
  42 #include <dt-bindings/pinctrl/rockchip.h>
  43
  44 #include "core.h"
  45 #include "pinconf.h"
  46
  47 /* GPIO control registers */
  48 #define GPIO_SWPORT_DR          0x00
  49 #define GPIO_SWPORT_DDR         0x04
  50 #define GPIO_INTEN              0x30
  51 #define GPIO_INTMASK            0x34
  52 #define GPIO_INTTYPE_LEVEL      0x38
  53 #define GPIO_INT_POLARITY       0x3c
  54 #define GPIO_INT_STATUS         0x40
  55 #define GPIO_INT_RAWSTATUS      0x44
  56 #define GPIO_DEBOUNCE           0x48
  57 #define GPIO_PORTS_EOI          0x4c
  58 #define GPIO_EXT_PORT           0x50
  59 #define GPIO_LS_SYNC            0x60
  60
  61 enum rockchip_pinctrl_type {
  62         RK1108,
  63         RK2928,
  64         RK3066B,
  65         RK3188,
  66         RK3288,
  67         RK3368,
  68         RK3399,
  69 };
  70
  71 /**
  72  * Encode variants of iomux registers into a type variable
  73  */
  74 #define IOMUX_GPIO_ONLY         BIT(0)
  75 #define IOMUX_WIDTH_4BIT        BIT(1)
  76 #define IOMUX_SOURCE_PMU        BIT(2)
  77 #define IOMUX_UNROUTED          BIT(3)
  78
  79 /**
  80  * @type: iomux variant using IOMUX_* constants
  81  * @offset: if initialized to -1 it will be autocalculated, by specifying
  82  *          an initial offset value the relevant source offset can be reset
  83  *          to a new value for autocalculating the following iomux registers.
  84  */
  85 struct rockchip_iomux {
  86         int                             type;
  87         int                             offset;
  88 };
  89
  90 /**
  91  * enum type index corresponding to rockchip_perpin_drv_list arrays index.
  92  */
  93 enum rockchip_pin_drv_type {
  94         DRV_TYPE_IO_DEFAULT = 0,
  95         DRV_TYPE_IO_1V8_OR_3V0,
  96         DRV_TYPE_IO_1V8_ONLY,
  97         DRV_TYPE_IO_1V8_3V0_AUTO,
  98         DRV_TYPE_IO_3V3_ONLY,
  99         DRV_TYPE_MAX
 100 };
 101
 102 /**
 103  * enum type index corresponding to rockchip_pull_list arrays index.
 104  */
 105 enum rockchip_pin_pull_type {
 106         PULL_TYPE_IO_DEFAULT = 0,
 107         PULL_TYPE_IO_1V8_ONLY,
 108         PULL_TYPE_MAX
 109 };
 110
 111 /**
 112  * @drv_type: drive strength variant using rockchip_perpin_drv_type
 113  * @offset: if initialized to -1 it will be autocalculated, by specifying
 114  *          an initial offset value the relevant source offset can be reset
 115  *          to a new value for autocalculating the following drive strength
 116  *          registers. if used chips own cal_drv func instead to calculate
 117  *          registers offset, the variant could be ignored.
 118  */
 119 struct rockchip_drv {
 120         enum rockchip_pin_drv_type      drv_type;
 121         int                             offset;
 122 };
 123
 124 /**
 125  * @reg_base: register base of the gpio bank
 126  * @reg_pull: optional separate register for additional pull settings
 127  * @clk: clock of the gpio bank
 128  * @irq: interrupt of the gpio bank
 129  * @saved_masks: Saved content of GPIO_INTEN at suspend time.
 130  * @pin_base: first pin number
 131  * @nr_pins: number of pins in this bank
 132  * @name: name of the bank
 133  * @bank_num: number of the bank, to account for holes
 134  * @iomux: array describing the 4 iomux sources of the bank
 135  * @drv: array describing the 4 drive strength sources of the bank
 136  * @pull_type: array describing the 4 pull type sources of the bank
 137  * @valid: are all necessary informations present
 138  * @of_node: dt node of this bank
 139  * @drvdata: common pinctrl basedata
 140  * @domain: irqdomain of the gpio bank
 141  * @gpio_chip: gpiolib chip
 142  * @grange: gpio range
 143  * @slock: spinlock for the gpio bank
 144  */
 145 struct rockchip_pin_bank {
 146         void __iomem                    *reg_base;
 147         struct regmap                   *regmap_pull;
 148         struct clk                      *clk;
 149         int                             irq;
 150         u32                             saved_masks;
 151         u32                             pin_base;
 152         u8                              nr_pins;
 153         char                            *name;
 154         u8                              bank_num;
 155         struct rockchip_iomux           iomux[4];
 156         struct rockchip_drv             drv[4];
 157         enum rockchip_pin_pull_type     pull_type[4];
 158         bool                            valid;
 159         struct device_node              *of_node;
 160         struct rockchip_pinctrl         *drvdata;
 161         struct irq_domain               *domain;
 162         struct gpio_chip                gpio_chip;
 163         struct pinctrl_gpio_range       grange;
 164         spinlock_t                      slock;
 165         u32                             toggle_edge_mode;
 166 };
 167
 168 #define PIN_BANK(id, pins, label)                       \
 169         {                                               \
 170                 .bank_num       = id,                   \
 171                 .nr_pins        = pins,                 \
 172                 .name           = label,                \
 173                 .iomux          = {                     \
 174                         { .offset = -1 },               \
 175                         { .offset = -1 },               \
 176                         { .offset = -1 },               \
 177                         { .offset = -1 },               \
 178                 },                                      \
 179         }
 180
 181 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
 182         {                                                               \
 183                 .bank_num       = id,                                   \
 184                 .nr_pins        = pins,                                 \
 185                 .name           = label,                                \
 186                 .iomux          = {                                     \
 187                         { .type = iom0, .offset = -1 },                 \
 188                         { .type = iom1, .offset = -1 },                 \
 189                         { .type = iom2, .offset = -1 },                 \
 190                         { .type = iom3, .offset = -1 },                 \
 191                 },                                                      \
 192         }
 193
 194 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
 195         {                                                               \
 196                 .bank_num       = id,                                   \
 197                 .nr_pins        = pins,                                 \
 198                 .name           = label,                                \
 199                 .iomux          = {                                     \
 200                         { .offset = -1 },                               \
 201                         { .offset = -1 },                               \
 202                         { .offset = -1 },                               \
 203                         { .offset = -1 },                               \
 204                 },                                                      \
 205                 .drv            = {                                     \
 206                         { .drv_type = type0, .offset = -1 },            \
 207                         { .drv_type = type1, .offset = -1 },            \
 208                         { .drv_type = type2, .offset = -1 },            \
 209                         { .drv_type = type3, .offset = -1 },            \
 210                 },                                                      \
 211         }
 212
 213 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1,      \
 214                                       drv2, drv3, pull0, pull1,         \
 215                                       pull2, pull3)                     \
 216         {                                                               \
 217                 .bank_num       = id,                                   \
 218                 .nr_pins        = pins,                                 \
 219                 .name           = label,                                \
 220                 .iomux          = {                                     \
 221                         { .offset = -1 },                               \
 222                         { .offset = -1 },                               \
 223                         { .offset = -1 },                               \
 224                         { .offset = -1 },                               \
 225                 },                                                      \
 226                 .drv            = {                                     \
 227                         { .drv_type = drv0, .offset = -1 },             \
 228                         { .drv_type = drv1, .offset = -1 },             \
 229                         { .drv_type = drv2, .offset = -1 },             \
 230                         { .drv_type = drv3, .offset = -1 },             \
 231                 },                                                      \
 232                 .pull_type[0] = pull0,                                  \
 233                 .pull_type[1] = pull1,                                  \
 234                 .pull_type[2] = pull2,                                  \
 235                 .pull_type[3] = pull3,                                  \
 236         }
 237
 238 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1,    \
 239                                         iom2, iom3, drv0, drv1, drv2,   \
 240                                         drv3, offset0, offset1,         \
 241                                         offset2, offset3)               \
 242         {                                                               \
 243                 .bank_num       = id,                                   \
 244                 .nr_pins        = pins,                                 \
 245                 .name           = label,                                \
 246                 .iomux          = {                                     \
 247                         { .type = iom0, .offset = -1 },                 \
 248                         { .type = iom1, .offset = -1 },                 \
 249                         { .type = iom2, .offset = -1 },                 \
 250                         { .type = iom3, .offset = -1 },                 \
 251                 },                                                      \
 252                 .drv            = {                                     \
 253                         { .drv_type = drv0, .offset = offset0 },        \
 254                         { .drv_type = drv1, .offset = offset1 },        \
 255                         { .drv_type = drv2, .offset = offset2 },        \
 256                         { .drv_type = drv3, .offset = offset3 },        \
 257                 },                                                      \
 258         }
 259
 260 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins,      \
 261                                               label, iom0, iom1, iom2,  \
 262                                               iom3, drv0, drv1, drv2,   \
 263                                               drv3, offset0, offset1,   \
 264                                               offset2, offset3, pull0,  \
 265                                               pull1, pull2, pull3)      \
 266         {                                                               \
 267                 .bank_num       = id,                                   \
 268                 .nr_pins        = pins,                                 \
 269                 .name           = label,                                \
 270                 .iomux          = {                                     \
 271                         { .type = iom0, .offset = -1 },                 \
 272                         { .type = iom1, .offset = -1 },                 \
 273                         { .type = iom2, .offset = -1 },                 \
 274                         { .type = iom3, .offset = -1 },                 \
 275                 },                                                      \
 276                 .drv            = {                                     \
 277                         { .drv_type = drv0, .offset = offset0 },        \
 278                         { .drv_type = drv1, .offset = offset1 },        \
 279                         { .drv_type = drv2, .offset = offset2 },        \
 280                         { .drv_type = drv3, .offset = offset3 },        \
 281                 },                                                      \
 282                 .pull_type[0] = pull0,                                  \
 283                 .pull_type[1] = pull1,                                  \
 284                 .pull_type[2] = pull2,                                  \
 285                 .pull_type[3] = pull3,                                  \
 286         }
 287
 288 /**
 289  */
 290 struct rockchip_pin_ctrl {
 291         struct rockchip_pin_bank        *pin_banks;
 292         u32                             nr_banks;
 293         u32                             nr_pins;
 294         char                            *label;
 295         enum rockchip_pinctrl_type      type;
 296         int                             grf_mux_offset;
 297         int                             pmu_mux_offset;
 298         int                             grf_drv_offset;
 299         int                             pmu_drv_offset;
 300
 301         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank,
 302                                     int pin_num, struct regmap **regmap,
 303                                     int *reg, u8 *bit);
 304         void    (*drv_calc_reg)(struct rockchip_pin_bank *bank,
 305                                     int pin_num, struct regmap **regmap,
 306                                     int *reg, u8 *bit);
 307 };
 308
 309 struct rockchip_pin_config {
 310         unsigned int            func;
 311         unsigned long           *configs;
 312         unsigned int            nconfigs;
 313 };
 314
 315 /**
 316  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 317  * @name: name of the pin group, used to lookup the group.
 318  * @pins: the pins included in this group.
 319  * @npins: number of pins included in this group.
 320  * @func: the mux function number to be programmed when selected.
 321  * @configs: the config values to be set for each pin
 322  * @nconfigs: number of configs for each pin
 323  */
 324 struct rockchip_pin_group {
 325         const char                      *name;
 326         unsigned int                    npins;
 327         unsigned int                    *pins;
 328         struct rockchip_pin_config      *data;
 329 };
 330
 331 /**
 332  * struct rockchip_pmx_func: represent a pin function.
 333  * @name: name of the pin function, used to lookup the function.
 334  * @groups: one or more names of pin groups that provide this function.
 335  * @num_groups: number of groups included in @groups.
 336  */
 337 struct rockchip_pmx_func {
 338         const char              *name;
 339         const char              **groups;
 340         u8                      ngroups;
 341 };
 342
 343 struct rockchip_pinctrl {
 344         struct regmap                   *regmap_base;
 345         int                             reg_size;
 346         struct regmap                   *regmap_pull;
 347         struct regmap                   *regmap_pmu;
 348         struct device                   *dev;
 349         struct rockchip_pin_ctrl        *ctrl;
 350         struct pinctrl_desc             pctl;
 351         struct pinctrl_dev              *pctl_dev;
 352         struct rockchip_pin_group       *groups;
 353         unsigned int                    ngroups;
 354         struct rockchip_pmx_func        *functions;
 355         unsigned int                    nfunctions;
 356 };
 357
 358 static struct regmap_config rockchip_regmap_config = {
 359         .reg_bits = 32,
 360         .val_bits = 32,
 361         .reg_stride = 4,
 362 };
 363
 364 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
 365                                         const struct rockchip_pinctrl *info,
 366                                         const char *name)
 367 {
 368         int i;
 369
 370         for (i = 0; i < info->ngroups; i++) {
 371                 if (!strcmp(info->groups[i].name, name))
 372                         return &info->groups[i];
 373         }
 374
 375         return NULL;
 376 }
 377
 378 /*
 379  * given a pin number that is local to a pin controller, find out the pin bank
 380  * and the register base of the pin bank.
 381  */
 382 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 383                                                                 unsigned pin)
 384 {
 385         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 386
 387         while (pin >= (b->pin_base + b->nr_pins))
 388                 b++;
 389
 390         return b;
 391 }
 392
 393 static struct rockchip_pin_bank *bank_num_to_bank(
 394                                         struct rockchip_pinctrl *info,
 395                                         unsigned num)
 396 {
 397         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 398         int i;
 399
 400         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 401                 if (b->bank_num == num)
 402                         return b;
 403         }
 404
 405         return ERR_PTR(-EINVAL);
 406 }
 407
 408 /*
 409  * Pinctrl_ops handling
 410  */
 411
 412 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 413 {
 414         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 415
 416         return info->ngroups;
 417 }
 418
 419 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 420                                                         unsigned selector)
 421 {
 422         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 423
 424         return info->groups[selector].name;
 425 }
 426
 427 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 428                                       unsigned selector, const unsigned **pins,
 429                                       unsigned *npins)
 430 {
 431         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 432
 433         if (selector >= info->ngroups)
 434                 return -EINVAL;
 435
 436         *pins = info->groups[selector].pins;
 437         *npins = info->groups[selector].npins;
 438
 439         return 0;
 440 }
 441
 442 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 443                                  struct device_node *np,
 444                                  struct pinctrl_map **map, unsigned *num_maps)
 445 {
 446         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 447         const struct rockchip_pin_group *grp;
 448         struct pinctrl_map *new_map;
 449         struct device_node *parent;
 450         int map_num = 1;
 451         int i;
 452
 453         /*
 454          * first find the group of this node and check if we need to create
 455          * config maps for pins
 456          */
 457         grp = pinctrl_name_to_group(info, np->name);
 458         if (!grp) {
 459                 dev_err(info->dev, "unable to find group for node %s\n",
 460                         np->name);
 461                 return -EINVAL;
 462         }
 463
 464         map_num += grp->npins;
 465         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 466                                                                 GFP_KERNEL);
 467         if (!new_map)
 468                 return -ENOMEM;
 469
 470         *map = new_map;
 471         *num_maps = map_num;
 472
 473         /* create mux map */
 474         parent = of_get_parent(np);
 475         if (!parent) {
 476                 devm_kfree(pctldev->dev, new_map);
 477                 return -EINVAL;
 478         }
 479         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 480         new_map[0].data.mux.function = parent->name;
 481         new_map[0].data.mux.group = np->name;
 482         of_node_put(parent);
 483
 484         /* create config map */
 485         new_map++;
 486         for (i = 0; i < grp->npins; i++) {
 487                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 488                 new_map[i].data.configs.group_or_pin =
 489                                 pin_get_name(pctldev, grp->pins[i]);
 490                 new_map[i].data.configs.configs = grp->data[i].configs;
 491                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 492         }
 493
 494         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 495                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 496
 497         return 0;
 498 }
 499
 500 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 501                                     struct pinctrl_map *map, unsigned num_maps)
 502 {
 503 }
 504
 505 static const struct pinctrl_ops rockchip_pctrl_ops = {
 506         .get_groups_count       = rockchip_get_groups_count,
 507         .get_group_name         = rockchip_get_group_name,
 508         .get_group_pins         = rockchip_get_group_pins,
 509         .dt_node_to_map         = rockchip_dt_node_to_map,
 510         .dt_free_map            = rockchip_dt_free_map,
 511 };
 512
 513 /*
 514  * Hardware access
 515  */
 516
 517 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
 518 {
 519         struct rockchip_pinctrl *info = bank->drvdata;
 520         int iomux_num = (pin / 8);
 521         struct regmap *regmap;
 522         unsigned int val;
 523         int reg, ret, mask;
 524         u8 bit;
 525
 526         if (iomux_num > 3)
 527                 return -EINVAL;
 528
 529         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 530                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 531                 return -EINVAL;
 532         }
 533
 534         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
 535                 return RK_FUNC_GPIO;
 536
 537         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 538                                 ? info->regmap_pmu : info->regmap_base;
 539
 540         /* get basic quadrupel of mux registers and the correct reg inside */
 541         mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
 542         reg = bank->iomux[iomux_num].offset;
 543         if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
 544                 if ((pin % 8) >= 4)
 545                         reg += 0x4;
 546                 bit = (pin % 4) * 4;
 547         } else {
 548                 bit = (pin % 8) * 2;
 549         }
 550
 551         ret = regmap_read(regmap, reg, &val);
 552         if (ret)
 553                 return ret;
 554
 555         return ((val >> bit) & mask);
 556 }
 557
 558 /*
 559  * Set a new mux function for a pin.
 560  *
 561  * The register is divided into the upper and lower 16 bit. When changing
 562  * a value, the previous register value is not read and changed. Instead
 563  * it seems the changed bits are marked in the upper 16 bit, while the
 564  * changed value gets set in the same offset in the lower 16 bit.
 565  * All pin settings seem to be 2 bit wide in both the upper and lower
 566  * parts.
 567  * @bank: pin bank to change
 568  * @pin: pin to change
 569  * @mux: new mux function to set
 570  */
 571 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 572 {
 573         struct rockchip_pinctrl *info = bank->drvdata;
 574         int iomux_num = (pin / 8);
 575         struct regmap *regmap;
 576         int reg, ret, mask;
 577         unsigned long flags;
 578         u8 bit;
 579         u32 data, rmask;
 580
 581         if (iomux_num > 3)
 582                 return -EINVAL;
 583
 584         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 585                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 586                 return -EINVAL;
 587         }
 588
 589         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
 590                 if (mux != RK_FUNC_GPIO) {
 591                         dev_err(info->dev,
 592                                 "pin %d only supports a gpio mux\n", pin);
 593                         return -ENOTSUPP;
 594                 } else {
 595                         return 0;
 596                 }
 597         }
 598
 599         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
 600                                                 bank->bank_num, pin, mux);
 601
 602         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 603                                 ? info->regmap_pmu : info->regmap_base;
 604
 605         /* get basic quadrupel of mux registers and the correct reg inside */
 606         mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
 607         reg = bank->iomux[iomux_num].offset;
 608         if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
 609                 if ((pin % 8) >= 4)
 610                         reg += 0x4;
 611                 bit = (pin % 4) * 4;
 612         } else {
 613                 bit = (pin % 8) * 2;
 614         }
 615
 616         spin_lock_irqsave(&bank->slock, flags);
 617
 618         data = (mask << (bit + 16));
 619         rmask = data | (data >> 16);
 620         data |= (mux & mask) << bit;
 621         ret = regmap_update_bits(regmap, reg, rmask, data);
 622
 623         spin_unlock_irqrestore(&bank->slock, flags);
 624
 625         return ret;
 626 }
 627
 628 #define RK1108_PULL_PMU_OFFSET          0x10
 629 #define RK1108_PULL_OFFSET              0x110
 630 #define RK1108_PULL_PINS_PER_REG        8
 631 #define RK1108_PULL_BITS_PER_PIN        2
 632 #define RK1108_PULL_BANK_STRIDE         16
 633
 634 static void rk1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 635                                          int pin_num, struct regmap **regmap,
 636                                          int *reg, u8 *bit)
 637 {
 638         struct rockchip_pinctrl *info = bank->drvdata;
 639
 640         /* The first 24 pins of the first bank are located in PMU */
 641         if (bank->bank_num == 0) {
 642                 *regmap = info->regmap_pmu;
 643                 *reg = RK1108_PULL_PMU_OFFSET;
 644         } else {
 645                 *reg = RK1108_PULL_OFFSET;
 646                 *regmap = info->regmap_base;
 647                 /* correct the offset, as we're starting with the 2nd bank */
 648                 *reg -= 0x10;
 649                 *reg += bank->bank_num * RK1108_PULL_BANK_STRIDE;
 650         }
 651
 652         *reg += ((pin_num / RK1108_PULL_PINS_PER_REG) * 4);
 653         *bit = (pin_num % RK1108_PULL_PINS_PER_REG);
 654         *bit *= RK1108_PULL_BITS_PER_PIN;
 655 }
 656
 657 #define RK1108_DRV_PMU_OFFSET           0x20
 658 #define RK1108_DRV_GRF_OFFSET           0x210
 659 #define RK1108_DRV_BITS_PER_PIN         2
 660 #define RK1108_DRV_PINS_PER_REG         8
 661 #define RK1108_DRV_BANK_STRIDE          16
 662
 663 static void rk1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 664                                         int pin_num, struct regmap **regmap,
 665                                         int *reg, u8 *bit)
 666 {
 667         struct rockchip_pinctrl *info = bank->drvdata;
 668
 669         /* The first 24 pins of the first bank are located in PMU */
 670         if (bank->bank_num == 0) {
 671                 *regmap = info->regmap_pmu;
 672                 *reg = RK1108_DRV_PMU_OFFSET;
 673         } else {
 674                 *regmap = info->regmap_base;
 675                 *reg = RK1108_DRV_GRF_OFFSET;
 676
 677                 /* correct the offset, as we're starting with the 2nd bank */
 678                 *reg -= 0x10;
 679                 *reg += bank->bank_num * RK1108_DRV_BANK_STRIDE;
 680         }
 681
 682         *reg += ((pin_num / RK1108_DRV_PINS_PER_REG) * 4);
 683         *bit = pin_num % RK1108_DRV_PINS_PER_REG;
 684         *bit *= RK1108_DRV_BITS_PER_PIN;
 685 }
 686
 687 #define RK2928_PULL_OFFSET              0x118
 688 #define RK2928_PULL_PINS_PER_REG        16
 689 #define RK2928_PULL_BANK_STRIDE         8
 690
 691 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 692                                     int pin_num, struct regmap **regmap,
 693                                     int *reg, u8 *bit)
 694 {
 695         struct rockchip_pinctrl *info = bank->drvdata;
 696
 697         *regmap = info->regmap_base;
 698         *reg = RK2928_PULL_OFFSET;
 699         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
 700         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
 701
 702         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
 703 };
 704
 705 #define RK3188_PULL_OFFSET              0x164
 706 #define RK3188_PULL_BITS_PER_PIN        2
 707 #define RK3188_PULL_PINS_PER_REG        8
 708 #define RK3188_PULL_BANK_STRIDE         16
 709 #define RK3188_PULL_PMU_OFFSET          0x64
 710
 711 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 712                                     int pin_num, struct regmap **regmap,
 713                                     int *reg, u8 *bit)
 714 {
 715         struct rockchip_pinctrl *info = bank->drvdata;
 716
 717         /* The first 12 pins of the first bank are located elsewhere */
 718         if (bank->bank_num == 0 && pin_num < 12) {
 719                 *regmap = info->regmap_pmu ? info->regmap_pmu
 720                                            : bank->regmap_pull;
 721                 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
 722                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 723                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 724                 *bit *= RK3188_PULL_BITS_PER_PIN;
 725         } else {
 726                 *regmap = info->regmap_pull ? info->regmap_pull
 727                                             : info->regmap_base;
 728                 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
 729
 730                 /* correct the offset, as it is the 2nd pull register */
 731                 *reg -= 4;
 732                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 733                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 734
 735                 /*
 736                  * The bits in these registers have an inverse ordering
 737                  * with the lowest pin being in bits 15:14 and the highest
 738                  * pin in bits 1:0
 739                  */
 740                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
 741                 *bit *= RK3188_PULL_BITS_PER_PIN;
 742         }
 743 }
 744
 745 #define RK3288_PULL_OFFSET              0x140
 746 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 747                                     int pin_num, struct regmap **regmap,
 748                                     int *reg, u8 *bit)
 749 {
 750         struct rockchip_pinctrl *info = bank->drvdata;
 751
 752         /* The first 24 pins of the first bank are located in PMU */
 753         if (bank->bank_num == 0) {
 754                 *regmap = info->regmap_pmu;
 755                 *reg = RK3188_PULL_PMU_OFFSET;
 756
 757                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 758                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 759                 *bit *= RK3188_PULL_BITS_PER_PIN;
 760         } else {
 761                 *regmap = info->regmap_base;
 762                 *reg = RK3288_PULL_OFFSET;
 763
 764                 /* correct the offset, as we're starting with the 2nd bank */
 765                 *reg -= 0x10;
 766                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 767                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 768
 769                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
 770                 *bit *= RK3188_PULL_BITS_PER_PIN;
 771         }
 772 }
 773
 774 #define RK3288_DRV_PMU_OFFSET           0x70
 775 #define RK3288_DRV_GRF_OFFSET           0x1c0
 776 #define RK3288_DRV_BITS_PER_PIN         2
 777 #define RK3288_DRV_PINS_PER_REG         8
 778 #define RK3288_DRV_BANK_STRIDE          16
 779
 780 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 781                                     int pin_num, struct regmap **regmap,
 782                                     int *reg, u8 *bit)
 783 {
 784         struct rockchip_pinctrl *info = bank->drvdata;
 785
 786         /* The first 24 pins of the first bank are located in PMU */
 787         if (bank->bank_num == 0) {
 788                 *regmap = info->regmap_pmu;
 789                 *reg = RK3288_DRV_PMU_OFFSET;
 790
 791                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 792                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
 793                 *bit *= RK3288_DRV_BITS_PER_PIN;
 794         } else {
 795                 *regmap = info->regmap_base;
 796                 *reg = RK3288_DRV_GRF_OFFSET;
 797
 798                 /* correct the offset, as we're starting with the 2nd bank */
 799                 *reg -= 0x10;
 800                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
 801                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 802
 803                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
 804                 *bit *= RK3288_DRV_BITS_PER_PIN;
 805         }
 806 }
 807
 808 #define RK3228_PULL_OFFSET              0x100
 809
 810 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 811                                     int pin_num, struct regmap **regmap,
 812                                     int *reg, u8 *bit)
 813 {
 814         struct rockchip_pinctrl *info = bank->drvdata;
 815
 816         *regmap = info->regmap_base;
 817         *reg = RK3228_PULL_OFFSET;
 818         *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 819         *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 820
 821         *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
 822         *bit *= RK3188_PULL_BITS_PER_PIN;
 823 }
 824
 825 #define RK3228_DRV_GRF_OFFSET           0x200
 826
 827 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 828                                     int pin_num, struct regmap **regmap,
 829                                     int *reg, u8 *bit)
 830 {
 831         struct rockchip_pinctrl *info = bank->drvdata;
 832
 833         *regmap = info->regmap_base;
 834         *reg = RK3228_DRV_GRF_OFFSET;
 835         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
 836         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 837
 838         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
 839         *bit *= RK3288_DRV_BITS_PER_PIN;
 840 }
 841
 842 #define RK3368_PULL_GRF_OFFSET          0x100
 843 #define RK3368_PULL_PMU_OFFSET          0x10
 844
 845 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 846                                     int pin_num, struct regmap **regmap,
 847                                     int *reg, u8 *bit)
 848 {
 849         struct rockchip_pinctrl *info = bank->drvdata;
 850
 851         /* The first 32 pins of the first bank are located in PMU */
 852         if (bank->bank_num == 0) {
 853                 *regmap = info->regmap_pmu;
 854                 *reg = RK3368_PULL_PMU_OFFSET;
 855
 856                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 857                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 858                 *bit *= RK3188_PULL_BITS_PER_PIN;
 859         } else {
 860                 *regmap = info->regmap_base;
 861                 *reg = RK3368_PULL_GRF_OFFSET;
 862
 863                 /* correct the offset, as we're starting with the 2nd bank */
 864                 *reg -= 0x10;
 865                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 866                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 867
 868                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
 869                 *bit *= RK3188_PULL_BITS_PER_PIN;
 870         }
 871 }
 872
 873 #define RK3368_DRV_PMU_OFFSET           0x20
 874 #define RK3368_DRV_GRF_OFFSET           0x200
 875
 876 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 877                                     int pin_num, struct regmap **regmap,
 878                                     int *reg, u8 *bit)
 879 {
 880         struct rockchip_pinctrl *info = bank->drvdata;
 881
 882         /* The first 32 pins of the first bank are located in PMU */
 883         if (bank->bank_num == 0) {
 884                 *regmap = info->regmap_pmu;
 885                 *reg = RK3368_DRV_PMU_OFFSET;
 886
 887                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 888                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
 889                 *bit *= RK3288_DRV_BITS_PER_PIN;
 890         } else {
 891                 *regmap = info->regmap_base;
 892                 *reg = RK3368_DRV_GRF_OFFSET;
 893
 894                 /* correct the offset, as we're starting with the 2nd bank */
 895                 *reg -= 0x10;
 896                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
 897                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 898
 899                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
 900                 *bit *= RK3288_DRV_BITS_PER_PIN;
 901         }
 902 }
 903
 904 #define RK3399_PULL_GRF_OFFSET          0xe040
 905 #define RK3399_PULL_PMU_OFFSET          0x40
 906 #define RK3399_DRV_3BITS_PER_PIN        3
 907
 908 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 909                                          int pin_num, struct regmap **regmap,
 910                                          int *reg, u8 *bit)
 911 {
 912         struct rockchip_pinctrl *info = bank->drvdata;
 913
 914         /* The bank0:16 and bank1:32 pins are located in PMU */
 915         if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
 916                 *regmap = info->regmap_pmu;
 917                 *reg = RK3399_PULL_PMU_OFFSET;
 918
 919                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 920
 921                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 922                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 923                 *bit *= RK3188_PULL_BITS_PER_PIN;
 924         } else {
 925                 *regmap = info->regmap_base;
 926                 *reg = RK3399_PULL_GRF_OFFSET;
 927
 928                 /* correct the offset, as we're starting with the 3rd bank */
 929                 *reg -= 0x20;
 930                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 931                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 932
 933                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
 934                 *bit *= RK3188_PULL_BITS_PER_PIN;
 935         }
 936 }
 937
 938 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 939                                         int pin_num, struct regmap **regmap,
 940                                         int *reg, u8 *bit)
 941 {
 942         struct rockchip_pinctrl *info = bank->drvdata;
 943         int drv_num = (pin_num / 8);
 944
 945         /*  The bank0:16 and bank1:32 pins are located in PMU */
 946         if ((bank->bank_num == 0) || (bank->bank_num == 1))
 947                 *regmap = info->regmap_pmu;
 948         else
 949                 *regmap = info->regmap_base;
 950
 951         *reg = bank->drv[drv_num].offset;
 952         if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
 953             (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
 954                 *bit = (pin_num % 8) * 3;
 955         else
 956                 *bit = (pin_num % 8) * 2;
 957 }
 958
 959 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
 960         { 2, 4, 8, 12, -1, -1, -1, -1 },
 961         { 3, 6, 9, 12, -1, -1, -1, -1 },
 962         { 5, 10, 15, 20, -1, -1, -1, -1 },
 963         { 4, 6, 8, 10, 12, 14, 16, 18 },
 964         { 4, 7, 10, 13, 16, 19, 22, 26 }
 965 };
 966
 967 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
 968                                      int pin_num)
 969 {
 970         struct rockchip_pinctrl *info = bank->drvdata;
 971         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 972         struct regmap *regmap;
 973         int reg, ret;
 974         u32 data, temp, rmask_bits;
 975         u8 bit;
 976         int drv_type = bank->drv[pin_num / 8].drv_type;
 977
 978         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 979
 980         switch (drv_type) {
 981         case DRV_TYPE_IO_1V8_3V0_AUTO:
 982         case DRV_TYPE_IO_3V3_ONLY:
 983                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
 984                 switch (bit) {
 985                 case 0 ... 12:
 986                         /* regular case, nothing to do */
 987                         break;
 988                 case 15:
 989                         /*
 990                          * drive-strength offset is special, as it is
 991                          * spread over 2 registers
 992                          */
 993                         ret = regmap_read(regmap, reg, &data);
 994                         if (ret)
 995                                 return ret;
 996
 997                         ret = regmap_read(regmap, reg + 0x4, &temp);
 998                         if (ret)
 999                                 return ret;
1000
1001                         /*
1002                          * the bit data[15] contains bit 0 of the value
1003                          * while temp[1:0] contains bits 2 and 1
1004                          */
1005                         data >>= 15;
1006                         temp &= 0x3;
1007                         temp <<= 1;
1008                         data |= temp;
1009
1010                         return rockchip_perpin_drv_list[drv_type][data];
1011                 case 18 ... 21:
1012                         /* setting fully enclosed in the second register */
1013                         reg += 4;
1014                         bit -= 16;
1015                         break;
1016                 default:
1017                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1018                                 bit, drv_type);
1019                         return -EINVAL;
1020                 }
1021
1022                 break;
1023         case DRV_TYPE_IO_DEFAULT:
1024         case DRV_TYPE_IO_1V8_OR_3V0:
1025         case DRV_TYPE_IO_1V8_ONLY:
1026                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1027                 break;
1028         default:
1029                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1030                         drv_type);
1031                 return -EINVAL;
1032         }
1033
1034         ret = regmap_read(regmap, reg, &data);
1035         if (ret)
1036                 return ret;
1037
1038         data >>= bit;
1039         data &= (1 << rmask_bits) - 1;
1040
1041         return rockchip_perpin_drv_list[drv_type][data];
1042 }
1043
1044 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1045                                      int pin_num, int strength)
1046 {
1047         struct rockchip_pinctrl *info = bank->drvdata;
1048         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1049         struct regmap *regmap;
1050         unsigned long flags;
1051         int reg, ret, i;
1052         u32 data, rmask, rmask_bits, temp;
1053         u8 bit;
1054         int drv_type = bank->drv[pin_num / 8].drv_type;
1055
1056         dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
1057                 bank->bank_num, pin_num, strength);
1058
1059         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1060
1061         ret = -EINVAL;
1062         for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1063                 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
1064                         ret = i;
1065                         break;
1066                 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1067                         ret = rockchip_perpin_drv_list[drv_type][i];
1068                         break;
1069                 }
1070         }
1071
1072         if (ret < 0) {
1073                 dev_err(info->dev, "unsupported driver strength %d\n",
1074                         strength);
1075                 return ret;
1076         }
1077
1078         spin_lock_irqsave(&bank->slock, flags);
1079
1080         switch (drv_type) {
1081         case DRV_TYPE_IO_1V8_3V0_AUTO:
1082         case DRV_TYPE_IO_3V3_ONLY:
1083                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1084                 switch (bit) {
1085                 case 0 ... 12:
1086                         /* regular case, nothing to do */
1087                         break;
1088                 case 15:
1089                         /*
1090                          * drive-strength offset is special, as it is spread
1091                          * over 2 registers, the bit data[15] contains bit 0
1092                          * of the value while temp[1:0] contains bits 2 and 1
1093                          */
1094                         data = (ret & 0x1) << 15;
1095                         temp = (ret >> 0x1) & 0x3;
1096
1097                         rmask = BIT(15) | BIT(31);
1098                         data |= BIT(31);
1099                         ret = regmap_update_bits(regmap, reg, rmask, data);
1100                         if (ret) {
1101                                 spin_unlock_irqrestore(&bank->slock, flags);
1102                                 return ret;
1103                         }
1104
1105                         rmask = 0x3 | (0x3 << 16);
1106                         temp |= (0x3 << 16);
1107                         reg += 0x4;
1108                         ret = regmap_update_bits(regmap, reg, rmask, temp);
1109
1110                         spin_unlock_irqrestore(&bank->slock, flags);
1111                         return ret;
1112                 case 18 ... 21:
1113                         /* setting fully enclosed in the second register */
1114                         reg += 4;
1115                         bit -= 16;
1116                         break;
1117                 default:
1118                         spin_unlock_irqrestore(&bank->slock, flags);
1119                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1120                                 bit, drv_type);
1121                         return -EINVAL;
1122                 }
1123                 break;
1124         case DRV_TYPE_IO_DEFAULT:
1125         case DRV_TYPE_IO_1V8_OR_3V0:
1126         case DRV_TYPE_IO_1V8_ONLY:
1127                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1128                 break;
1129         default:
1130                 spin_unlock_irqrestore(&bank->slock, flags);
1131                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1132                         drv_type);
1133                 return -EINVAL;
1134         }
1135
1136         /* enable the write to the equivalent lower bits */
1137         data = ((1 << rmask_bits) - 1) << (bit + 16);
1138         rmask = data | (data >> 16);
1139         data |= (ret << bit);
1140
1141         ret = regmap_update_bits(regmap, reg, rmask, data);
1142         spin_unlock_irqrestore(&bank->slock, flags);
1143
1144         return ret;
1145 }
1146
1147 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1148         {
1149                 PIN_CONFIG_BIAS_DISABLE,
1150                 PIN_CONFIG_BIAS_PULL_UP,
1151                 PIN_CONFIG_BIAS_PULL_DOWN,
1152                 PIN_CONFIG_BIAS_BUS_HOLD
1153         },
1154         {
1155                 PIN_CONFIG_BIAS_DISABLE,
1156                 PIN_CONFIG_BIAS_PULL_DOWN,
1157                 PIN_CONFIG_BIAS_DISABLE,
1158                 PIN_CONFIG_BIAS_PULL_UP
1159         },
1160 };
1161
1162 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1163 {
1164         struct rockchip_pinctrl *info = bank->drvdata;
1165         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1166         struct regmap *regmap;
1167         int reg, ret, pull_type;
1168         u8 bit;
1169         u32 data;
1170
1171         /* rk3066b does support any pulls */
1172         if (ctrl->type == RK3066B)
1173                 return PIN_CONFIG_BIAS_DISABLE;
1174
1175         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1176
1177         ret = regmap_read(regmap, reg, &data);
1178         if (ret)
1179                 return ret;
1180
1181         switch (ctrl->type) {
1182         case RK2928:
1183                 return !(data & BIT(bit))
1184                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1185                                 : PIN_CONFIG_BIAS_DISABLE;
1186         case RK1108:
1187         case RK3188:
1188         case RK3288:
1189         case RK3368:
1190         case RK3399:
1191                 pull_type = bank->pull_type[pin_num / 8];
1192                 data >>= bit;
1193                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1194
1195                 return rockchip_pull_list[pull_type][data];
1196         default:
1197                 dev_err(info->dev, "unsupported pinctrl type\n");
1198                 return -EINVAL;
1199         };
1200 }
1201
1202 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1203                                         int pin_num, int pull)
1204 {
1205         struct rockchip_pinctrl *info = bank->drvdata;
1206         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1207         struct regmap *regmap;
1208         int reg, ret, i, pull_type;
1209         unsigned long flags;
1210         u8 bit;
1211         u32 data, rmask;
1212
1213         dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
1214                  bank->bank_num, pin_num, pull);
1215
1216         /* rk3066b does support any pulls */
1217         if (ctrl->type == RK3066B)
1218                 return pull ? -EINVAL : 0;
1219
1220         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1221
1222         switch (ctrl->type) {
1223         case RK2928:
1224                 spin_lock_irqsave(&bank->slock, flags);
1225
1226                 data = BIT(bit + 16);
1227                 if (pull == PIN_CONFIG_BIAS_DISABLE)
1228                         data |= BIT(bit);
1229                 ret = regmap_write(regmap, reg, data);
1230
1231                 spin_unlock_irqrestore(&bank->slock, flags);
1232                 break;
1233         case RK1108:
1234         case RK3188:
1235         case RK3288:
1236         case RK3368:
1237         case RK3399:
1238                 pull_type = bank->pull_type[pin_num / 8];
1239                 ret = -EINVAL;
1240                 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
1241                         i++) {
1242                         if (rockchip_pull_list[pull_type][i] == pull) {
1243                                 ret = i;
1244                                 break;
1245                         }
1246                 }
1247
1248                 if (ret < 0) {
1249                         dev_err(info->dev, "unsupported pull setting %d\n",
1250                                 pull);
1251                         return ret;
1252                 }
1253
1254                 spin_lock_irqsave(&bank->slock, flags);
1255
1256                 /* enable the write to the equivalent lower bits */
1257                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
1258                 rmask = data | (data >> 16);
1259                 data |= (ret << bit);
1260
1261                 ret = regmap_update_bits(regmap, reg, rmask, data);
1262
1263                 spin_unlock_irqrestore(&bank->slock, flags);
1264                 break;
1265         default:
1266                 dev_err(info->dev, "unsupported pinctrl type\n");
1267                 return -EINVAL;
1268         }
1269
1270         return ret;
1271 }
1272
1273 /*
1274  * Pinmux_ops handling
1275  */
1276
1277 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
1278 {
1279         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1280
1281         return info->nfunctions;
1282 }
1283
1284 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
1285                                           unsigned selector)
1286 {
1287         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1288
1289         return info->functions[selector].name;
1290 }
1291
1292 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
1293                                 unsigned selector, const char * const **groups,
1294                                 unsigned * const num_groups)
1295 {
1296         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1297
1298         *groups = info->functions[selector].groups;
1299         *num_groups = info->functions[selector].ngroups;
1300
1301         return 0;
1302 }
1303
1304 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
1305                             unsigned group)
1306 {
1307         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1308         const unsigned int *pins = info->groups[group].pins;
1309         const struct rockchip_pin_config *data = info->groups[group].data;
1310         struct rockchip_pin_bank *bank;
1311         int cnt, ret = 0;
1312
1313         dev_dbg(info->dev, "enable function %s group %s\n",
1314                 info->functions[selector].name, info->groups[group].name);
1315
1316         /*
1317          * for each pin in the pin group selected, program the correspoding pin
1318          * pin function number in the config register.
1319          */
1320         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
1321                 bank = pin_to_bank(info, pins[cnt]);
1322                 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
1323                                        data[cnt].func);
1324                 if (ret)
1325                         break;
1326         }
1327
1328         if (ret) {
1329                 /* revert the already done pin settings */
1330                 for (cnt--; cnt >= 0; cnt--)
1331                         rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
1332
1333                 return ret;
1334         }
1335
1336         return 0;
1337 }
1338
1339 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1340 {
1341         struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
1342         u32 data;
1343
1344         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1345
1346         return !(data & BIT(offset));
1347 }
1348
1349 /*
1350  * The calls to gpio_direction_output() and gpio_direction_input()
1351  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
1352  * function called from the gpiolib interface).
1353  */
1354 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
1355                                             int pin, bool input)
1356 {
1357         struct rockchip_pin_bank *bank;
1358         int ret;
1359         unsigned long flags;
1360         u32 data;
1361
1362         bank = gpiochip_get_data(chip);
1363
1364         ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
1365         if (ret < 0)
1366                 return ret;
1367
1368         clk_enable(bank->clk);
1369         spin_lock_irqsave(&bank->slock, flags);
1370
1371         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1372         /* set bit to 1 for output, 0 for input */
1373         if (!input)
1374                 data |= BIT(pin);
1375         else
1376                 data &= ~BIT(pin);
1377         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1378
1379         spin_unlock_irqrestore(&bank->slock, flags);
1380         clk_disable(bank->clk);
1381
1382         return 0;
1383 }
1384
1385 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
1386                                               struct pinctrl_gpio_range *range,
1387                                               unsigned offset, bool input)
1388 {
1389         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1390         struct gpio_chip *chip;
1391         int pin;
1392
1393         chip = range->gc;
1394         pin = offset - chip->base;
1395         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
1396                  offset, range->name, pin, input ? "input" : "output");
1397
1398         return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
1399                                                 input);
1400 }
1401
1402 static const struct pinmux_ops rockchip_pmx_ops = {
1403         .get_functions_count    = rockchip_pmx_get_funcs_count,
1404         .get_function_name      = rockchip_pmx_get_func_name,
1405         .get_function_groups    = rockchip_pmx_get_groups,
1406         .set_mux                = rockchip_pmx_set,
1407         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
1408 };
1409
1410 /*
1411  * Pinconf_ops handling
1412  */
1413
1414 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
1415                                         enum pin_config_param pull)
1416 {
1417         switch (ctrl->type) {
1418         case RK2928:
1419                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
1420                                         pull == PIN_CONFIG_BIAS_DISABLE);
1421         case RK3066B:
1422                 return pull ? false : true;
1423         case RK1108:
1424         case RK3188:
1425         case RK3288:
1426         case RK3368:
1427         case RK3399:
1428                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
1429         }
1430
1431         return false;
1432 }
1433
1434 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
1435 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
1436
1437 /* set the pin config settings for a specified pin */
1438 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1439                                 unsigned long *configs, unsigned num_configs)
1440 {
1441         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1442         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1443         enum pin_config_param param;
1444         u16 arg;
1445         int i;
1446         int rc;
1447
1448         for (i = 0; i < num_configs; i++) {
1449                 param = pinconf_to_config_param(configs[i]);
1450                 arg = pinconf_to_config_argument(configs[i]);
1451
1452                 switch (param) {
1453                 case PIN_CONFIG_BIAS_DISABLE:
1454                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
1455                                 param);
1456                         if (rc)
1457                                 return rc;
1458                         break;
1459                 case PIN_CONFIG_BIAS_PULL_UP:
1460                 case PIN_CONFIG_BIAS_PULL_DOWN:
1461                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1462                 case PIN_CONFIG_BIAS_BUS_HOLD:
1463                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1464                                 return -ENOTSUPP;
1465
1466                         if (!arg)
1467                                 return -EINVAL;
1468
1469                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
1470                                 param);
1471                         if (rc)
1472                                 return rc;
1473                         break;
1474                 case PIN_CONFIG_OUTPUT:
1475                         rockchip_gpio_set(&bank->gpio_chip,
1476                                           pin - bank->pin_base, arg);
1477                         rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
1478                                           pin - bank->pin_base, false);
1479                         if (rc)
1480                                 return rc;
1481                         break;
1482                 case PIN_CONFIG_DRIVE_STRENGTH:
1483                         /* rk3288 is the first with per-pin drive-strength */
1484                         if (!info->ctrl->drv_calc_reg)
1485                                 return -ENOTSUPP;
1486
1487                         rc = rockchip_set_drive_perpin(bank,
1488                                                 pin - bank->pin_base, arg);
1489                         if (rc < 0)
1490                                 return rc;
1491                         break;
1492                 default:
1493                         return -ENOTSUPP;
1494                         break;
1495                 }
1496         } /* for each config */
1497
1498         return 0;
1499 }
1500
1501 /* get the pin config settings for a specified pin */
1502 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1503                                                         unsigned long *config)
1504 {
1505         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1506         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1507         enum pin_config_param param = pinconf_to_config_param(*config);
1508         u16 arg;
1509         int rc;
1510
1511         switch (param) {
1512         case PIN_CONFIG_BIAS_DISABLE:
1513                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1514                         return -EINVAL;
1515
1516                 arg = 0;
1517                 break;
1518         case PIN_CONFIG_BIAS_PULL_UP:
1519         case PIN_CONFIG_BIAS_PULL_DOWN:
1520         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1521         case PIN_CONFIG_BIAS_BUS_HOLD:
1522                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1523                         return -ENOTSUPP;
1524
1525                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1526                         return -EINVAL;
1527
1528                 arg = 1;
1529                 break;
1530         case PIN_CONFIG_OUTPUT:
1531                 rc = rockchip_get_mux(bank, pin - bank->pin_base);
1532                 if (rc != RK_FUNC_GPIO)
1533                         return -EINVAL;
1534
1535                 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
1536                 if (rc < 0)
1537                         return rc;
1538
1539                 arg = rc ? 1 : 0;
1540                 break;
1541         case PIN_CONFIG_DRIVE_STRENGTH:
1542                 /* rk3288 is the first with per-pin drive-strength */
1543                 if (!info->ctrl->drv_calc_reg)
1544                         return -ENOTSUPP;
1545
1546                 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
1547                 if (rc < 0)
1548                         return rc;
1549
1550                 arg = rc;
1551                 break;
1552         default:
1553                 return -ENOTSUPP;
1554                 break;
1555         }
1556
1557         *config = pinconf_to_config_packed(param, arg);
1558
1559         return 0;
1560 }
1561
1562 static const struct pinconf_ops rockchip_pinconf_ops = {
1563         .pin_config_get                 = rockchip_pinconf_get,
1564         .pin_config_set                 = rockchip_pinconf_set,
1565         .is_generic                     = true,
1566 };
1567
1568 static const struct of_device_id rockchip_bank_match[] = {
1569         { .compatible = "rockchip,gpio-bank" },
1570         { .compatible = "rockchip,rk3188-gpio-bank0" },
1571         {},
1572 };
1573
1574 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
1575                                                 struct device_node *np)
1576 {
1577         struct device_node *child;
1578
1579         for_each_child_of_node(np, child) {
1580                 if (of_match_node(rockchip_bank_match, child))
1581                         continue;
1582
1583                 info->nfunctions++;
1584                 info->ngroups += of_get_child_count(child);
1585         }
1586 }
1587
1588 static int rockchip_pinctrl_parse_groups(struct device_node *np,
1589                                               struct rockchip_pin_group *grp,
1590                                               struct rockchip_pinctrl *info,
1591                                               u32 index)
1592 {
1593         struct rockchip_pin_bank *bank;
1594         int size;
1595         const __be32 *list;
1596         int num;
1597         int i, j;
1598         int ret;
1599
1600         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1601
1602         /* Initialise group */
1603         grp->name = np->name;
1604
1605         /*
1606          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
1607          * do sanity check and calculate pins number
1608          */
1609         list = of_get_property(np, "rockchip,pins", &size);
1610         /* we do not check return since it's safe node passed down */
1611         size /= sizeof(*list);
1612         if (!size || size % 4) {
1613                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1614                 return -EINVAL;
1615         }
1616
1617         grp->npins = size / 4;
1618
1619         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1620                                                 GFP_KERNEL);
1621         grp->data = devm_kzalloc(info->dev, grp->npins *
1622                                           sizeof(struct rockchip_pin_config),
1623                                         GFP_KERNEL);
1624         if (!grp->pins || !grp->data)
1625                 return -ENOMEM;
1626
1627         for (i = 0, j = 0; i < size; i += 4, j++) {
1628                 const __be32 *phandle;
1629                 struct device_node *np_config;
1630
1631                 num = be32_to_cpu(*list++);
1632                 bank = bank_num_to_bank(info, num);
1633                 if (IS_ERR(bank))
1634                         return PTR_ERR(bank);
1635
1636                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
1637                 grp->data[j].func = be32_to_cpu(*list++);
1638
1639                 phandle = list++;
1640                 if (!phandle)
1641                         return -EINVAL;
1642
1643                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
1644                 ret = pinconf_generic_parse_dt_config(np_config, NULL,
1645                                 &grp->data[j].configs, &grp->data[j].nconfigs);
1646                 if (ret)
1647                         return ret;
1648         }
1649
1650         return 0;
1651 }
1652
1653 static int rockchip_pinctrl_parse_functions(struct device_node *np,
1654                                                 struct rockchip_pinctrl *info,
1655                                                 u32 index)
1656 {
1657         struct device_node *child;
1658         struct rockchip_pmx_func *func;
1659         struct rockchip_pin_group *grp;
1660         int ret;
1661         static u32 grp_index;
1662         u32 i = 0;
1663
1664         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1665
1666         func = &info->functions[index];
1667
1668         /* Initialise function */
1669         func->name = np->name;
1670         func->ngroups = of_get_child_count(np);
1671         if (func->ngroups <= 0)
1672                 return 0;
1673
1674         func->groups = devm_kzalloc(info->dev,
1675                         func->ngroups * sizeof(char *), GFP_KERNEL);
1676         if (!func->groups)
1677                 return -ENOMEM;
1678
1679         for_each_child_of_node(np, child) {
1680                 func->groups[i] = child->name;
1681                 grp = &info->groups[grp_index++];
1682                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
1683                 if (ret) {
1684                         of_node_put(child);
1685                         return ret;
1686                 }
1687         }
1688
1689         return 0;
1690 }
1691
1692 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1693                                               struct rockchip_pinctrl *info)
1694 {
1695         struct device *dev = &pdev->dev;
1696         struct device_node *np = dev->of_node;
1697         struct device_node *child;
1698         int ret;
1699         int i;
1700
1701         rockchip_pinctrl_child_count(info, np);
1702
1703         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1704         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1705
1706         info->functions = devm_kzalloc(dev, info->nfunctions *
1707                                               sizeof(struct rockchip_pmx_func),
1708                                               GFP_KERNEL);
1709         if (!info->functions) {
1710                 dev_err(dev, "failed to allocate memory for function list\n");
1711                 return -EINVAL;
1712         }
1713
1714         info->groups = devm_kzalloc(dev, info->ngroups *
1715                                             sizeof(struct rockchip_pin_group),
1716                                             GFP_KERNEL);
1717         if (!info->groups) {
1718                 dev_err(dev, "failed allocate memory for ping group list\n");
1719                 return -EINVAL;
1720         }
1721
1722         i = 0;
1723
1724         for_each_child_of_node(np, child) {
1725                 if (of_match_node(rockchip_bank_match, child))
1726                         continue;
1727
1728                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1729                 if (ret) {
1730                         dev_err(&pdev->dev, "failed to parse function\n");
1731                         of_node_put(child);
1732                         return ret;
1733                 }
1734         }
1735
1736         return 0;
1737 }
1738
1739 static int rockchip_pinctrl_register(struct platform_device *pdev,
1740                                         struct rockchip_pinctrl *info)
1741 {
1742         struct pinctrl_desc *ctrldesc = &info->pctl;
1743         struct pinctrl_pin_desc *pindesc, *pdesc;
1744         struct rockchip_pin_bank *pin_bank;
1745         int pin, bank, ret;
1746         int k;
1747
1748         ctrldesc->name = "rockchip-pinctrl";
1749         ctrldesc->owner = THIS_MODULE;
1750         ctrldesc->pctlops = &rockchip_pctrl_ops;
1751         ctrldesc->pmxops = &rockchip_pmx_ops;
1752         ctrldesc->confops = &rockchip_pinconf_ops;
1753
1754         pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1755                         info->ctrl->nr_pins, GFP_KERNEL);
1756         if (!pindesc) {
1757                 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1758                 return -ENOMEM;
1759         }
1760         ctrldesc->pins = pindesc;
1761         ctrldesc->npins = info->ctrl->nr_pins;
1762
1763         pdesc = pindesc;
1764         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1765                 pin_bank = &info->ctrl->pin_banks[bank];
1766                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1767                         pdesc->number = k;
1768                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1769                                                 pin_bank->name, pin);
1770                         pdesc++;
1771                 }
1772         }
1773
1774         ret = rockchip_pinctrl_parse_dt(pdev, info);
1775         if (ret)
1776                 return ret;
1777
1778         info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
1779         if (IS_ERR(info->pctl_dev)) {
1780                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1781                 return PTR_ERR(info->pctl_dev);
1782         }
1783
1784         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1785                 pin_bank = &info->ctrl->pin_banks[bank];
1786                 pin_bank->grange.name = pin_bank->name;
1787                 pin_bank->grange.id = bank;
1788                 pin_bank->grange.pin_base = pin_bank->pin_base;
1789                 pin_bank->grange.base = pin_bank->gpio_chip.base;
1790                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1791                 pin_bank->grange.gc = &pin_bank->gpio_chip;
1792                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1793         }
1794
1795         return 0;
1796 }
1797
1798 /*
1799  * GPIO handling
1800  */
1801
1802 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1803 {
1804         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
1805         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1806         unsigned long flags;
1807         u32 data;
1808
1809         clk_enable(bank->clk);
1810         spin_lock_irqsave(&bank->slock, flags);
1811
1812         data = readl(reg);
1813         data &= ~BIT(offset);
1814         if (value)
1815                 data |= BIT(offset);
1816         writel(data, reg);
1817
1818         spin_unlock_irqrestore(&bank->slock, flags);
1819         clk_disable(bank->clk);
1820 }
1821
1822 /*
1823  * Returns the level of the pin for input direction and setting of the DR
1824  * register for output gpios.
1825  */
1826 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1827 {
1828         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
1829         u32 data;
1830
1831         clk_enable(bank->clk);
1832         data = readl(bank->reg_base + GPIO_EXT_PORT);
1833         clk_disable(bank->clk);
1834         data >>= offset;
1835         data &= 1;
1836         return data;
1837 }
1838
1839 /*
1840  * gpiolib gpio_direction_input callback function. The setting of the pin
1841  * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1842  * interface.
1843  */
1844 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1845 {
1846         return pinctrl_gpio_direction_input(gc->base + offset);
1847 }
1848
1849 /*
1850  * gpiolib gpio_direction_output callback function. The setting of the pin
1851  * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1852  * interface.
1853  */
1854 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1855                                           unsigned offset, int value)
1856 {
1857         rockchip_gpio_set(gc, offset, value);
1858         return pinctrl_gpio_direction_output(gc->base + offset);
1859 }
1860
1861 /*
1862  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1863  * and a virtual IRQ, if not already present.
1864  */
1865 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1866 {
1867         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
1868         unsigned int virq;
1869
1870         if (!bank->domain)
1871                 return -ENXIO;
1872
1873         virq = irq_create_mapping(bank->domain, offset);
1874
1875         return (virq) ? : -ENXIO;
1876 }
1877
1878 static const struct gpio_chip rockchip_gpiolib_chip = {
1879         .request = gpiochip_generic_request,
1880         .free = gpiochip_generic_free,
1881         .set = rockchip_gpio_set,
1882         .get = rockchip_gpio_get,
1883         .get_direction  = rockchip_gpio_get_direction,
1884         .direction_input = rockchip_gpio_direction_input,
1885         .direction_output = rockchip_gpio_direction_output,
1886         .to_irq = rockchip_gpio_to_irq,
1887         .owner = THIS_MODULE,
1888 };
1889
1890 /*
1891  * Interrupt handling
1892  */
1893
1894 static void rockchip_irq_demux(struct irq_desc *desc)
1895 {
1896         struct irq_chip *chip = irq_desc_get_chip(desc);
1897         struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
1898         u32 pend;
1899
1900         dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1901
1902         chained_irq_enter(chip, desc);
1903
1904         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1905
1906         while (pend) {
1907                 unsigned int irq, virq;
1908
1909                 irq = __ffs(pend);
1910                 pend &= ~BIT(irq);
1911                 virq = irq_linear_revmap(bank->domain, irq);
1912
1913                 if (!virq) {
1914                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1915                         continue;
1916                 }
1917
1918                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1919
1920                 /*
1921                  * Triggering IRQ on both rising and falling edge
1922                  * needs manual intervention.
1923                  */
1924                 if (bank->toggle_edge_mode & BIT(irq)) {
1925                         u32 data, data_old, polarity;
1926                         unsigned long flags;
1927
1928                         data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1929                         do {
1930                                 spin_lock_irqsave(&bank->slock, flags);
1931
1932                                 polarity = readl_relaxed(bank->reg_base +
1933                                                          GPIO_INT_POLARITY);
1934                                 if (data & BIT(irq))
1935                                         polarity &= ~BIT(irq);
1936                                 else
1937                                         polarity |= BIT(irq);
1938                                 writel(polarity,
1939                                        bank->reg_base + GPIO_INT_POLARITY);
1940
1941                                 spin_unlock_irqrestore(&bank->slock, flags);
1942
1943                                 data_old = data;
1944                                 data = readl_relaxed(bank->reg_base +
1945                                                      GPIO_EXT_PORT);
1946                         } while ((data & BIT(irq)) != (data_old & BIT(irq)));
1947                 }
1948
1949                 generic_handle_irq(virq);
1950         }
1951
1952         chained_irq_exit(chip, desc);
1953 }
1954
1955 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1956 {
1957         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1958         struct rockchip_pin_bank *bank = gc->private;
1959         u32 mask = BIT(d->hwirq);
1960         u32 polarity;
1961         u32 level;
1962         u32 data;
1963         unsigned long flags;
1964         int ret;
1965
1966         /* make sure the pin is configured as gpio input */
1967         ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1968         if (ret < 0)
1969                 return ret;
1970
1971         clk_enable(bank->clk);
1972         spin_lock_irqsave(&bank->slock, flags);
1973
1974         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1975         data &= ~mask;
1976         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1977
1978         spin_unlock_irqrestore(&bank->slock, flags);
1979
1980         if (type & IRQ_TYPE_EDGE_BOTH)
1981                 irq_set_handler_locked(d, handle_edge_irq);
1982         else
1983                 irq_set_handler_locked(d, handle_level_irq);
1984
1985         spin_lock_irqsave(&bank->slock, flags);
1986         irq_gc_lock(gc);
1987
1988         level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1989         polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1990
1991         switch (type) {
1992         case IRQ_TYPE_EDGE_BOTH:
1993                 bank->toggle_edge_mode |= mask;
1994                 level |= mask;
1995
1996                 /*
1997                  * Determine gpio state. If 1 next interrupt should be falling
1998                  * otherwise rising.
1999                  */
2000                 data = readl(bank->reg_base + GPIO_EXT_PORT);
2001                 if (data & mask)
2002                         polarity &= ~mask;
2003                 else
2004                         polarity |= mask;
2005                 break;
2006         case IRQ_TYPE_EDGE_RISING:
2007                 bank->toggle_edge_mode &= ~mask;
2008                 level |= mask;
2009                 polarity |= mask;
2010                 break;
2011         case IRQ_TYPE_EDGE_FALLING:
2012                 bank->toggle_edge_mode &= ~mask;
2013                 level |= mask;
2014                 polarity &= ~mask;
2015                 break;
2016         case IRQ_TYPE_LEVEL_HIGH:
2017                 bank->toggle_edge_mode &= ~mask;
2018                 level &= ~mask;
2019                 polarity |= mask;
2020                 break;
2021         case IRQ_TYPE_LEVEL_LOW:
2022                 bank->toggle_edge_mode &= ~mask;
2023                 level &= ~mask;
2024                 polarity &= ~mask;
2025                 break;
2026         default:
2027                 irq_gc_unlock(gc);
2028                 spin_unlock_irqrestore(&bank->slock, flags);
2029                 clk_disable(bank->clk);
2030                 return -EINVAL;
2031         }
2032
2033         writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
2034         writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
2035
2036         irq_gc_unlock(gc);
2037         spin_unlock_irqrestore(&bank->slock, flags);
2038         clk_disable(bank->clk);
2039
2040         return 0;
2041 }
2042
2043 static void rockchip_irq_suspend(struct irq_data *d)
2044 {
2045         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2046         struct rockchip_pin_bank *bank = gc->private;
2047
2048         clk_enable(bank->clk);
2049         bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
2050         irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
2051         clk_disable(bank->clk);
2052 }
2053
2054 static void rockchip_irq_resume(struct irq_data *d)
2055 {
2056         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2057         struct rockchip_pin_bank *bank = gc->private;
2058
2059         clk_enable(bank->clk);
2060         irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
2061         clk_disable(bank->clk);
2062 }
2063
2064 static void rockchip_irq_gc_mask_clr_bit(struct irq_data *d)
2065 {
2066         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2067         struct rockchip_pin_bank *bank = gc->private;
2068
2069         clk_enable(bank->clk);
2070         irq_gc_mask_clr_bit(d);
2071 }
2072
2073 static void rockchip_irq_gc_mask_set_bit(struct irq_data *d)
2074 {
2075         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2076         struct rockchip_pin_bank *bank = gc->private;
2077
2078         irq_gc_mask_set_bit(d);
2079         clk_disable(bank->clk);
2080 }
2081
2082 static int rockchip_interrupts_register(struct platform_device *pdev,
2083                                                 struct rockchip_pinctrl *info)
2084 {
2085         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2086         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2087         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
2088         struct irq_chip_generic *gc;
2089         int ret;
2090         int i, j;
2091
2092         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2093                 if (!bank->valid) {
2094                         dev_warn(&pdev->dev, "bank %s is not valid\n",
2095                                  bank->name);
2096                         continue;
2097                 }
2098
2099                 ret = clk_enable(bank->clk);
2100                 if (ret) {
2101                         dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
2102                                 bank->name);
2103                         continue;
2104                 }
2105
2106                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
2107                                                 &irq_generic_chip_ops, NULL);
2108                 if (!bank->domain) {
2109                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
2110                                  bank->name);
2111                         clk_disable(bank->clk);
2112                         continue;
2113                 }
2114
2115                 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
2116                                          "rockchip_gpio_irq", handle_level_irq,
2117                                          clr, 0, IRQ_GC_INIT_MASK_CACHE);
2118                 if (ret) {
2119                         dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
2120                                 bank->name);
2121                         irq_domain_remove(bank->domain);
2122                         clk_disable(bank->clk);
2123                         continue;
2124                 }
2125
2126                 /*
2127                  * Linux assumes that all interrupts start out disabled/masked.
2128                  * Our driver only uses the concept of masked and always keeps
2129                  * things enabled, so for us that's all masked and all enabled.
2130                  */
2131                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
2132                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
2133
2134                 gc = irq_get_domain_generic_chip(bank->domain, 0);
2135                 gc->reg_base = bank->reg_base;
2136                 gc->private = bank;
2137                 gc->chip_types[0].regs.mask = GPIO_INTMASK;
2138                 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
2139                 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
2140                 gc->chip_types[0].chip.irq_mask = rockchip_irq_gc_mask_set_bit;
2141                 gc->chip_types[0].chip.irq_unmask =
2142                                                   rockchip_irq_gc_mask_clr_bit;
2143                 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
2144                 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
2145                 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
2146                 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
2147                 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
2148
2149                 irq_set_chained_handler_and_data(bank->irq,
2150                                                  rockchip_irq_demux, bank);
2151
2152                 /* map the gpio irqs here, when the clock is still running */
2153                 for (j = 0 ; j < 32 ; j++)
2154                         irq_create_mapping(bank->domain, j);
2155
2156                 clk_disable(bank->clk);
2157         }
2158
2159         return 0;
2160 }
2161
2162 static int rockchip_gpiolib_register(struct platform_device *pdev,
2163                                                 struct rockchip_pinctrl *info)
2164 {
2165         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2166         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2167         struct gpio_chip *gc;
2168         int ret;
2169         int i;
2170
2171         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2172                 if (!bank->valid) {
2173                         dev_warn(&pdev->dev, "bank %s is not valid\n",
2174                                  bank->name);
2175                         continue;
2176                 }
2177
2178                 bank->gpio_chip = rockchip_gpiolib_chip;
2179
2180                 gc = &bank->gpio_chip;
2181                 gc->base = bank->pin_base;
2182                 gc->ngpio = bank->nr_pins;
2183                 gc->parent = &pdev->dev;
2184                 gc->of_node = bank->of_node;
2185                 gc->label = bank->name;
2186
2187                 ret = gpiochip_add_data(gc, bank);
2188                 if (ret) {
2189                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
2190                                                         gc->label, ret);
2191                         goto fail;
2192                 }
2193         }
2194
2195         rockchip_interrupts_register(pdev, info);
2196
2197         return 0;
2198
2199 fail:
2200         for (--i, --bank; i >= 0; --i, --bank) {
2201                 if (!bank->valid)
2202                         continue;
2203                 gpiochip_remove(&bank->gpio_chip);
2204         }
2205         return ret;
2206 }
2207
2208 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
2209                                                 struct rockchip_pinctrl *info)
2210 {
2211         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2212         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2213         int i;
2214
2215         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2216                 if (!bank->valid)
2217                         continue;
2218                 gpiochip_remove(&bank->gpio_chip);
2219         }
2220
2221         return 0;
2222 }
2223
2224 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
2225                                   struct rockchip_pinctrl *info)
2226 {
2227         struct resource res;
2228         void __iomem *base;
2229
2230         if (of_address_to_resource(bank->of_node, 0, &res)) {
2231                 dev_err(info->dev, "cannot find IO resource for bank\n");
2232                 return -ENOENT;
2233         }
2234
2235         bank->reg_base = devm_ioremap_resource(info->dev, &res);
2236         if (IS_ERR(bank->reg_base))
2237                 return PTR_ERR(bank->reg_base);
2238
2239         /*
2240          * special case, where parts of the pull setting-registers are
2241          * part of the PMU register space
2242          */
2243         if (of_device_is_compatible(bank->of_node,
2244                                     "rockchip,rk3188-gpio-bank0")) {
2245                 struct device_node *node;
2246
2247                 node = of_parse_phandle(bank->of_node->parent,
2248                                         "rockchip,pmu", 0);
2249                 if (!node) {
2250                         if (of_address_to_resource(bank->of_node, 1, &res)) {
2251                                 dev_err(info->dev, "cannot find IO resource for bank\n");
2252                                 return -ENOENT;
2253                         }
2254
2255                         base = devm_ioremap_resource(info->dev, &res);
2256                         if (IS_ERR(base))
2257                                 return PTR_ERR(base);
2258                         rockchip_regmap_config.max_register =
2259                                                     resource_size(&res) - 4;
2260                         rockchip_regmap_config.name =
2261                                             "rockchip,rk3188-gpio-bank0-pull";
2262                         bank->regmap_pull = devm_regmap_init_mmio(info->dev,
2263                                                     base,
2264                                                     &rockchip_regmap_config);
2265                 }
2266         }
2267
2268         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
2269
2270         bank->clk = of_clk_get(bank->of_node, 0);
2271         if (IS_ERR(bank->clk))
2272                 return PTR_ERR(bank->clk);
2273
2274         return clk_prepare(bank->clk);
2275 }
2276
2277 static const struct of_device_id rockchip_pinctrl_dt_match[];
2278
2279 /* retrieve the soc specific data */
2280 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
2281                                                 struct rockchip_pinctrl *d,
2282                                                 struct platform_device *pdev)
2283 {
2284         const struct of_device_id *match;
2285         struct device_node *node = pdev->dev.of_node;
2286         struct device_node *np;
2287         struct rockchip_pin_ctrl *ctrl;
2288         struct rockchip_pin_bank *bank;
2289         int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
2290
2291         match = of_match_node(rockchip_pinctrl_dt_match, node);
2292         ctrl = (struct rockchip_pin_ctrl *)match->data;
2293
2294         for_each_child_of_node(node, np) {
2295                 if (!of_find_property(np, "gpio-controller", NULL))
2296                         continue;
2297
2298                 bank = ctrl->pin_banks;
2299                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2300                         if (!strcmp(bank->name, np->name)) {
2301                                 bank->of_node = np;
2302
2303                                 if (!rockchip_get_bank_data(bank, d))
2304                                         bank->valid = true;
2305
2306                                 break;
2307                         }
2308                 }
2309         }
2310
2311         grf_offs = ctrl->grf_mux_offset;
2312         pmu_offs = ctrl->pmu_mux_offset;
2313         drv_pmu_offs = ctrl->pmu_drv_offset;
2314         drv_grf_offs = ctrl->grf_drv_offset;
2315         bank = ctrl->pin_banks;
2316         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2317                 int bank_pins = 0;
2318
2319                 spin_lock_init(&bank->slock);
2320                 bank->drvdata = d;
2321                 bank->pin_base = ctrl->nr_pins;
2322                 ctrl->nr_pins += bank->nr_pins;
2323
2324                 /* calculate iomux and drv offsets */
2325                 for (j = 0; j < 4; j++) {
2326                         struct rockchip_iomux *iom = &bank->iomux[j];
2327                         struct rockchip_drv *drv = &bank->drv[j];
2328                         int inc;
2329
2330                         if (bank_pins >= bank->nr_pins)
2331                                 break;
2332
2333                         /* preset iomux offset value, set new start value */
2334                         if (iom->offset >= 0) {
2335                                 if (iom->type & IOMUX_SOURCE_PMU)
2336                                         pmu_offs = iom->offset;
2337                                 else
2338                                         grf_offs = iom->offset;
2339                         } else { /* set current iomux offset */
2340                                 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2341                                                         pmu_offs : grf_offs;
2342                         }
2343
2344                         /* preset drv offset value, set new start value */
2345                         if (drv->offset >= 0) {
2346                                 if (iom->type & IOMUX_SOURCE_PMU)
2347                                         drv_pmu_offs = drv->offset;
2348                                 else
2349                                         drv_grf_offs = drv->offset;
2350                         } else { /* set current drv offset */
2351                                 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2352                                                 drv_pmu_offs : drv_grf_offs;
2353                         }
2354
2355                         dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
2356                                 i, j, iom->offset, drv->offset);
2357
2358                         /*
2359                          * Increase offset according to iomux width.
2360                          * 4bit iomux'es are spread over two registers.
2361                          */
2362                         inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4;
2363                         if (iom->type & IOMUX_SOURCE_PMU)
2364                                 pmu_offs += inc;
2365                         else
2366                                 grf_offs += inc;
2367
2368                         /*
2369                          * Increase offset according to drv width.
2370                          * 3bit drive-strenth'es are spread over two registers.
2371                          */
2372                         if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2373                             (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
2374                                 inc = 8;
2375                         else
2376                                 inc = 4;
2377
2378                         if (iom->type & IOMUX_SOURCE_PMU)
2379                                 drv_pmu_offs += inc;
2380                         else
2381                                 drv_grf_offs += inc;
2382
2383                         bank_pins += 8;
2384                 }
2385         }
2386
2387         return ctrl;
2388 }
2389
2390 #define RK3288_GRF_GPIO6C_IOMUX         0x64
2391 #define GPIO6C6_SEL_WRITE_ENABLE        BIT(28)
2392
2393 static u32 rk3288_grf_gpio6c_iomux;
2394
2395 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
2396 {
2397         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2398         int ret = pinctrl_force_sleep(info->pctl_dev);
2399
2400         if (ret)
2401                 return ret;
2402
2403         /*
2404          * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
2405          * the setting here, and restore it at resume.
2406          */
2407         if (info->ctrl->type == RK3288) {
2408                 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2409                                   &rk3288_grf_gpio6c_iomux);
2410                 if (ret) {
2411                         pinctrl_force_default(info->pctl_dev);
2412                         return ret;
2413                 }
2414         }
2415
2416         return 0;
2417 }
2418
2419 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
2420 {
2421         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2422         int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2423                                rk3288_grf_gpio6c_iomux |
2424                                GPIO6C6_SEL_WRITE_ENABLE);
2425
2426         if (ret)
2427                 return ret;
2428
2429         return pinctrl_force_default(info->pctl_dev);
2430 }
2431
2432 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
2433                          rockchip_pinctrl_resume);
2434
2435 static int rockchip_pinctrl_probe(struct platform_device *pdev)
2436 {
2437         struct rockchip_pinctrl *info;
2438         struct device *dev = &pdev->dev;
2439         struct rockchip_pin_ctrl *ctrl;
2440         struct device_node *np = pdev->dev.of_node, *node;
2441         struct resource *res;
2442         void __iomem *base;
2443         int ret;
2444
2445         if (!dev->of_node) {
2446                 dev_err(dev, "device tree node not found\n");
2447                 return -ENODEV;
2448         }
2449
2450         info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
2451         if (!info)
2452                 return -ENOMEM;
2453
2454         info->dev = dev;
2455
2456         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2457         if (!ctrl) {
2458                 dev_err(dev, "driver data not available\n");
2459                 return -EINVAL;
2460         }
2461         info->ctrl = ctrl;
2462
2463         node = of_parse_phandle(np, "rockchip,grf", 0);
2464         if (node) {
2465                 info->regmap_base = syscon_node_to_regmap(node);
2466                 if (IS_ERR(info->regmap_base))
2467                         return PTR_ERR(info->regmap_base);
2468         } else {
2469                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2470                 base = devm_ioremap_resource(&pdev->dev, res);
2471                 if (IS_ERR(base))
2472                         return PTR_ERR(base);
2473
2474                 rockchip_regmap_config.max_register = resource_size(res) - 4;
2475                 rockchip_regmap_config.name = "rockchip,pinctrl";
2476                 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
2477                                                     &rockchip_regmap_config);
2478
2479                 /* to check for the old dt-bindings */
2480                 info->reg_size = resource_size(res);
2481
2482                 /* Honor the old binding, with pull registers as 2nd resource */
2483                 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
2484                         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2485                         base = devm_ioremap_resource(&pdev->dev, res);
2486                         if (IS_ERR(base))
2487                                 return PTR_ERR(base);
2488
2489                         rockchip_regmap_config.max_register =
2490                                                         resource_size(res) - 4;
2491                         rockchip_regmap_config.name = "rockchip,pinctrl-pull";
2492                         info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
2493                                                     base,
2494                                                     &rockchip_regmap_config);
2495                 }
2496         }
2497
2498         /* try to find the optional reference to the pmu syscon */
2499         node = of_parse_phandle(np, "rockchip,pmu", 0);
2500         if (node) {
2501                 info->regmap_pmu = syscon_node_to_regmap(node);
2502                 if (IS_ERR(info->regmap_pmu))
2503                         return PTR_ERR(info->regmap_pmu);
2504         }
2505
2506         ret = rockchip_gpiolib_register(pdev, info);
2507         if (ret)
2508                 return ret;
2509
2510         ret = rockchip_pinctrl_register(pdev, info);
2511         if (ret) {
2512                 rockchip_gpiolib_unregister(pdev, info);
2513                 return ret;
2514         }
2515
2516         platform_set_drvdata(pdev, info);
2517
2518         return 0;
2519 }
2520
2521 static struct rockchip_pin_bank rk1108_pin_banks[] = {
2522         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2523                                              IOMUX_SOURCE_PMU,
2524                                              IOMUX_SOURCE_PMU,
2525                                              IOMUX_SOURCE_PMU),
2526         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
2527         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
2528         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
2529 };
2530
2531 static struct rockchip_pin_ctrl rk1108_pin_ctrl = {
2532         .pin_banks              = rk1108_pin_banks,
2533         .nr_banks               = ARRAY_SIZE(rk1108_pin_banks),
2534         .label                  = "RK1108-GPIO",
2535         .type                   = RK1108,
2536         .grf_mux_offset         = 0x10,
2537         .pmu_mux_offset         = 0x0,
2538         .pull_calc_reg          = rk1108_calc_pull_reg_and_bit,
2539         .drv_calc_reg           = rk1108_calc_drv_reg_and_bit,
2540 };
2541
2542 static struct rockchip_pin_bank rk2928_pin_banks[] = {
2543         PIN_BANK(0, 32, "gpio0"),
2544         PIN_BANK(1, 32, "gpio1"),
2545         PIN_BANK(2, 32, "gpio2"),
2546         PIN_BANK(3, 32, "gpio3"),
2547 };
2548
2549 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2550                 .pin_banks              = rk2928_pin_banks,
2551                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
2552                 .label                  = "RK2928-GPIO",
2553                 .type                   = RK2928,
2554                 .grf_mux_offset         = 0xa8,
2555                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2556 };
2557
2558 static struct rockchip_pin_bank rk3036_pin_banks[] = {
2559         PIN_BANK(0, 32, "gpio0"),
2560         PIN_BANK(1, 32, "gpio1"),
2561         PIN_BANK(2, 32, "gpio2"),
2562 };
2563
2564 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
2565                 .pin_banks              = rk3036_pin_banks,
2566                 .nr_banks               = ARRAY_SIZE(rk3036_pin_banks),
2567                 .label                  = "RK3036-GPIO",
2568                 .type                   = RK2928,
2569                 .grf_mux_offset         = 0xa8,
2570                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2571 };
2572
2573 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
2574         PIN_BANK(0, 32, "gpio0"),
2575         PIN_BANK(1, 32, "gpio1"),
2576         PIN_BANK(2, 32, "gpio2"),
2577         PIN_BANK(3, 32, "gpio3"),
2578         PIN_BANK(4, 32, "gpio4"),
2579         PIN_BANK(6, 16, "gpio6"),
2580 };
2581
2582 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
2583                 .pin_banks              = rk3066a_pin_banks,
2584                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
2585                 .label                  = "RK3066a-GPIO",
2586                 .type                   = RK2928,
2587                 .grf_mux_offset         = 0xa8,
2588                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2589 };
2590
2591 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
2592         PIN_BANK(0, 32, "gpio0"),
2593         PIN_BANK(1, 32, "gpio1"),
2594         PIN_BANK(2, 32, "gpio2"),
2595         PIN_BANK(3, 32, "gpio3"),
2596 };
2597
2598 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2599                 .pin_banks      = rk3066b_pin_banks,
2600                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
2601                 .label          = "RK3066b-GPIO",
2602                 .type           = RK3066B,
2603                 .grf_mux_offset = 0x60,
2604 };
2605
2606 static struct rockchip_pin_bank rk3188_pin_banks[] = {
2607         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
2608         PIN_BANK(1, 32, "gpio1"),
2609         PIN_BANK(2, 32, "gpio2"),
2610         PIN_BANK(3, 32, "gpio3"),
2611 };
2612
2613 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
2614                 .pin_banks              = rk3188_pin_banks,
2615                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
2616                 .label                  = "RK3188-GPIO",
2617                 .type                   = RK3188,
2618                 .grf_mux_offset         = 0x60,
2619                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
2620 };
2621
2622 static struct rockchip_pin_bank rk3228_pin_banks[] = {
2623         PIN_BANK(0, 32, "gpio0"),
2624         PIN_BANK(1, 32, "gpio1"),
2625         PIN_BANK(2, 32, "gpio2"),
2626         PIN_BANK(3, 32, "gpio3"),
2627 };
2628
2629 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
2630                 .pin_banks              = rk3228_pin_banks,
2631                 .nr_banks               = ARRAY_SIZE(rk3228_pin_banks),
2632                 .label                  = "RK3228-GPIO",
2633                 .type                   = RK3288,
2634                 .grf_mux_offset         = 0x0,
2635                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
2636                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
2637 };
2638
2639 static struct rockchip_pin_bank rk3288_pin_banks[] = {
2640         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
2641                                              IOMUX_SOURCE_PMU,
2642                                              IOMUX_SOURCE_PMU,
2643                                              IOMUX_UNROUTED
2644                             ),
2645         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
2646                                              IOMUX_UNROUTED,
2647                                              IOMUX_UNROUTED,
2648                                              0
2649                             ),
2650         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
2651         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
2652         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
2653                                              IOMUX_WIDTH_4BIT,
2654                                              0,
2655                                              0
2656                             ),
2657         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
2658                                              0,
2659                                              0,
2660                                              IOMUX_UNROUTED
2661                             ),
2662         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
2663         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
2664                                              0,
2665                                              IOMUX_WIDTH_4BIT,
2666                                              IOMUX_UNROUTED
2667                             ),
2668         PIN_BANK(8, 16, "gpio8"),
2669 };
2670
2671 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
2672                 .pin_banks              = rk3288_pin_banks,
2673                 .nr_banks               = ARRAY_SIZE(rk3288_pin_banks),
2674                 .label                  = "RK3288-GPIO",
2675                 .type                   = RK3288,
2676                 .grf_mux_offset         = 0x0,
2677                 .pmu_mux_offset         = 0x84,
2678                 .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
2679                 .drv_calc_reg           = rk3288_calc_drv_reg_and_bit,
2680 };
2681
2682 static struct rockchip_pin_bank rk3368_pin_banks[] = {
2683         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2684                                              IOMUX_SOURCE_PMU,
2685                                              IOMUX_SOURCE_PMU,
2686                                              IOMUX_SOURCE_PMU
2687                             ),
2688         PIN_BANK(1, 32, "gpio1"),
2689         PIN_BANK(2, 32, "gpio2"),
2690         PIN_BANK(3, 32, "gpio3"),
2691 };
2692
2693 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
2694                 .pin_banks              = rk3368_pin_banks,
2695                 .nr_banks               = ARRAY_SIZE(rk3368_pin_banks),
2696                 .label                  = "RK3368-GPIO",
2697                 .type                   = RK3368,
2698                 .grf_mux_offset         = 0x0,
2699                 .pmu_mux_offset         = 0x0,
2700                 .pull_calc_reg          = rk3368_calc_pull_reg_and_bit,
2701                 .drv_calc_reg           = rk3368_calc_drv_reg_and_bit,
2702 };
2703
2704 static struct rockchip_pin_bank rk3399_pin_banks[] = {
2705         PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
2706                                                          IOMUX_SOURCE_PMU,
2707                                                          IOMUX_SOURCE_PMU,
2708                                                          IOMUX_SOURCE_PMU,
2709                                                          IOMUX_SOURCE_PMU,
2710                                                          DRV_TYPE_IO_1V8_ONLY,
2711                                                          DRV_TYPE_IO_1V8_ONLY,
2712                                                          DRV_TYPE_IO_DEFAULT,
2713                                                          DRV_TYPE_IO_DEFAULT,
2714                                                          0x0,
2715                                                          0x8,
2716                                                          -1,
2717                                                          -1,
2718                                                          PULL_TYPE_IO_1V8_ONLY,
2719                                                          PULL_TYPE_IO_1V8_ONLY,
2720                                                          PULL_TYPE_IO_DEFAULT,
2721                                                          PULL_TYPE_IO_DEFAULT
2722                                                         ),
2723         PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
2724                                         IOMUX_SOURCE_PMU,
2725                                         IOMUX_SOURCE_PMU,
2726                                         IOMUX_SOURCE_PMU,
2727                                         DRV_TYPE_IO_1V8_OR_3V0,
2728                                         DRV_TYPE_IO_1V8_OR_3V0,
2729                                         DRV_TYPE_IO_1V8_OR_3V0,
2730                                         DRV_TYPE_IO_1V8_OR_3V0,
2731                                         0x20,
2732                                         0x28,
2733                                         0x30,
2734                                         0x38
2735                                         ),
2736         PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
2737                                       DRV_TYPE_IO_1V8_OR_3V0,
2738                                       DRV_TYPE_IO_1V8_ONLY,
2739                                       DRV_TYPE_IO_1V8_ONLY,
2740                                       PULL_TYPE_IO_DEFAULT,
2741                                       PULL_TYPE_IO_DEFAULT,
2742                                       PULL_TYPE_IO_1V8_ONLY,
2743                                       PULL_TYPE_IO_1V8_ONLY
2744                                       ),
2745         PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
2746                            DRV_TYPE_IO_3V3_ONLY,
2747                            DRV_TYPE_IO_3V3_ONLY,
2748                            DRV_TYPE_IO_1V8_OR_3V0
2749                            ),
2750         PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
2751                            DRV_TYPE_IO_1V8_3V0_AUTO,
2752                            DRV_TYPE_IO_1V8_OR_3V0,
2753                            DRV_TYPE_IO_1V8_OR_3V0
2754                            ),
2755 };
2756
2757 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
2758                 .pin_banks              = rk3399_pin_banks,
2759                 .nr_banks               = ARRAY_SIZE(rk3399_pin_banks),
2760                 .label                  = "RK3399-GPIO",
2761                 .type                   = RK3399,
2762                 .grf_mux_offset         = 0xe000,
2763                 .pmu_mux_offset         = 0x0,
2764                 .grf_drv_offset         = 0xe100,
2765                 .pmu_drv_offset         = 0x80,
2766                 .pull_calc_reg          = rk3399_calc_pull_reg_and_bit,
2767                 .drv_calc_reg           = rk3399_calc_drv_reg_and_bit,
2768 };
2769
2770 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
2771         { .compatible = "rockchip,rk1108-pinctrl",
2772                 .data = (void *)&rk1108_pin_ctrl },
2773         { .compatible = "rockchip,rk2928-pinctrl",
2774                 .data = (void *)&rk2928_pin_ctrl },
2775         { .compatible = "rockchip,rk3036-pinctrl",
2776                 .data = (void *)&rk3036_pin_ctrl },
2777         { .compatible = "rockchip,rk3066a-pinctrl",
2778                 .data = (void *)&rk3066a_pin_ctrl },
2779         { .compatible = "rockchip,rk3066b-pinctrl",
2780                 .data = (void *)&rk3066b_pin_ctrl },
2781         { .compatible = "rockchip,rk3188-pinctrl",
2782                 .data = (void *)&rk3188_pin_ctrl },
2783         { .compatible = "rockchip,rk3228-pinctrl",
2784                 .data = (void *)&rk3228_pin_ctrl },
2785         { .compatible = "rockchip,rk3288-pinctrl",
2786                 .data = (void *)&rk3288_pin_ctrl },
2787         { .compatible = "rockchip,rk3368-pinctrl",
2788                 .data = (void *)&rk3368_pin_ctrl },
2789         { .compatible = "rockchip,rk3399-pinctrl",
2790                 .data = (void *)&rk3399_pin_ctrl },
2791         {},
2792 };
2793
2794 static struct platform_driver rockchip_pinctrl_driver = {
2795         .probe          = rockchip_pinctrl_probe,
2796         .driver = {
2797                 .name   = "rockchip-pinctrl",
2798                 .pm = &rockchip_pinctrl_dev_pm_ops,
2799                 .of_match_table = rockchip_pinctrl_dt_match,
2800         },
2801 };
2802
2803 static int __init rockchip_pinctrl_drv_register(void)
2804 {
2805         return platform_driver_register(&rockchip_pinctrl_driver);
2806 }
2807 postcore_initcall(rockchip_pinctrl_drv_register);