2 * Pinctrl driver for Rockchip SoCs
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
26 #include <linux/init.h>
27 #include <linux/platform_device.h>
29 #include <linux/bitops.h>
30 #include <linux/gpio/driver.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/pinctrl/machine.h>
34 #include <linux/pinctrl/pinconf.h>
35 #include <linux/pinctrl/pinctrl.h>
36 #include <linux/pinctrl/pinmux.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38 #include <linux/irqchip/chained_irq.h>
39 #include <linux/clk.h>
40 #include <linux/regmap.h>
41 #include <linux/mfd/syscon.h>
42 #include <dt-bindings/pinctrl/rockchip.h>
47 /* GPIO control registers */
48 #define GPIO_SWPORT_DR 0x00
49 #define GPIO_SWPORT_DDR 0x04
50 #define GPIO_INTEN 0x30
51 #define GPIO_INTMASK 0x34
52 #define GPIO_INTTYPE_LEVEL 0x38
53 #define GPIO_INT_POLARITY 0x3c
54 #define GPIO_INT_STATUS 0x40
55 #define GPIO_INT_RAWSTATUS 0x44
56 #define GPIO_DEBOUNCE 0x48
57 #define GPIO_PORTS_EOI 0x4c
58 #define GPIO_EXT_PORT 0x50
59 #define GPIO_LS_SYNC 0x60
61 enum rockchip_pinctrl_type {
74 * Encode variants of iomux registers into a type variable
76 #define IOMUX_GPIO_ONLY BIT(0)
77 #define IOMUX_WIDTH_4BIT BIT(1)
78 #define IOMUX_SOURCE_PMU BIT(2)
79 #define IOMUX_UNROUTED BIT(3)
80 #define IOMUX_WIDTH_3BIT BIT(4)
83 * @type: iomux variant using IOMUX_* constants
84 * @offset: if initialized to -1 it will be autocalculated, by specifying
85 * an initial offset value the relevant source offset can be reset
86 * to a new value for autocalculating the following iomux registers.
88 struct rockchip_iomux {
94 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
96 enum rockchip_pin_drv_type {
97 DRV_TYPE_IO_DEFAULT = 0,
98 DRV_TYPE_IO_1V8_OR_3V0,
100 DRV_TYPE_IO_1V8_3V0_AUTO,
101 DRV_TYPE_IO_3V3_ONLY,
106 * enum type index corresponding to rockchip_pull_list arrays index.
108 enum rockchip_pin_pull_type {
109 PULL_TYPE_IO_DEFAULT = 0,
110 PULL_TYPE_IO_1V8_ONLY,
115 * @drv_type: drive strength variant using rockchip_perpin_drv_type
116 * @offset: if initialized to -1 it will be autocalculated, by specifying
117 * an initial offset value the relevant source offset can be reset
118 * to a new value for autocalculating the following drive strength
119 * registers. if used chips own cal_drv func instead to calculate
120 * registers offset, the variant could be ignored.
122 struct rockchip_drv {
123 enum rockchip_pin_drv_type drv_type;
128 * @reg_base: register base of the gpio bank
129 * @reg_pull: optional separate register for additional pull settings
130 * @clk: clock of the gpio bank
131 * @irq: interrupt of the gpio bank
132 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
133 * @pin_base: first pin number
134 * @nr_pins: number of pins in this bank
135 * @name: name of the bank
136 * @bank_num: number of the bank, to account for holes
137 * @iomux: array describing the 4 iomux sources of the bank
138 * @drv: array describing the 4 drive strength sources of the bank
139 * @pull_type: array describing the 4 pull type sources of the bank
140 * @valid: is all necessary information present
141 * @of_node: dt node of this bank
142 * @drvdata: common pinctrl basedata
143 * @domain: irqdomain of the gpio bank
144 * @gpio_chip: gpiolib chip
145 * @grange: gpio range
146 * @slock: spinlock for the gpio bank
147 * @route_mask: bits describing the routing pins of per bank
149 struct rockchip_pin_bank {
150 void __iomem *reg_base;
151 struct regmap *regmap_pull;
159 struct rockchip_iomux iomux[4];
160 struct rockchip_drv drv[4];
161 enum rockchip_pin_pull_type pull_type[4];
163 struct device_node *of_node;
164 struct rockchip_pinctrl *drvdata;
165 struct irq_domain *domain;
166 struct gpio_chip gpio_chip;
167 struct pinctrl_gpio_range grange;
168 raw_spinlock_t slock;
169 u32 toggle_edge_mode;
174 #define PIN_BANK(id, pins, label) \
187 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
193 { .type = iom0, .offset = -1 }, \
194 { .type = iom1, .offset = -1 }, \
195 { .type = iom2, .offset = -1 }, \
196 { .type = iom3, .offset = -1 }, \
200 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
212 { .drv_type = type0, .offset = -1 }, \
213 { .drv_type = type1, .offset = -1 }, \
214 { .drv_type = type2, .offset = -1 }, \
215 { .drv_type = type3, .offset = -1 }, \
219 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
220 drv2, drv3, pull0, pull1, \
233 { .drv_type = drv0, .offset = -1 }, \
234 { .drv_type = drv1, .offset = -1 }, \
235 { .drv_type = drv2, .offset = -1 }, \
236 { .drv_type = drv3, .offset = -1 }, \
238 .pull_type[0] = pull0, \
239 .pull_type[1] = pull1, \
240 .pull_type[2] = pull2, \
241 .pull_type[3] = pull3, \
244 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
245 iom2, iom3, drv0, drv1, drv2, \
246 drv3, offset0, offset1, \
253 { .type = iom0, .offset = -1 }, \
254 { .type = iom1, .offset = -1 }, \
255 { .type = iom2, .offset = -1 }, \
256 { .type = iom3, .offset = -1 }, \
259 { .drv_type = drv0, .offset = offset0 }, \
260 { .drv_type = drv1, .offset = offset1 }, \
261 { .drv_type = drv2, .offset = offset2 }, \
262 { .drv_type = drv3, .offset = offset3 }, \
266 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
267 label, iom0, iom1, iom2, \
268 iom3, drv0, drv1, drv2, \
269 drv3, offset0, offset1, \
270 offset2, offset3, pull0, \
271 pull1, pull2, pull3) \
277 { .type = iom0, .offset = -1 }, \
278 { .type = iom1, .offset = -1 }, \
279 { .type = iom2, .offset = -1 }, \
280 { .type = iom3, .offset = -1 }, \
283 { .drv_type = drv0, .offset = offset0 }, \
284 { .drv_type = drv1, .offset = offset1 }, \
285 { .drv_type = drv2, .offset = offset2 }, \
286 { .drv_type = drv3, .offset = offset3 }, \
288 .pull_type[0] = pull0, \
289 .pull_type[1] = pull1, \
290 .pull_type[2] = pull2, \
291 .pull_type[3] = pull3, \
295 * struct rockchip_mux_recalced_data: represent a pin iomux data.
298 * @bit: index at register.
299 * @reg: register offset.
302 struct rockchip_mux_recalced_data {
310 enum rockchip_mux_route_location {
311 ROCKCHIP_ROUTE_SAME = 0,
317 * struct rockchip_mux_recalced_data: represent a pin iomux data.
318 * @bank_num: bank number.
319 * @pin: index at register or used to calc index.
320 * @func: the min pin.
321 * @route_offset: the max pin.
322 * @route_val: the register offset.
324 struct rockchip_mux_route_data {
328 enum rockchip_mux_route_location route_location;
335 struct rockchip_pin_ctrl {
336 struct rockchip_pin_bank *pin_banks;
340 enum rockchip_pinctrl_type type;
345 struct rockchip_mux_recalced_data *iomux_recalced;
347 struct rockchip_mux_route_data *iomux_routes;
350 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
351 int pin_num, struct regmap **regmap,
353 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
354 int pin_num, struct regmap **regmap,
356 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
357 int pin_num, struct regmap **regmap,
361 struct rockchip_pin_config {
363 unsigned long *configs;
364 unsigned int nconfigs;
368 * struct rockchip_pin_group: represent group of pins of a pinmux function.
369 * @name: name of the pin group, used to lookup the group.
370 * @pins: the pins included in this group.
371 * @npins: number of pins included in this group.
372 * @func: the mux function number to be programmed when selected.
373 * @configs: the config values to be set for each pin
374 * @nconfigs: number of configs for each pin
376 struct rockchip_pin_group {
380 struct rockchip_pin_config *data;
384 * struct rockchip_pmx_func: represent a pin function.
385 * @name: name of the pin function, used to lookup the function.
386 * @groups: one or more names of pin groups that provide this function.
387 * @num_groups: number of groups included in @groups.
389 struct rockchip_pmx_func {
395 struct rockchip_pinctrl {
396 struct regmap *regmap_base;
398 struct regmap *regmap_pull;
399 struct regmap *regmap_pmu;
401 struct rockchip_pin_ctrl *ctrl;
402 struct pinctrl_desc pctl;
403 struct pinctrl_dev *pctl_dev;
404 struct rockchip_pin_group *groups;
405 unsigned int ngroups;
406 struct rockchip_pmx_func *functions;
407 unsigned int nfunctions;
410 static struct regmap_config rockchip_regmap_config = {
416 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
417 const struct rockchip_pinctrl *info,
422 for (i = 0; i < info->ngroups; i++) {
423 if (!strcmp(info->groups[i].name, name))
424 return &info->groups[i];
431 * given a pin number that is local to a pin controller, find out the pin bank
432 * and the register base of the pin bank.
434 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
437 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
439 while (pin >= (b->pin_base + b->nr_pins))
445 static struct rockchip_pin_bank *bank_num_to_bank(
446 struct rockchip_pinctrl *info,
449 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
452 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
453 if (b->bank_num == num)
457 return ERR_PTR(-EINVAL);
461 * Pinctrl_ops handling
464 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
466 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
468 return info->ngroups;
471 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
474 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
476 return info->groups[selector].name;
479 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
480 unsigned selector, const unsigned **pins,
483 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
485 if (selector >= info->ngroups)
488 *pins = info->groups[selector].pins;
489 *npins = info->groups[selector].npins;
494 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
495 struct device_node *np,
496 struct pinctrl_map **map, unsigned *num_maps)
498 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
499 const struct rockchip_pin_group *grp;
500 struct pinctrl_map *new_map;
501 struct device_node *parent;
506 * first find the group of this node and check if we need to create
507 * config maps for pins
509 grp = pinctrl_name_to_group(info, np->name);
511 dev_err(info->dev, "unable to find group for node %pOFn\n",
516 map_num += grp->npins;
517 new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map),
526 parent = of_get_parent(np);
528 devm_kfree(pctldev->dev, new_map);
531 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
532 new_map[0].data.mux.function = parent->name;
533 new_map[0].data.mux.group = np->name;
536 /* create config map */
538 for (i = 0; i < grp->npins; i++) {
539 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
540 new_map[i].data.configs.group_or_pin =
541 pin_get_name(pctldev, grp->pins[i]);
542 new_map[i].data.configs.configs = grp->data[i].configs;
543 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
546 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
547 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
552 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
553 struct pinctrl_map *map, unsigned num_maps)
557 static const struct pinctrl_ops rockchip_pctrl_ops = {
558 .get_groups_count = rockchip_get_groups_count,
559 .get_group_name = rockchip_get_group_name,
560 .get_group_pins = rockchip_get_group_pins,
561 .dt_node_to_map = rockchip_dt_node_to_map,
562 .dt_free_map = rockchip_dt_free_map,
569 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
633 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
667 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
689 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
690 int *reg, u8 *bit, int *mask)
692 struct rockchip_pinctrl *info = bank->drvdata;
693 struct rockchip_pin_ctrl *ctrl = info->ctrl;
694 struct rockchip_mux_recalced_data *data;
697 for (i = 0; i < ctrl->niomux_recalced; i++) {
698 data = &ctrl->iomux_recalced[i];
699 if (data->num == bank->bank_num &&
704 if (i >= ctrl->niomux_recalced)
712 static struct rockchip_mux_route_data px30_mux_route_data[] = {
718 .route_offset = 0x184,
719 .route_val = BIT(16 + 7),
725 .route_offset = 0x184,
726 .route_val = BIT(16 + 7) | BIT(7),
732 .route_offset = 0x184,
733 .route_val = BIT(16 + 8),
739 .route_offset = 0x184,
740 .route_val = BIT(16 + 8) | BIT(8),
746 .route_offset = 0x184,
747 .route_val = BIT(16 + 10),
753 .route_offset = 0x184,
754 .route_val = BIT(16 + 10) | BIT(10),
760 .route_offset = 0x184,
761 .route_val = BIT(16 + 9),
767 .route_offset = 0x184,
768 .route_val = BIT(16 + 9) | BIT(9),
772 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
778 .route_offset = 0x144,
779 .route_val = BIT(16 + 3) | BIT(16 + 4),
785 .route_offset = 0x144,
786 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
792 .route_offset = 0x144,
793 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
799 .route_offset = 0x144,
800 .route_val = BIT(16 + 5),
806 .route_offset = 0x144,
807 .route_val = BIT(16 + 5) | BIT(5),
813 .route_offset = 0x144,
814 .route_val = BIT(16 + 6),
820 .route_offset = 0x144,
821 .route_val = BIT(16 + 6) | BIT(6),
825 static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
827 /* non-iomuxed emmc/flash pins on flash-dqs */
831 .route_location = ROCKCHIP_ROUTE_GRF,
832 .route_offset = 0xa0,
833 .route_val = BIT(16 + 11),
835 /* non-iomuxed emmc/flash pins on emmc-clk */
839 .route_location = ROCKCHIP_ROUTE_GRF,
840 .route_offset = 0xa0,
841 .route_val = BIT(16 + 11) | BIT(11),
845 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
851 .route_offset = 0x50,
852 .route_val = BIT(16),
858 .route_offset = 0x50,
859 .route_val = BIT(16) | BIT(0),
865 .route_offset = 0x50,
866 .route_val = BIT(16 + 1),
872 .route_offset = 0x50,
873 .route_val = BIT(16 + 1) | BIT(1),
879 .route_offset = 0x50,
880 .route_val = BIT(16 + 2),
886 .route_offset = 0x50,
887 .route_val = BIT(16 + 2) | BIT(2),
893 .route_offset = 0x50,
894 .route_val = BIT(16 + 3),
900 .route_offset = 0x50,
901 .route_val = BIT(16 + 3) | BIT(3),
907 .route_offset = 0x50,
908 .route_val = BIT(16 + 4),
914 .route_offset = 0x50,
915 .route_val = BIT(16 + 4) | BIT(4),
921 .route_offset = 0x50,
922 .route_val = BIT(16 + 5),
928 .route_offset = 0x50,
929 .route_val = BIT(16 + 5) | BIT(5),
935 .route_offset = 0x50,
936 .route_val = BIT(16 + 7),
942 .route_offset = 0x50,
943 .route_val = BIT(16 + 7) | BIT(7),
949 .route_offset = 0x50,
950 .route_val = BIT(16 + 8),
956 .route_offset = 0x50,
957 .route_val = BIT(16 + 8) | BIT(8),
963 .route_offset = 0x50,
964 .route_val = BIT(16 + 11),
970 .route_offset = 0x50,
971 .route_val = BIT(16 + 11) | BIT(11),
975 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
977 /* edphdmi_cecinoutt1 */
981 .route_offset = 0x264,
982 .route_val = BIT(16 + 12) | BIT(12),
984 /* edphdmi_cecinout */
988 .route_offset = 0x264,
989 .route_val = BIT(16 + 12),
993 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
999 .route_offset = 0x50,
1000 .route_val = BIT(16) | BIT(16 + 1),
1006 .route_offset = 0x50,
1007 .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
1013 .route_offset = 0x50,
1014 .route_val = BIT(16 + 2) | BIT(2),
1016 /* gmac-m1-optimized_rxd3 */
1020 .route_offset = 0x50,
1021 .route_val = BIT(16 + 10) | BIT(10),
1027 .route_offset = 0x50,
1028 .route_val = BIT(16 + 3),
1034 .route_offset = 0x50,
1035 .route_val = BIT(16 + 3) | BIT(3),
1041 .route_offset = 0x50,
1042 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5),
1048 .route_offset = 0x50,
1049 .route_val = BIT(16 + 6),
1055 .route_offset = 0x50,
1056 .route_val = BIT(16 + 6) | BIT(6),
1062 .route_offset = 0x50,
1063 .route_val = BIT(16 + 7) | BIT(7),
1069 .route_offset = 0x50,
1070 .route_val = BIT(16 + 8) | BIT(8),
1076 .route_offset = 0x50,
1077 .route_val = BIT(16 + 9) | BIT(9),
1081 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
1087 .route_offset = 0xe21c,
1088 .route_val = BIT(16 + 10) | BIT(16 + 11),
1094 .route_offset = 0xe21c,
1095 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
1101 .route_offset = 0xe21c,
1102 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
1108 .route_offset = 0xe21c,
1109 .route_val = BIT(16 + 14),
1115 .route_offset = 0xe21c,
1116 .route_val = BIT(16 + 14) | BIT(14),
1120 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1121 int mux, u32 *loc, u32 *reg, u32 *value)
1123 struct rockchip_pinctrl *info = bank->drvdata;
1124 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1125 struct rockchip_mux_route_data *data;
1128 for (i = 0; i < ctrl->niomux_routes; i++) {
1129 data = &ctrl->iomux_routes[i];
1130 if ((data->bank_num == bank->bank_num) &&
1131 (data->pin == pin) && (data->func == mux))
1135 if (i >= ctrl->niomux_routes)
1138 *loc = data->route_location;
1139 *reg = data->route_offset;
1140 *value = data->route_val;
1145 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1147 struct rockchip_pinctrl *info = bank->drvdata;
1148 int iomux_num = (pin / 8);
1149 struct regmap *regmap;
1151 int reg, ret, mask, mux_type;
1157 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1158 dev_err(info->dev, "pin %d is unrouted\n", pin);
1162 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1163 return RK_FUNC_GPIO;
1165 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1166 ? info->regmap_pmu : info->regmap_base;
1168 /* get basic quadrupel of mux registers and the correct reg inside */
1169 mux_type = bank->iomux[iomux_num].type;
1170 reg = bank->iomux[iomux_num].offset;
1171 if (mux_type & IOMUX_WIDTH_4BIT) {
1174 bit = (pin % 4) * 4;
1176 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1179 bit = (pin % 8 % 5) * 3;
1182 bit = (pin % 8) * 2;
1186 if (bank->recalced_mask & BIT(pin))
1187 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1189 ret = regmap_read(regmap, reg, &val);
1193 return ((val >> bit) & mask);
1196 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1199 struct rockchip_pinctrl *info = bank->drvdata;
1200 int iomux_num = (pin / 8);
1205 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1206 dev_err(info->dev, "pin %d is unrouted\n", pin);
1210 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1211 if (mux != RK_FUNC_GPIO) {
1213 "pin %d only supports a gpio mux\n", pin);
1222 * Set a new mux function for a pin.
1224 * The register is divided into the upper and lower 16 bit. When changing
1225 * a value, the previous register value is not read and changed. Instead
1226 * it seems the changed bits are marked in the upper 16 bit, while the
1227 * changed value gets set in the same offset in the lower 16 bit.
1228 * All pin settings seem to be 2 bit wide in both the upper and lower
1230 * @bank: pin bank to change
1231 * @pin: pin to change
1232 * @mux: new mux function to set
1234 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1236 struct rockchip_pinctrl *info = bank->drvdata;
1237 int iomux_num = (pin / 8);
1238 struct regmap *regmap;
1239 int reg, ret, mask, mux_type;
1241 u32 data, rmask, route_location, route_reg, route_val;
1243 ret = rockchip_verify_mux(bank, pin, mux);
1247 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1250 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
1251 bank->bank_num, pin, mux);
1253 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1254 ? info->regmap_pmu : info->regmap_base;
1256 /* get basic quadrupel of mux registers and the correct reg inside */
1257 mux_type = bank->iomux[iomux_num].type;
1258 reg = bank->iomux[iomux_num].offset;
1259 if (mux_type & IOMUX_WIDTH_4BIT) {
1262 bit = (pin % 4) * 4;
1264 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1267 bit = (pin % 8 % 5) * 3;
1270 bit = (pin % 8) * 2;
1274 if (bank->recalced_mask & BIT(pin))
1275 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1277 if (bank->route_mask & BIT(pin)) {
1278 if (rockchip_get_mux_route(bank, pin, mux, &route_location,
1279 &route_reg, &route_val)) {
1280 struct regmap *route_regmap = regmap;
1282 /* handle special locations */
1283 switch (route_location) {
1284 case ROCKCHIP_ROUTE_PMU:
1285 route_regmap = info->regmap_pmu;
1287 case ROCKCHIP_ROUTE_GRF:
1288 route_regmap = info->regmap_base;
1292 ret = regmap_write(route_regmap, route_reg, route_val);
1298 data = (mask << (bit + 16));
1299 rmask = data | (data >> 16);
1300 data |= (mux & mask) << bit;
1301 ret = regmap_update_bits(regmap, reg, rmask, data);
1306 #define PX30_PULL_PMU_OFFSET 0x10
1307 #define PX30_PULL_GRF_OFFSET 0x60
1308 #define PX30_PULL_BITS_PER_PIN 2
1309 #define PX30_PULL_PINS_PER_REG 8
1310 #define PX30_PULL_BANK_STRIDE 16
1312 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1313 int pin_num, struct regmap **regmap,
1316 struct rockchip_pinctrl *info = bank->drvdata;
1318 /* The first 32 pins of the first bank are located in PMU */
1319 if (bank->bank_num == 0) {
1320 *regmap = info->regmap_pmu;
1321 *reg = PX30_PULL_PMU_OFFSET;
1323 *regmap = info->regmap_base;
1324 *reg = PX30_PULL_GRF_OFFSET;
1326 /* correct the offset, as we're starting with the 2nd bank */
1328 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1331 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1332 *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1333 *bit *= PX30_PULL_BITS_PER_PIN;
1336 #define PX30_DRV_PMU_OFFSET 0x20
1337 #define PX30_DRV_GRF_OFFSET 0xf0
1338 #define PX30_DRV_BITS_PER_PIN 2
1339 #define PX30_DRV_PINS_PER_REG 8
1340 #define PX30_DRV_BANK_STRIDE 16
1342 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1343 int pin_num, struct regmap **regmap,
1346 struct rockchip_pinctrl *info = bank->drvdata;
1348 /* The first 32 pins of the first bank are located in PMU */
1349 if (bank->bank_num == 0) {
1350 *regmap = info->regmap_pmu;
1351 *reg = PX30_DRV_PMU_OFFSET;
1353 *regmap = info->regmap_base;
1354 *reg = PX30_DRV_GRF_OFFSET;
1356 /* correct the offset, as we're starting with the 2nd bank */
1358 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1361 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1362 *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1363 *bit *= PX30_DRV_BITS_PER_PIN;
1366 #define PX30_SCHMITT_PMU_OFFSET 0x38
1367 #define PX30_SCHMITT_GRF_OFFSET 0xc0
1368 #define PX30_SCHMITT_PINS_PER_PMU_REG 16
1369 #define PX30_SCHMITT_BANK_STRIDE 16
1370 #define PX30_SCHMITT_PINS_PER_GRF_REG 8
1372 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1374 struct regmap **regmap,
1377 struct rockchip_pinctrl *info = bank->drvdata;
1380 if (bank->bank_num == 0) {
1381 *regmap = info->regmap_pmu;
1382 *reg = PX30_SCHMITT_PMU_OFFSET;
1383 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1385 *regmap = info->regmap_base;
1386 *reg = PX30_SCHMITT_GRF_OFFSET;
1387 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1388 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
1391 *reg += ((pin_num / pins_per_reg) * 4);
1392 *bit = pin_num % pins_per_reg;
1397 #define RV1108_PULL_PMU_OFFSET 0x10
1398 #define RV1108_PULL_OFFSET 0x110
1399 #define RV1108_PULL_PINS_PER_REG 8
1400 #define RV1108_PULL_BITS_PER_PIN 2
1401 #define RV1108_PULL_BANK_STRIDE 16
1403 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1404 int pin_num, struct regmap **regmap,
1407 struct rockchip_pinctrl *info = bank->drvdata;
1409 /* The first 24 pins of the first bank are located in PMU */
1410 if (bank->bank_num == 0) {
1411 *regmap = info->regmap_pmu;
1412 *reg = RV1108_PULL_PMU_OFFSET;
1414 *reg = RV1108_PULL_OFFSET;
1415 *regmap = info->regmap_base;
1416 /* correct the offset, as we're starting with the 2nd bank */
1418 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1421 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1422 *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1423 *bit *= RV1108_PULL_BITS_PER_PIN;
1426 #define RV1108_DRV_PMU_OFFSET 0x20
1427 #define RV1108_DRV_GRF_OFFSET 0x210
1428 #define RV1108_DRV_BITS_PER_PIN 2
1429 #define RV1108_DRV_PINS_PER_REG 8
1430 #define RV1108_DRV_BANK_STRIDE 16
1432 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1433 int pin_num, struct regmap **regmap,
1436 struct rockchip_pinctrl *info = bank->drvdata;
1438 /* The first 24 pins of the first bank are located in PMU */
1439 if (bank->bank_num == 0) {
1440 *regmap = info->regmap_pmu;
1441 *reg = RV1108_DRV_PMU_OFFSET;
1443 *regmap = info->regmap_base;
1444 *reg = RV1108_DRV_GRF_OFFSET;
1446 /* correct the offset, as we're starting with the 2nd bank */
1448 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1451 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1452 *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1453 *bit *= RV1108_DRV_BITS_PER_PIN;
1456 #define RV1108_SCHMITT_PMU_OFFSET 0x30
1457 #define RV1108_SCHMITT_GRF_OFFSET 0x388
1458 #define RV1108_SCHMITT_BANK_STRIDE 8
1459 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16
1460 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8
1462 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1464 struct regmap **regmap,
1467 struct rockchip_pinctrl *info = bank->drvdata;
1470 if (bank->bank_num == 0) {
1471 *regmap = info->regmap_pmu;
1472 *reg = RV1108_SCHMITT_PMU_OFFSET;
1473 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1475 *regmap = info->regmap_base;
1476 *reg = RV1108_SCHMITT_GRF_OFFSET;
1477 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1478 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
1480 *reg += ((pin_num / pins_per_reg) * 4);
1481 *bit = pin_num % pins_per_reg;
1486 #define RK2928_PULL_OFFSET 0x118
1487 #define RK2928_PULL_PINS_PER_REG 16
1488 #define RK2928_PULL_BANK_STRIDE 8
1490 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1491 int pin_num, struct regmap **regmap,
1494 struct rockchip_pinctrl *info = bank->drvdata;
1496 *regmap = info->regmap_base;
1497 *reg = RK2928_PULL_OFFSET;
1498 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1499 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1501 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1504 #define RK3128_PULL_OFFSET 0x118
1506 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1507 int pin_num, struct regmap **regmap,
1510 struct rockchip_pinctrl *info = bank->drvdata;
1512 *regmap = info->regmap_base;
1513 *reg = RK3128_PULL_OFFSET;
1514 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1515 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1517 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1520 #define RK3188_PULL_OFFSET 0x164
1521 #define RK3188_PULL_BITS_PER_PIN 2
1522 #define RK3188_PULL_PINS_PER_REG 8
1523 #define RK3188_PULL_BANK_STRIDE 16
1524 #define RK3188_PULL_PMU_OFFSET 0x64
1526 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1527 int pin_num, struct regmap **regmap,
1530 struct rockchip_pinctrl *info = bank->drvdata;
1532 /* The first 12 pins of the first bank are located elsewhere */
1533 if (bank->bank_num == 0 && pin_num < 12) {
1534 *regmap = info->regmap_pmu ? info->regmap_pmu
1535 : bank->regmap_pull;
1536 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1537 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1538 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1539 *bit *= RK3188_PULL_BITS_PER_PIN;
1541 *regmap = info->regmap_pull ? info->regmap_pull
1542 : info->regmap_base;
1543 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1545 /* correct the offset, as it is the 2nd pull register */
1547 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1548 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1551 * The bits in these registers have an inverse ordering
1552 * with the lowest pin being in bits 15:14 and the highest
1555 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1556 *bit *= RK3188_PULL_BITS_PER_PIN;
1560 #define RK3288_PULL_OFFSET 0x140
1561 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1562 int pin_num, struct regmap **regmap,
1565 struct rockchip_pinctrl *info = bank->drvdata;
1567 /* The first 24 pins of the first bank are located in PMU */
1568 if (bank->bank_num == 0) {
1569 *regmap = info->regmap_pmu;
1570 *reg = RK3188_PULL_PMU_OFFSET;
1572 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1573 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1574 *bit *= RK3188_PULL_BITS_PER_PIN;
1576 *regmap = info->regmap_base;
1577 *reg = RK3288_PULL_OFFSET;
1579 /* correct the offset, as we're starting with the 2nd bank */
1581 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1582 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1584 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1585 *bit *= RK3188_PULL_BITS_PER_PIN;
1589 #define RK3288_DRV_PMU_OFFSET 0x70
1590 #define RK3288_DRV_GRF_OFFSET 0x1c0
1591 #define RK3288_DRV_BITS_PER_PIN 2
1592 #define RK3288_DRV_PINS_PER_REG 8
1593 #define RK3288_DRV_BANK_STRIDE 16
1595 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1596 int pin_num, struct regmap **regmap,
1599 struct rockchip_pinctrl *info = bank->drvdata;
1601 /* The first 24 pins of the first bank are located in PMU */
1602 if (bank->bank_num == 0) {
1603 *regmap = info->regmap_pmu;
1604 *reg = RK3288_DRV_PMU_OFFSET;
1606 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1607 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1608 *bit *= RK3288_DRV_BITS_PER_PIN;
1610 *regmap = info->regmap_base;
1611 *reg = RK3288_DRV_GRF_OFFSET;
1613 /* correct the offset, as we're starting with the 2nd bank */
1615 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1616 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1618 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1619 *bit *= RK3288_DRV_BITS_PER_PIN;
1623 #define RK3228_PULL_OFFSET 0x100
1625 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1626 int pin_num, struct regmap **regmap,
1629 struct rockchip_pinctrl *info = bank->drvdata;
1631 *regmap = info->regmap_base;
1632 *reg = RK3228_PULL_OFFSET;
1633 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1634 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1636 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1637 *bit *= RK3188_PULL_BITS_PER_PIN;
1640 #define RK3228_DRV_GRF_OFFSET 0x200
1642 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1643 int pin_num, struct regmap **regmap,
1646 struct rockchip_pinctrl *info = bank->drvdata;
1648 *regmap = info->regmap_base;
1649 *reg = RK3228_DRV_GRF_OFFSET;
1650 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1651 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1653 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1654 *bit *= RK3288_DRV_BITS_PER_PIN;
1657 #define RK3368_PULL_GRF_OFFSET 0x100
1658 #define RK3368_PULL_PMU_OFFSET 0x10
1660 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1661 int pin_num, struct regmap **regmap,
1664 struct rockchip_pinctrl *info = bank->drvdata;
1666 /* The first 32 pins of the first bank are located in PMU */
1667 if (bank->bank_num == 0) {
1668 *regmap = info->regmap_pmu;
1669 *reg = RK3368_PULL_PMU_OFFSET;
1671 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1672 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1673 *bit *= RK3188_PULL_BITS_PER_PIN;
1675 *regmap = info->regmap_base;
1676 *reg = RK3368_PULL_GRF_OFFSET;
1678 /* correct the offset, as we're starting with the 2nd bank */
1680 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1681 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1683 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1684 *bit *= RK3188_PULL_BITS_PER_PIN;
1688 #define RK3368_DRV_PMU_OFFSET 0x20
1689 #define RK3368_DRV_GRF_OFFSET 0x200
1691 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1692 int pin_num, struct regmap **regmap,
1695 struct rockchip_pinctrl *info = bank->drvdata;
1697 /* The first 32 pins of the first bank are located in PMU */
1698 if (bank->bank_num == 0) {
1699 *regmap = info->regmap_pmu;
1700 *reg = RK3368_DRV_PMU_OFFSET;
1702 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1703 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1704 *bit *= RK3288_DRV_BITS_PER_PIN;
1706 *regmap = info->regmap_base;
1707 *reg = RK3368_DRV_GRF_OFFSET;
1709 /* correct the offset, as we're starting with the 2nd bank */
1711 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1712 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1714 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1715 *bit *= RK3288_DRV_BITS_PER_PIN;
1719 #define RK3399_PULL_GRF_OFFSET 0xe040
1720 #define RK3399_PULL_PMU_OFFSET 0x40
1721 #define RK3399_DRV_3BITS_PER_PIN 3
1723 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1724 int pin_num, struct regmap **regmap,
1727 struct rockchip_pinctrl *info = bank->drvdata;
1729 /* The bank0:16 and bank1:32 pins are located in PMU */
1730 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1731 *regmap = info->regmap_pmu;
1732 *reg = RK3399_PULL_PMU_OFFSET;
1734 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1736 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1737 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1738 *bit *= RK3188_PULL_BITS_PER_PIN;
1740 *regmap = info->regmap_base;
1741 *reg = RK3399_PULL_GRF_OFFSET;
1743 /* correct the offset, as we're starting with the 3rd bank */
1745 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1746 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1748 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1749 *bit *= RK3188_PULL_BITS_PER_PIN;
1753 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1754 int pin_num, struct regmap **regmap,
1757 struct rockchip_pinctrl *info = bank->drvdata;
1758 int drv_num = (pin_num / 8);
1760 /* The bank0:16 and bank1:32 pins are located in PMU */
1761 if ((bank->bank_num == 0) || (bank->bank_num == 1))
1762 *regmap = info->regmap_pmu;
1764 *regmap = info->regmap_base;
1766 *reg = bank->drv[drv_num].offset;
1767 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1768 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1769 *bit = (pin_num % 8) * 3;
1771 *bit = (pin_num % 8) * 2;
1774 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1775 { 2, 4, 8, 12, -1, -1, -1, -1 },
1776 { 3, 6, 9, 12, -1, -1, -1, -1 },
1777 { 5, 10, 15, 20, -1, -1, -1, -1 },
1778 { 4, 6, 8, 10, 12, 14, 16, 18 },
1779 { 4, 7, 10, 13, 16, 19, 22, 26 }
1782 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1785 struct rockchip_pinctrl *info = bank->drvdata;
1786 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1787 struct regmap *regmap;
1789 u32 data, temp, rmask_bits;
1791 int drv_type = bank->drv[pin_num / 8].drv_type;
1793 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
1796 case DRV_TYPE_IO_1V8_3V0_AUTO:
1797 case DRV_TYPE_IO_3V3_ONLY:
1798 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1801 /* regular case, nothing to do */
1805 * drive-strength offset is special, as it is
1806 * spread over 2 registers
1808 ret = regmap_read(regmap, reg, &data);
1812 ret = regmap_read(regmap, reg + 0x4, &temp);
1817 * the bit data[15] contains bit 0 of the value
1818 * while temp[1:0] contains bits 2 and 1
1825 return rockchip_perpin_drv_list[drv_type][data];
1827 /* setting fully enclosed in the second register */
1832 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1838 case DRV_TYPE_IO_DEFAULT:
1839 case DRV_TYPE_IO_1V8_OR_3V0:
1840 case DRV_TYPE_IO_1V8_ONLY:
1841 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1844 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1849 ret = regmap_read(regmap, reg, &data);
1854 data &= (1 << rmask_bits) - 1;
1856 return rockchip_perpin_drv_list[drv_type][data];
1859 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1860 int pin_num, int strength)
1862 struct rockchip_pinctrl *info = bank->drvdata;
1863 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1864 struct regmap *regmap;
1866 u32 data, rmask, rmask_bits, temp;
1868 int drv_type = bank->drv[pin_num / 8].drv_type;
1870 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
1871 bank->bank_num, pin_num, strength);
1873 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
1876 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1877 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
1880 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1881 ret = rockchip_perpin_drv_list[drv_type][i];
1887 dev_err(info->dev, "unsupported driver strength %d\n",
1893 case DRV_TYPE_IO_1V8_3V0_AUTO:
1894 case DRV_TYPE_IO_3V3_ONLY:
1895 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1898 /* regular case, nothing to do */
1902 * drive-strength offset is special, as it is spread
1903 * over 2 registers, the bit data[15] contains bit 0
1904 * of the value while temp[1:0] contains bits 2 and 1
1906 data = (ret & 0x1) << 15;
1907 temp = (ret >> 0x1) & 0x3;
1909 rmask = BIT(15) | BIT(31);
1911 ret = regmap_update_bits(regmap, reg, rmask, data);
1915 rmask = 0x3 | (0x3 << 16);
1916 temp |= (0x3 << 16);
1918 ret = regmap_update_bits(regmap, reg, rmask, temp);
1922 /* setting fully enclosed in the second register */
1927 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1932 case DRV_TYPE_IO_DEFAULT:
1933 case DRV_TYPE_IO_1V8_OR_3V0:
1934 case DRV_TYPE_IO_1V8_ONLY:
1935 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1938 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1943 /* enable the write to the equivalent lower bits */
1944 data = ((1 << rmask_bits) - 1) << (bit + 16);
1945 rmask = data | (data >> 16);
1946 data |= (ret << bit);
1948 ret = regmap_update_bits(regmap, reg, rmask, data);
1953 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1955 PIN_CONFIG_BIAS_DISABLE,
1956 PIN_CONFIG_BIAS_PULL_UP,
1957 PIN_CONFIG_BIAS_PULL_DOWN,
1958 PIN_CONFIG_BIAS_BUS_HOLD
1961 PIN_CONFIG_BIAS_DISABLE,
1962 PIN_CONFIG_BIAS_PULL_DOWN,
1963 PIN_CONFIG_BIAS_DISABLE,
1964 PIN_CONFIG_BIAS_PULL_UP
1968 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1970 struct rockchip_pinctrl *info = bank->drvdata;
1971 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1972 struct regmap *regmap;
1973 int reg, ret, pull_type;
1977 /* rk3066b does support any pulls */
1978 if (ctrl->type == RK3066B)
1979 return PIN_CONFIG_BIAS_DISABLE;
1981 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
1983 ret = regmap_read(regmap, reg, &data);
1987 switch (ctrl->type) {
1990 return !(data & BIT(bit))
1991 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1992 : PIN_CONFIG_BIAS_DISABLE;
1999 pull_type = bank->pull_type[pin_num / 8];
2001 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
2003 return rockchip_pull_list[pull_type][data];
2005 dev_err(info->dev, "unsupported pinctrl type\n");
2010 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
2011 int pin_num, int pull)
2013 struct rockchip_pinctrl *info = bank->drvdata;
2014 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2015 struct regmap *regmap;
2016 int reg, ret, i, pull_type;
2020 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
2021 bank->bank_num, pin_num, pull);
2023 /* rk3066b does support any pulls */
2024 if (ctrl->type == RK3066B)
2025 return pull ? -EINVAL : 0;
2027 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
2029 switch (ctrl->type) {
2032 data = BIT(bit + 16);
2033 if (pull == PIN_CONFIG_BIAS_DISABLE)
2035 ret = regmap_write(regmap, reg, data);
2043 pull_type = bank->pull_type[pin_num / 8];
2045 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
2047 if (rockchip_pull_list[pull_type][i] == pull) {
2054 dev_err(info->dev, "unsupported pull setting %d\n",
2059 /* enable the write to the equivalent lower bits */
2060 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
2061 rmask = data | (data >> 16);
2062 data |= (ret << bit);
2064 ret = regmap_update_bits(regmap, reg, rmask, data);
2067 dev_err(info->dev, "unsupported pinctrl type\n");
2074 #define RK3328_SCHMITT_BITS_PER_PIN 1
2075 #define RK3328_SCHMITT_PINS_PER_REG 16
2076 #define RK3328_SCHMITT_BANK_STRIDE 8
2077 #define RK3328_SCHMITT_GRF_OFFSET 0x380
2079 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2081 struct regmap **regmap,
2084 struct rockchip_pinctrl *info = bank->drvdata;
2086 *regmap = info->regmap_base;
2087 *reg = RK3328_SCHMITT_GRF_OFFSET;
2089 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
2090 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
2091 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
2096 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
2098 struct rockchip_pinctrl *info = bank->drvdata;
2099 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2100 struct regmap *regmap;
2105 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
2109 ret = regmap_read(regmap, reg, &data);
2117 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
2118 int pin_num, int enable)
2120 struct rockchip_pinctrl *info = bank->drvdata;
2121 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2122 struct regmap *regmap;
2127 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
2128 bank->bank_num, pin_num, enable);
2130 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
2134 /* enable the write to the equivalent lower bits */
2135 data = BIT(bit + 16) | (enable << bit);
2136 rmask = BIT(bit + 16) | BIT(bit);
2138 return regmap_update_bits(regmap, reg, rmask, data);
2142 * Pinmux_ops handling
2145 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2147 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2149 return info->nfunctions;
2152 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2155 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2157 return info->functions[selector].name;
2160 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2161 unsigned selector, const char * const **groups,
2162 unsigned * const num_groups)
2164 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2166 *groups = info->functions[selector].groups;
2167 *num_groups = info->functions[selector].ngroups;
2172 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2175 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2176 const unsigned int *pins = info->groups[group].pins;
2177 const struct rockchip_pin_config *data = info->groups[group].data;
2178 struct rockchip_pin_bank *bank;
2181 dev_dbg(info->dev, "enable function %s group %s\n",
2182 info->functions[selector].name, info->groups[group].name);
2185 * for each pin in the pin group selected, program the corresponding
2186 * pin function number in the config register.
2188 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2189 bank = pin_to_bank(info, pins[cnt]);
2190 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2197 /* revert the already done pin settings */
2198 for (cnt--; cnt >= 0; cnt--)
2199 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2207 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
2209 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
2213 ret = clk_enable(bank->clk);
2215 dev_err(bank->drvdata->dev,
2216 "failed to enable clock for bank %s\n", bank->name);
2219 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2220 clk_disable(bank->clk);
2222 return !(data & BIT(offset));
2226 * The calls to gpio_direction_output() and gpio_direction_input()
2227 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
2228 * function called from the gpiolib interface).
2230 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
2231 int pin, bool input)
2233 struct rockchip_pin_bank *bank;
2235 unsigned long flags;
2238 bank = gpiochip_get_data(chip);
2240 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
2244 clk_enable(bank->clk);
2245 raw_spin_lock_irqsave(&bank->slock, flags);
2247 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2248 /* set bit to 1 for output, 0 for input */
2253 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2255 raw_spin_unlock_irqrestore(&bank->slock, flags);
2256 clk_disable(bank->clk);
2261 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
2262 struct pinctrl_gpio_range *range,
2263 unsigned offset, bool input)
2265 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2266 struct gpio_chip *chip;
2270 pin = offset - chip->base;
2271 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
2272 offset, range->name, pin, input ? "input" : "output");
2274 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
2278 static const struct pinmux_ops rockchip_pmx_ops = {
2279 .get_functions_count = rockchip_pmx_get_funcs_count,
2280 .get_function_name = rockchip_pmx_get_func_name,
2281 .get_function_groups = rockchip_pmx_get_groups,
2282 .set_mux = rockchip_pmx_set,
2283 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
2287 * Pinconf_ops handling
2290 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2291 enum pin_config_param pull)
2293 switch (ctrl->type) {
2296 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2297 pull == PIN_CONFIG_BIAS_DISABLE);
2299 return pull ? false : true;
2306 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2312 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
2313 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
2315 /* set the pin config settings for a specified pin */
2316 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2317 unsigned long *configs, unsigned num_configs)
2319 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2320 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2321 enum pin_config_param param;
2326 for (i = 0; i < num_configs; i++) {
2327 param = pinconf_to_config_param(configs[i]);
2328 arg = pinconf_to_config_argument(configs[i]);
2331 case PIN_CONFIG_BIAS_DISABLE:
2332 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2337 case PIN_CONFIG_BIAS_PULL_UP:
2338 case PIN_CONFIG_BIAS_PULL_DOWN:
2339 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2340 case PIN_CONFIG_BIAS_BUS_HOLD:
2341 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2347 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2352 case PIN_CONFIG_OUTPUT:
2353 rockchip_gpio_set(&bank->gpio_chip,
2354 pin - bank->pin_base, arg);
2355 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
2356 pin - bank->pin_base, false);
2360 case PIN_CONFIG_DRIVE_STRENGTH:
2361 /* rk3288 is the first with per-pin drive-strength */
2362 if (!info->ctrl->drv_calc_reg)
2365 rc = rockchip_set_drive_perpin(bank,
2366 pin - bank->pin_base, arg);
2370 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2371 if (!info->ctrl->schmitt_calc_reg)
2374 rc = rockchip_set_schmitt(bank,
2375 pin - bank->pin_base, arg);
2383 } /* for each config */
2388 /* get the pin config settings for a specified pin */
2389 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2390 unsigned long *config)
2392 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2393 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2394 enum pin_config_param param = pinconf_to_config_param(*config);
2399 case PIN_CONFIG_BIAS_DISABLE:
2400 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2405 case PIN_CONFIG_BIAS_PULL_UP:
2406 case PIN_CONFIG_BIAS_PULL_DOWN:
2407 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2408 case PIN_CONFIG_BIAS_BUS_HOLD:
2409 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2412 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2417 case PIN_CONFIG_OUTPUT:
2418 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2419 if (rc != RK_FUNC_GPIO)
2422 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
2428 case PIN_CONFIG_DRIVE_STRENGTH:
2429 /* rk3288 is the first with per-pin drive-strength */
2430 if (!info->ctrl->drv_calc_reg)
2433 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
2439 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2440 if (!info->ctrl->schmitt_calc_reg)
2443 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2454 *config = pinconf_to_config_packed(param, arg);
2459 static const struct pinconf_ops rockchip_pinconf_ops = {
2460 .pin_config_get = rockchip_pinconf_get,
2461 .pin_config_set = rockchip_pinconf_set,
2465 static const struct of_device_id rockchip_bank_match[] = {
2466 { .compatible = "rockchip,gpio-bank" },
2467 { .compatible = "rockchip,rk3188-gpio-bank0" },
2471 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2472 struct device_node *np)
2474 struct device_node *child;
2476 for_each_child_of_node(np, child) {
2477 if (of_match_node(rockchip_bank_match, child))
2481 info->ngroups += of_get_child_count(child);
2485 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2486 struct rockchip_pin_group *grp,
2487 struct rockchip_pinctrl *info,
2490 struct rockchip_pin_bank *bank;
2497 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
2499 /* Initialise group */
2500 grp->name = np->name;
2503 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2504 * do sanity check and calculate pins number
2506 list = of_get_property(np, "rockchip,pins", &size);
2507 /* we do not check return since it's safe node passed down */
2508 size /= sizeof(*list);
2509 if (!size || size % 4) {
2510 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
2514 grp->npins = size / 4;
2516 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
2518 grp->data = devm_kcalloc(info->dev,
2520 sizeof(struct rockchip_pin_config),
2522 if (!grp->pins || !grp->data)
2525 for (i = 0, j = 0; i < size; i += 4, j++) {
2526 const __be32 *phandle;
2527 struct device_node *np_config;
2529 num = be32_to_cpu(*list++);
2530 bank = bank_num_to_bank(info, num);
2532 return PTR_ERR(bank);
2534 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2535 grp->data[j].func = be32_to_cpu(*list++);
2541 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
2542 ret = pinconf_generic_parse_dt_config(np_config, NULL,
2543 &grp->data[j].configs, &grp->data[j].nconfigs);
2551 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2552 struct rockchip_pinctrl *info,
2555 struct device_node *child;
2556 struct rockchip_pmx_func *func;
2557 struct rockchip_pin_group *grp;
2559 static u32 grp_index;
2562 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
2564 func = &info->functions[index];
2566 /* Initialise function */
2567 func->name = np->name;
2568 func->ngroups = of_get_child_count(np);
2569 if (func->ngroups <= 0)
2572 func->groups = devm_kcalloc(info->dev,
2573 func->ngroups, sizeof(char *), GFP_KERNEL);
2577 for_each_child_of_node(np, child) {
2578 func->groups[i] = child->name;
2579 grp = &info->groups[grp_index++];
2580 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2590 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2591 struct rockchip_pinctrl *info)
2593 struct device *dev = &pdev->dev;
2594 struct device_node *np = dev->of_node;
2595 struct device_node *child;
2599 rockchip_pinctrl_child_count(info, np);
2601 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2602 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2604 info->functions = devm_kcalloc(dev,
2606 sizeof(struct rockchip_pmx_func),
2608 if (!info->functions)
2611 info->groups = devm_kcalloc(dev,
2613 sizeof(struct rockchip_pin_group),
2620 for_each_child_of_node(np, child) {
2621 if (of_match_node(rockchip_bank_match, child))
2624 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2626 dev_err(&pdev->dev, "failed to parse function\n");
2635 static int rockchip_pinctrl_register(struct platform_device *pdev,
2636 struct rockchip_pinctrl *info)
2638 struct pinctrl_desc *ctrldesc = &info->pctl;
2639 struct pinctrl_pin_desc *pindesc, *pdesc;
2640 struct rockchip_pin_bank *pin_bank;
2644 ctrldesc->name = "rockchip-pinctrl";
2645 ctrldesc->owner = THIS_MODULE;
2646 ctrldesc->pctlops = &rockchip_pctrl_ops;
2647 ctrldesc->pmxops = &rockchip_pmx_ops;
2648 ctrldesc->confops = &rockchip_pinconf_ops;
2650 pindesc = devm_kcalloc(&pdev->dev,
2651 info->ctrl->nr_pins, sizeof(*pindesc),
2656 ctrldesc->pins = pindesc;
2657 ctrldesc->npins = info->ctrl->nr_pins;
2660 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
2661 pin_bank = &info->ctrl->pin_banks[bank];
2662 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2664 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
2665 pin_bank->name, pin);
2670 ret = rockchip_pinctrl_parse_dt(pdev, info);
2674 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
2675 if (IS_ERR(info->pctl_dev)) {
2676 dev_err(&pdev->dev, "could not register pinctrl driver\n");
2677 return PTR_ERR(info->pctl_dev);
2680 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
2681 pin_bank = &info->ctrl->pin_banks[bank];
2682 pin_bank->grange.name = pin_bank->name;
2683 pin_bank->grange.id = bank;
2684 pin_bank->grange.pin_base = pin_bank->pin_base;
2685 pin_bank->grange.base = pin_bank->gpio_chip.base;
2686 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
2687 pin_bank->grange.gc = &pin_bank->gpio_chip;
2688 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
2698 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2700 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2701 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
2702 unsigned long flags;
2705 clk_enable(bank->clk);
2706 raw_spin_lock_irqsave(&bank->slock, flags);
2709 data &= ~BIT(offset);
2711 data |= BIT(offset);
2714 raw_spin_unlock_irqrestore(&bank->slock, flags);
2715 clk_disable(bank->clk);
2719 * Returns the level of the pin for input direction and setting of the DR
2720 * register for output gpios.
2722 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
2724 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2727 clk_enable(bank->clk);
2728 data = readl(bank->reg_base + GPIO_EXT_PORT);
2729 clk_disable(bank->clk);
2736 * gpiolib gpio_direction_input callback function. The setting of the pin
2737 * mux function as 'gpio input' will be handled by the pinctrl subsystem
2740 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2742 return pinctrl_gpio_direction_input(gc->base + offset);
2746 * gpiolib gpio_direction_output callback function. The setting of the pin
2747 * mux function as 'gpio output' will be handled by the pinctrl subsystem
2750 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
2751 unsigned offset, int value)
2753 rockchip_gpio_set(gc, offset, value);
2754 return pinctrl_gpio_direction_output(gc->base + offset);
2757 static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
2758 unsigned int offset, bool enable)
2760 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2761 void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE;
2762 unsigned long flags;
2765 clk_enable(bank->clk);
2766 raw_spin_lock_irqsave(&bank->slock, flags);
2770 data |= BIT(offset);
2772 data &= ~BIT(offset);
2775 raw_spin_unlock_irqrestore(&bank->slock, flags);
2776 clk_disable(bank->clk);
2780 * gpiolib set_config callback function. The setting of the pin
2781 * mux function as 'gpio output' will be handled by the pinctrl subsystem
2784 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
2785 unsigned long config)
2787 enum pin_config_param param = pinconf_to_config_param(config);
2790 case PIN_CONFIG_INPUT_DEBOUNCE:
2791 rockchip_gpio_set_debounce(gc, offset, true);
2793 * Rockchip's gpio could only support up to one period
2794 * of the debounce clock(pclk), which is far away from
2795 * satisftying the requirement, as pclk is usually near
2796 * 100MHz shared by all peripherals. So the fact is it
2797 * has crippled debounce capability could only be useful
2798 * to prevent any spurious glitches from waking up the system
2799 * if the gpio is conguired as wakeup interrupt source. Let's
2800 * still return -ENOTSUPP as before, to make sure the caller
2801 * of gpiod_set_debounce won't change its behaviour.
2809 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
2810 * and a virtual IRQ, if not already present.
2812 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2814 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2820 virq = irq_create_mapping(bank->domain, offset);
2822 return (virq) ? : -ENXIO;
2825 static const struct gpio_chip rockchip_gpiolib_chip = {
2826 .request = gpiochip_generic_request,
2827 .free = gpiochip_generic_free,
2828 .set = rockchip_gpio_set,
2829 .get = rockchip_gpio_get,
2830 .get_direction = rockchip_gpio_get_direction,
2831 .direction_input = rockchip_gpio_direction_input,
2832 .direction_output = rockchip_gpio_direction_output,
2833 .set_config = rockchip_gpio_set_config,
2834 .to_irq = rockchip_gpio_to_irq,
2835 .owner = THIS_MODULE,
2839 * Interrupt handling
2842 static void rockchip_irq_demux(struct irq_desc *desc)
2844 struct irq_chip *chip = irq_desc_get_chip(desc);
2845 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
2848 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
2850 chained_irq_enter(chip, desc);
2852 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2855 unsigned int irq, virq;
2859 virq = irq_linear_revmap(bank->domain, irq);
2862 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2866 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2869 * Triggering IRQ on both rising and falling edge
2870 * needs manual intervention.
2872 if (bank->toggle_edge_mode & BIT(irq)) {
2873 u32 data, data_old, polarity;
2874 unsigned long flags;
2876 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
2878 raw_spin_lock_irqsave(&bank->slock, flags);
2880 polarity = readl_relaxed(bank->reg_base +
2882 if (data & BIT(irq))
2883 polarity &= ~BIT(irq);
2885 polarity |= BIT(irq);
2887 bank->reg_base + GPIO_INT_POLARITY);
2889 raw_spin_unlock_irqrestore(&bank->slock, flags);
2892 data = readl_relaxed(bank->reg_base +
2894 } while ((data & BIT(irq)) != (data_old & BIT(irq)));
2897 generic_handle_irq(virq);
2900 chained_irq_exit(chip, desc);
2903 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
2905 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2906 struct rockchip_pin_bank *bank = gc->private;
2907 u32 mask = BIT(d->hwirq);
2911 unsigned long flags;
2914 /* make sure the pin is configured as gpio input */
2915 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
2919 clk_enable(bank->clk);
2920 raw_spin_lock_irqsave(&bank->slock, flags);
2922 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2924 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2926 raw_spin_unlock_irqrestore(&bank->slock, flags);
2928 if (type & IRQ_TYPE_EDGE_BOTH)
2929 irq_set_handler_locked(d, handle_edge_irq);
2931 irq_set_handler_locked(d, handle_level_irq);
2933 raw_spin_lock_irqsave(&bank->slock, flags);
2936 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
2937 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
2940 case IRQ_TYPE_EDGE_BOTH:
2941 bank->toggle_edge_mode |= mask;
2945 * Determine gpio state. If 1 next interrupt should be falling
2948 data = readl(bank->reg_base + GPIO_EXT_PORT);
2954 case IRQ_TYPE_EDGE_RISING:
2955 bank->toggle_edge_mode &= ~mask;
2959 case IRQ_TYPE_EDGE_FALLING:
2960 bank->toggle_edge_mode &= ~mask;
2964 case IRQ_TYPE_LEVEL_HIGH:
2965 bank->toggle_edge_mode &= ~mask;
2969 case IRQ_TYPE_LEVEL_LOW:
2970 bank->toggle_edge_mode &= ~mask;
2976 raw_spin_unlock_irqrestore(&bank->slock, flags);
2977 clk_disable(bank->clk);
2981 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
2982 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
2985 raw_spin_unlock_irqrestore(&bank->slock, flags);
2986 clk_disable(bank->clk);
2991 static void rockchip_irq_suspend(struct irq_data *d)
2993 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2994 struct rockchip_pin_bank *bank = gc->private;
2996 clk_enable(bank->clk);
2997 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
2998 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
2999 clk_disable(bank->clk);
3002 static void rockchip_irq_resume(struct irq_data *d)
3004 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3005 struct rockchip_pin_bank *bank = gc->private;
3007 clk_enable(bank->clk);
3008 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
3009 clk_disable(bank->clk);
3012 static void rockchip_irq_enable(struct irq_data *d)
3014 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3015 struct rockchip_pin_bank *bank = gc->private;
3017 clk_enable(bank->clk);
3018 irq_gc_mask_clr_bit(d);
3021 static void rockchip_irq_disable(struct irq_data *d)
3023 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3024 struct rockchip_pin_bank *bank = gc->private;
3026 irq_gc_mask_set_bit(d);
3027 clk_disable(bank->clk);
3030 static int rockchip_interrupts_register(struct platform_device *pdev,
3031 struct rockchip_pinctrl *info)
3033 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3034 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3035 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
3036 struct irq_chip_generic *gc;
3040 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3042 dev_warn(&pdev->dev, "bank %s is not valid\n",
3047 ret = clk_enable(bank->clk);
3049 dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
3054 bank->domain = irq_domain_add_linear(bank->of_node, 32,
3055 &irq_generic_chip_ops, NULL);
3056 if (!bank->domain) {
3057 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
3059 clk_disable(bank->clk);
3063 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
3064 "rockchip_gpio_irq", handle_level_irq,
3065 clr, 0, IRQ_GC_INIT_MASK_CACHE);
3067 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
3069 irq_domain_remove(bank->domain);
3070 clk_disable(bank->clk);
3075 * Linux assumes that all interrupts start out disabled/masked.
3076 * Our driver only uses the concept of masked and always keeps
3077 * things enabled, so for us that's all masked and all enabled.
3079 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
3080 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
3082 gc = irq_get_domain_generic_chip(bank->domain, 0);
3083 gc->reg_base = bank->reg_base;
3085 gc->chip_types[0].regs.mask = GPIO_INTMASK;
3086 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
3087 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
3088 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
3089 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
3090 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
3091 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
3092 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
3093 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
3094 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
3095 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
3096 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
3098 irq_set_chained_handler_and_data(bank->irq,
3099 rockchip_irq_demux, bank);
3101 /* map the gpio irqs here, when the clock is still running */
3102 for (j = 0 ; j < 32 ; j++)
3103 irq_create_mapping(bank->domain, j);
3105 clk_disable(bank->clk);
3111 static int rockchip_gpiolib_register(struct platform_device *pdev,
3112 struct rockchip_pinctrl *info)
3114 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3115 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3116 struct gpio_chip *gc;
3120 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3122 dev_warn(&pdev->dev, "bank %s is not valid\n",
3127 bank->gpio_chip = rockchip_gpiolib_chip;
3129 gc = &bank->gpio_chip;
3130 gc->base = bank->pin_base;
3131 gc->ngpio = bank->nr_pins;
3132 gc->parent = &pdev->dev;
3133 gc->of_node = bank->of_node;
3134 gc->label = bank->name;
3136 ret = gpiochip_add_data(gc, bank);
3138 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
3144 rockchip_interrupts_register(pdev, info);
3149 for (--i, --bank; i >= 0; --i, --bank) {
3152 gpiochip_remove(&bank->gpio_chip);
3157 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
3158 struct rockchip_pinctrl *info)
3160 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3161 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3164 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3167 gpiochip_remove(&bank->gpio_chip);
3173 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
3174 struct rockchip_pinctrl *info)
3176 struct resource res;
3179 if (of_address_to_resource(bank->of_node, 0, &res)) {
3180 dev_err(info->dev, "cannot find IO resource for bank\n");
3184 bank->reg_base = devm_ioremap_resource(info->dev, &res);
3185 if (IS_ERR(bank->reg_base))
3186 return PTR_ERR(bank->reg_base);
3189 * special case, where parts of the pull setting-registers are
3190 * part of the PMU register space
3192 if (of_device_is_compatible(bank->of_node,
3193 "rockchip,rk3188-gpio-bank0")) {
3194 struct device_node *node;
3196 node = of_parse_phandle(bank->of_node->parent,
3199 if (of_address_to_resource(bank->of_node, 1, &res)) {
3200 dev_err(info->dev, "cannot find IO resource for bank\n");
3204 base = devm_ioremap_resource(info->dev, &res);
3206 return PTR_ERR(base);
3207 rockchip_regmap_config.max_register =
3208 resource_size(&res) - 4;
3209 rockchip_regmap_config.name =
3210 "rockchip,rk3188-gpio-bank0-pull";
3211 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
3213 &rockchip_regmap_config);
3217 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
3219 bank->clk = of_clk_get(bank->of_node, 0);
3220 if (IS_ERR(bank->clk))
3221 return PTR_ERR(bank->clk);
3223 return clk_prepare(bank->clk);
3226 static const struct of_device_id rockchip_pinctrl_dt_match[];
3228 /* retrieve the soc specific data */
3229 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
3230 struct rockchip_pinctrl *d,
3231 struct platform_device *pdev)
3233 const struct of_device_id *match;
3234 struct device_node *node = pdev->dev.of_node;
3235 struct device_node *np;
3236 struct rockchip_pin_ctrl *ctrl;
3237 struct rockchip_pin_bank *bank;
3238 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
3240 match = of_match_node(rockchip_pinctrl_dt_match, node);
3241 ctrl = (struct rockchip_pin_ctrl *)match->data;
3243 for_each_child_of_node(node, np) {
3244 if (!of_find_property(np, "gpio-controller", NULL))
3247 bank = ctrl->pin_banks;
3248 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3249 if (!strcmp(bank->name, np->name)) {
3252 if (!rockchip_get_bank_data(bank, d))
3260 grf_offs = ctrl->grf_mux_offset;
3261 pmu_offs = ctrl->pmu_mux_offset;
3262 drv_pmu_offs = ctrl->pmu_drv_offset;
3263 drv_grf_offs = ctrl->grf_drv_offset;
3264 bank = ctrl->pin_banks;
3265 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3268 raw_spin_lock_init(&bank->slock);
3270 bank->pin_base = ctrl->nr_pins;
3271 ctrl->nr_pins += bank->nr_pins;
3273 /* calculate iomux and drv offsets */
3274 for (j = 0; j < 4; j++) {
3275 struct rockchip_iomux *iom = &bank->iomux[j];
3276 struct rockchip_drv *drv = &bank->drv[j];
3279 if (bank_pins >= bank->nr_pins)
3282 /* preset iomux offset value, set new start value */
3283 if (iom->offset >= 0) {
3284 if (iom->type & IOMUX_SOURCE_PMU)
3285 pmu_offs = iom->offset;
3287 grf_offs = iom->offset;
3288 } else { /* set current iomux offset */
3289 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3290 pmu_offs : grf_offs;
3293 /* preset drv offset value, set new start value */
3294 if (drv->offset >= 0) {
3295 if (iom->type & IOMUX_SOURCE_PMU)
3296 drv_pmu_offs = drv->offset;
3298 drv_grf_offs = drv->offset;
3299 } else { /* set current drv offset */
3300 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3301 drv_pmu_offs : drv_grf_offs;
3304 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3305 i, j, iom->offset, drv->offset);
3308 * Increase offset according to iomux width.
3309 * 4bit iomux'es are spread over two registers.
3311 inc = (iom->type & (IOMUX_WIDTH_4BIT |
3312 IOMUX_WIDTH_3BIT)) ? 8 : 4;
3313 if (iom->type & IOMUX_SOURCE_PMU)
3319 * Increase offset according to drv width.
3320 * 3bit drive-strenth'es are spread over two registers.
3322 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3323 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3328 if (iom->type & IOMUX_SOURCE_PMU)
3329 drv_pmu_offs += inc;
3331 drv_grf_offs += inc;
3336 /* calculate the per-bank recalced_mask */
3337 for (j = 0; j < ctrl->niomux_recalced; j++) {
3340 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3341 pin = ctrl->iomux_recalced[j].pin;
3342 bank->recalced_mask |= BIT(pin);
3346 /* calculate the per-bank route_mask */
3347 for (j = 0; j < ctrl->niomux_routes; j++) {
3350 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3351 pin = ctrl->iomux_routes[j].pin;
3352 bank->route_mask |= BIT(pin);
3360 #define RK3288_GRF_GPIO6C_IOMUX 0x64
3361 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
3363 static u32 rk3288_grf_gpio6c_iomux;
3365 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
3367 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3368 int ret = pinctrl_force_sleep(info->pctl_dev);
3374 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3375 * the setting here, and restore it at resume.
3377 if (info->ctrl->type == RK3288) {
3378 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3379 &rk3288_grf_gpio6c_iomux);
3381 pinctrl_force_default(info->pctl_dev);
3389 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3391 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3392 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3393 rk3288_grf_gpio6c_iomux |
3394 GPIO6C6_SEL_WRITE_ENABLE);
3399 return pinctrl_force_default(info->pctl_dev);
3402 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3403 rockchip_pinctrl_resume);
3405 static int rockchip_pinctrl_probe(struct platform_device *pdev)
3407 struct rockchip_pinctrl *info;
3408 struct device *dev = &pdev->dev;
3409 struct rockchip_pin_ctrl *ctrl;
3410 struct device_node *np = pdev->dev.of_node, *node;
3411 struct resource *res;
3415 if (!dev->of_node) {
3416 dev_err(dev, "device tree node not found\n");
3420 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
3426 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3428 dev_err(dev, "driver data not available\n");
3433 node = of_parse_phandle(np, "rockchip,grf", 0);
3435 info->regmap_base = syscon_node_to_regmap(node);
3436 if (IS_ERR(info->regmap_base))
3437 return PTR_ERR(info->regmap_base);
3439 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3440 base = devm_ioremap_resource(&pdev->dev, res);
3442 return PTR_ERR(base);
3444 rockchip_regmap_config.max_register = resource_size(res) - 4;
3445 rockchip_regmap_config.name = "rockchip,pinctrl";
3446 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
3447 &rockchip_regmap_config);
3449 /* to check for the old dt-bindings */
3450 info->reg_size = resource_size(res);
3452 /* Honor the old binding, with pull registers as 2nd resource */
3453 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3454 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3455 base = devm_ioremap_resource(&pdev->dev, res);
3457 return PTR_ERR(base);
3459 rockchip_regmap_config.max_register =
3460 resource_size(res) - 4;
3461 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3462 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
3464 &rockchip_regmap_config);
3468 /* try to find the optional reference to the pmu syscon */
3469 node = of_parse_phandle(np, "rockchip,pmu", 0);
3471 info->regmap_pmu = syscon_node_to_regmap(node);
3472 if (IS_ERR(info->regmap_pmu))
3473 return PTR_ERR(info->regmap_pmu);
3476 ret = rockchip_gpiolib_register(pdev, info);
3480 ret = rockchip_pinctrl_register(pdev, info);
3482 rockchip_gpiolib_unregister(pdev, info);
3486 platform_set_drvdata(pdev, info);
3491 static struct rockchip_pin_bank px30_pin_banks[] = {
3492 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3497 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3502 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3507 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3514 static struct rockchip_pin_ctrl px30_pin_ctrl = {
3515 .pin_banks = px30_pin_banks,
3516 .nr_banks = ARRAY_SIZE(px30_pin_banks),
3517 .label = "PX30-GPIO",
3519 .grf_mux_offset = 0x0,
3520 .pmu_mux_offset = 0x0,
3521 .iomux_routes = px30_mux_route_data,
3522 .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
3523 .pull_calc_reg = px30_calc_pull_reg_and_bit,
3524 .drv_calc_reg = px30_calc_drv_reg_and_bit,
3525 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
3528 static struct rockchip_pin_bank rv1108_pin_banks[] = {
3529 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3533 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3534 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3535 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3538 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
3539 .pin_banks = rv1108_pin_banks,
3540 .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
3541 .label = "RV1108-GPIO",
3543 .grf_mux_offset = 0x10,
3544 .pmu_mux_offset = 0x0,
3545 .iomux_recalced = rv1108_mux_recalced_data,
3546 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
3547 .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
3548 .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
3549 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
3552 static struct rockchip_pin_bank rk2928_pin_banks[] = {
3553 PIN_BANK(0, 32, "gpio0"),
3554 PIN_BANK(1, 32, "gpio1"),
3555 PIN_BANK(2, 32, "gpio2"),
3556 PIN_BANK(3, 32, "gpio3"),
3559 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3560 .pin_banks = rk2928_pin_banks,
3561 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
3562 .label = "RK2928-GPIO",
3564 .grf_mux_offset = 0xa8,
3565 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3568 static struct rockchip_pin_bank rk3036_pin_banks[] = {
3569 PIN_BANK(0, 32, "gpio0"),
3570 PIN_BANK(1, 32, "gpio1"),
3571 PIN_BANK(2, 32, "gpio2"),
3574 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3575 .pin_banks = rk3036_pin_banks,
3576 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
3577 .label = "RK3036-GPIO",
3579 .grf_mux_offset = 0xa8,
3580 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3583 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3584 PIN_BANK(0, 32, "gpio0"),
3585 PIN_BANK(1, 32, "gpio1"),
3586 PIN_BANK(2, 32, "gpio2"),
3587 PIN_BANK(3, 32, "gpio3"),
3588 PIN_BANK(4, 32, "gpio4"),
3589 PIN_BANK(6, 16, "gpio6"),
3592 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3593 .pin_banks = rk3066a_pin_banks,
3594 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
3595 .label = "RK3066a-GPIO",
3597 .grf_mux_offset = 0xa8,
3598 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3601 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3602 PIN_BANK(0, 32, "gpio0"),
3603 PIN_BANK(1, 32, "gpio1"),
3604 PIN_BANK(2, 32, "gpio2"),
3605 PIN_BANK(3, 32, "gpio3"),
3608 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3609 .pin_banks = rk3066b_pin_banks,
3610 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
3611 .label = "RK3066b-GPIO",
3613 .grf_mux_offset = 0x60,
3616 static struct rockchip_pin_bank rk3128_pin_banks[] = {
3617 PIN_BANK(0, 32, "gpio0"),
3618 PIN_BANK(1, 32, "gpio1"),
3619 PIN_BANK(2, 32, "gpio2"),
3620 PIN_BANK(3, 32, "gpio3"),
3623 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3624 .pin_banks = rk3128_pin_banks,
3625 .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
3626 .label = "RK3128-GPIO",
3628 .grf_mux_offset = 0xa8,
3629 .iomux_recalced = rk3128_mux_recalced_data,
3630 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
3631 .iomux_routes = rk3128_mux_route_data,
3632 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
3633 .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
3636 static struct rockchip_pin_bank rk3188_pin_banks[] = {
3637 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3638 PIN_BANK(1, 32, "gpio1"),
3639 PIN_BANK(2, 32, "gpio2"),
3640 PIN_BANK(3, 32, "gpio3"),
3643 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3644 .pin_banks = rk3188_pin_banks,
3645 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
3646 .label = "RK3188-GPIO",
3648 .grf_mux_offset = 0x60,
3649 .iomux_routes = rk3188_mux_route_data,
3650 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data),
3651 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
3654 static struct rockchip_pin_bank rk3228_pin_banks[] = {
3655 PIN_BANK(0, 32, "gpio0"),
3656 PIN_BANK(1, 32, "gpio1"),
3657 PIN_BANK(2, 32, "gpio2"),
3658 PIN_BANK(3, 32, "gpio3"),
3661 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
3662 .pin_banks = rk3228_pin_banks,
3663 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
3664 .label = "RK3228-GPIO",
3666 .grf_mux_offset = 0x0,
3667 .iomux_routes = rk3228_mux_route_data,
3668 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
3669 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3670 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3673 static struct rockchip_pin_bank rk3288_pin_banks[] = {
3674 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
3679 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
3684 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3685 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3686 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3691 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
3696 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3697 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3702 PIN_BANK(8, 16, "gpio8"),
3705 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3706 .pin_banks = rk3288_pin_banks,
3707 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
3708 .label = "RK3288-GPIO",
3710 .grf_mux_offset = 0x0,
3711 .pmu_mux_offset = 0x84,
3712 .iomux_routes = rk3288_mux_route_data,
3713 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
3714 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
3715 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
3718 static struct rockchip_pin_bank rk3328_pin_banks[] = {
3719 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3720 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3721 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3725 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3732 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3733 .pin_banks = rk3328_pin_banks,
3734 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
3735 .label = "RK3328-GPIO",
3737 .grf_mux_offset = 0x0,
3738 .iomux_recalced = rk3328_mux_recalced_data,
3739 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
3740 .iomux_routes = rk3328_mux_route_data,
3741 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
3742 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3743 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3744 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
3747 static struct rockchip_pin_bank rk3368_pin_banks[] = {
3748 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3753 PIN_BANK(1, 32, "gpio1"),
3754 PIN_BANK(2, 32, "gpio2"),
3755 PIN_BANK(3, 32, "gpio3"),
3758 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3759 .pin_banks = rk3368_pin_banks,
3760 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
3761 .label = "RK3368-GPIO",
3763 .grf_mux_offset = 0x0,
3764 .pmu_mux_offset = 0x0,
3765 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
3766 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
3769 static struct rockchip_pin_bank rk3399_pin_banks[] = {
3770 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3775 DRV_TYPE_IO_1V8_ONLY,
3776 DRV_TYPE_IO_1V8_ONLY,
3777 DRV_TYPE_IO_DEFAULT,
3778 DRV_TYPE_IO_DEFAULT,
3783 PULL_TYPE_IO_1V8_ONLY,
3784 PULL_TYPE_IO_1V8_ONLY,
3785 PULL_TYPE_IO_DEFAULT,
3786 PULL_TYPE_IO_DEFAULT
3788 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3792 DRV_TYPE_IO_1V8_OR_3V0,
3793 DRV_TYPE_IO_1V8_OR_3V0,
3794 DRV_TYPE_IO_1V8_OR_3V0,
3795 DRV_TYPE_IO_1V8_OR_3V0,
3801 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3802 DRV_TYPE_IO_1V8_OR_3V0,
3803 DRV_TYPE_IO_1V8_ONLY,
3804 DRV_TYPE_IO_1V8_ONLY,
3805 PULL_TYPE_IO_DEFAULT,
3806 PULL_TYPE_IO_DEFAULT,
3807 PULL_TYPE_IO_1V8_ONLY,
3808 PULL_TYPE_IO_1V8_ONLY
3810 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3811 DRV_TYPE_IO_3V3_ONLY,
3812 DRV_TYPE_IO_3V3_ONLY,
3813 DRV_TYPE_IO_1V8_OR_3V0
3815 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3816 DRV_TYPE_IO_1V8_3V0_AUTO,
3817 DRV_TYPE_IO_1V8_OR_3V0,
3818 DRV_TYPE_IO_1V8_OR_3V0
3822 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3823 .pin_banks = rk3399_pin_banks,
3824 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
3825 .label = "RK3399-GPIO",
3827 .grf_mux_offset = 0xe000,
3828 .pmu_mux_offset = 0x0,
3829 .grf_drv_offset = 0xe100,
3830 .pmu_drv_offset = 0x80,
3831 .iomux_routes = rk3399_mux_route_data,
3832 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
3833 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
3834 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
3837 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3838 { .compatible = "rockchip,px30-pinctrl",
3839 .data = &px30_pin_ctrl },
3840 { .compatible = "rockchip,rv1108-pinctrl",
3841 .data = &rv1108_pin_ctrl },
3842 { .compatible = "rockchip,rk2928-pinctrl",
3843 .data = &rk2928_pin_ctrl },
3844 { .compatible = "rockchip,rk3036-pinctrl",
3845 .data = &rk3036_pin_ctrl },
3846 { .compatible = "rockchip,rk3066a-pinctrl",
3847 .data = &rk3066a_pin_ctrl },
3848 { .compatible = "rockchip,rk3066b-pinctrl",
3849 .data = &rk3066b_pin_ctrl },
3850 { .compatible = "rockchip,rk3128-pinctrl",
3851 .data = (void *)&rk3128_pin_ctrl },
3852 { .compatible = "rockchip,rk3188-pinctrl",
3853 .data = &rk3188_pin_ctrl },
3854 { .compatible = "rockchip,rk3228-pinctrl",
3855 .data = &rk3228_pin_ctrl },
3856 { .compatible = "rockchip,rk3288-pinctrl",
3857 .data = &rk3288_pin_ctrl },
3858 { .compatible = "rockchip,rk3328-pinctrl",
3859 .data = &rk3328_pin_ctrl },
3860 { .compatible = "rockchip,rk3368-pinctrl",
3861 .data = &rk3368_pin_ctrl },
3862 { .compatible = "rockchip,rk3399-pinctrl",
3863 .data = &rk3399_pin_ctrl },
3867 static struct platform_driver rockchip_pinctrl_driver = {
3868 .probe = rockchip_pinctrl_probe,
3870 .name = "rockchip-pinctrl",
3871 .pm = &rockchip_pinctrl_dev_pm_ops,
3872 .of_match_table = rockchip_pinctrl_dt_match,
3876 static int __init rockchip_pinctrl_drv_register(void)
3878 return platform_driver_register(&rockchip_pinctrl_driver);
3880 postcore_initcall(rockchip_pinctrl_drv_register);