1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi SoCs pinctrl driver
5 * Author: <alexandre.belloni@free-electrons.com>
6 * License: Dual MIT/GPL
7 * Copyright (c) 2017 Microsemi Corporation
10 #include <linux/gpio/driver.h>
11 #include <linux/interrupt.h>
13 #include <linux/of_device.h>
14 #include <linux/of_irq.h>
15 #include <linux/of_platform.h>
16 #include <linux/pinctrl/pinctrl.h>
17 #include <linux/pinctrl/pinmux.h>
18 #include <linux/pinctrl/pinconf.h>
19 #include <linux/pinctrl/pinconf-generic.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 #include <linux/reset.h>
23 #include <linux/slab.h>
29 #define ocelot_clrsetbits(addr, clear, set) \
30 writel((readl(addr) & ~(clear)) | (set), (addr))
32 /* PINCONFIG bits (sparx5 only) */
36 PINCONF_DRIVE_STRENGTH,
39 #define BIAS_PD_BIT BIT(4)
40 #define BIAS_PU_BIT BIT(3)
41 #define BIAS_BITS (BIAS_PD_BIT|BIAS_PU_BIT)
42 #define SCHMITT_BIT BIT(2)
43 #define DRIVE_BITS GENMASK(1, 0)
45 /* GPIO standard registers */
46 #define OCELOT_GPIO_OUT_SET 0x0
47 #define OCELOT_GPIO_OUT_CLR 0x4
48 #define OCELOT_GPIO_OUT 0x8
49 #define OCELOT_GPIO_IN 0xc
50 #define OCELOT_GPIO_OE 0x10
51 #define OCELOT_GPIO_INTR 0x14
52 #define OCELOT_GPIO_INTR_ENA 0x18
53 #define OCELOT_GPIO_INTR_IDENT 0x1c
54 #define OCELOT_GPIO_ALT0 0x20
55 #define OCELOT_GPIO_ALT1 0x24
56 #define OCELOT_GPIO_SD_MAP 0x28
58 #define OCELOT_FUNC_PER_PIN 4
169 FUNC_TWI_SLC_GATE_AD,
187 static const char *const ocelot_function_names[] = {
188 [FUNC_CAN0_a] = "can0_a",
189 [FUNC_CAN0_b] = "can0_b",
190 [FUNC_CAN1] = "can1",
191 [FUNC_CLKMON] = "clkmon",
192 [FUNC_NONE] = "none",
193 [FUNC_FC0_a] = "fc0_a",
194 [FUNC_FC0_b] = "fc0_b",
195 [FUNC_FC0_c] = "fc0_c",
196 [FUNC_FC1_a] = "fc1_a",
197 [FUNC_FC1_b] = "fc1_b",
198 [FUNC_FC1_c] = "fc1_c",
199 [FUNC_FC2_a] = "fc2_a",
200 [FUNC_FC2_b] = "fc2_b",
201 [FUNC_FC3_a] = "fc3_a",
202 [FUNC_FC3_b] = "fc3_b",
203 [FUNC_FC3_c] = "fc3_c",
204 [FUNC_FC4_a] = "fc4_a",
205 [FUNC_FC4_b] = "fc4_b",
206 [FUNC_FC4_c] = "fc4_c",
207 [FUNC_FC_SHRD0] = "fc_shrd0",
208 [FUNC_FC_SHRD1] = "fc_shrd1",
209 [FUNC_FC_SHRD2] = "fc_shrd2",
210 [FUNC_FC_SHRD3] = "fc_shrd3",
211 [FUNC_FC_SHRD4] = "fc_shrd4",
212 [FUNC_FC_SHRD5] = "fc_shrd5",
213 [FUNC_FC_SHRD6] = "fc_shrd6",
214 [FUNC_FC_SHRD7] = "fc_shrd7",
215 [FUNC_FC_SHRD8] = "fc_shrd8",
216 [FUNC_FC_SHRD9] = "fc_shrd9",
217 [FUNC_FC_SHRD10] = "fc_shrd10",
218 [FUNC_FC_SHRD11] = "fc_shrd11",
219 [FUNC_FC_SHRD12] = "fc_shrd12",
220 [FUNC_FC_SHRD13] = "fc_shrd13",
221 [FUNC_FC_SHRD14] = "fc_shrd14",
222 [FUNC_FC_SHRD15] = "fc_shrd15",
223 [FUNC_FC_SHRD16] = "fc_shrd16",
224 [FUNC_FC_SHRD17] = "fc_shrd17",
225 [FUNC_FC_SHRD18] = "fc_shrd18",
226 [FUNC_FC_SHRD19] = "fc_shrd19",
227 [FUNC_FC_SHRD20] = "fc_shrd20",
228 [FUNC_GPIO] = "gpio",
229 [FUNC_IB_TRG_a] = "ib_trig_a",
230 [FUNC_IB_TRG_b] = "ib_trig_b",
231 [FUNC_IB_TRG_c] = "ib_trig_c",
232 [FUNC_IRQ0] = "irq0",
233 [FUNC_IRQ_IN_a] = "irq_in_a",
234 [FUNC_IRQ_IN_b] = "irq_in_b",
235 [FUNC_IRQ_IN_c] = "irq_in_c",
236 [FUNC_IRQ0_IN] = "irq0_in",
237 [FUNC_IRQ_OUT_a] = "irq_out_a",
238 [FUNC_IRQ_OUT_b] = "irq_out_b",
239 [FUNC_IRQ_OUT_c] = "irq_out_c",
240 [FUNC_IRQ0_OUT] = "irq0_out",
241 [FUNC_IRQ1] = "irq1",
242 [FUNC_IRQ1_IN] = "irq1_in",
243 [FUNC_IRQ1_OUT] = "irq1_out",
244 [FUNC_EXT_IRQ] = "ext_irq",
245 [FUNC_MIIM] = "miim",
246 [FUNC_MIIM_a] = "miim_a",
247 [FUNC_MIIM_b] = "miim_b",
248 [FUNC_MIIM_c] = "miim_c",
249 [FUNC_MIIM_Sa] = "miim_slave_a",
250 [FUNC_MIIM_Sb] = "miim_slave_b",
251 [FUNC_PHY_LED] = "phy_led",
252 [FUNC_PCI_WAKE] = "pci_wake",
254 [FUNC_OB_TRG] = "ob_trig",
255 [FUNC_OB_TRG_a] = "ob_trig_a",
256 [FUNC_OB_TRG_b] = "ob_trig_b",
257 [FUNC_PTP0] = "ptp0",
258 [FUNC_PTP1] = "ptp1",
259 [FUNC_PTP2] = "ptp2",
260 [FUNC_PTP3] = "ptp3",
261 [FUNC_PTPSYNC_0] = "ptpsync_0",
262 [FUNC_PTPSYNC_1] = "ptpsync_1",
263 [FUNC_PTPSYNC_2] = "ptpsync_2",
264 [FUNC_PTPSYNC_3] = "ptpsync_3",
265 [FUNC_PTPSYNC_4] = "ptpsync_4",
266 [FUNC_PTPSYNC_5] = "ptpsync_5",
267 [FUNC_PTPSYNC_6] = "ptpsync_6",
268 [FUNC_PTPSYNC_7] = "ptpsync_7",
270 [FUNC_PWM_a] = "pwm_a",
271 [FUNC_PWM_b] = "pwm_b",
272 [FUNC_QSPI1] = "qspi1",
273 [FUNC_QSPI2] = "qspi2",
274 [FUNC_R] = "reserved",
275 [FUNC_RECO_a] = "reco_a",
276 [FUNC_RECO_b] = "reco_b",
277 [FUNC_RECO_CLK] = "reco_clk",
280 [FUNC_SFP_SD] = "sfp_sd",
284 [FUNC_SGPIO_a] = "sgpio_a",
285 [FUNC_SGPIO_b] = "sgpio_b",
288 [FUNC_TACHO] = "tacho",
289 [FUNC_TACHO_a] = "tacho_a",
290 [FUNC_TACHO_b] = "tacho_b",
292 [FUNC_TWI2] = "twi2",
293 [FUNC_TWI3] = "twi3",
294 [FUNC_TWI_SCL_M] = "twi_scl_m",
295 [FUNC_TWI_SLC_GATE] = "twi_slc_gate",
296 [FUNC_TWI_SLC_GATE_AD] = "twi_slc_gate_ad",
297 [FUNC_USB_H_a] = "usb_host_a",
298 [FUNC_USB_H_b] = "usb_host_b",
299 [FUNC_USB_H_c] = "usb_host_c",
300 [FUNC_USB_S_a] = "usb_slave_a",
301 [FUNC_USB_S_b] = "usb_slave_b",
302 [FUNC_USB_S_c] = "usb_slave_c",
303 [FUNC_UART] = "uart",
304 [FUNC_UART2] = "uart2",
305 [FUNC_UART3] = "uart3",
306 [FUNC_PLL_STAT] = "pll_stat",
307 [FUNC_EMMC] = "emmc",
308 [FUNC_EMMC_SD] = "emmc_sd",
309 [FUNC_REF_CLK] = "ref_clk",
310 [FUNC_RCVRD_CLK] = "rcvrd_clk",
313 struct ocelot_pmx_func {
315 unsigned int ngroups;
318 struct ocelot_pin_caps {
320 unsigned char functions[OCELOT_FUNC_PER_PIN];
321 unsigned char a_functions[OCELOT_FUNC_PER_PIN]; /* Additional functions */
324 struct ocelot_pinctrl {
326 struct pinctrl_dev *pctl;
327 struct gpio_chip gpio_chip;
329 struct regmap *pincfg;
330 struct pinctrl_desc *desc;
331 struct ocelot_pmx_func func[FUNC_MAX];
335 #define LUTON_P(p, f0, f1) \
336 static struct ocelot_pin_caps luton_pin_##p = { \
339 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE, \
343 LUTON_P(0, SG0, NONE);
344 LUTON_P(1, SG0, NONE);
345 LUTON_P(2, SG0, NONE);
346 LUTON_P(3, SG0, NONE);
347 LUTON_P(4, TACHO, NONE);
348 LUTON_P(5, TWI, PHY_LED);
349 LUTON_P(6, TWI, PHY_LED);
350 LUTON_P(7, NONE, PHY_LED);
351 LUTON_P(8, EXT_IRQ, PHY_LED);
352 LUTON_P(9, EXT_IRQ, PHY_LED);
353 LUTON_P(10, SFP, PHY_LED);
354 LUTON_P(11, SFP, PHY_LED);
355 LUTON_P(12, SFP, PHY_LED);
356 LUTON_P(13, SFP, PHY_LED);
357 LUTON_P(14, SI, PHY_LED);
358 LUTON_P(15, SI, PHY_LED);
359 LUTON_P(16, SI, PHY_LED);
360 LUTON_P(17, SFP, PHY_LED);
361 LUTON_P(18, SFP, PHY_LED);
362 LUTON_P(19, SFP, PHY_LED);
363 LUTON_P(20, SFP, PHY_LED);
364 LUTON_P(21, SFP, PHY_LED);
365 LUTON_P(22, SFP, PHY_LED);
366 LUTON_P(23, SFP, PHY_LED);
367 LUTON_P(24, SFP, PHY_LED);
368 LUTON_P(25, SFP, PHY_LED);
369 LUTON_P(26, SFP, PHY_LED);
370 LUTON_P(27, SFP, PHY_LED);
371 LUTON_P(28, SFP, PHY_LED);
372 LUTON_P(29, PWM, NONE);
373 LUTON_P(30, UART, NONE);
374 LUTON_P(31, UART, NONE);
376 #define LUTON_PIN(n) { \
379 .drv_data = &luton_pin_##n \
382 static const struct pinctrl_pin_desc luton_pins[] = {
417 #define SERVAL_P(p, f0, f1, f2) \
418 static struct ocelot_pin_caps serval_pin_##p = { \
421 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
425 SERVAL_P(0, SG0, NONE, NONE);
426 SERVAL_P(1, SG0, NONE, NONE);
427 SERVAL_P(2, SG0, NONE, NONE);
428 SERVAL_P(3, SG0, NONE, NONE);
429 SERVAL_P(4, TACHO, NONE, NONE);
430 SERVAL_P(5, PWM, NONE, NONE);
431 SERVAL_P(6, TWI, NONE, NONE);
432 SERVAL_P(7, TWI, NONE, NONE);
433 SERVAL_P(8, SI, NONE, NONE);
434 SERVAL_P(9, SI, MD, NONE);
435 SERVAL_P(10, SI, MD, NONE);
436 SERVAL_P(11, SFP, MD, TWI_SCL_M);
437 SERVAL_P(12, SFP, MD, TWI_SCL_M);
438 SERVAL_P(13, SFP, UART2, TWI_SCL_M);
439 SERVAL_P(14, SFP, UART2, TWI_SCL_M);
440 SERVAL_P(15, SFP, PTP0, TWI_SCL_M);
441 SERVAL_P(16, SFP, PTP0, TWI_SCL_M);
442 SERVAL_P(17, SFP, PCI_WAKE, TWI_SCL_M);
443 SERVAL_P(18, SFP, NONE, TWI_SCL_M);
444 SERVAL_P(19, SFP, NONE, TWI_SCL_M);
445 SERVAL_P(20, SFP, NONE, TWI_SCL_M);
446 SERVAL_P(21, SFP, NONE, TWI_SCL_M);
447 SERVAL_P(22, NONE, NONE, NONE);
448 SERVAL_P(23, NONE, NONE, NONE);
449 SERVAL_P(24, NONE, NONE, NONE);
450 SERVAL_P(25, NONE, NONE, NONE);
451 SERVAL_P(26, UART, NONE, NONE);
452 SERVAL_P(27, UART, NONE, NONE);
453 SERVAL_P(28, IRQ0, NONE, NONE);
454 SERVAL_P(29, IRQ1, NONE, NONE);
455 SERVAL_P(30, PTP0, NONE, NONE);
456 SERVAL_P(31, PTP0, NONE, NONE);
458 #define SERVAL_PIN(n) { \
461 .drv_data = &serval_pin_##n \
464 static const struct pinctrl_pin_desc serval_pins[] = {
499 #define OCELOT_P(p, f0, f1, f2) \
500 static struct ocelot_pin_caps ocelot_pin_##p = { \
503 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
507 OCELOT_P(0, SG0, NONE, NONE);
508 OCELOT_P(1, SG0, NONE, NONE);
509 OCELOT_P(2, SG0, NONE, NONE);
510 OCELOT_P(3, SG0, NONE, NONE);
511 OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M);
512 OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE);
513 OCELOT_P(6, UART, TWI_SCL_M, NONE);
514 OCELOT_P(7, UART, TWI_SCL_M, NONE);
515 OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT);
516 OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT);
517 OCELOT_P(10, PTP2, TWI_SCL_M, SFP);
518 OCELOT_P(11, PTP3, TWI_SCL_M, SFP);
519 OCELOT_P(12, UART2, TWI_SCL_M, SFP);
520 OCELOT_P(13, UART2, TWI_SCL_M, SFP);
521 OCELOT_P(14, MIIM, TWI_SCL_M, SFP);
522 OCELOT_P(15, MIIM, TWI_SCL_M, SFP);
523 OCELOT_P(16, TWI, NONE, SI);
524 OCELOT_P(17, TWI, TWI_SCL_M, SI);
525 OCELOT_P(18, PTP0, TWI_SCL_M, NONE);
526 OCELOT_P(19, PTP1, TWI_SCL_M, NONE);
527 OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M);
528 OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M);
530 #define OCELOT_PIN(n) { \
533 .drv_data = &ocelot_pin_##n \
536 static const struct pinctrl_pin_desc ocelot_pins[] = {
561 #define JAGUAR2_P(p, f0, f1) \
562 static struct ocelot_pin_caps jaguar2_pin_##p = { \
565 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \
569 JAGUAR2_P(0, SG0, NONE);
570 JAGUAR2_P(1, SG0, NONE);
571 JAGUAR2_P(2, SG0, NONE);
572 JAGUAR2_P(3, SG0, NONE);
573 JAGUAR2_P(4, SG1, NONE);
574 JAGUAR2_P(5, SG1, NONE);
575 JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT);
576 JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT);
577 JAGUAR2_P(8, PTP0, NONE);
578 JAGUAR2_P(9, PTP1, NONE);
579 JAGUAR2_P(10, UART, NONE);
580 JAGUAR2_P(11, UART, NONE);
581 JAGUAR2_P(12, SG1, NONE);
582 JAGUAR2_P(13, SG1, NONE);
583 JAGUAR2_P(14, TWI, TWI_SCL_M);
584 JAGUAR2_P(15, TWI, NONE);
585 JAGUAR2_P(16, SI, TWI_SCL_M);
586 JAGUAR2_P(17, SI, TWI_SCL_M);
587 JAGUAR2_P(18, SI, TWI_SCL_M);
588 JAGUAR2_P(19, PCI_WAKE, NONE);
589 JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M);
590 JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M);
591 JAGUAR2_P(22, TACHO, NONE);
592 JAGUAR2_P(23, PWM, NONE);
593 JAGUAR2_P(24, UART2, NONE);
594 JAGUAR2_P(25, UART2, SI);
595 JAGUAR2_P(26, PTP2, SI);
596 JAGUAR2_P(27, PTP3, SI);
597 JAGUAR2_P(28, TWI2, SI);
598 JAGUAR2_P(29, TWI2, SI);
599 JAGUAR2_P(30, SG2, SI);
600 JAGUAR2_P(31, SG2, SI);
601 JAGUAR2_P(32, SG2, SI);
602 JAGUAR2_P(33, SG2, SI);
603 JAGUAR2_P(34, NONE, TWI_SCL_M);
604 JAGUAR2_P(35, NONE, TWI_SCL_M);
605 JAGUAR2_P(36, NONE, TWI_SCL_M);
606 JAGUAR2_P(37, NONE, TWI_SCL_M);
607 JAGUAR2_P(38, NONE, TWI_SCL_M);
608 JAGUAR2_P(39, NONE, TWI_SCL_M);
609 JAGUAR2_P(40, NONE, TWI_SCL_M);
610 JAGUAR2_P(41, NONE, TWI_SCL_M);
611 JAGUAR2_P(42, NONE, TWI_SCL_M);
612 JAGUAR2_P(43, NONE, TWI_SCL_M);
613 JAGUAR2_P(44, NONE, SFP);
614 JAGUAR2_P(45, NONE, SFP);
615 JAGUAR2_P(46, NONE, SFP);
616 JAGUAR2_P(47, NONE, SFP);
617 JAGUAR2_P(48, SFP, NONE);
618 JAGUAR2_P(49, SFP, SI);
619 JAGUAR2_P(50, SFP, SI);
620 JAGUAR2_P(51, SFP, SI);
621 JAGUAR2_P(52, SFP, NONE);
622 JAGUAR2_P(53, SFP, NONE);
623 JAGUAR2_P(54, SFP, NONE);
624 JAGUAR2_P(55, SFP, NONE);
625 JAGUAR2_P(56, MIIM, SFP);
626 JAGUAR2_P(57, MIIM, SFP);
627 JAGUAR2_P(58, MIIM, SFP);
628 JAGUAR2_P(59, MIIM, SFP);
629 JAGUAR2_P(60, NONE, NONE);
630 JAGUAR2_P(61, NONE, NONE);
631 JAGUAR2_P(62, NONE, NONE);
632 JAGUAR2_P(63, NONE, NONE);
634 #define JAGUAR2_PIN(n) { \
637 .drv_data = &jaguar2_pin_##n \
640 static const struct pinctrl_pin_desc jaguar2_pins[] = {
707 #define SERVALT_P(p, f0, f1, f2) \
708 static struct ocelot_pin_caps servalt_pin_##p = { \
711 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \
715 SERVALT_P(0, SG0, NONE, NONE);
716 SERVALT_P(1, SG0, NONE, NONE);
717 SERVALT_P(2, SG0, NONE, NONE);
718 SERVALT_P(3, SG0, NONE, NONE);
719 SERVALT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M);
720 SERVALT_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M);
721 SERVALT_P(6, UART, NONE, NONE);
722 SERVALT_P(7, UART, NONE, NONE);
723 SERVALT_P(8, SI, SFP, TWI_SCL_M);
724 SERVALT_P(9, PCI_WAKE, SFP, SI);
725 SERVALT_P(10, PTP0, SFP, TWI_SCL_M);
726 SERVALT_P(11, PTP1, SFP, TWI_SCL_M);
727 SERVALT_P(12, REF_CLK, SFP, TWI_SCL_M);
728 SERVALT_P(13, REF_CLK, SFP, TWI_SCL_M);
729 SERVALT_P(14, REF_CLK, IRQ0_OUT, SI);
730 SERVALT_P(15, REF_CLK, IRQ1_OUT, SI);
731 SERVALT_P(16, TACHO, SFP, SI);
732 SERVALT_P(17, PWM, NONE, TWI_SCL_M);
733 SERVALT_P(18, PTP2, SFP, SI);
734 SERVALT_P(19, PTP3, SFP, SI);
735 SERVALT_P(20, UART2, SFP, SI);
736 SERVALT_P(21, UART2, NONE, NONE);
737 SERVALT_P(22, MIIM, SFP, TWI2);
738 SERVALT_P(23, MIIM, SFP, TWI2);
739 SERVALT_P(24, TWI, NONE, NONE);
740 SERVALT_P(25, TWI, SFP, TWI_SCL_M);
741 SERVALT_P(26, TWI_SCL_M, SFP, SI);
742 SERVALT_P(27, TWI_SCL_M, SFP, SI);
743 SERVALT_P(28, TWI_SCL_M, SFP, SI);
744 SERVALT_P(29, TWI_SCL_M, NONE, NONE);
745 SERVALT_P(30, TWI_SCL_M, NONE, NONE);
746 SERVALT_P(31, TWI_SCL_M, NONE, NONE);
747 SERVALT_P(32, TWI_SCL_M, NONE, NONE);
748 SERVALT_P(33, RCVRD_CLK, NONE, NONE);
749 SERVALT_P(34, RCVRD_CLK, NONE, NONE);
750 SERVALT_P(35, RCVRD_CLK, NONE, NONE);
751 SERVALT_P(36, RCVRD_CLK, NONE, NONE);
753 #define SERVALT_PIN(n) { \
756 .drv_data = &servalt_pin_##n \
759 static const struct pinctrl_pin_desc servalt_pins[] = {
799 #define SPARX5_P(p, f0, f1, f2) \
800 static struct ocelot_pin_caps sparx5_pin_##p = { \
803 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \
807 SPARX5_P(0, SG0, PLL_STAT, NONE);
808 SPARX5_P(1, SG0, NONE, NONE);
809 SPARX5_P(2, SG0, NONE, NONE);
810 SPARX5_P(3, SG0, NONE, NONE);
811 SPARX5_P(4, SG1, NONE, NONE);
812 SPARX5_P(5, SG1, NONE, NONE);
813 SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP);
814 SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP);
815 SPARX5_P(8, PTP0, NONE, SFP);
816 SPARX5_P(9, PTP1, SFP, TWI_SCL_M);
817 SPARX5_P(10, UART, NONE, NONE);
818 SPARX5_P(11, UART, NONE, NONE);
819 SPARX5_P(12, SG1, NONE, NONE);
820 SPARX5_P(13, SG1, NONE, NONE);
821 SPARX5_P(14, TWI, TWI_SCL_M, NONE);
822 SPARX5_P(15, TWI, NONE, NONE);
823 SPARX5_P(16, SI, TWI_SCL_M, SFP);
824 SPARX5_P(17, SI, TWI_SCL_M, SFP);
825 SPARX5_P(18, SI, TWI_SCL_M, SFP);
826 SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP);
827 SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP);
828 SPARX5_P(21, IRQ1_OUT, TACHO, SFP);
829 SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M);
830 SPARX5_P(23, PWM, UART3, TWI_SCL_M);
831 SPARX5_P(24, PTP2, UART3, TWI_SCL_M);
832 SPARX5_P(25, PTP3, SI, TWI_SCL_M);
833 SPARX5_P(26, UART2, SI, TWI_SCL_M);
834 SPARX5_P(27, UART2, SI, TWI_SCL_M);
835 SPARX5_P(28, TWI2, SI, SFP);
836 SPARX5_P(29, TWI2, SI, SFP);
837 SPARX5_P(30, SG2, SI, PWM);
838 SPARX5_P(31, SG2, SI, TWI_SCL_M);
839 SPARX5_P(32, SG2, SI, TWI_SCL_M);
840 SPARX5_P(33, SG2, SI, SFP);
841 SPARX5_P(34, NONE, TWI_SCL_M, EMMC);
842 SPARX5_P(35, SFP, TWI_SCL_M, EMMC);
843 SPARX5_P(36, SFP, TWI_SCL_M, EMMC);
844 SPARX5_P(37, SFP, NONE, EMMC);
845 SPARX5_P(38, NONE, TWI_SCL_M, EMMC);
846 SPARX5_P(39, SI2, TWI_SCL_M, EMMC);
847 SPARX5_P(40, SI2, TWI_SCL_M, EMMC);
848 SPARX5_P(41, SI2, TWI_SCL_M, EMMC);
849 SPARX5_P(42, SI2, TWI_SCL_M, EMMC);
850 SPARX5_P(43, SI2, TWI_SCL_M, EMMC);
851 SPARX5_P(44, SI, SFP, EMMC);
852 SPARX5_P(45, SI, SFP, EMMC);
853 SPARX5_P(46, NONE, SFP, EMMC);
854 SPARX5_P(47, NONE, SFP, EMMC);
855 SPARX5_P(48, TWI3, SI, SFP);
856 SPARX5_P(49, TWI3, NONE, SFP);
857 SPARX5_P(50, SFP, NONE, TWI_SCL_M);
858 SPARX5_P(51, SFP, SI, TWI_SCL_M);
859 SPARX5_P(52, SFP, MIIM, TWI_SCL_M);
860 SPARX5_P(53, SFP, MIIM, TWI_SCL_M);
861 SPARX5_P(54, SFP, PTP2, TWI_SCL_M);
862 SPARX5_P(55, SFP, PTP3, PCI_WAKE);
863 SPARX5_P(56, MIIM, SFP, TWI_SCL_M);
864 SPARX5_P(57, MIIM, SFP, TWI_SCL_M);
865 SPARX5_P(58, MIIM, SFP, TWI_SCL_M);
866 SPARX5_P(59, MIIM, SFP, NONE);
867 SPARX5_P(60, RECO_CLK, NONE, NONE);
868 SPARX5_P(61, RECO_CLK, NONE, NONE);
869 SPARX5_P(62, RECO_CLK, PLL_STAT, NONE);
870 SPARX5_P(63, RECO_CLK, NONE, NONE);
872 #define SPARX5_PIN(n) { \
875 .drv_data = &sparx5_pin_##n \
878 static const struct pinctrl_pin_desc sparx5_pins[] = {
945 #define LAN966X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \
946 static struct ocelot_pin_caps lan966x_pin_##p = { \
949 FUNC_##f0, FUNC_##f1, FUNC_##f2, \
953 FUNC_##f4, FUNC_##f5, FUNC_##f6, \
958 /* Pinmuxing table taken from data sheet */
959 /* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */
960 LAN966X_P(0, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
961 LAN966X_P(1, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
962 LAN966X_P(2, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
963 LAN966X_P(3, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
964 LAN966X_P(4, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
965 LAN966X_P(5, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
966 LAN966X_P(6, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
967 LAN966X_P(7, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
968 LAN966X_P(8, GPIO, FC0_a, USB_H_b, NONE, USB_S_b, NONE, NONE, R);
969 LAN966X_P(9, GPIO, FC0_a, USB_H_b, NONE, NONE, NONE, NONE, R);
970 LAN966X_P(10, GPIO, FC0_a, NONE, NONE, NONE, NONE, NONE, R);
971 LAN966X_P(11, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R);
972 LAN966X_P(12, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R);
973 LAN966X_P(13, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R);
974 LAN966X_P(14, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R);
975 LAN966X_P(15, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R);
976 LAN966X_P(16, GPIO, FC2_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R);
977 LAN966X_P(17, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R);
978 LAN966X_P(18, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R);
979 LAN966X_P(19, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R);
980 LAN966X_P(20, GPIO, FC4_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, NONE, R);
981 LAN966X_P(21, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R);
982 LAN966X_P(22, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R);
983 LAN966X_P(23, GPIO, NONE, NONE, NONE, OB_TRG_a, NONE, NONE, R);
984 LAN966X_P(24, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_IN_c, TACHO_a, R);
985 LAN966X_P(25, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_OUT_c, SFP_SD, R);
986 LAN966X_P(26, GPIO, FC0_b, IB_TRG_a, USB_S_c, OB_TRG_a, CAN0_a, SFP_SD, R);
987 LAN966X_P(27, GPIO, NONE, NONE, NONE, OB_TRG_a, CAN0_a, PWM_a, R);
988 LAN966X_P(28, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, IRQ_OUT_c, SFP_SD, R);
989 LAN966X_P(29, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, NONE, NONE, R);
990 LAN966X_P(30, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R);
991 LAN966X_P(31, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R);
992 LAN966X_P(32, GPIO, FC3_c, NONE, SGPIO_a, NONE, MIIM_Sa, NONE, R);
993 LAN966X_P(33, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R);
994 LAN966X_P(34, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R);
995 LAN966X_P(35, GPIO, FC1_b, PTPSYNC_0, SGPIO_a, CAN0_b, NONE, NONE, R);
996 LAN966X_P(36, GPIO, NONE, PTPSYNC_1, NONE, CAN0_b, NONE, NONE, R);
997 LAN966X_P(37, GPIO, FC_SHRD0, PTPSYNC_2, TWI_SLC_GATE_AD, NONE, NONE, NONE, R);
998 LAN966X_P(38, GPIO, NONE, PTPSYNC_3, NONE, NONE, NONE, NONE, R);
999 LAN966X_P(39, GPIO, NONE, PTPSYNC_4, NONE, NONE, NONE, NONE, R);
1000 LAN966X_P(40, GPIO, FC_SHRD1, PTPSYNC_5, NONE, NONE, NONE, NONE, R);
1001 LAN966X_P(41, GPIO, FC_SHRD2, PTPSYNC_6, TWI_SLC_GATE_AD, NONE, NONE, NONE, R);
1002 LAN966X_P(42, GPIO, FC_SHRD3, PTPSYNC_7, TWI_SLC_GATE_AD, NONE, NONE, NONE, R);
1003 LAN966X_P(43, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R);
1004 LAN966X_P(44, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R);
1005 LAN966X_P(45, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, NONE, IRQ_IN_a, R);
1006 LAN966X_P(46, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD4, IRQ_IN_a, R);
1007 LAN966X_P(47, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD5, IRQ_IN_a, R);
1008 LAN966X_P(48, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD6, IRQ_IN_a, R);
1009 LAN966X_P(49, GPIO, FC_SHRD7, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, IRQ_IN_a, R);
1010 LAN966X_P(50, GPIO, FC_SHRD16, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, NONE, R);
1011 LAN966X_P(51, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, PWM_b, IRQ_IN_b, R);
1012 LAN966X_P(52, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TACHO_b, IRQ_IN_b, R);
1013 LAN966X_P(53, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R);
1014 LAN966X_P(54, GPIO, FC_SHRD8, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R);
1015 LAN966X_P(55, GPIO, FC_SHRD9, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R);
1016 LAN966X_P(56, GPIO, FC4_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, FC_SHRD10, IRQ_IN_b, R);
1017 LAN966X_P(57, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD11, IRQ_IN_b, R);
1018 LAN966X_P(58, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD12, IRQ_IN_b, R);
1019 LAN966X_P(59, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R);
1020 LAN966X_P(60, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R);
1021 LAN966X_P(61, GPIO, QSPI1, NONE, SGPIO_b, FC0_c, MIIM_Sb, NONE, R);
1022 LAN966X_P(62, GPIO, QSPI1, FC_SHRD13, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R);
1023 LAN966X_P(63, GPIO, QSPI1, FC_SHRD14, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R);
1024 LAN966X_P(64, GPIO, QSPI1, FC4_c, SGPIO_b, FC_SHRD15, TWI_SLC_GATE, SFP_SD, R);
1025 LAN966X_P(65, GPIO, USB_H_a, FC4_c, NONE, IRQ_OUT_c, TWI_SLC_GATE_AD, NONE, R);
1026 LAN966X_P(66, GPIO, USB_H_a, FC4_c, USB_S_a, IRQ_OUT_c, IRQ_IN_c, NONE, R);
1027 LAN966X_P(67, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
1028 LAN966X_P(68, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
1029 LAN966X_P(69, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
1030 LAN966X_P(70, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
1031 LAN966X_P(71, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
1032 LAN966X_P(72, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
1033 LAN966X_P(73, GPIO, EMMC, NONE, NONE, SD, NONE, NONE, R);
1034 LAN966X_P(74, GPIO, EMMC, NONE, FC_SHRD17, SD, TWI_SLC_GATE, NONE, R);
1035 LAN966X_P(75, GPIO, EMMC, NONE, FC_SHRD18, SD, TWI_SLC_GATE, NONE, R);
1036 LAN966X_P(76, GPIO, EMMC, NONE, FC_SHRD19, SD, TWI_SLC_GATE, NONE, R);
1037 LAN966X_P(77, GPIO, EMMC_SD, NONE, FC_SHRD20, NONE, TWI_SLC_GATE, NONE, R);
1039 #define LAN966X_PIN(n) { \
1041 .name = "GPIO_"#n, \
1042 .drv_data = &lan966x_pin_##n \
1045 static const struct pinctrl_pin_desc lan966x_pins[] = {
1126 static int ocelot_get_functions_count(struct pinctrl_dev *pctldev)
1128 return ARRAY_SIZE(ocelot_function_names);
1131 static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev,
1132 unsigned int function)
1134 return ocelot_function_names[function];
1137 static int ocelot_get_function_groups(struct pinctrl_dev *pctldev,
1138 unsigned int function,
1139 const char *const **groups,
1140 unsigned *const num_groups)
1142 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1144 *groups = info->func[function].groups;
1145 *num_groups = info->func[function].ngroups;
1150 static int ocelot_pin_function_idx(struct ocelot_pinctrl *info,
1151 unsigned int pin, unsigned int function)
1153 struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data;
1156 for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) {
1157 if (function == p->functions[i])
1160 if (function == p->a_functions[i])
1161 return i + OCELOT_FUNC_PER_PIN;
1167 #define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32))))
1169 static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
1170 unsigned int selector, unsigned int group)
1172 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1173 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data;
1174 unsigned int p = pin->pin % 32;
1177 f = ocelot_pin_function_idx(info, group, selector);
1182 * f is encoded on two bits.
1183 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of
1185 * This is racy because both registers can't be updated at the same time
1186 * but it doesn't matter much for now.
1187 * Note: ALT0/ALT1 are organized specially for 64 gpio targets
1189 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
1191 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
1192 BIT(p), f << (p - 1));
1197 static int lan966x_pinmux_set_mux(struct pinctrl_dev *pctldev,
1198 unsigned int selector, unsigned int group)
1200 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1201 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data;
1202 unsigned int p = pin->pin % 32;
1205 f = ocelot_pin_function_idx(info, group, selector);
1210 * f is encoded on three bits.
1211 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of
1212 * ALT[1], bit 2 of f goes in BIT(pin) of ALT[2]
1213 * This is racy because three registers can't be updated at the same time
1214 * but it doesn't matter much for now.
1215 * Note: ALT0/ALT1/ALT2 are organized specially for 78 gpio targets
1217 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
1219 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
1220 BIT(p), (f >> 1) << p);
1221 regmap_update_bits(info->map, REG_ALT(2, info, pin->pin),
1222 BIT(p), (f >> 2) << p);
1227 #define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))
1229 static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
1230 struct pinctrl_gpio_range *range,
1231 unsigned int pin, bool input)
1233 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1234 unsigned int p = pin % 32;
1236 regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p),
1237 input ? 0 : BIT(p));
1242 static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev,
1243 struct pinctrl_gpio_range *range,
1244 unsigned int offset)
1246 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1247 unsigned int p = offset % 32;
1249 regmap_update_bits(info->map, REG_ALT(0, info, offset),
1251 regmap_update_bits(info->map, REG_ALT(1, info, offset),
1257 static int lan966x_gpio_request_enable(struct pinctrl_dev *pctldev,
1258 struct pinctrl_gpio_range *range,
1259 unsigned int offset)
1261 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1262 unsigned int p = offset % 32;
1264 regmap_update_bits(info->map, REG_ALT(0, info, offset),
1266 regmap_update_bits(info->map, REG_ALT(1, info, offset),
1268 regmap_update_bits(info->map, REG_ALT(2, info, offset),
1274 static const struct pinmux_ops ocelot_pmx_ops = {
1275 .get_functions_count = ocelot_get_functions_count,
1276 .get_function_name = ocelot_get_function_name,
1277 .get_function_groups = ocelot_get_function_groups,
1278 .set_mux = ocelot_pinmux_set_mux,
1279 .gpio_set_direction = ocelot_gpio_set_direction,
1280 .gpio_request_enable = ocelot_gpio_request_enable,
1283 static const struct pinmux_ops lan966x_pmx_ops = {
1284 .get_functions_count = ocelot_get_functions_count,
1285 .get_function_name = ocelot_get_function_name,
1286 .get_function_groups = ocelot_get_function_groups,
1287 .set_mux = lan966x_pinmux_set_mux,
1288 .gpio_set_direction = ocelot_gpio_set_direction,
1289 .gpio_request_enable = lan966x_gpio_request_enable,
1292 static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev)
1294 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1296 return info->desc->npins;
1299 static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev,
1302 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1304 return info->desc->pins[group].name;
1307 static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev,
1309 const unsigned int **pins,
1310 unsigned int *num_pins)
1312 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1314 *pins = &info->desc->pins[group].number;
1320 static int ocelot_hw_get_value(struct ocelot_pinctrl *info,
1325 int ret = -EOPNOTSUPP;
1330 ret = regmap_read(info->pincfg, pin, ®cfg);
1337 *val = regcfg & BIAS_BITS;
1340 case PINCONF_SCHMITT:
1341 *val = regcfg & SCHMITT_BIT;
1344 case PINCONF_DRIVE_STRENGTH:
1345 *val = regcfg & DRIVE_BITS;
1356 static int ocelot_pincfg_clrsetbits(struct ocelot_pinctrl *info, u32 regaddr,
1357 u32 clrbits, u32 setbits)
1362 ret = regmap_read(info->pincfg, regaddr, &val);
1369 ret = regmap_write(info->pincfg, regaddr, val);
1374 static int ocelot_hw_set_value(struct ocelot_pinctrl *info,
1379 int ret = -EOPNOTSUPP;
1386 ret = ocelot_pincfg_clrsetbits(info, pin, BIAS_BITS,
1390 case PINCONF_SCHMITT:
1391 ret = ocelot_pincfg_clrsetbits(info, pin, SCHMITT_BIT,
1395 case PINCONF_DRIVE_STRENGTH:
1397 ret = ocelot_pincfg_clrsetbits(info, pin,
1411 static int ocelot_pinconf_get(struct pinctrl_dev *pctldev,
1412 unsigned int pin, unsigned long *config)
1414 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1415 u32 param = pinconf_to_config_param(*config);
1419 case PIN_CONFIG_BIAS_DISABLE:
1420 case PIN_CONFIG_BIAS_PULL_UP:
1421 case PIN_CONFIG_BIAS_PULL_DOWN:
1422 err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val);
1425 if (param == PIN_CONFIG_BIAS_DISABLE)
1427 else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
1428 val = (val & BIAS_PD_BIT ? true : false);
1429 else /* PIN_CONFIG_BIAS_PULL_UP */
1430 val = (val & BIAS_PU_BIT ? true : false);
1433 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1434 err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val);
1438 val = (val & SCHMITT_BIT ? true : false);
1441 case PIN_CONFIG_DRIVE_STRENGTH:
1442 err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH,
1448 case PIN_CONFIG_OUTPUT:
1449 err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin),
1453 val = !!(val & BIT(pin % 32));
1456 case PIN_CONFIG_INPUT_ENABLE:
1457 case PIN_CONFIG_OUTPUT_ENABLE:
1458 err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin),
1462 val = val & BIT(pin % 32);
1463 if (param == PIN_CONFIG_OUTPUT_ENABLE)
1473 *config = pinconf_to_config_packed(param, val);
1478 static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1479 unsigned long *configs, unsigned int num_configs)
1481 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1485 for (cfg = 0; cfg < num_configs; cfg++) {
1486 param = pinconf_to_config_param(configs[cfg]);
1487 arg = pinconf_to_config_argument(configs[cfg]);
1490 case PIN_CONFIG_BIAS_DISABLE:
1491 case PIN_CONFIG_BIAS_PULL_UP:
1492 case PIN_CONFIG_BIAS_PULL_DOWN:
1493 arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
1494 (param == PIN_CONFIG_BIAS_PULL_UP) ? BIAS_PU_BIT :
1497 err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg);
1503 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1504 arg = arg ? SCHMITT_BIT : 0;
1505 err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT,
1512 case PIN_CONFIG_DRIVE_STRENGTH:
1513 err = ocelot_hw_set_value(info, pin,
1514 PINCONF_DRIVE_STRENGTH,
1521 case PIN_CONFIG_OUTPUT_ENABLE:
1522 case PIN_CONFIG_INPUT_ENABLE:
1523 case PIN_CONFIG_OUTPUT:
1526 regmap_write(info->map,
1527 REG(OCELOT_GPIO_OUT_SET, info,
1531 regmap_write(info->map,
1532 REG(OCELOT_GPIO_OUT_CLR, info,
1535 regmap_update_bits(info->map,
1536 REG(OCELOT_GPIO_OE, info, pin),
1538 param == PIN_CONFIG_INPUT_ENABLE ?
1550 static const struct pinconf_ops ocelot_confops = {
1552 .pin_config_get = ocelot_pinconf_get,
1553 .pin_config_set = ocelot_pinconf_set,
1554 .pin_config_config_dbg_show = pinconf_generic_dump_config,
1557 static const struct pinctrl_ops ocelot_pctl_ops = {
1558 .get_groups_count = ocelot_pctl_get_groups_count,
1559 .get_group_name = ocelot_pctl_get_group_name,
1560 .get_group_pins = ocelot_pctl_get_group_pins,
1561 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1562 .dt_free_map = pinconf_generic_dt_free_map,
1565 static struct pinctrl_desc luton_desc = {
1566 .name = "luton-pinctrl",
1568 .npins = ARRAY_SIZE(luton_pins),
1569 .pctlops = &ocelot_pctl_ops,
1570 .pmxops = &ocelot_pmx_ops,
1571 .owner = THIS_MODULE,
1574 static struct pinctrl_desc serval_desc = {
1575 .name = "serval-pinctrl",
1576 .pins = serval_pins,
1577 .npins = ARRAY_SIZE(serval_pins),
1578 .pctlops = &ocelot_pctl_ops,
1579 .pmxops = &ocelot_pmx_ops,
1580 .owner = THIS_MODULE,
1583 static struct pinctrl_desc ocelot_desc = {
1584 .name = "ocelot-pinctrl",
1585 .pins = ocelot_pins,
1586 .npins = ARRAY_SIZE(ocelot_pins),
1587 .pctlops = &ocelot_pctl_ops,
1588 .pmxops = &ocelot_pmx_ops,
1589 .owner = THIS_MODULE,
1592 static struct pinctrl_desc jaguar2_desc = {
1593 .name = "jaguar2-pinctrl",
1594 .pins = jaguar2_pins,
1595 .npins = ARRAY_SIZE(jaguar2_pins),
1596 .pctlops = &ocelot_pctl_ops,
1597 .pmxops = &ocelot_pmx_ops,
1598 .owner = THIS_MODULE,
1601 static struct pinctrl_desc servalt_desc = {
1602 .name = "servalt-pinctrl",
1603 .pins = servalt_pins,
1604 .npins = ARRAY_SIZE(servalt_pins),
1605 .pctlops = &ocelot_pctl_ops,
1606 .pmxops = &ocelot_pmx_ops,
1607 .owner = THIS_MODULE,
1610 static struct pinctrl_desc sparx5_desc = {
1611 .name = "sparx5-pinctrl",
1612 .pins = sparx5_pins,
1613 .npins = ARRAY_SIZE(sparx5_pins),
1614 .pctlops = &ocelot_pctl_ops,
1615 .pmxops = &ocelot_pmx_ops,
1616 .confops = &ocelot_confops,
1617 .owner = THIS_MODULE,
1620 static struct pinctrl_desc lan966x_desc = {
1621 .name = "lan966x-pinctrl",
1622 .pins = lan966x_pins,
1623 .npins = ARRAY_SIZE(lan966x_pins),
1624 .pctlops = &ocelot_pctl_ops,
1625 .pmxops = &lan966x_pmx_ops,
1626 .confops = &ocelot_confops,
1627 .owner = THIS_MODULE,
1630 static int ocelot_create_group_func_map(struct device *dev,
1631 struct ocelot_pinctrl *info)
1634 u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL);
1639 for (f = 0; f < FUNC_MAX; f++) {
1640 for (npins = 0, i = 0; i < info->desc->npins; i++) {
1641 if (ocelot_pin_function_idx(info, i, f) >= 0)
1648 info->func[f].ngroups = npins;
1649 info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *),
1651 if (!info->func[f].groups) {
1656 for (i = 0; i < npins; i++)
1657 info->func[f].groups[i] =
1658 info->desc->pins[pins[i]].name;
1666 static int ocelot_pinctrl_register(struct platform_device *pdev,
1667 struct ocelot_pinctrl *info)
1671 ret = ocelot_create_group_func_map(&pdev->dev, info);
1673 dev_err(&pdev->dev, "Unable to create group func map.\n");
1677 info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info);
1678 if (IS_ERR(info->pctl)) {
1679 dev_err(&pdev->dev, "Failed to register pinctrl\n");
1680 return PTR_ERR(info->pctl);
1686 static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset)
1688 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1691 regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val);
1693 return !!(val & BIT(offset % 32));
1696 static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset,
1699 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1702 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
1705 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
1709 static int ocelot_gpio_get_direction(struct gpio_chip *chip,
1710 unsigned int offset)
1712 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1715 regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val);
1717 if (val & BIT(offset % 32))
1718 return GPIO_LINE_DIRECTION_OUT;
1720 return GPIO_LINE_DIRECTION_IN;
1723 static int ocelot_gpio_direction_input(struct gpio_chip *chip,
1724 unsigned int offset)
1726 return pinctrl_gpio_direction_input(chip->base + offset);
1729 static int ocelot_gpio_direction_output(struct gpio_chip *chip,
1730 unsigned int offset, int value)
1732 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1733 unsigned int pin = BIT(offset % 32);
1736 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
1739 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
1742 return pinctrl_gpio_direction_output(chip->base + offset);
1745 static const struct gpio_chip ocelot_gpiolib_chip = {
1746 .request = gpiochip_generic_request,
1747 .free = gpiochip_generic_free,
1748 .set = ocelot_gpio_set,
1749 .get = ocelot_gpio_get,
1750 .get_direction = ocelot_gpio_get_direction,
1751 .direction_input = ocelot_gpio_direction_input,
1752 .direction_output = ocelot_gpio_direction_output,
1753 .owner = THIS_MODULE,
1756 static void ocelot_irq_mask(struct irq_data *data)
1758 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1759 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1760 unsigned int gpio = irqd_to_hwirq(data);
1762 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
1766 static void ocelot_irq_unmask(struct irq_data *data)
1768 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1769 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1770 unsigned int gpio = irqd_to_hwirq(data);
1772 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
1773 BIT(gpio % 32), BIT(gpio % 32));
1776 static void ocelot_irq_ack(struct irq_data *data)
1778 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1779 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1780 unsigned int gpio = irqd_to_hwirq(data);
1782 regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio),
1783 BIT(gpio % 32), BIT(gpio % 32));
1786 static int ocelot_irq_set_type(struct irq_data *data, unsigned int type);
1788 static struct irq_chip ocelot_eoi_irqchip = {
1790 .irq_mask = ocelot_irq_mask,
1791 .irq_eoi = ocelot_irq_ack,
1792 .irq_unmask = ocelot_irq_unmask,
1793 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED,
1794 .irq_set_type = ocelot_irq_set_type,
1797 static struct irq_chip ocelot_irqchip = {
1799 .irq_mask = ocelot_irq_mask,
1800 .irq_ack = ocelot_irq_ack,
1801 .irq_unmask = ocelot_irq_unmask,
1802 .irq_set_type = ocelot_irq_set_type,
1805 static int ocelot_irq_set_type(struct irq_data *data, unsigned int type)
1807 type &= IRQ_TYPE_SENSE_MASK;
1809 if (!(type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_HIGH)))
1812 if (type & IRQ_TYPE_LEVEL_HIGH)
1813 irq_set_chip_handler_name_locked(data, &ocelot_eoi_irqchip,
1814 handle_fasteoi_irq, NULL);
1815 if (type & IRQ_TYPE_EDGE_BOTH)
1816 irq_set_chip_handler_name_locked(data, &ocelot_irqchip,
1817 handle_edge_irq, NULL);
1822 static void ocelot_irq_handler(struct irq_desc *desc)
1824 struct irq_chip *parent_chip = irq_desc_get_chip(desc);
1825 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
1826 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1827 unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride;
1828 unsigned int reg = 0, irq, i;
1831 for (i = 0; i < info->stride; i++) {
1832 regmap_read(info->map, id_reg + 4 * i, ®);
1836 chained_irq_enter(parent_chip, desc);
1840 for_each_set_bit(irq, &irqs,
1841 min(32U, info->desc->npins - 32 * i))
1842 generic_handle_domain_irq(chip->irq.domain, irq + 32 * i);
1844 chained_irq_exit(parent_chip, desc);
1848 static int ocelot_gpiochip_register(struct platform_device *pdev,
1849 struct ocelot_pinctrl *info)
1851 struct gpio_chip *gc;
1852 struct gpio_irq_chip *girq;
1855 info->gpio_chip = ocelot_gpiolib_chip;
1857 gc = &info->gpio_chip;
1858 gc->ngpio = info->desc->npins;
1859 gc->parent = &pdev->dev;
1861 gc->label = "ocelot-gpio";
1863 irq = platform_get_irq_optional(pdev, 0);
1866 girq->chip = &ocelot_irqchip;
1867 girq->parent_handler = ocelot_irq_handler;
1868 girq->num_parents = 1;
1869 girq->parents = devm_kcalloc(&pdev->dev, 1,
1870 sizeof(*girq->parents),
1874 girq->parents[0] = irq;
1875 girq->default_type = IRQ_TYPE_NONE;
1876 girq->handler = handle_edge_irq;
1879 return devm_gpiochip_add_data(&pdev->dev, gc, info);
1882 static const struct of_device_id ocelot_pinctrl_of_match[] = {
1883 { .compatible = "mscc,luton-pinctrl", .data = &luton_desc },
1884 { .compatible = "mscc,serval-pinctrl", .data = &serval_desc },
1885 { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc },
1886 { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc },
1887 { .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc },
1888 { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc },
1889 { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc },
1893 static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev)
1897 const struct regmap_config regmap_config = {
1905 base = devm_platform_ioremap_resource(pdev, 1);
1907 dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n");
1911 return devm_regmap_init_mmio(&pdev->dev, base, ®map_config);
1914 static int ocelot_pinctrl_probe(struct platform_device *pdev)
1916 struct device *dev = &pdev->dev;
1917 struct ocelot_pinctrl *info;
1918 struct reset_control *reset;
1919 struct regmap *pincfg;
1922 struct regmap_config regmap_config = {
1928 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
1932 info->desc = (struct pinctrl_desc *)device_get_match_data(dev);
1934 reset = devm_reset_control_get_optional_shared(dev, "switch");
1936 return dev_err_probe(dev, PTR_ERR(reset),
1937 "Failed to get reset\n");
1938 reset_control_reset(reset);
1940 base = devm_ioremap_resource(dev,
1941 platform_get_resource(pdev, IORESOURCE_MEM, 0));
1943 return PTR_ERR(base);
1945 info->stride = 1 + (info->desc->npins - 1) / 32;
1947 regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4;
1949 info->map = devm_regmap_init_mmio(dev, base, ®map_config);
1950 if (IS_ERR(info->map)) {
1951 dev_err(dev, "Failed to create regmap\n");
1952 return PTR_ERR(info->map);
1954 dev_set_drvdata(dev, info->map);
1957 /* Pinconf registers */
1958 if (info->desc->confops) {
1959 pincfg = ocelot_pinctrl_create_pincfg(pdev);
1961 dev_dbg(dev, "Failed to create pincfg regmap\n");
1963 info->pincfg = pincfg;
1966 ret = ocelot_pinctrl_register(pdev, info);
1970 ret = ocelot_gpiochip_register(pdev, info);
1974 dev_info(dev, "driver registered\n");
1979 static struct platform_driver ocelot_pinctrl_driver = {
1981 .name = "pinctrl-ocelot",
1982 .of_match_table = of_match_ptr(ocelot_pinctrl_of_match),
1983 .suppress_bind_attrs = true,
1985 .probe = ocelot_pinctrl_probe,
1987 builtin_platform_driver(ocelot_pinctrl_driver);