drivers/pinctrl/pinctrl-ingenic.c

   1 /*
   2  * Ingenic SoCs pinctrl driver
   3  *
   4  * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net>
   5  *
   6  * License terms: GNU General Public License (GPL) version 2
   7  */
   8
   9 #include <linux/compiler.h>
  10 #include <linux/gpio/driver.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/io.h>
  13 #include <linux/of_device.h>
  14 #include <linux/of_irq.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/pinctrl/pinctrl.h>
  17 #include <linux/pinctrl/pinmux.h>
  18 #include <linux/pinctrl/pinconf.h>
  19 #include <linux/pinctrl/pinconf-generic.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/regmap.h>
  22 #include <linux/slab.h>
  23
  24 #include "core.h"
  25 #include "pinconf.h"
  26 #include "pinmux.h"
  27
  28 #define GPIO_PIN        0x00
  29 #define GPIO_MSK        0x20
  30
  31 #define JZ4740_GPIO_DATA        0x10
  32 #define JZ4740_GPIO_PULL_DIS    0x30
  33 #define JZ4740_GPIO_FUNC        0x40
  34 #define JZ4740_GPIO_SELECT      0x50
  35 #define JZ4740_GPIO_DIR         0x60
  36 #define JZ4740_GPIO_TRIG        0x70
  37 #define JZ4740_GPIO_FLAG        0x80
  38
  39 #define JZ4770_GPIO_INT         0x10
  40 #define JZ4770_GPIO_PAT1        0x30
  41 #define JZ4770_GPIO_PAT0        0x40
  42 #define JZ4770_GPIO_FLAG        0x50
  43 #define JZ4770_GPIO_PEN         0x70
  44
  45 #define REG_SET(x) ((x) + 0x4)
  46 #define REG_CLEAR(x) ((x) + 0x8)
  47
  48 #define PINS_PER_GPIO_CHIP 32
  49
  50 enum jz_version {
  51         ID_JZ4740,
  52         ID_JZ4725B,
  53         ID_JZ4770,
  54         ID_JZ4780,
  55 };
  56
  57 struct ingenic_chip_info {
  58         unsigned int num_chips;
  59
  60         const struct group_desc *groups;
  61         unsigned int num_groups;
  62
  63         const struct function_desc *functions;
  64         unsigned int num_functions;
  65
  66         const u32 *pull_ups, *pull_downs;
  67 };
  68
  69 struct ingenic_pinctrl {
  70         struct device *dev;
  71         struct regmap *map;
  72         struct pinctrl_dev *pctl;
  73         struct pinctrl_pin_desc *pdesc;
  74         enum jz_version version;
  75
  76         const struct ingenic_chip_info *info;
  77 };
  78
  79 struct ingenic_gpio_chip {
  80         struct ingenic_pinctrl *jzpc;
  81         struct gpio_chip gc;
  82         struct irq_chip irq_chip;
  83         unsigned int irq, reg_base;
  84 };
  85
  86 static const u32 jz4740_pull_ups[4] = {
  87         0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  88 };
  89
  90 static const u32 jz4740_pull_downs[4] = {
  91         0x00000000, 0x00000000, 0x00000000, 0x00000000,
  92 };
  93
  94 static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, };
  95 static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };
  96 static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, };
  97 static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
  98 static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, };
  99 static int jz4740_lcd_8bit_pins[] = {
 100         0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x52, 0x53, 0x54,
 101 };
 102 static int jz4740_lcd_16bit_pins[] = {
 103         0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x55,
 104 };
 105 static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, };
 106 static int jz4740_lcd_18bit_tft_pins[] = { 0x56, 0x57, 0x31, 0x32, };
 107 static int jz4740_nand_cs1_pins[] = { 0x39, };
 108 static int jz4740_nand_cs2_pins[] = { 0x3a, };
 109 static int jz4740_nand_cs3_pins[] = { 0x3b, };
 110 static int jz4740_nand_cs4_pins[] = { 0x3c, };
 111 static int jz4740_pwm_pwm0_pins[] = { 0x77, };
 112 static int jz4740_pwm_pwm1_pins[] = { 0x78, };
 113 static int jz4740_pwm_pwm2_pins[] = { 0x79, };
 114 static int jz4740_pwm_pwm3_pins[] = { 0x7a, };
 115 static int jz4740_pwm_pwm4_pins[] = { 0x7b, };
 116 static int jz4740_pwm_pwm5_pins[] = { 0x7c, };
 117 static int jz4740_pwm_pwm6_pins[] = { 0x7e, };
 118 static int jz4740_pwm_pwm7_pins[] = { 0x7f, };
 119
 120 static int jz4740_mmc_1bit_funcs[] = { 0, 0, 0, };
 121 static int jz4740_mmc_4bit_funcs[] = { 0, 0, 0, };
 122 static int jz4740_uart0_data_funcs[] = { 1, 1, };
 123 static int jz4740_uart0_hwflow_funcs[] = { 1, 1, };
 124 static int jz4740_uart1_data_funcs[] = { 2, 2, };
 125 static int jz4740_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
 126 static int jz4740_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, };
 127 static int jz4740_lcd_18bit_funcs[] = { 0, 0, };
 128 static int jz4740_lcd_18bit_tft_funcs[] = { 0, 0, 0, 0, };
 129 static int jz4740_nand_cs1_funcs[] = { 0, };
 130 static int jz4740_nand_cs2_funcs[] = { 0, };
 131 static int jz4740_nand_cs3_funcs[] = { 0, };
 132 static int jz4740_nand_cs4_funcs[] = { 0, };
 133 static int jz4740_pwm_pwm0_funcs[] = { 0, };
 134 static int jz4740_pwm_pwm1_funcs[] = { 0, };
 135 static int jz4740_pwm_pwm2_funcs[] = { 0, };
 136 static int jz4740_pwm_pwm3_funcs[] = { 0, };
 137 static int jz4740_pwm_pwm4_funcs[] = { 0, };
 138 static int jz4740_pwm_pwm5_funcs[] = { 0, };
 139 static int jz4740_pwm_pwm6_funcs[] = { 0, };
 140 static int jz4740_pwm_pwm7_funcs[] = { 0, };
 141
 142 #define INGENIC_PIN_GROUP(name, id)                     \
 143         {                                               \
 144                 name,                                   \
 145                 id##_pins,                              \
 146                 ARRAY_SIZE(id##_pins),                  \
 147                 id##_funcs,                             \
 148         }
 149
 150 static const struct group_desc jz4740_groups[] = {
 151         INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit),
 152         INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit),
 153         INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data),
 154         INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow),
 155         INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data),
 156         INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit),
 157         INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit),
 158         INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit),
 159         INGENIC_PIN_GROUP("lcd-18bit-tft", jz4740_lcd_18bit_tft),
 160         { "lcd-no-pins", },
 161         INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1),
 162         INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2),
 163         INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3),
 164         INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4),
 165         INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0),
 166         INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1),
 167         INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2),
 168         INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3),
 169         INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4),
 170         INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5),
 171         INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6),
 172         INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7),
 173 };
 174
 175 static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
 176 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
 177 static const char *jz4740_uart1_groups[] = { "uart1-data", };
 178 static const char *jz4740_lcd_groups[] = {
 179         "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-18bit-tft", "lcd-no-pins",
 180 };
 181 static const char *jz4740_nand_groups[] = {
 182         "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
 183 };
 184 static const char *jz4740_pwm0_groups[] = { "pwm0", };
 185 static const char *jz4740_pwm1_groups[] = { "pwm1", };
 186 static const char *jz4740_pwm2_groups[] = { "pwm2", };
 187 static const char *jz4740_pwm3_groups[] = { "pwm3", };
 188 static const char *jz4740_pwm4_groups[] = { "pwm4", };
 189 static const char *jz4740_pwm5_groups[] = { "pwm5", };
 190 static const char *jz4740_pwm6_groups[] = { "pwm6", };
 191 static const char *jz4740_pwm7_groups[] = { "pwm7", };
 192
 193 static const struct function_desc jz4740_functions[] = {
 194         { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
 195         { "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), },
 196         { "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), },
 197         { "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), },
 198         { "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), },
 199         { "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), },
 200         { "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), },
 201         { "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), },
 202         { "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), },
 203         { "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), },
 204         { "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), },
 205         { "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), },
 206         { "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), },
 207 };
 208
 209 static const struct ingenic_chip_info jz4740_chip_info = {
 210         .num_chips = 4,
 211         .groups = jz4740_groups,
 212         .num_groups = ARRAY_SIZE(jz4740_groups),
 213         .functions = jz4740_functions,
 214         .num_functions = ARRAY_SIZE(jz4740_functions),
 215         .pull_ups = jz4740_pull_ups,
 216         .pull_downs = jz4740_pull_downs,
 217 };
 218
 219 static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, };
 220 static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, };
 221 static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, };
 222 static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, };
 223 static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, };
 224 static int jz4725b_nand_cs1_pins[] = { 0x55, };
 225 static int jz4725b_nand_cs2_pins[] = { 0x56, };
 226 static int jz4725b_nand_cs3_pins[] = { 0x57, };
 227 static int jz4725b_nand_cs4_pins[] = { 0x58, };
 228 static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 };
 229 static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d };
 230 static int jz4725b_pwm_pwm0_pins[] = { 0x4a, };
 231 static int jz4725b_pwm_pwm1_pins[] = { 0x4b, };
 232 static int jz4725b_pwm_pwm2_pins[] = { 0x4c, };
 233 static int jz4725b_pwm_pwm3_pins[] = { 0x4d, };
 234 static int jz4725b_pwm_pwm4_pins[] = { 0x4e, };
 235 static int jz4725b_pwm_pwm5_pins[] = { 0x4f, };
 236
 237 static int jz4725b_mmc0_1bit_funcs[] = { 1, 1, 1, };
 238 static int jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, };
 239 static int jz4725b_mmc1_1bit_funcs[] = { 0, 0, 0, };
 240 static int jz4725b_mmc1_4bit_funcs[] = { 0, 0, 0, };
 241 static int jz4725b_uart_data_funcs[] = { 1, 1, };
 242 static int jz4725b_nand_cs1_funcs[] = { 0, };
 243 static int jz4725b_nand_cs2_funcs[] = { 0, };
 244 static int jz4725b_nand_cs3_funcs[] = { 0, };
 245 static int jz4725b_nand_cs4_funcs[] = { 0, };
 246 static int jz4725b_nand_cle_ale_funcs[] = { 0, 0, };
 247 static int jz4725b_nand_fre_fwe_funcs[] = { 0, 0, };
 248 static int jz4725b_pwm_pwm0_funcs[] = { 0, };
 249 static int jz4725b_pwm_pwm1_funcs[] = { 0, };
 250 static int jz4725b_pwm_pwm2_funcs[] = { 0, };
 251 static int jz4725b_pwm_pwm3_funcs[] = { 0, };
 252 static int jz4725b_pwm_pwm4_funcs[] = { 0, };
 253 static int jz4725b_pwm_pwm5_funcs[] = { 0, };
 254
 255 static const struct group_desc jz4725b_groups[] = {
 256         INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit),
 257         INGENIC_PIN_GROUP("mmc0-4bit", jz4725b_mmc0_4bit),
 258         INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit),
 259         INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit),
 260         INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data),
 261         INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1),
 262         INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2),
 263         INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3),
 264         INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4),
 265         INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale),
 266         INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe),
 267         INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0),
 268         INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1),
 269         INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2),
 270         INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3),
 271         INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4),
 272         INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5),
 273 };
 274
 275 static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
 276 static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
 277 static const char *jz4725b_uart_groups[] = { "uart-data", };
 278 static const char *jz4725b_nand_groups[] = {
 279         "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
 280         "nand-cle-ale", "nand-fre-fwe",
 281 };
 282 static const char *jz4725b_pwm0_groups[] = { "pwm0", };
 283 static const char *jz4725b_pwm1_groups[] = { "pwm1", };
 284 static const char *jz4725b_pwm2_groups[] = { "pwm2", };
 285 static const char *jz4725b_pwm3_groups[] = { "pwm3", };
 286 static const char *jz4725b_pwm4_groups[] = { "pwm4", };
 287 static const char *jz4725b_pwm5_groups[] = { "pwm5", };
 288
 289 static const struct function_desc jz4725b_functions[] = {
 290         { "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), },
 291         { "mmc1", jz4725b_mmc1_groups, ARRAY_SIZE(jz4725b_mmc1_groups), },
 292         { "uart", jz4725b_uart_groups, ARRAY_SIZE(jz4725b_uart_groups), },
 293         { "nand", jz4725b_nand_groups, ARRAY_SIZE(jz4725b_nand_groups), },
 294         { "pwm0", jz4725b_pwm0_groups, ARRAY_SIZE(jz4725b_pwm0_groups), },
 295         { "pwm1", jz4725b_pwm1_groups, ARRAY_SIZE(jz4725b_pwm1_groups), },
 296         { "pwm2", jz4725b_pwm2_groups, ARRAY_SIZE(jz4725b_pwm2_groups), },
 297         { "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), },
 298         { "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), },
 299         { "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), },
 300 };
 301
 302 static const struct ingenic_chip_info jz4725b_chip_info = {
 303         .num_chips = 4,
 304         .groups = jz4725b_groups,
 305         .num_groups = ARRAY_SIZE(jz4725b_groups),
 306         .functions = jz4725b_functions,
 307         .num_functions = ARRAY_SIZE(jz4725b_functions),
 308         .pull_ups = jz4740_pull_ups,
 309         .pull_downs = jz4740_pull_downs,
 310 };
 311
 312 static const u32 jz4770_pull_ups[6] = {
 313         0x3fffffff, 0xfff0030c, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0xffa7f00f,
 314 };
 315
 316 static const u32 jz4770_pull_downs[6] = {
 317         0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0,
 318 };
 319
 320 static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, };
 321 static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
 322 static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, };
 323 static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
 324 static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, };
 325 static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
 326 static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, };
 327 static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, };
 328 static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
 329 static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
 330 static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
 331 static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
 332 static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
 333 static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
 334 static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
 335 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
 336 static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
 337 static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
 338 static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
 339 static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
 340 static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
 341 static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
 342 static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
 343 static int jz4770_nemc_8bit_data_pins[] = {
 344         0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
 345 };
 346 static int jz4770_nemc_16bit_data_pins[] = {
 347         0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
 348 };
 349 static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, };
 350 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
 351 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };
 352 static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
 353 static int jz4770_nemc_wait_pins[] = { 0x1b, };
 354 static int jz4770_nemc_cs1_pins[] = { 0x15, };
 355 static int jz4770_nemc_cs2_pins[] = { 0x16, };
 356 static int jz4770_nemc_cs3_pins[] = { 0x17, };
 357 static int jz4770_nemc_cs4_pins[] = { 0x18, };
 358 static int jz4770_nemc_cs5_pins[] = { 0x19, };
 359 static int jz4770_nemc_cs6_pins[] = { 0x1a, };
 360 static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, };
 361 static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, };
 362 static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, };
 363 static int jz4770_cim_8bit_pins[] = {
 364         0x26, 0x27, 0x28, 0x29,
 365         0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
 366 };
 367 static int jz4770_cim_12bit_pins[] = {
 368         0x32, 0x33, 0xb0, 0xb1,
 369 };
 370 static int jz4770_lcd_24bit_pins[] = {
 371         0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
 372         0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
 373         0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
 374         0x58, 0x59, 0x5a, 0x5b,
 375 };
 376 static int jz4770_pwm_pwm0_pins[] = { 0x80, };
 377 static int jz4770_pwm_pwm1_pins[] = { 0x81, };
 378 static int jz4770_pwm_pwm2_pins[] = { 0x82, };
 379 static int jz4770_pwm_pwm3_pins[] = { 0x83, };
 380 static int jz4770_pwm_pwm4_pins[] = { 0x84, };
 381 static int jz4770_pwm_pwm5_pins[] = { 0x85, };
 382 static int jz4770_pwm_pwm6_pins[] = { 0x6a, };
 383 static int jz4770_pwm_pwm7_pins[] = { 0x6b, };
 384 static int jz4770_mac_rmii_pins[] = {
 385         0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
 386 };
 387 static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, };
 388
 389 static int jz4770_uart0_data_funcs[] = { 0, 0, };
 390 static int jz4770_uart0_hwflow_funcs[] = { 0, 0, };
 391 static int jz4770_uart1_data_funcs[] = { 0, 0, };
 392 static int jz4770_uart1_hwflow_funcs[] = { 0, 0, };
 393 static int jz4770_uart2_data_funcs[] = { 0, 0, };
 394 static int jz4770_uart2_hwflow_funcs[] = { 0, 0, };
 395 static int jz4770_uart3_data_funcs[] = { 0, 1, };
 396 static int jz4770_uart3_hwflow_funcs[] = { 0, 0, };
 397 static int jz4770_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
 398 static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
 399 static int jz4770_mmc0_1bit_e_funcs[] = { 0, 0, 0, };
 400 static int jz4770_mmc0_4bit_e_funcs[] = { 0, 0, 0, };
 401 static int jz4770_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, };
 402 static int jz4770_mmc1_1bit_d_funcs[] = { 0, 0, 0, };
 403 static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
 404 static int jz4770_mmc1_1bit_e_funcs[] = { 1, 1, 1, };
 405 static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
 406 static int jz4770_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, };
 407 static int jz4770_mmc2_1bit_b_funcs[] = { 0, 0, 0, };
 408 static int jz4770_mmc2_4bit_b_funcs[] = { 0, 0, 0, };
 409 static int jz4770_mmc2_1bit_e_funcs[] = { 2, 2, 2, };
 410 static int jz4770_mmc2_4bit_e_funcs[] = { 2, 2, 2, };
 411 static int jz4770_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, };
 412 static int jz4770_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
 413 static int jz4770_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
 414 static int jz4770_nemc_cle_ale_funcs[] = { 0, 0, };
 415 static int jz4770_nemc_addr_funcs[] = { 0, 0, 0, 0, };
 416 static int jz4770_nemc_rd_we_funcs[] = { 0, 0, };
 417 static int jz4770_nemc_frd_fwe_funcs[] = { 0, 0, };
 418 static int jz4770_nemc_wait_funcs[] = { 0, };
 419 static int jz4770_nemc_cs1_funcs[] = { 0, };
 420 static int jz4770_nemc_cs2_funcs[] = { 0, };
 421 static int jz4770_nemc_cs3_funcs[] = { 0, };
 422 static int jz4770_nemc_cs4_funcs[] = { 0, };
 423 static int jz4770_nemc_cs5_funcs[] = { 0, };
 424 static int jz4770_nemc_cs6_funcs[] = { 0, };
 425 static int jz4770_i2c0_funcs[] = { 0, 0, };
 426 static int jz4770_i2c1_funcs[] = { 0, 0, };
 427 static int jz4770_i2c2_funcs[] = { 2, 2, };
 428 static int jz4770_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
 429 static int jz4770_cim_12bit_funcs[] = { 0, 0, 0, 0, };
 430 static int jz4770_lcd_24bit_funcs[] = {
 431         0, 0, 0, 0, 0, 0, 0, 0,
 432         0, 0, 0, 0, 0, 0, 0, 0,
 433         0, 0, 0, 0, 0, 0, 0, 0,
 434         0, 0, 0, 0,
 435 };
 436 static int jz4770_pwm_pwm0_funcs[] = { 0, };
 437 static int jz4770_pwm_pwm1_funcs[] = { 0, };
 438 static int jz4770_pwm_pwm2_funcs[] = { 0, };
 439 static int jz4770_pwm_pwm3_funcs[] = { 0, };
 440 static int jz4770_pwm_pwm4_funcs[] = { 0, };
 441 static int jz4770_pwm_pwm5_funcs[] = { 0, };
 442 static int jz4770_pwm_pwm6_funcs[] = { 0, };
 443 static int jz4770_pwm_pwm7_funcs[] = { 0, };
 444 static int jz4770_mac_rmii_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
 445 static int jz4770_mac_mii_funcs[] = { 0, 0, };
 446
 447 static const struct group_desc jz4770_groups[] = {
 448         INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
 449         INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow),
 450         INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data),
 451         INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow),
 452         INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data),
 453         INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow),
 454         INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
 455         INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
 456         INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
 457         INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
 458         INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
 459         INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
 460         INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e),
 461         INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
 462         INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
 463         INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
 464         INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
 465         INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e),
 466         INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b),
 467         INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b),
 468         INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e),
 469         INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e),
 470         INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e),
 471         INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data),
 472         INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data),
 473         INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
 474         INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
 475         INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
 476         INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
 477         INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait),
 478         INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
 479         INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
 480         INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
 481         INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4),
 482         INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5),
 483         INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6),
 484         INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
 485         INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
 486         INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
 487         INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit),
 488         INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit),
 489         INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
 490         { "lcd-no-pins", },
 491         INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0),
 492         INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1),
 493         INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2),
 494         INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3),
 495         INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4),
 496         INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5),
 497         INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6),
 498         INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
 499         INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii),
 500         INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii),
 501 };
 502
 503 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
 504 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
 505 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
 506 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
 507 static const char *jz4770_mmc0_groups[] = {
 508         "mmc0-1bit-a", "mmc0-4bit-a",
 509         "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
 510 };
 511 static const char *jz4770_mmc1_groups[] = {
 512         "mmc1-1bit-d", "mmc1-4bit-d",
 513         "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
 514 };
 515 static const char *jz4770_mmc2_groups[] = {
 516         "mmc2-1bit-b", "mmc2-4bit-b",
 517         "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
 518 };
 519 static const char *jz4770_nemc_groups[] = {
 520         "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
 521         "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
 522 };
 523 static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
 524 static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
 525 static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
 526 static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
 527 static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
 528 static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
 529 static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
 530 static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
 531 static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
 532 static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
 533 static const char *jz4770_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", };
 534 static const char *jz4770_pwm0_groups[] = { "pwm0", };
 535 static const char *jz4770_pwm1_groups[] = { "pwm1", };
 536 static const char *jz4770_pwm2_groups[] = { "pwm2", };
 537 static const char *jz4770_pwm3_groups[] = { "pwm3", };
 538 static const char *jz4770_pwm4_groups[] = { "pwm4", };
 539 static const char *jz4770_pwm5_groups[] = { "pwm5", };
 540 static const char *jz4770_pwm6_groups[] = { "pwm6", };
 541 static const char *jz4770_pwm7_groups[] = { "pwm7", };
 542 static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
 543
 544 static const struct function_desc jz4770_functions[] = {
 545         { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
 546         { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
 547         { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), },
 548         { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
 549         { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), },
 550         { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), },
 551         { "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), },
 552         { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), },
 553         { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
 554         { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
 555         { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
 556         { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
 557         { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
 558         { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
 559         { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
 560         { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
 561         { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
 562         { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), },
 563         { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
 564         { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
 565         { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
 566         { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
 567         { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
 568         { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
 569         { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
 570         { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
 571         { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
 572         { "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), },
 573 };
 574
 575 static const struct ingenic_chip_info jz4770_chip_info = {
 576         .num_chips = 6,
 577         .groups = jz4770_groups,
 578         .num_groups = ARRAY_SIZE(jz4770_groups),
 579         .functions = jz4770_functions,
 580         .num_functions = ARRAY_SIZE(jz4770_functions),
 581         .pull_ups = jz4770_pull_ups,
 582         .pull_downs = jz4770_pull_downs,
 583 };
 584
 585 static int jz4780_uart2_data_pins[] = { 0x66, 0x67, };
 586 static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, };
 587 static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, };
 588 static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, };
 589 static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, };
 590 static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, };
 591 static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, };
 592
 593 static int jz4780_uart2_data_funcs[] = { 1, 1, };
 594 static int jz4780_uart2_hwflow_funcs[] = { 1, 1, };
 595 static int jz4780_uart4_data_funcs[] = { 2, 2, };
 596 static int jz4780_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, };
 597 static int jz4780_i2c3_funcs[] = { 1, 1, };
 598 static int jz4780_i2c4_e_funcs[] = { 1, 1, };
 599 static int jz4780_i2c4_f_funcs[] = { 1, 1, };
 600
 601 static const struct group_desc jz4780_groups[] = {
 602         INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
 603         INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow),
 604         INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data),
 605         INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow),
 606         INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data),
 607         INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow),
 608         INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
 609         INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
 610         INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data),
 611         INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
 612         INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
 613         INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a),
 614         INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
 615         INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
 616         INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
 617         INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
 618         INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
 619         INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
 620         INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b),
 621         INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b),
 622         INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e),
 623         INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e),
 624         INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data),
 625         INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
 626         INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
 627         INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
 628         INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
 629         INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait),
 630         INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
 631         INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
 632         INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
 633         INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4),
 634         INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5),
 635         INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6),
 636         INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
 637         INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
 638         INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
 639         INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3),
 640         INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e),
 641         INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f),
 642         INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit),
 643         INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
 644         { "lcd-no-pins", },
 645         INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0),
 646         INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1),
 647         INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2),
 648         INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3),
 649         INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4),
 650         INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5),
 651         INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6),
 652         INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
 653 };
 654
 655 static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
 656 static const char *jz4780_uart4_groups[] = { "uart4-data", };
 657 static const char *jz4780_mmc0_groups[] = {
 658         "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
 659         "mmc0-1bit-e", "mmc0-4bit-e",
 660 };
 661 static const char *jz4780_mmc1_groups[] = {
 662         "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
 663 };
 664 static const char *jz4780_mmc2_groups[] = {
 665         "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
 666 };
 667 static const char *jz4780_nemc_groups[] = {
 668         "nemc-data", "nemc-cle-ale", "nemc-addr",
 669         "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
 670 };
 671 static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
 672 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
 673 static const char *jz4780_cim_groups[] = { "cim-data", };
 674
 675 static const struct function_desc jz4780_functions[] = {
 676         { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
 677         { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
 678         { "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), },
 679         { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
 680         { "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), },
 681         { "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), },
 682         { "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), },
 683         { "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), },
 684         { "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), },
 685         { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
 686         { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
 687         { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
 688         { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
 689         { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
 690         { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
 691         { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
 692         { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
 693         { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
 694         { "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), },
 695         { "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), },
 696         { "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), },
 697         { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
 698         { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
 699         { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
 700         { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
 701         { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
 702         { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
 703         { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
 704         { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
 705         { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
 706 };
 707
 708 static const struct ingenic_chip_info jz4780_chip_info = {
 709         .num_chips = 6,
 710         .groups = jz4780_groups,
 711         .num_groups = ARRAY_SIZE(jz4780_groups),
 712         .functions = jz4780_functions,
 713         .num_functions = ARRAY_SIZE(jz4780_functions),
 714         .pull_ups = jz4770_pull_ups,
 715         .pull_downs = jz4770_pull_downs,
 716 };
 717
 718 static u32 gpio_ingenic_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
 719 {
 720         unsigned int val;
 721
 722         regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val);
 723
 724         return (u32) val;
 725 }
 726
 727 static void gpio_ingenic_set_bit(struct ingenic_gpio_chip *jzgc,
 728                 u8 reg, u8 offset, bool set)
 729 {
 730         if (set)
 731                 reg = REG_SET(reg);
 732         else
 733                 reg = REG_CLEAR(reg);
 734
 735         regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));
 736 }
 737
 738 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
 739                                           u8 offset)
 740 {
 741         unsigned int val = gpio_ingenic_read_reg(jzgc, GPIO_PIN);
 742
 743         return !!(val & BIT(offset));
 744 }
 745
 746 static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
 747                                    u8 offset, int value)
 748 {
 749         if (jzgc->jzpc->version >= ID_JZ4770)
 750                 gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
 751         else
 752                 gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
 753 }
 754
 755 static void irq_set_type(struct ingenic_gpio_chip *jzgc,
 756                 u8 offset, unsigned int type)
 757 {
 758         u8 reg1, reg2;
 759
 760         if (jzgc->jzpc->version >= ID_JZ4770) {
 761                 reg1 = JZ4770_GPIO_PAT1;
 762                 reg2 = JZ4770_GPIO_PAT0;
 763         } else {
 764                 reg1 = JZ4740_GPIO_TRIG;
 765                 reg2 = JZ4740_GPIO_DIR;
 766         }
 767
 768         switch (type) {
 769         case IRQ_TYPE_EDGE_RISING:
 770                 gpio_ingenic_set_bit(jzgc, reg2, offset, true);
 771                 gpio_ingenic_set_bit(jzgc, reg1, offset, true);
 772                 break;
 773         case IRQ_TYPE_EDGE_FALLING:
 774                 gpio_ingenic_set_bit(jzgc, reg2, offset, false);
 775                 gpio_ingenic_set_bit(jzgc, reg1, offset, true);
 776                 break;
 777         case IRQ_TYPE_LEVEL_HIGH:
 778                 gpio_ingenic_set_bit(jzgc, reg2, offset, true);
 779                 gpio_ingenic_set_bit(jzgc, reg1, offset, false);
 780                 break;
 781         case IRQ_TYPE_LEVEL_LOW:
 782         default:
 783                 gpio_ingenic_set_bit(jzgc, reg2, offset, false);
 784                 gpio_ingenic_set_bit(jzgc, reg1, offset, false);
 785                 break;
 786         }
 787 }
 788
 789 static void ingenic_gpio_irq_mask(struct irq_data *irqd)
 790 {
 791         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
 792         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 793
 794         gpio_ingenic_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true);
 795 }
 796
 797 static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
 798 {
 799         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
 800         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 801
 802         gpio_ingenic_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false);
 803 }
 804
 805 static void ingenic_gpio_irq_enable(struct irq_data *irqd)
 806 {
 807         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
 808         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 809         int irq = irqd->hwirq;
 810
 811         if (jzgc->jzpc->version >= ID_JZ4770)
 812                 gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
 813         else
 814                 gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
 815
 816         ingenic_gpio_irq_unmask(irqd);
 817 }
 818
 819 static void ingenic_gpio_irq_disable(struct irq_data *irqd)
 820 {
 821         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
 822         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 823         int irq = irqd->hwirq;
 824
 825         ingenic_gpio_irq_mask(irqd);
 826
 827         if (jzgc->jzpc->version >= ID_JZ4770)
 828                 gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
 829         else
 830                 gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
 831 }
 832
 833 static void ingenic_gpio_irq_ack(struct irq_data *irqd)
 834 {
 835         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
 836         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 837         int irq = irqd->hwirq;
 838         bool high;
 839
 840         if (irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) {
 841                 /*
 842                  * Switch to an interrupt for the opposite edge to the one that
 843                  * triggered the interrupt being ACKed.
 844                  */
 845                 high = ingenic_gpio_get_value(jzgc, irq);
 846                 if (high)
 847                         irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_FALLING);
 848                 else
 849                         irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_RISING);
 850         }
 851
 852         if (jzgc->jzpc->version >= ID_JZ4770)
 853                 gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
 854         else
 855                 gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
 856 }
 857
 858 static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
 859 {
 860         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
 861         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 862
 863         switch (type) {
 864         case IRQ_TYPE_EDGE_BOTH:
 865         case IRQ_TYPE_EDGE_RISING:
 866         case IRQ_TYPE_EDGE_FALLING:
 867                 irq_set_handler_locked(irqd, handle_edge_irq);
 868                 break;
 869         case IRQ_TYPE_LEVEL_HIGH:
 870         case IRQ_TYPE_LEVEL_LOW:
 871                 irq_set_handler_locked(irqd, handle_level_irq);
 872                 break;
 873         default:
 874                 irq_set_handler_locked(irqd, handle_bad_irq);
 875         }
 876
 877         if (type == IRQ_TYPE_EDGE_BOTH) {
 878                 /*
 879                  * The hardware does not support interrupts on both edges. The
 880                  * best we can do is to set up a single-edge interrupt and then
 881                  * switch to the opposing edge when ACKing the interrupt.
 882                  */
 883                 bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq);
 884
 885                 type = high ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING;
 886         }
 887
 888         irq_set_type(jzgc, irqd->hwirq, type);
 889         return 0;
 890 }
 891
 892 static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on)
 893 {
 894         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
 895         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 896
 897         return irq_set_irq_wake(jzgc->irq, on);
 898 }
 899
 900 static void ingenic_gpio_irq_handler(struct irq_desc *desc)
 901 {
 902         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 903         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 904         struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);
 905         unsigned long flag, i;
 906
 907         chained_irq_enter(irq_chip, desc);
 908
 909         if (jzgc->jzpc->version >= ID_JZ4770)
 910                 flag = gpio_ingenic_read_reg(jzgc, JZ4770_GPIO_FLAG);
 911         else
 912                 flag = gpio_ingenic_read_reg(jzgc, JZ4740_GPIO_FLAG);
 913
 914         for_each_set_bit(i, &flag, 32)
 915                 generic_handle_irq(irq_linear_revmap(gc->irq.domain, i));
 916         chained_irq_exit(irq_chip, desc);
 917 }
 918
 919 static void ingenic_gpio_set(struct gpio_chip *gc,
 920                 unsigned int offset, int value)
 921 {
 922         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 923
 924         ingenic_gpio_set_value(jzgc, offset, value);
 925 }
 926
 927 static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset)
 928 {
 929         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 930
 931         return (int) ingenic_gpio_get_value(jzgc, offset);
 932 }
 933
 934 static int ingenic_gpio_direction_input(struct gpio_chip *gc,
 935                 unsigned int offset)
 936 {
 937         return pinctrl_gpio_direction_input(gc->base + offset);
 938 }
 939
 940 static int ingenic_gpio_direction_output(struct gpio_chip *gc,
 941                 unsigned int offset, int value)
 942 {
 943         ingenic_gpio_set(gc, offset, value);
 944         return pinctrl_gpio_direction_output(gc->base + offset);
 945 }
 946
 947 static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc,
 948                 unsigned int pin, u8 reg, bool set)
 949 {
 950         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
 951         unsigned int offt = pin / PINS_PER_GPIO_CHIP;
 952
 953         regmap_write(jzpc->map, offt * 0x100 +
 954                         (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
 955 }
 956
 957 static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc,
 958                 unsigned int pin, u8 reg)
 959 {
 960         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
 961         unsigned int offt = pin / PINS_PER_GPIO_CHIP;
 962         unsigned int val;
 963
 964         regmap_read(jzpc->map, offt * 0x100 + reg, &val);
 965
 966         return val & BIT(idx);
 967 }
 968
 969 static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
 970 {
 971         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 972         struct ingenic_pinctrl *jzpc = jzgc->jzpc;
 973         unsigned int pin = gc->base + offset;
 974
 975         if (jzpc->version >= ID_JZ4770)
 976                 return ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PAT1);
 977
 978         if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT))
 979                 return true;
 980
 981         return !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR);
 982 }
 983
 984 static const struct pinctrl_ops ingenic_pctlops = {
 985         .get_groups_count = pinctrl_generic_get_group_count,
 986         .get_group_name = pinctrl_generic_get_group_name,
 987         .get_group_pins = pinctrl_generic_get_group_pins,
 988         .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
 989         .dt_free_map = pinconf_generic_dt_free_map,
 990 };
 991
 992 static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc,
 993                 int pin, int func)
 994 {
 995         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
 996         unsigned int offt = pin / PINS_PER_GPIO_CHIP;
 997
 998         dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",
 999                         'A' + offt, idx, func);
1000
1001         if (jzpc->version >= ID_JZ4770) {
1002                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
1003                 ingenic_config_pin(jzpc, pin, GPIO_MSK, false);
1004                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);
1005                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);
1006         } else {
1007                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true);
1008                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2);
1009                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func > 0);
1010         }
1011
1012         return 0;
1013 }
1014
1015 static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev,
1016                 unsigned int selector, unsigned int group)
1017 {
1018         struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
1019         struct function_desc *func;
1020         struct group_desc *grp;
1021         unsigned int i;
1022
1023         func = pinmux_generic_get_function(pctldev, selector);
1024         if (!func)
1025                 return -EINVAL;
1026
1027         grp = pinctrl_generic_get_group(pctldev, group);
1028         if (!grp)
1029                 return -EINVAL;
1030
1031         dev_dbg(pctldev->dev, "enable function %s group %s\n",
1032                 func->name, grp->name);
1033
1034         for (i = 0; i < grp->num_pins; i++) {
1035                 int *pin_modes = grp->data;
1036
1037                 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]);
1038         }
1039
1040         return 0;
1041 }
1042
1043 static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
1044                 struct pinctrl_gpio_range *range,
1045                 unsigned int pin, bool input)
1046 {
1047         struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
1048         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1049         unsigned int offt = pin / PINS_PER_GPIO_CHIP;
1050
1051         dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",
1052                         'A' + offt, idx, input ? "in" : "out");
1053
1054         if (jzpc->version >= ID_JZ4770) {
1055                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
1056                 ingenic_config_pin(jzpc, pin, GPIO_MSK, true);
1057                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
1058         } else {
1059                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false);
1060                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input);
1061                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false);
1062         }
1063
1064         return 0;
1065 }
1066
1067 static const struct pinmux_ops ingenic_pmxops = {
1068         .get_functions_count = pinmux_generic_get_function_count,
1069         .get_function_name = pinmux_generic_get_function_name,
1070         .get_function_groups = pinmux_generic_get_function_groups,
1071         .set_mux = ingenic_pinmux_set_mux,
1072         .gpio_set_direction = ingenic_pinmux_gpio_set_direction,
1073 };
1074
1075 static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
1076                 unsigned int pin, unsigned long *config)
1077 {
1078         struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
1079         enum pin_config_param param = pinconf_to_config_param(*config);
1080         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1081         unsigned int offt = pin / PINS_PER_GPIO_CHIP;
1082         bool pull;
1083
1084         if (jzpc->version >= ID_JZ4770)
1085                 pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN);
1086         else
1087                 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);
1088
1089         switch (param) {
1090         case PIN_CONFIG_BIAS_DISABLE:
1091                 if (pull)
1092                         return -EINVAL;
1093                 break;
1094
1095         case PIN_CONFIG_BIAS_PULL_UP:
1096                 if (!pull || !(jzpc->info->pull_ups[offt] & BIT(idx)))
1097                         return -EINVAL;
1098                 break;
1099
1100         case PIN_CONFIG_BIAS_PULL_DOWN:
1101                 if (!pull || !(jzpc->info->pull_downs[offt] & BIT(idx)))
1102                         return -EINVAL;
1103                 break;
1104
1105         default:
1106                 return -ENOTSUPP;
1107         }
1108
1109         *config = pinconf_to_config_packed(param, 1);
1110         return 0;
1111 }
1112
1113 static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
1114                 unsigned int pin, bool enabled)
1115 {
1116         if (jzpc->version >= ID_JZ4770)
1117                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !enabled);
1118         else
1119                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !enabled);
1120 }
1121
1122 static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1123                 unsigned long *configs, unsigned int num_configs)
1124 {
1125         struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
1126         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1127         unsigned int offt = pin / PINS_PER_GPIO_CHIP;
1128         unsigned int cfg;
1129
1130         for (cfg = 0; cfg < num_configs; cfg++) {
1131                 switch (pinconf_to_config_param(configs[cfg])) {
1132                 case PIN_CONFIG_BIAS_DISABLE:
1133                 case PIN_CONFIG_BIAS_PULL_UP:
1134                 case PIN_CONFIG_BIAS_PULL_DOWN:
1135                         continue;
1136                 default:
1137                         return -ENOTSUPP;
1138                 }
1139         }
1140
1141         for (cfg = 0; cfg < num_configs; cfg++) {
1142                 switch (pinconf_to_config_param(configs[cfg])) {
1143                 case PIN_CONFIG_BIAS_DISABLE:
1144                         dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n",
1145                                         'A' + offt, idx);
1146                         ingenic_set_bias(jzpc, pin, false);
1147                         break;
1148
1149                 case PIN_CONFIG_BIAS_PULL_UP:
1150                         if (!(jzpc->info->pull_ups[offt] & BIT(idx)))
1151                                 return -EINVAL;
1152                         dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n",
1153                                         'A' + offt, idx);
1154                         ingenic_set_bias(jzpc, pin, true);
1155                         break;
1156
1157                 case PIN_CONFIG_BIAS_PULL_DOWN:
1158                         if (!(jzpc->info->pull_downs[offt] & BIT(idx)))
1159                                 return -EINVAL;
1160                         dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n",
1161                                         'A' + offt, idx);
1162                         ingenic_set_bias(jzpc, pin, true);
1163                         break;
1164
1165                 default:
1166                         unreachable();
1167                 }
1168         }
1169
1170         return 0;
1171 }
1172
1173 static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev,
1174                 unsigned int group, unsigned long *config)
1175 {
1176         const unsigned int *pins;
1177         unsigned int i, npins, old = 0;
1178         int ret;
1179
1180         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
1181         if (ret)
1182                 return ret;
1183
1184         for (i = 0; i < npins; i++) {
1185                 if (ingenic_pinconf_get(pctldev, pins[i], config))
1186                         return -ENOTSUPP;
1187
1188                 /* configs do not match between two pins */
1189                 if (i && (old != *config))
1190                         return -ENOTSUPP;
1191
1192                 old = *config;
1193         }
1194
1195         return 0;
1196 }
1197
1198 static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev,
1199                 unsigned int group, unsigned long *configs,
1200                 unsigned int num_configs)
1201 {
1202         const unsigned int *pins;
1203         unsigned int i, npins;
1204         int ret;
1205
1206         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
1207         if (ret)
1208                 return ret;
1209
1210         for (i = 0; i < npins; i++) {
1211                 ret = ingenic_pinconf_set(pctldev,
1212                                 pins[i], configs, num_configs);
1213                 if (ret)
1214                         return ret;
1215         }
1216
1217         return 0;
1218 }
1219
1220 static const struct pinconf_ops ingenic_confops = {
1221         .is_generic = true,
1222         .pin_config_get = ingenic_pinconf_get,
1223         .pin_config_set = ingenic_pinconf_set,
1224         .pin_config_group_get = ingenic_pinconf_group_get,
1225         .pin_config_group_set = ingenic_pinconf_group_set,
1226 };
1227
1228 static const struct regmap_config ingenic_pinctrl_regmap_config = {
1229         .reg_bits = 32,
1230         .val_bits = 32,
1231         .reg_stride = 4,
1232 };
1233
1234 static const struct of_device_id ingenic_pinctrl_of_match[] = {
1235         { .compatible = "ingenic,jz4740-pinctrl", .data = (void *) ID_JZ4740 },
1236         { .compatible = "ingenic,jz4725b-pinctrl", .data = (void *)ID_JZ4725B },
1237         { .compatible = "ingenic,jz4770-pinctrl", .data = (void *) ID_JZ4770 },
1238         { .compatible = "ingenic,jz4780-pinctrl", .data = (void *) ID_JZ4780 },
1239         {},
1240 };
1241
1242 static const struct of_device_id ingenic_gpio_of_match[] __initconst = {
1243         { .compatible = "ingenic,jz4740-gpio", },
1244         { .compatible = "ingenic,jz4770-gpio", },
1245         { .compatible = "ingenic,jz4780-gpio", },
1246         {},
1247 };
1248
1249 static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc,
1250                                      struct device_node *node)
1251 {
1252         struct ingenic_gpio_chip *jzgc;
1253         struct device *dev = jzpc->dev;
1254         unsigned int bank;
1255         int err;
1256
1257         err = of_property_read_u32(node, "reg", &bank);
1258         if (err) {
1259                 dev_err(dev, "Cannot read \"reg\" property: %i\n", err);
1260                 return err;
1261         }
1262
1263         jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL);
1264         if (!jzgc)
1265                 return -ENOMEM;
1266
1267         jzgc->jzpc = jzpc;
1268         jzgc->reg_base = bank * 0x100;
1269
1270         jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);
1271         if (!jzgc->gc.label)
1272                 return -ENOMEM;
1273
1274         /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY
1275          * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN
1276          * <linux/gpio/consumer.h> INSTEAD.
1277          */
1278         jzgc->gc.base = bank * 32;
1279
1280         jzgc->gc.ngpio = 32;
1281         jzgc->gc.parent = dev;
1282         jzgc->gc.of_node = node;
1283         jzgc->gc.owner = THIS_MODULE;
1284
1285         jzgc->gc.set = ingenic_gpio_set;
1286         jzgc->gc.get = ingenic_gpio_get;
1287         jzgc->gc.direction_input = ingenic_gpio_direction_input;
1288         jzgc->gc.direction_output = ingenic_gpio_direction_output;
1289         jzgc->gc.get_direction = ingenic_gpio_get_direction;
1290
1291         if (of_property_read_bool(node, "gpio-ranges")) {
1292                 jzgc->gc.request = gpiochip_generic_request;
1293                 jzgc->gc.free = gpiochip_generic_free;
1294         }
1295
1296         err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);
1297         if (err)
1298                 return err;
1299
1300         jzgc->irq = irq_of_parse_and_map(node, 0);
1301         if (!jzgc->irq)
1302                 return -EINVAL;
1303
1304         jzgc->irq_chip.name = jzgc->gc.label;
1305         jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable;
1306         jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable;
1307         jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask;
1308         jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask;
1309         jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack;
1310         jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type;
1311         jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake;
1312         jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
1313
1314         err = gpiochip_irqchip_add(&jzgc->gc, &jzgc->irq_chip, 0,
1315                         handle_level_irq, IRQ_TYPE_NONE);
1316         if (err)
1317                 return err;
1318
1319         gpiochip_set_chained_irqchip(&jzgc->gc, &jzgc->irq_chip,
1320                         jzgc->irq, ingenic_gpio_irq_handler);
1321         return 0;
1322 }
1323
1324 static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
1325 {
1326         struct device *dev = &pdev->dev;
1327         struct ingenic_pinctrl *jzpc;
1328         struct pinctrl_desc *pctl_desc;
1329         void __iomem *base;
1330         const struct platform_device_id *id = platform_get_device_id(pdev);
1331         const struct of_device_id *of_id = of_match_device(
1332                         ingenic_pinctrl_of_match, dev);
1333         const struct ingenic_chip_info *chip_info;
1334         struct device_node *node;
1335         unsigned int i;
1336         int err;
1337
1338         jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL);
1339         if (!jzpc)
1340                 return -ENOMEM;
1341
1342         base = devm_ioremap_resource(dev,
1343                         platform_get_resource(pdev, IORESOURCE_MEM, 0));
1344         if (IS_ERR(base))
1345                 return PTR_ERR(base);
1346
1347         jzpc->map = devm_regmap_init_mmio(dev, base,
1348                         &ingenic_pinctrl_regmap_config);
1349         if (IS_ERR(jzpc->map)) {
1350                 dev_err(dev, "Failed to create regmap\n");
1351                 return PTR_ERR(jzpc->map);
1352         }
1353
1354         jzpc->dev = dev;
1355
1356         if (of_id)
1357                 jzpc->version = (enum jz_version)of_id->data;
1358         else
1359                 jzpc->version = (enum jz_version)id->driver_data;
1360
1361         if (jzpc->version >= ID_JZ4780)
1362                 chip_info = &jz4780_chip_info;
1363         else if (jzpc->version >= ID_JZ4770)
1364                 chip_info = &jz4770_chip_info;
1365         else if (jzpc->version >= ID_JZ4725B)
1366                 chip_info = &jz4725b_chip_info;
1367         else
1368                 chip_info = &jz4740_chip_info;
1369         jzpc->info = chip_info;
1370
1371         pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
1372         if (!pctl_desc)
1373                 return -ENOMEM;
1374
1375         /* fill in pinctrl_desc structure */
1376         pctl_desc->name = dev_name(dev);
1377         pctl_desc->owner = THIS_MODULE;
1378         pctl_desc->pctlops = &ingenic_pctlops;
1379         pctl_desc->pmxops = &ingenic_pmxops;
1380         pctl_desc->confops = &ingenic_confops;
1381         pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP;
1382         pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev,
1383                         pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL);
1384         if (!jzpc->pdesc)
1385                 return -ENOMEM;
1386
1387         for (i = 0; i < pctl_desc->npins; i++) {
1388                 jzpc->pdesc[i].number = i;
1389                 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
1390                                                 'A' + (i / PINS_PER_GPIO_CHIP),
1391                                                 i % PINS_PER_GPIO_CHIP);
1392         }
1393
1394         jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc);
1395         if (IS_ERR(jzpc->pctl)) {
1396                 dev_err(dev, "Failed to register pinctrl\n");
1397                 return PTR_ERR(jzpc->pctl);
1398         }
1399
1400         for (i = 0; i < chip_info->num_groups; i++) {
1401                 const struct group_desc *group = &chip_info->groups[i];
1402
1403                 err = pinctrl_generic_add_group(jzpc->pctl, group->name,
1404                                 group->pins, group->num_pins, group->data);
1405                 if (err < 0) {
1406                         dev_err(dev, "Failed to register group %s\n",
1407                                         group->name);
1408                         return err;
1409                 }
1410         }
1411
1412         for (i = 0; i < chip_info->num_functions; i++) {
1413                 const struct function_desc *func = &chip_info->functions[i];
1414
1415                 err = pinmux_generic_add_function(jzpc->pctl, func->name,
1416                                 func->group_names, func->num_group_names,
1417                                 func->data);
1418                 if (err < 0) {
1419                         dev_err(dev, "Failed to register function %s\n",
1420                                         func->name);
1421                         return err;
1422                 }
1423         }
1424
1425         dev_set_drvdata(dev, jzpc->map);
1426
1427         for_each_child_of_node(dev->of_node, node) {
1428                 if (of_match_node(ingenic_gpio_of_match, node)) {
1429                         err = ingenic_gpio_probe(jzpc, node);
1430                         if (err)
1431                                 return err;
1432                 }
1433         }
1434
1435         return 0;
1436 }
1437
1438 static const struct platform_device_id ingenic_pinctrl_ids[] = {
1439         { "jz4740-pinctrl", ID_JZ4740 },
1440         { "jz4725b-pinctrl", ID_JZ4725B },
1441         { "jz4770-pinctrl", ID_JZ4770 },
1442         { "jz4780-pinctrl", ID_JZ4780 },
1443         {},
1444 };
1445
1446 static struct platform_driver ingenic_pinctrl_driver = {
1447         .driver = {
1448                 .name = "pinctrl-ingenic",
1449                 .of_match_table = of_match_ptr(ingenic_pinctrl_of_match),
1450         },
1451         .id_table = ingenic_pinctrl_ids,
1452 };
1453
1454 static int __init ingenic_pinctrl_drv_register(void)
1455 {
1456         return platform_driver_probe(&ingenic_pinctrl_driver,
1457                                      ingenic_pinctrl_probe);
1458 }
1459 subsys_initcall(ingenic_pinctrl_drv_register);