drivers/pinctrl/pinctrl-ingenic.c

   1 /*
   2  * Ingenic SoCs pinctrl driver
   3  *
   4  * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net>
   5  *
   6  * License terms: GNU General Public License (GPL) version 2
   7  */
   8
   9 #include <linux/compiler.h>
  10 #include <linux/gpio.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/io.h>
  13 #include <linux/of_device.h>
  14 #include <linux/of_irq.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/pinctrl/pinctrl.h>
  17 #include <linux/pinctrl/pinmux.h>
  18 #include <linux/pinctrl/pinconf.h>
  19 #include <linux/pinctrl/pinconf-generic.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/regmap.h>
  22 #include <linux/slab.h>
  23
  24 #include "core.h"
  25 #include "pinconf.h"
  26 #include "pinmux.h"
  27
  28 #define GPIO_PIN        0x00
  29 #define GPIO_MSK        0x20
  30
  31 #define JZ4740_GPIO_DATA        0x10
  32 #define JZ4740_GPIO_PULL_DIS    0x30
  33 #define JZ4740_GPIO_FUNC        0x40
  34 #define JZ4740_GPIO_SELECT      0x50
  35 #define JZ4740_GPIO_DIR         0x60
  36 #define JZ4740_GPIO_TRIG        0x70
  37 #define JZ4740_GPIO_FLAG        0x80
  38
  39 #define JZ4770_GPIO_INT         0x10
  40 #define JZ4770_GPIO_PAT1        0x30
  41 #define JZ4770_GPIO_PAT0        0x40
  42 #define JZ4770_GPIO_FLAG        0x50
  43 #define JZ4770_GPIO_PEN         0x70
  44
  45 #define REG_SET(x) ((x) + 0x4)
  46 #define REG_CLEAR(x) ((x) + 0x8)
  47
  48 #define PINS_PER_GPIO_CHIP 32
  49
  50 enum jz_version {
  51         ID_JZ4740,
  52         ID_JZ4770,
  53         ID_JZ4780,
  54 };
  55
  56 struct ingenic_chip_info {
  57         unsigned int num_chips;
  58
  59         const struct group_desc *groups;
  60         unsigned int num_groups;
  61
  62         const struct function_desc *functions;
  63         unsigned int num_functions;
  64
  65         const u32 *pull_ups, *pull_downs;
  66 };
  67
  68 struct ingenic_pinctrl {
  69         struct device *dev;
  70         struct regmap *map;
  71         struct pinctrl_dev *pctl;
  72         struct pinctrl_pin_desc *pdesc;
  73         enum jz_version version;
  74
  75         const struct ingenic_chip_info *info;
  76 };
  77
  78 struct ingenic_gpio_chip {
  79         struct ingenic_pinctrl *jzpc;
  80         struct gpio_chip gc;
  81         struct irq_chip irq_chip;
  82         unsigned int irq, reg_base;
  83 };
  84
  85 static const u32 jz4740_pull_ups[4] = {
  86         0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  87 };
  88
  89 static const u32 jz4740_pull_downs[4] = {
  90         0x00000000, 0x00000000, 0x00000000, 0x00000000,
  91 };
  92
  93 static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, };
  94 static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };
  95 static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, };
  96 static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
  97 static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, };
  98 static int jz4740_lcd_8bit_pins[] = {
  99         0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x52, 0x53, 0x54,
 100 };
 101 static int jz4740_lcd_16bit_pins[] = {
 102         0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x55,
 103 };
 104 static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, };
 105 static int jz4740_lcd_18bit_tft_pins[] = { 0x56, 0x57, 0x31, 0x32, };
 106 static int jz4740_nand_cs1_pins[] = { 0x39, };
 107 static int jz4740_nand_cs2_pins[] = { 0x3a, };
 108 static int jz4740_nand_cs3_pins[] = { 0x3b, };
 109 static int jz4740_nand_cs4_pins[] = { 0x3c, };
 110 static int jz4740_pwm_pwm0_pins[] = { 0x77, };
 111 static int jz4740_pwm_pwm1_pins[] = { 0x78, };
 112 static int jz4740_pwm_pwm2_pins[] = { 0x79, };
 113 static int jz4740_pwm_pwm3_pins[] = { 0x7a, };
 114 static int jz4740_pwm_pwm4_pins[] = { 0x7b, };
 115 static int jz4740_pwm_pwm5_pins[] = { 0x7c, };
 116 static int jz4740_pwm_pwm6_pins[] = { 0x7e, };
 117 static int jz4740_pwm_pwm7_pins[] = { 0x7f, };
 118
 119 static int jz4740_mmc_1bit_funcs[] = { 0, 0, 0, };
 120 static int jz4740_mmc_4bit_funcs[] = { 0, 0, 0, };
 121 static int jz4740_uart0_data_funcs[] = { 1, 1, };
 122 static int jz4740_uart0_hwflow_funcs[] = { 1, 1, };
 123 static int jz4740_uart1_data_funcs[] = { 2, 2, };
 124 static int jz4740_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
 125 static int jz4740_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, };
 126 static int jz4740_lcd_18bit_funcs[] = { 0, 0, };
 127 static int jz4740_lcd_18bit_tft_funcs[] = { 0, 0, 0, 0, };
 128 static int jz4740_nand_cs1_funcs[] = { 0, };
 129 static int jz4740_nand_cs2_funcs[] = { 0, };
 130 static int jz4740_nand_cs3_funcs[] = { 0, };
 131 static int jz4740_nand_cs4_funcs[] = { 0, };
 132 static int jz4740_pwm_pwm0_funcs[] = { 0, };
 133 static int jz4740_pwm_pwm1_funcs[] = { 0, };
 134 static int jz4740_pwm_pwm2_funcs[] = { 0, };
 135 static int jz4740_pwm_pwm3_funcs[] = { 0, };
 136 static int jz4740_pwm_pwm4_funcs[] = { 0, };
 137 static int jz4740_pwm_pwm5_funcs[] = { 0, };
 138 static int jz4740_pwm_pwm6_funcs[] = { 0, };
 139 static int jz4740_pwm_pwm7_funcs[] = { 0, };
 140
 141 #define INGENIC_PIN_GROUP(name, id)                     \
 142         {                                               \
 143                 name,                                   \
 144                 id##_pins,                              \
 145                 ARRAY_SIZE(id##_pins),                  \
 146                 id##_funcs,                             \
 147         }
 148
 149 static const struct group_desc jz4740_groups[] = {
 150         INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit),
 151         INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit),
 152         INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data),
 153         INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow),
 154         INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data),
 155         INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit),
 156         INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit),
 157         INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit),
 158         INGENIC_PIN_GROUP("lcd-18bit-tft", jz4740_lcd_18bit_tft),
 159         { "lcd-no-pins", },
 160         INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1),
 161         INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2),
 162         INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3),
 163         INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4),
 164         INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0),
 165         INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1),
 166         INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2),
 167         INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3),
 168         INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4),
 169         INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5),
 170         INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6),
 171         INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7),
 172 };
 173
 174 static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
 175 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
 176 static const char *jz4740_uart1_groups[] = { "uart1-data", };
 177 static const char *jz4740_lcd_groups[] = {
 178         "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-18bit-tft", "lcd-no-pins",
 179 };
 180 static const char *jz4740_nand_groups[] = {
 181         "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
 182 };
 183 static const char *jz4740_pwm0_groups[] = { "pwm0", };
 184 static const char *jz4740_pwm1_groups[] = { "pwm1", };
 185 static const char *jz4740_pwm2_groups[] = { "pwm2", };
 186 static const char *jz4740_pwm3_groups[] = { "pwm3", };
 187 static const char *jz4740_pwm4_groups[] = { "pwm4", };
 188 static const char *jz4740_pwm5_groups[] = { "pwm5", };
 189 static const char *jz4740_pwm6_groups[] = { "pwm6", };
 190 static const char *jz4740_pwm7_groups[] = { "pwm7", };
 191
 192 static const struct function_desc jz4740_functions[] = {
 193         { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
 194         { "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), },
 195         { "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), },
 196         { "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), },
 197         { "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), },
 198         { "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), },
 199         { "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), },
 200         { "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), },
 201         { "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), },
 202         { "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), },
 203         { "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), },
 204         { "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), },
 205         { "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), },
 206 };
 207
 208 static const struct ingenic_chip_info jz4740_chip_info = {
 209         .num_chips = 4,
 210         .groups = jz4740_groups,
 211         .num_groups = ARRAY_SIZE(jz4740_groups),
 212         .functions = jz4740_functions,
 213         .num_functions = ARRAY_SIZE(jz4740_functions),
 214         .pull_ups = jz4740_pull_ups,
 215         .pull_downs = jz4740_pull_downs,
 216 };
 217
 218 static const u32 jz4770_pull_ups[6] = {
 219         0x3fffffff, 0xfff0030c, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0xffa7f00f,
 220 };
 221
 222 static const u32 jz4770_pull_downs[6] = {
 223         0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0,
 224 };
 225
 226 static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, };
 227 static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
 228 static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, };
 229 static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
 230 static int jz4770_uart2_data_pins[] = { 0x66, 0x67, };
 231 static int jz4770_uart2_hwflow_pins[] = { 0x65, 0x64, };
 232 static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, };
 233 static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, };
 234 static int jz4770_uart4_data_pins[] = { 0x54, 0x4a, };
 235 static int jz4770_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, };
 236 static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
 237 static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
 238 static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
 239 static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
 240 static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
 241 static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
 242 static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
 243 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
 244 static int jz4770_nemc_data_pins[] = {
 245         0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
 246 };
 247 static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, };
 248 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
 249 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };
 250 static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
 251 static int jz4770_nemc_cs1_pins[] = { 0x15, };
 252 static int jz4770_nemc_cs2_pins[] = { 0x16, };
 253 static int jz4770_nemc_cs3_pins[] = { 0x17, };
 254 static int jz4770_nemc_cs4_pins[] = { 0x18, };
 255 static int jz4770_nemc_cs5_pins[] = { 0x19, };
 256 static int jz4770_nemc_cs6_pins[] = { 0x1a, };
 257 static int jz4770_i2c0_pins[] = { 0x6e, 0x6f, };
 258 static int jz4770_i2c1_pins[] = { 0x8e, 0x8f, };
 259 static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, };
 260 static int jz4770_i2c3_pins[] = { 0x6a, 0x6b, };
 261 static int jz4770_i2c4_e_pins[] = { 0x8c, 0x8d, };
 262 static int jz4770_i2c4_f_pins[] = { 0xb9, 0xb8, };
 263 static int jz4770_cim_pins[] = {
 264         0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
 265 };
 266 static int jz4770_lcd_32bit_pins[] = {
 267         0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
 268         0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
 269         0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
 270         0x58, 0x59, 0x51,
 271 };
 272 static int jz4770_pwm_pwm0_pins[] = { 0x80, };
 273 static int jz4770_pwm_pwm1_pins[] = { 0x81, };
 274 static int jz4770_pwm_pwm2_pins[] = { 0x82, };
 275 static int jz4770_pwm_pwm3_pins[] = { 0x83, };
 276 static int jz4770_pwm_pwm4_pins[] = { 0x84, };
 277 static int jz4770_pwm_pwm5_pins[] = { 0x85, };
 278 static int jz4770_pwm_pwm6_pins[] = { 0x6a, };
 279 static int jz4770_pwm_pwm7_pins[] = { 0x6b, };
 280
 281 static int jz4770_uart0_data_funcs[] = { 0, 0, };
 282 static int jz4770_uart0_hwflow_funcs[] = { 0, 0, };
 283 static int jz4770_uart1_data_funcs[] = { 0, 0, };
 284 static int jz4770_uart1_hwflow_funcs[] = { 0, 0, };
 285 static int jz4770_uart2_data_funcs[] = { 1, 1, };
 286 static int jz4770_uart2_hwflow_funcs[] = { 1, 1, };
 287 static int jz4770_uart3_data_funcs[] = { 0, 1, };
 288 static int jz4770_uart3_hwflow_funcs[] = { 0, 0, };
 289 static int jz4770_uart4_data_funcs[] = { 2, 2, };
 290 static int jz4770_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, };
 291 static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
 292 static int jz4770_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
 293 static int jz4770_mmc0_4bit_e_funcs[] = { 0, 0, 0, };
 294 static int jz4770_mmc0_1bit_e_funcs[] = { 0, 0, 0, };
 295 static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
 296 static int jz4770_mmc1_1bit_d_funcs[] = { 0, 0, 0, };
 297 static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
 298 static int jz4770_mmc1_1bit_e_funcs[] = { 1, 1, 1, };
 299 static int jz4770_nemc_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
 300 static int jz4770_nemc_cle_ale_funcs[] = { 0, 0, };
 301 static int jz4770_nemc_addr_funcs[] = { 0, 0, 0, 0, };
 302 static int jz4770_nemc_rd_we_funcs[] = { 0, 0, };
 303 static int jz4770_nemc_frd_fwe_funcs[] = { 0, 0, };
 304 static int jz4770_nemc_cs1_funcs[] = { 0, };
 305 static int jz4770_nemc_cs2_funcs[] = { 0, };
 306 static int jz4770_nemc_cs3_funcs[] = { 0, };
 307 static int jz4770_nemc_cs4_funcs[] = { 0, };
 308 static int jz4770_nemc_cs5_funcs[] = { 0, };
 309 static int jz4770_nemc_cs6_funcs[] = { 0, };
 310 static int jz4770_i2c0_funcs[] = { 0, 0, };
 311 static int jz4770_i2c1_funcs[] = { 0, 0, };
 312 static int jz4770_i2c2_funcs[] = { 2, 2, };
 313 static int jz4770_i2c3_funcs[] = { 1, 1, };
 314 static int jz4770_i2c4_e_funcs[] = { 1, 1, };
 315 static int jz4770_i2c4_f_funcs[] = { 1, 1, };
 316 static int jz4770_cim_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
 317 static int jz4770_lcd_32bit_funcs[] = {
 318         0, 0, 0, 0, 0, 0, 0, 0,
 319         0, 0, 0, 0, 0, 0, 0, 0,
 320         0, 0, 0,
 321 };
 322 static int jz4770_pwm_pwm0_funcs[] = { 0, };
 323 static int jz4770_pwm_pwm1_funcs[] = { 0, };
 324 static int jz4770_pwm_pwm2_funcs[] = { 0, };
 325 static int jz4770_pwm_pwm3_funcs[] = { 0, };
 326 static int jz4770_pwm_pwm4_funcs[] = { 0, };
 327 static int jz4770_pwm_pwm5_funcs[] = { 0, };
 328 static int jz4770_pwm_pwm6_funcs[] = { 0, };
 329 static int jz4770_pwm_pwm7_funcs[] = { 0, };
 330
 331 static const struct group_desc jz4770_groups[] = {
 332         INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
 333         INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow),
 334         INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data),
 335         INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow),
 336         INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data),
 337         INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow),
 338         INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
 339         INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
 340         INGENIC_PIN_GROUP("uart4-data", jz4770_uart4_data),
 341         INGENIC_PIN_GROUP("mmc0-8bit-a", jz4770_mmc0_8bit_a),
 342         INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
 343         INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
 344         INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
 345         INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
 346         INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
 347         INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
 348         INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
 349         INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
 350         INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_data),
 351         INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
 352         INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
 353         INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
 354         INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
 355         INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
 356         INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
 357         INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
 358         INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4),
 359         INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5),
 360         INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6),
 361         INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
 362         INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
 363         INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
 364         INGENIC_PIN_GROUP("i2c3-data", jz4770_i2c3),
 365         INGENIC_PIN_GROUP("i2c4-data-e", jz4770_i2c4_e),
 366         INGENIC_PIN_GROUP("i2c4-data-f", jz4770_i2c4_f),
 367         INGENIC_PIN_GROUP("cim-data", jz4770_cim),
 368         INGENIC_PIN_GROUP("lcd-32bit", jz4770_lcd_32bit),
 369         { "lcd-no-pins", },
 370         INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0),
 371         INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1),
 372         INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2),
 373         INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3),
 374         INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4),
 375         INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5),
 376         INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6),
 377         INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
 378 };
 379
 380 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
 381 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
 382 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
 383 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
 384 static const char *jz4770_uart4_groups[] = { "uart4-data", };
 385 static const char *jz4770_mmc0_groups[] = {
 386         "mmc0-8bit-a", "mmc0-4bit-a", "mmc0-1bit-a",
 387         "mmc0-1bit-e", "mmc0-4bit-e",
 388 };
 389 static const char *jz4770_mmc1_groups[] = {
 390         "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
 391 };
 392 static const char *jz4770_nemc_groups[] = {
 393         "nemc-data", "nemc-cle-ale", "nemc-addr", "nemc-rd-we", "nemc-frd-fwe",
 394 };
 395 static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
 396 static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
 397 static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
 398 static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
 399 static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
 400 static const char *jz4770_i2c3_groups[] = { "i2c3-data", };
 401 static const char *jz4770_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
 402 static const char *jz4770_cim_groups[] = { "cim-data", };
 403 static const char *jz4770_lcd_groups[] = { "lcd-32bit", "lcd-no-pins", };
 404 static const char *jz4770_pwm0_groups[] = { "pwm0", };
 405 static const char *jz4770_pwm1_groups[] = { "pwm1", };
 406 static const char *jz4770_pwm2_groups[] = { "pwm2", };
 407 static const char *jz4770_pwm3_groups[] = { "pwm3", };
 408 static const char *jz4770_pwm4_groups[] = { "pwm4", };
 409 static const char *jz4770_pwm5_groups[] = { "pwm5", };
 410 static const char *jz4770_pwm6_groups[] = { "pwm6", };
 411 static const char *jz4770_pwm7_groups[] = { "pwm7", };
 412
 413 static const struct function_desc jz4770_functions[] = {
 414         { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
 415         { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
 416         { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), },
 417         { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
 418         { "uart4", jz4770_uart4_groups, ARRAY_SIZE(jz4770_uart4_groups), },
 419         { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), },
 420         { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), },
 421         { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), },
 422         { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
 423         { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
 424         { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
 425         { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
 426         { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
 427         { "i2c3", jz4770_i2c3_groups, ARRAY_SIZE(jz4770_i2c3_groups), },
 428         { "i2c4", jz4770_i2c4_groups, ARRAY_SIZE(jz4770_i2c4_groups), },
 429         { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), },
 430         { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
 431         { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
 432         { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
 433         { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
 434         { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
 435         { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
 436         { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
 437         { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
 438         { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
 439 };
 440
 441 static const struct ingenic_chip_info jz4770_chip_info = {
 442         .num_chips = 6,
 443         .groups = jz4770_groups,
 444         .num_groups = ARRAY_SIZE(jz4770_groups),
 445         .functions = jz4770_functions,
 446         .num_functions = ARRAY_SIZE(jz4770_functions),
 447         .pull_ups = jz4770_pull_ups,
 448         .pull_downs = jz4770_pull_downs,
 449 };
 450
 451 static u32 gpio_ingenic_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
 452 {
 453         unsigned int val;
 454
 455         regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val);
 456
 457         return (u32) val;
 458 }
 459
 460 static void gpio_ingenic_set_bit(struct ingenic_gpio_chip *jzgc,
 461                 u8 reg, u8 offset, bool set)
 462 {
 463         if (set)
 464                 reg = REG_SET(reg);
 465         else
 466                 reg = REG_CLEAR(reg);
 467
 468         regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));
 469 }
 470
 471 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
 472                                           u8 offset)
 473 {
 474         unsigned int val = gpio_ingenic_read_reg(jzgc, GPIO_PIN);
 475
 476         return !!(val & BIT(offset));
 477 }
 478
 479 static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
 480                                    u8 offset, int value)
 481 {
 482         if (jzgc->jzpc->version >= ID_JZ4770)
 483                 gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
 484         else
 485                 gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
 486 }
 487
 488 static void irq_set_type(struct ingenic_gpio_chip *jzgc,
 489                 u8 offset, unsigned int type)
 490 {
 491         u8 reg1, reg2;
 492
 493         if (jzgc->jzpc->version >= ID_JZ4770) {
 494                 reg1 = JZ4770_GPIO_PAT1;
 495                 reg2 = JZ4770_GPIO_PAT0;
 496         } else {
 497                 reg1 = JZ4740_GPIO_TRIG;
 498                 reg2 = JZ4740_GPIO_DIR;
 499         }
 500
 501         switch (type) {
 502         case IRQ_TYPE_EDGE_RISING:
 503                 gpio_ingenic_set_bit(jzgc, reg2, offset, true);
 504                 gpio_ingenic_set_bit(jzgc, reg1, offset, true);
 505                 break;
 506         case IRQ_TYPE_EDGE_FALLING:
 507                 gpio_ingenic_set_bit(jzgc, reg2, offset, false);
 508                 gpio_ingenic_set_bit(jzgc, reg1, offset, true);
 509                 break;
 510         case IRQ_TYPE_LEVEL_HIGH:
 511                 gpio_ingenic_set_bit(jzgc, reg2, offset, true);
 512                 gpio_ingenic_set_bit(jzgc, reg1, offset, false);
 513                 break;
 514         case IRQ_TYPE_LEVEL_LOW:
 515         default:
 516                 gpio_ingenic_set_bit(jzgc, reg2, offset, false);
 517                 gpio_ingenic_set_bit(jzgc, reg1, offset, false);
 518                 break;
 519         }
 520 }
 521
 522 static void ingenic_gpio_irq_mask(struct irq_data *irqd)
 523 {
 524         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
 525         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 526
 527         gpio_ingenic_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true);
 528 }
 529
 530 static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
 531 {
 532         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
 533         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 534
 535         gpio_ingenic_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false);
 536 }
 537
 538 static void ingenic_gpio_irq_enable(struct irq_data *irqd)
 539 {
 540         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
 541         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 542         int irq = irqd->hwirq;
 543
 544         if (jzgc->jzpc->version >= ID_JZ4770)
 545                 gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
 546         else
 547                 gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
 548
 549         ingenic_gpio_irq_unmask(irqd);
 550 }
 551
 552 static void ingenic_gpio_irq_disable(struct irq_data *irqd)
 553 {
 554         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
 555         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 556         int irq = irqd->hwirq;
 557
 558         ingenic_gpio_irq_mask(irqd);
 559
 560         if (jzgc->jzpc->version >= ID_JZ4770)
 561                 gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
 562         else
 563                 gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
 564 }
 565
 566 static void ingenic_gpio_irq_ack(struct irq_data *irqd)
 567 {
 568         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
 569         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 570         int irq = irqd->hwirq;
 571         bool high;
 572
 573         if (irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) {
 574                 /*
 575                  * Switch to an interrupt for the opposite edge to the one that
 576                  * triggered the interrupt being ACKed.
 577                  */
 578                 high = ingenic_gpio_get_value(jzgc, irq);
 579                 if (high)
 580                         irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_FALLING);
 581                 else
 582                         irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_RISING);
 583         }
 584
 585         if (jzgc->jzpc->version >= ID_JZ4770)
 586                 gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
 587         else
 588                 gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
 589 }
 590
 591 static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
 592 {
 593         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
 594         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 595
 596         switch (type) {
 597         case IRQ_TYPE_EDGE_BOTH:
 598         case IRQ_TYPE_EDGE_RISING:
 599         case IRQ_TYPE_EDGE_FALLING:
 600                 irq_set_handler_locked(irqd, handle_edge_irq);
 601                 break;
 602         case IRQ_TYPE_LEVEL_HIGH:
 603         case IRQ_TYPE_LEVEL_LOW:
 604                 irq_set_handler_locked(irqd, handle_level_irq);
 605                 break;
 606         default:
 607                 irq_set_handler_locked(irqd, handle_bad_irq);
 608         }
 609
 610         if (type == IRQ_TYPE_EDGE_BOTH) {
 611                 /*
 612                  * The hardware does not support interrupts on both edges. The
 613                  * best we can do is to set up a single-edge interrupt and then
 614                  * switch to the opposing edge when ACKing the interrupt.
 615                  */
 616                 bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq);
 617
 618                 type = high ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING;
 619         }
 620
 621         irq_set_type(jzgc, irqd->hwirq, type);
 622         return 0;
 623 }
 624
 625 static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on)
 626 {
 627         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
 628         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 629
 630         return irq_set_irq_wake(jzgc->irq, on);
 631 }
 632
 633 static void ingenic_gpio_irq_handler(struct irq_desc *desc)
 634 {
 635         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 636         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 637         struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);
 638         unsigned long flag, i;
 639
 640         chained_irq_enter(irq_chip, desc);
 641
 642         if (jzgc->jzpc->version >= ID_JZ4770)
 643                 flag = gpio_ingenic_read_reg(jzgc, JZ4770_GPIO_FLAG);
 644         else
 645                 flag = gpio_ingenic_read_reg(jzgc, JZ4740_GPIO_FLAG);
 646
 647         for_each_set_bit(i, &flag, 32)
 648                 generic_handle_irq(irq_linear_revmap(gc->irq.domain, i));
 649         chained_irq_exit(irq_chip, desc);
 650 }
 651
 652 static void ingenic_gpio_set(struct gpio_chip *gc,
 653                 unsigned int offset, int value)
 654 {
 655         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 656
 657         ingenic_gpio_set_value(jzgc, offset, value);
 658 }
 659
 660 static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset)
 661 {
 662         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 663
 664         return (int) ingenic_gpio_get_value(jzgc, offset);
 665 }
 666
 667 static int ingenic_gpio_direction_input(struct gpio_chip *gc,
 668                 unsigned int offset)
 669 {
 670         return pinctrl_gpio_direction_input(gc->base + offset);
 671 }
 672
 673 static int ingenic_gpio_direction_output(struct gpio_chip *gc,
 674                 unsigned int offset, int value)
 675 {
 676         ingenic_gpio_set(gc, offset, value);
 677         return pinctrl_gpio_direction_output(gc->base + offset);
 678 }
 679
 680 static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc,
 681                 unsigned int pin, u8 reg, bool set)
 682 {
 683         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
 684         unsigned int offt = pin / PINS_PER_GPIO_CHIP;
 685
 686         regmap_write(jzpc->map, offt * 0x100 +
 687                         (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
 688 }
 689
 690 static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc,
 691                 unsigned int pin, u8 reg)
 692 {
 693         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
 694         unsigned int offt = pin / PINS_PER_GPIO_CHIP;
 695         unsigned int val;
 696
 697         regmap_read(jzpc->map, offt * 0x100 + reg, &val);
 698
 699         return val & BIT(idx);
 700 }
 701
 702 static const struct pinctrl_ops ingenic_pctlops = {
 703         .get_groups_count = pinctrl_generic_get_group_count,
 704         .get_group_name = pinctrl_generic_get_group_name,
 705         .get_group_pins = pinctrl_generic_get_group_pins,
 706         .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
 707         .dt_free_map = pinconf_generic_dt_free_map,
 708 };
 709
 710 static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc,
 711                 int pin, int func)
 712 {
 713         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
 714         unsigned int offt = pin / PINS_PER_GPIO_CHIP;
 715
 716         dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",
 717                         'A' + offt, idx, func);
 718
 719         if (jzpc->version >= ID_JZ4770) {
 720                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
 721                 ingenic_config_pin(jzpc, pin, GPIO_MSK, false);
 722                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);
 723                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);
 724         } else {
 725                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true);
 726                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2);
 727                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func > 0);
 728         }
 729
 730         return 0;
 731 }
 732
 733 static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev,
 734                 unsigned int selector, unsigned int group)
 735 {
 736         struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
 737         struct function_desc *func;
 738         struct group_desc *grp;
 739         unsigned int i;
 740
 741         func = pinmux_generic_get_function(pctldev, selector);
 742         if (!func)
 743                 return -EINVAL;
 744
 745         grp = pinctrl_generic_get_group(pctldev, group);
 746         if (!grp)
 747                 return -EINVAL;
 748
 749         dev_dbg(pctldev->dev, "enable function %s group %s\n",
 750                 func->name, grp->name);
 751
 752         for (i = 0; i < grp->num_pins; i++) {
 753                 int *pin_modes = grp->data;
 754
 755                 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]);
 756         }
 757
 758         return 0;
 759 }
 760
 761 static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
 762                 struct pinctrl_gpio_range *range,
 763                 unsigned int pin, bool input)
 764 {
 765         struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
 766         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
 767         unsigned int offt = pin / PINS_PER_GPIO_CHIP;
 768
 769         dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",
 770                         'A' + offt, idx, input ? "in" : "out");
 771
 772         if (jzpc->version >= ID_JZ4770) {
 773                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
 774                 ingenic_config_pin(jzpc, pin, GPIO_MSK, true);
 775                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
 776         } else {
 777                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false);
 778                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input);
 779                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false);
 780         }
 781
 782         return 0;
 783 }
 784
 785 static const struct pinmux_ops ingenic_pmxops = {
 786         .get_functions_count = pinmux_generic_get_function_count,
 787         .get_function_name = pinmux_generic_get_function_name,
 788         .get_function_groups = pinmux_generic_get_function_groups,
 789         .set_mux = ingenic_pinmux_set_mux,
 790         .gpio_set_direction = ingenic_pinmux_gpio_set_direction,
 791 };
 792
 793 static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
 794                 unsigned int pin, unsigned long *config)
 795 {
 796         struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
 797         enum pin_config_param param = pinconf_to_config_param(*config);
 798         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
 799         unsigned int offt = pin / PINS_PER_GPIO_CHIP;
 800         bool pull;
 801
 802         if (jzpc->version >= ID_JZ4770)
 803                 pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN);
 804         else
 805                 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);
 806
 807         switch (param) {
 808         case PIN_CONFIG_BIAS_DISABLE:
 809                 if (pull)
 810                         return -EINVAL;
 811                 break;
 812
 813         case PIN_CONFIG_BIAS_PULL_UP:
 814                 if (!pull || !(jzpc->info->pull_ups[offt] & BIT(idx)))
 815                         return -EINVAL;
 816                 break;
 817
 818         case PIN_CONFIG_BIAS_PULL_DOWN:
 819                 if (!pull || !(jzpc->info->pull_downs[offt] & BIT(idx)))
 820                         return -EINVAL;
 821                 break;
 822
 823         default:
 824                 return -ENOTSUPP;
 825         }
 826
 827         *config = pinconf_to_config_packed(param, 1);
 828         return 0;
 829 }
 830
 831 static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
 832                 unsigned int pin, bool enabled)
 833 {
 834         if (jzpc->version >= ID_JZ4770)
 835                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !enabled);
 836         else
 837                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !enabled);
 838 }
 839
 840 static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 841                 unsigned long *configs, unsigned int num_configs)
 842 {
 843         struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
 844         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
 845         unsigned int offt = pin / PINS_PER_GPIO_CHIP;
 846         unsigned int cfg;
 847
 848         for (cfg = 0; cfg < num_configs; cfg++) {
 849                 switch (pinconf_to_config_param(configs[cfg])) {
 850                 case PIN_CONFIG_BIAS_DISABLE:
 851                 case PIN_CONFIG_BIAS_PULL_UP:
 852                 case PIN_CONFIG_BIAS_PULL_DOWN:
 853                         continue;
 854                 default:
 855                         return -ENOTSUPP;
 856                 }
 857         }
 858
 859         for (cfg = 0; cfg < num_configs; cfg++) {
 860                 switch (pinconf_to_config_param(configs[cfg])) {
 861                 case PIN_CONFIG_BIAS_DISABLE:
 862                         dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n",
 863                                         'A' + offt, idx);
 864                         ingenic_set_bias(jzpc, pin, false);
 865                         break;
 866
 867                 case PIN_CONFIG_BIAS_PULL_UP:
 868                         if (!(jzpc->info->pull_ups[offt] & BIT(idx)))
 869                                 return -EINVAL;
 870                         dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n",
 871                                         'A' + offt, idx);
 872                         ingenic_set_bias(jzpc, pin, true);
 873                         break;
 874
 875                 case PIN_CONFIG_BIAS_PULL_DOWN:
 876                         if (!(jzpc->info->pull_downs[offt] & BIT(idx)))
 877                                 return -EINVAL;
 878                         dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n",
 879                                         'A' + offt, idx);
 880                         ingenic_set_bias(jzpc, pin, true);
 881                         break;
 882
 883                 default:
 884                         unreachable();
 885                 }
 886         }
 887
 888         return 0;
 889 }
 890
 891 static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev,
 892                 unsigned int group, unsigned long *config)
 893 {
 894         const unsigned int *pins;
 895         unsigned int i, npins, old = 0;
 896         int ret;
 897
 898         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
 899         if (ret)
 900                 return ret;
 901
 902         for (i = 0; i < npins; i++) {
 903                 if (ingenic_pinconf_get(pctldev, pins[i], config))
 904                         return -ENOTSUPP;
 905
 906                 /* configs do not match between two pins */
 907                 if (i && (old != *config))
 908                         return -ENOTSUPP;
 909
 910                 old = *config;
 911         }
 912
 913         return 0;
 914 }
 915
 916 static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev,
 917                 unsigned int group, unsigned long *configs,
 918                 unsigned int num_configs)
 919 {
 920         const unsigned int *pins;
 921         unsigned int i, npins;
 922         int ret;
 923
 924         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
 925         if (ret)
 926                 return ret;
 927
 928         for (i = 0; i < npins; i++) {
 929                 ret = ingenic_pinconf_set(pctldev,
 930                                 pins[i], configs, num_configs);
 931                 if (ret)
 932                         return ret;
 933         }
 934
 935         return 0;
 936 }
 937
 938 static const struct pinconf_ops ingenic_confops = {
 939         .is_generic = true,
 940         .pin_config_get = ingenic_pinconf_get,
 941         .pin_config_set = ingenic_pinconf_set,
 942         .pin_config_group_get = ingenic_pinconf_group_get,
 943         .pin_config_group_set = ingenic_pinconf_group_set,
 944 };
 945
 946 static const struct regmap_config ingenic_pinctrl_regmap_config = {
 947         .reg_bits = 32,
 948         .val_bits = 32,
 949         .reg_stride = 4,
 950 };
 951
 952 static const struct of_device_id ingenic_pinctrl_of_match[] = {
 953         { .compatible = "ingenic,jz4740-pinctrl", .data = (void *) ID_JZ4740 },
 954         { .compatible = "ingenic,jz4770-pinctrl", .data = (void *) ID_JZ4770 },
 955         { .compatible = "ingenic,jz4780-pinctrl", .data = (void *) ID_JZ4780 },
 956         {},
 957 };
 958
 959 static const struct of_device_id ingenic_gpio_of_match[] __initconst = {
 960         { .compatible = "ingenic,jz4740-gpio", },
 961         { .compatible = "ingenic,jz4770-gpio", },
 962         { .compatible = "ingenic,jz4780-gpio", },
 963         {},
 964 };
 965
 966 static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc,
 967                                      struct device_node *node)
 968 {
 969         struct ingenic_gpio_chip *jzgc;
 970         struct device *dev = jzpc->dev;
 971         unsigned int bank;
 972         int err;
 973
 974         err = of_property_read_u32(node, "reg", &bank);
 975         if (err) {
 976                 dev_err(dev, "Cannot read \"reg\" property: %i\n", err);
 977                 return err;
 978         }
 979
 980         jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL);
 981         if (!jzgc)
 982                 return -ENOMEM;
 983
 984         jzgc->jzpc = jzpc;
 985         jzgc->reg_base = bank * 0x100;
 986
 987         jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);
 988         if (!jzgc->gc.label)
 989                 return -ENOMEM;
 990
 991         /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY
 992          * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN
 993          * <linux/gpio/consumer.h> INSTEAD.
 994          */
 995         jzgc->gc.base = bank * 32;
 996
 997         jzgc->gc.ngpio = 32;
 998         jzgc->gc.parent = dev;
 999         jzgc->gc.of_node = node;
1000         jzgc->gc.owner = THIS_MODULE;
1001
1002         jzgc->gc.set = ingenic_gpio_set;
1003         jzgc->gc.get = ingenic_gpio_get;
1004         jzgc->gc.direction_input = ingenic_gpio_direction_input;
1005         jzgc->gc.direction_output = ingenic_gpio_direction_output;
1006
1007         if (of_property_read_bool(node, "gpio-ranges")) {
1008                 jzgc->gc.request = gpiochip_generic_request;
1009                 jzgc->gc.free = gpiochip_generic_free;
1010         }
1011
1012         err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);
1013         if (err)
1014                 return err;
1015
1016         jzgc->irq = irq_of_parse_and_map(node, 0);
1017         if (!jzgc->irq)
1018                 return -EINVAL;
1019
1020         jzgc->irq_chip.name = jzgc->gc.label;
1021         jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable;
1022         jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable;
1023         jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask;
1024         jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask;
1025         jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack;
1026         jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type;
1027         jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake;
1028         jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
1029
1030         err = gpiochip_irqchip_add(&jzgc->gc, &jzgc->irq_chip, 0,
1031                         handle_level_irq, IRQ_TYPE_NONE);
1032         if (err)
1033                 return err;
1034
1035         gpiochip_set_chained_irqchip(&jzgc->gc, &jzgc->irq_chip,
1036                         jzgc->irq, ingenic_gpio_irq_handler);
1037         return 0;
1038 }
1039
1040 static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
1041 {
1042         struct device *dev = &pdev->dev;
1043         struct ingenic_pinctrl *jzpc;
1044         struct pinctrl_desc *pctl_desc;
1045         void __iomem *base;
1046         const struct platform_device_id *id = platform_get_device_id(pdev);
1047         const struct of_device_id *of_id = of_match_device(
1048                         ingenic_pinctrl_of_match, dev);
1049         const struct ingenic_chip_info *chip_info;
1050         struct device_node *node;
1051         unsigned int i;
1052         int err;
1053
1054         jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL);
1055         if (!jzpc)
1056                 return -ENOMEM;
1057
1058         base = devm_ioremap_resource(dev,
1059                         platform_get_resource(pdev, IORESOURCE_MEM, 0));
1060         if (IS_ERR(base))
1061                 return PTR_ERR(base);
1062
1063         jzpc->map = devm_regmap_init_mmio(dev, base,
1064                         &ingenic_pinctrl_regmap_config);
1065         if (IS_ERR(jzpc->map)) {
1066                 dev_err(dev, "Failed to create regmap\n");
1067                 return PTR_ERR(jzpc->map);
1068         }
1069
1070         jzpc->dev = dev;
1071
1072         if (of_id)
1073                 jzpc->version = (enum jz_version)of_id->data;
1074         else
1075                 jzpc->version = (enum jz_version)id->driver_data;
1076
1077         if (jzpc->version >= ID_JZ4770)
1078                 chip_info = &jz4770_chip_info;
1079         else
1080                 chip_info = &jz4740_chip_info;
1081         jzpc->info = chip_info;
1082
1083         pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
1084         if (!pctl_desc)
1085                 return -ENOMEM;
1086
1087         /* fill in pinctrl_desc structure */
1088         pctl_desc->name = dev_name(dev);
1089         pctl_desc->owner = THIS_MODULE;
1090         pctl_desc->pctlops = &ingenic_pctlops;
1091         pctl_desc->pmxops = &ingenic_pmxops;
1092         pctl_desc->confops = &ingenic_confops;
1093         pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP;
1094         pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev,
1095                         pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL);
1096         if (!jzpc->pdesc)
1097                 return -ENOMEM;
1098
1099         for (i = 0; i < pctl_desc->npins; i++) {
1100                 jzpc->pdesc[i].number = i;
1101                 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
1102                                                 'A' + (i / PINS_PER_GPIO_CHIP),
1103                                                 i % PINS_PER_GPIO_CHIP);
1104         }
1105
1106         jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc);
1107         if (IS_ERR(jzpc->pctl)) {
1108                 dev_err(dev, "Failed to register pinctrl\n");
1109                 return PTR_ERR(jzpc->pctl);
1110         }
1111
1112         for (i = 0; i < chip_info->num_groups; i++) {
1113                 const struct group_desc *group = &chip_info->groups[i];
1114
1115                 err = pinctrl_generic_add_group(jzpc->pctl, group->name,
1116                                 group->pins, group->num_pins, group->data);
1117                 if (err) {
1118                         dev_err(dev, "Failed to register group %s\n",
1119                                         group->name);
1120                         return err;
1121                 }
1122         }
1123
1124         for (i = 0; i < chip_info->num_functions; i++) {
1125                 const struct function_desc *func = &chip_info->functions[i];
1126
1127                 err = pinmux_generic_add_function(jzpc->pctl, func->name,
1128                                 func->group_names, func->num_group_names,
1129                                 func->data);
1130                 if (err) {
1131                         dev_err(dev, "Failed to register function %s\n",
1132                                         func->name);
1133                         return err;
1134                 }
1135         }
1136
1137         dev_set_drvdata(dev, jzpc->map);
1138
1139         for_each_child_of_node(dev->of_node, node) {
1140                 if (of_match_node(ingenic_gpio_of_match, node)) {
1141                         err = ingenic_gpio_probe(jzpc, node);
1142                         if (err)
1143                                 return err;
1144                 }
1145         }
1146
1147         return 0;
1148 }
1149
1150 static const struct platform_device_id ingenic_pinctrl_ids[] = {
1151         { "jz4740-pinctrl", ID_JZ4740 },
1152         { "jz4770-pinctrl", ID_JZ4770 },
1153         { "jz4780-pinctrl", ID_JZ4780 },
1154         {},
1155 };
1156
1157 static struct platform_driver ingenic_pinctrl_driver = {
1158         .driver = {
1159                 .name = "pinctrl-ingenic",
1160                 .of_match_table = of_match_ptr(ingenic_pinctrl_of_match),
1161         },
1162         .id_table = ingenic_pinctrl_ids,
1163 };
1164
1165 static int __init ingenic_pinctrl_drv_register(void)
1166 {
1167         return platform_driver_probe(&ingenic_pinctrl_driver,
1168                                      ingenic_pinctrl_probe);
1169 }
1170 subsys_initcall(ingenic_pinctrl_drv_register);