drivers/pinctrl/pinctrl-gemini.c

   1 /*
   2  * Driver for the Gemini pin controller
   3  *
   4  * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
   5  *
   6  * This is a group-only pin controller.
   7  */
   8 #include <linux/err.h>
   9 #include <linux/init.h>
  10 #include <linux/io.h>
  11 #include <linux/mfd/syscon.h>
  12 #include <linux/of.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/regmap.h>
  15 #include <linux/seq_file.h>
  16 #include <linux/slab.h>
  17
  18 #include <linux/pinctrl/machine.h>
  19 #include <linux/pinctrl/pinconf-generic.h>
  20 #include <linux/pinctrl/pinconf.h>
  21 #include <linux/pinctrl/pinctrl.h>
  22 #include <linux/pinctrl/pinmux.h>
  23
  24 #include "pinctrl-utils.h"
  25
  26 #define DRIVER_NAME "pinctrl-gemini"
  27
  28 /**
  29  * struct gemini_pin_conf - information about configuring a pin
  30  * @pin: the pin number
  31  * @reg: config register
  32  * @mask: the bits affecting the configuration of the pin
  33  */
  34 struct gemini_pin_conf {
  35         unsigned int pin;
  36         u32 reg;
  37         u32 mask;
  38 };
  39
  40 /**
  41  * struct gemini_pmx - state holder for the gemini pin controller
  42  * @dev: a pointer back to containing device
  43  * @virtbase: the offset to the controller in virtual memory
  44  * @map: regmap to access registers
  45  * @is_3512: whether the SoC/package is the 3512 variant
  46  * @is_3516: whether the SoC/package is the 3516 variant
  47  * @flash_pin: whether the flash pin (extended pins for parallel
  48  * flash) is set
  49  * @confs: pin config information
  50  * @nconfs: number of pin config information items
  51  */
  52 struct gemini_pmx {
  53         struct device *dev;
  54         struct pinctrl_dev *pctl;
  55         struct regmap *map;
  56         bool is_3512;
  57         bool is_3516;
  58         bool flash_pin;
  59         const struct gemini_pin_conf *confs;
  60         unsigned int nconfs;
  61 };
  62
  63 /**
  64  * struct gemini_pin_group - describes a Gemini pin group
  65  * @name: the name of this specific pin group
  66  * @pins: an array of discrete physical pins used in this group, taken
  67  *      from the driver-local pin enumeration space
  68  * @num_pins: the number of pins in this group array, i.e. the number of
  69  *      elements in .pins so we can iterate over that array
  70  * @mask: bits to clear to enable this when doing pin muxing
  71  * @value: bits to set to enable this when doing pin muxing
  72  * @driving_mask: bitmask for the IO Pad driving register for this
  73  *      group, if it supports altering the driving strength of
  74  *      its lines.
  75  */
  76 struct gemini_pin_group {
  77         const char *name;
  78         const unsigned int *pins;
  79         const unsigned int num_pins;
  80         u32 mask;
  81         u32 value;
  82         u32 driving_mask;
  83 };
  84
  85 /* Some straight-forward control registers */
  86 #define GLOBAL_WORD_ID          0x00
  87 #define GLOBAL_STATUS           0x04
  88 #define GLOBAL_STATUS_FLPIN     BIT(20)
  89 #define GLOBAL_IODRIVE          0x10
  90 #define GLOBAL_GMAC_CTRL_SKEW   0x1c
  91 #define GLOBAL_GMAC0_DATA_SKEW  0x20
  92 #define GLOBAL_GMAC1_DATA_SKEW  0x24
  93 /*
  94  * Global Miscellaneous Control Register
  95  * This register controls all Gemini pad/pin multiplexing
  96  *
  97  * It is a tricky register though:
  98  * - For the bits named *_ENABLE, once you DISABLE something, it simply cannot
  99  *   be brought back online, so it means permanent disablement of the
 100  *   corresponding pads.
 101  * - For the bits named *_DISABLE, once you enable something, it cannot be
 102  *   DISABLED again. So you select a flash configuration once, and then
 103  *   you are stuck with it.
 104  */
 105 #define GLOBAL_MISC_CTRL        0x30
 106 #define GEMINI_GMAC_IOSEL_MASK  GENMASK(28, 27)
 107 /* Not really used */
 108 #define GEMINI_GMAC_IOSEL_GMAC0_GMII    BIT(28)
 109 /* Activated with GMAC1 */
 110 #define GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII BIT(27)
 111 /* This will be the default */
 112 #define GEMINI_GMAC_IOSEL_GMAC0_RGMII_GMAC1_GPIO2 0
 113 #define TVC_CLK_PAD_ENABLE      BIT(20)
 114 #define PCI_CLK_PAD_ENABLE      BIT(17)
 115 #define LPC_CLK_PAD_ENABLE      BIT(16)
 116 #define TVC_PADS_ENABLE         BIT(9)
 117 #define SSP_PADS_ENABLE         BIT(8)
 118 #define LCD_PADS_ENABLE         BIT(7)
 119 #define LPC_PADS_ENABLE         BIT(6)
 120 #define PCI_PADS_ENABLE         BIT(5)
 121 #define IDE_PADS_ENABLE         BIT(4)
 122 #define DRAM_PADS_POWERDOWN     BIT(3)
 123 #define NAND_PADS_DISABLE       BIT(2)
 124 #define PFLASH_PADS_DISABLE     BIT(1)
 125 #define SFLASH_PADS_DISABLE     BIT(0)
 126 #define PADS_MASK               (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20) | BIT(27))
 127 #define PADS_MAXBIT             27
 128
 129 /* Ordered by bit index */
 130 static const char * const gemini_padgroups[] = {
 131         "serial flash",
 132         "parallel flash",
 133         "NAND flash",
 134         "DRAM",
 135         "IDE",
 136         "PCI",
 137         "LPC",
 138         "LCD",
 139         "SSP",
 140         "TVC",
 141         NULL, NULL, NULL, NULL, NULL, NULL,
 142         "LPC CLK",
 143         "PCI CLK",
 144         NULL, NULL,
 145         "TVC CLK",
 146         NULL, NULL, NULL, NULL, NULL,
 147         "GMAC1",
 148 };
 149
 150 static const struct pinctrl_pin_desc gemini_3512_pins[] = {
 151         /* Row A */
 152         PINCTRL_PIN(0, "A1 VREF CTRL"),
 153         PINCTRL_PIN(1, "A2 VCC2IO CTRL"),
 154         PINCTRL_PIN(2, "A3 DRAM CK"),
 155         PINCTRL_PIN(3, "A4 DRAM CK N"),
 156         PINCTRL_PIN(4, "A5 DRAM A5"),
 157         PINCTRL_PIN(5, "A6 DRAM CKE"),
 158         PINCTRL_PIN(6, "A7 DRAM DQ11"),
 159         PINCTRL_PIN(7, "A8 DRAM DQ0"),
 160         PINCTRL_PIN(8, "A9 DRAM DQ5"),
 161         PINCTRL_PIN(9, "A10 DRAM DQ6"),
 162         PINCTRL_PIN(10, "A11 DRAM DRAM VREF"),
 163         PINCTRL_PIN(11, "A12 DRAM BA1"),
 164         PINCTRL_PIN(12, "A13 DRAM A2"),
 165         PINCTRL_PIN(13, "A14 PCI GNT1 N"),
 166         PINCTRL_PIN(14, "A15 PCI REQ9 N"),
 167         PINCTRL_PIN(15, "A16 PCI REQ2 N"),
 168         PINCTRL_PIN(16, "A17 PCI REQ3 N"),
 169         PINCTRL_PIN(17, "A18 PCI AD31"),
 170         /* Row B */
 171         PINCTRL_PIN(18, "B1 VCCK CTRL"),
 172         PINCTRL_PIN(19, "B2 PWR EN"),
 173         PINCTRL_PIN(20, "B3 RTC CLKI"),
 174         PINCTRL_PIN(21, "B4 DRAM A4"),
 175         PINCTRL_PIN(22, "B5 DRAM A6"),
 176         PINCTRL_PIN(23, "B6 DRAM A12"),
 177         PINCTRL_PIN(24, "B7 DRAM DQS1"),
 178         PINCTRL_PIN(25, "B8 DRAM DQ15"),
 179         PINCTRL_PIN(26, "B9 DRAM DQ4"),
 180         PINCTRL_PIN(27, "B10 DRAM DQS0"),
 181         PINCTRL_PIN(28, "B11 DRAM WE N"),
 182         PINCTRL_PIN(29, "B12 DRAM A10"),
 183         PINCTRL_PIN(30, "B13 DRAM A3"),
 184         PINCTRL_PIN(31, "B14 PCI GNT0 N"),
 185         PINCTRL_PIN(32, "B15 PCI GNT3 N"),
 186         PINCTRL_PIN(33, "B16 PCI REQ1 N"),
 187         PINCTRL_PIN(34, "B17 PCI AD30"),
 188         PINCTRL_PIN(35, "B18 PCI AD29"),
 189         /* Row C */
 190         PINCTRL_PIN(36, "C1 CIR RST N"), /* REALLY? CIR is not in 3512... */
 191         PINCTRL_PIN(37, "C2 XTALI"),
 192         PINCTRL_PIN(38, "C3 PWR BTN"),
 193         PINCTRL_PIN(39, "C4 RTC CLKO"),
 194         PINCTRL_PIN(40, "C5 DRAM A7"),
 195         PINCTRL_PIN(41, "C6 DRAM A11"),
 196         PINCTRL_PIN(42, "C7 DRAM DQ10"),
 197         PINCTRL_PIN(43, "C8 DRAM DQ14"),
 198         PINCTRL_PIN(44, "C9 DRAM DQ3"),
 199         PINCTRL_PIN(45, "C10 DRAM DQ7"),
 200         PINCTRL_PIN(46, "C11 DRAM CAS N"),
 201         PINCTRL_PIN(47, "C12 DRAM A0"),
 202         PINCTRL_PIN(48, "C13 PCI INT0 N"),
 203         PINCTRL_PIN(49, "C14 EXT RESET N"),
 204         PINCTRL_PIN(50, "C15 PCI GNT2 N"),
 205         PINCTRL_PIN(51, "C16 PCI AD28"),
 206         PINCTRL_PIN(52, "C17 PCI AD27"),
 207         PINCTRL_PIN(53, "C18 PCI AD26"),
 208         /* Row D */
 209         PINCTRL_PIN(54, "D1 AVCCKHA"),
 210         PINCTRL_PIN(55, "D2 AGNDIOHA"),
 211         PINCTRL_PIN(56, "D3 XTALO"),
 212         PINCTRL_PIN(57, "D4 AVCC3IOHA"),
 213         PINCTRL_PIN(58, "D5 DRAM A8"),
 214         PINCTRL_PIN(59, "D6 DRAM A9"),
 215         PINCTRL_PIN(60, "D7 DRAM DQ9"),
 216         PINCTRL_PIN(61, "D8 DRAM DQ13"),
 217         PINCTRL_PIN(62, "D9 DRAM DQ2"),
 218         PINCTRL_PIN(63, "D10 DRAM A13"),
 219         PINCTRL_PIN(64, "D11 DRAM RAS N"),
 220         PINCTRL_PIN(65, "D12 DRAM A1"),
 221         PINCTRL_PIN(66, "D13 PCI INTC N"),
 222         PINCTRL_PIN(67, "D14 PCI CLK"),
 223         PINCTRL_PIN(68, "D15 PCI AD25"),
 224         PINCTRL_PIN(69, "D16 PCI AD24"),
 225         PINCTRL_PIN(70, "D17 PCI CBE3 N"),
 226         PINCTRL_PIN(71, "D18 PCI AD23"),
 227         /* Row E */
 228         PINCTRL_PIN(72, "E1 AVCC3IOHA"),
 229         PINCTRL_PIN(73, "E2 EBG"),
 230         PINCTRL_PIN(74, "E3 AVCC3IOHB"),
 231         PINCTRL_PIN(75, "E4 REXT"),
 232         PINCTRL_PIN(76, "E5 GND"),
 233         PINCTRL_PIN(77, "E6 DRAM DQM1"),
 234         PINCTRL_PIN(78, "E7 DRAM DQ8"),
 235         PINCTRL_PIN(79, "E8 DRAM DQ12"),
 236         PINCTRL_PIN(80, "E9 DRAM DQ1"),
 237         PINCTRL_PIN(81, "E10 DRAM DQM0"),
 238         PINCTRL_PIN(82, "E11 DRAM BA0"),
 239         PINCTRL_PIN(83, "E12 PCI INTA N"),
 240         PINCTRL_PIN(84, "E13 PCI INTB N"),
 241         PINCTRL_PIN(85, "E14 GND"),
 242         PINCTRL_PIN(86, "E15 PCI AD22"),
 243         PINCTRL_PIN(87, "E16 PCI AD21"),
 244         PINCTRL_PIN(88, "E17 PCI AD20"),
 245         PINCTRL_PIN(89, "E18 PCI AD19"),
 246         /* Row F */
 247         PINCTRL_PIN(90, "F1 SATA0 RXDP"),
 248         PINCTRL_PIN(91, "F2 SATA0 RXDN"),
 249         PINCTRL_PIN(92, "F3 AGNDK 0"),
 250         PINCTRL_PIN(93, "F4 AVCC3 S"),
 251         PINCTRL_PIN(94, "F5 AVCCK P"),
 252         PINCTRL_PIN(95, "F6 GND"),
 253         PINCTRL_PIN(96, "F7 VCC2IOHA 2"),
 254         PINCTRL_PIN(97, "F8 VCC2IOHA 2"),
 255         PINCTRL_PIN(98, "F9 V1"),
 256         PINCTRL_PIN(99, "F10 V1"),
 257         PINCTRL_PIN(100, "F11 VCC2IOHA 2"),
 258         PINCTRL_PIN(101, "F12 VCC2IOHA 2"),
 259         PINCTRL_PIN(102, "F13 GND"),
 260         PINCTRL_PIN(103, "F14 PCI AD18"),
 261         PINCTRL_PIN(104, "F15 PCI AD17"),
 262         PINCTRL_PIN(105, "F16 PCI AD16"),
 263         PINCTRL_PIN(106, "F17 PCI CBE2 N"),
 264         PINCTRL_PIN(107, "F18 PCI FRAME N"),
 265         /* Row G */
 266         PINCTRL_PIN(108, "G1 SATA0 TXDP"),
 267         PINCTRL_PIN(109, "G2 SATA0 TXDN"),
 268         PINCTRL_PIN(110, "G3 AGNDK 1"),
 269         PINCTRL_PIN(111, "G4 AVCCK 0"),
 270         PINCTRL_PIN(112, "G5 TEST CLKOUT"),
 271         PINCTRL_PIN(113, "G6 AGND"),
 272         PINCTRL_PIN(114, "G7 GND"),
 273         PINCTRL_PIN(115, "G8 VCC2IOHA 2"),
 274         PINCTRL_PIN(116, "G9 V1"),
 275         PINCTRL_PIN(117, "G10 V1"),
 276         PINCTRL_PIN(118, "G11 VCC2IOHA 2"),
 277         PINCTRL_PIN(119, "G12 GND"),
 278         PINCTRL_PIN(120, "G13 VCC3IOHA"),
 279         PINCTRL_PIN(121, "G14 PCI IRDY N"),
 280         PINCTRL_PIN(122, "G15 PCI TRDY N"),
 281         PINCTRL_PIN(123, "G16 PCI DEVSEL N"),
 282         PINCTRL_PIN(124, "G17 PCI STOP N"),
 283         PINCTRL_PIN(125, "G18 PCI PAR"),
 284         /* Row H */
 285         PINCTRL_PIN(126, "H1 SATA1 TXDP"),
 286         PINCTRL_PIN(127, "H2 SATA1 TXDN"),
 287         PINCTRL_PIN(128, "H3 AGNDK 2"),
 288         PINCTRL_PIN(129, "H4 AVCCK 1"),
 289         PINCTRL_PIN(130, "H5 AVCCK S"),
 290         PINCTRL_PIN(131, "H6 AVCCKHB"),
 291         PINCTRL_PIN(132, "H7 AGND"),
 292         PINCTRL_PIN(133, "H8 GND"),
 293         PINCTRL_PIN(134, "H9 GND"),
 294         PINCTRL_PIN(135, "H10 GND"),
 295         PINCTRL_PIN(136, "H11 GND"),
 296         PINCTRL_PIN(137, "H12 VCC3IOHA"),
 297         PINCTRL_PIN(138, "H13 VCC3IOHA"),
 298         PINCTRL_PIN(139, "H14 PCI CBE1 N"),
 299         PINCTRL_PIN(140, "H15 PCI AD15"),
 300         PINCTRL_PIN(141, "H16 PCI AD14"),
 301         PINCTRL_PIN(142, "H17 PCI AD13"),
 302         PINCTRL_PIN(143, "H18 PCI AD12"),
 303         /* Row J (for some reason I is skipped) */
 304         PINCTRL_PIN(144, "J1 SATA1 RXDP"),
 305         PINCTRL_PIN(145, "J2 SATA1 RXDN"),
 306         PINCTRL_PIN(146, "J3 AGNDK 3"),
 307         PINCTRL_PIN(147, "J4 AVCCK 2"),
 308         PINCTRL_PIN(148, "J5 IDE DA1"),
 309         PINCTRL_PIN(149, "J6 V1"),
 310         PINCTRL_PIN(150, "J7 V1"),
 311         PINCTRL_PIN(151, "J8 GND"),
 312         PINCTRL_PIN(152, "J9 GND"),
 313         PINCTRL_PIN(153, "J10 GND"),
 314         PINCTRL_PIN(154, "J11 GND"),
 315         PINCTRL_PIN(155, "J12 V1"),
 316         PINCTRL_PIN(156, "J13 V1"),
 317         PINCTRL_PIN(157, "J14 PCI AD11"),
 318         PINCTRL_PIN(158, "J15 PCI AD10"),
 319         PINCTRL_PIN(159, "J16 PCI AD9"),
 320         PINCTRL_PIN(160, "J17 PCI AD8"),
 321         PINCTRL_PIN(161, "J18 PCI CBE0 N"),
 322         /* Row K */
 323         PINCTRL_PIN(162, "K1 IDE CS1 N"),
 324         PINCTRL_PIN(163, "K2 IDE CS0 N"),
 325         PINCTRL_PIN(164, "K3 AVCCK 3"),
 326         PINCTRL_PIN(165, "K4 IDE DA2"),
 327         PINCTRL_PIN(166, "K5 IDE DA0"),
 328         PINCTRL_PIN(167, "K6 V1"),
 329         PINCTRL_PIN(168, "K7 V1"),
 330         PINCTRL_PIN(169, "K8 GND"),
 331         PINCTRL_PIN(170, "K9 GND"),
 332         PINCTRL_PIN(171, "K10 GND"),
 333         PINCTRL_PIN(172, "K11 GND"),
 334         PINCTRL_PIN(173, "K12 V1"),
 335         PINCTRL_PIN(174, "K13 V1"),
 336         PINCTRL_PIN(175, "K14 PCI AD3"),
 337         PINCTRL_PIN(176, "K15 PCI AD4"),
 338         PINCTRL_PIN(177, "K16 PCI AD5"),
 339         PINCTRL_PIN(178, "K17 PCI AD6"),
 340         PINCTRL_PIN(179, "K18 PCI AD7"),
 341         /* Row L */
 342         PINCTRL_PIN(180, "L1 IDE INTRQ"),
 343         PINCTRL_PIN(181, "L2 IDE DMACK N"),
 344         PINCTRL_PIN(182, "L3 IDE IORDY"),
 345         PINCTRL_PIN(183, "L4 IDE DIOR N"),
 346         PINCTRL_PIN(184, "L5 IDE DIOW N"),
 347         PINCTRL_PIN(185, "L6 VCC3IOHA"),
 348         PINCTRL_PIN(186, "L7 VCC3IOHA"),
 349         PINCTRL_PIN(187, "L8 GND"),
 350         PINCTRL_PIN(188, "L9 GND"),
 351         PINCTRL_PIN(189, "L10 GND"),
 352         PINCTRL_PIN(190, "L11 GND"),
 353         PINCTRL_PIN(191, "L12 VCC3IOHA"),
 354         PINCTRL_PIN(192, "L13 VCC3IOHA"),
 355         PINCTRL_PIN(193, "L14 GPIO0 30"),
 356         PINCTRL_PIN(194, "L15 GPIO0 31"),
 357         PINCTRL_PIN(195, "L16 PCI AD0"),
 358         PINCTRL_PIN(196, "L17 PCI AD1"),
 359         PINCTRL_PIN(197, "L18 PCI AD2"),
 360         /* Row M */
 361         PINCTRL_PIN(198, "M1 IDE DMARQ"),
 362         PINCTRL_PIN(199, "M2 IDE DD15"),
 363         PINCTRL_PIN(200, "M3 IDE DD0"),
 364         PINCTRL_PIN(201, "M4 IDE DD14"),
 365         PINCTRL_PIN(202, "M5 IDE DD1"),
 366         PINCTRL_PIN(203, "M6 VCC3IOHA"),
 367         PINCTRL_PIN(204, "M7 GND"),
 368         PINCTRL_PIN(205, "M8 VCC2IOHA 1"),
 369         PINCTRL_PIN(206, "M9 V1"),
 370         PINCTRL_PIN(207, "M10 V1"),
 371         PINCTRL_PIN(208, "M11 VCC3IOHA"),
 372         PINCTRL_PIN(209, "M12 GND"),
 373         PINCTRL_PIN(210, "M13 VCC3IOHA"),
 374         PINCTRL_PIN(211, "M14 GPIO0 25"),
 375         PINCTRL_PIN(212, "M15 GPIO0 26"),
 376         PINCTRL_PIN(213, "M16 GPIO0 27"),
 377         PINCTRL_PIN(214, "M17 GPIO0 28"),
 378         PINCTRL_PIN(215, "M18 GPIO0 29"),
 379         /* Row N */
 380         PINCTRL_PIN(216, "N1 IDE DD13"),
 381         PINCTRL_PIN(217, "N2 IDE DD2"),
 382         PINCTRL_PIN(218, "N3 IDE DD12"),
 383         PINCTRL_PIN(219, "N4 IDE DD3"),
 384         PINCTRL_PIN(220, "N5 IDE DD11"),
 385         PINCTRL_PIN(221, "N6 GND"),
 386         PINCTRL_PIN(222, "N7 VCC2IOHA 1"),
 387         PINCTRL_PIN(223, "N8 VCC2IOHA 1"),
 388         PINCTRL_PIN(224, "N9 V1"),
 389         PINCTRL_PIN(225, "N10 V1"),
 390         PINCTRL_PIN(226, "N11 VCC3IOHA"),
 391         PINCTRL_PIN(227, "N12 VCC3IOHA"),
 392         PINCTRL_PIN(228, "N13 GND"),
 393         PINCTRL_PIN(229, "N14 GPIO0 20"),
 394         PINCTRL_PIN(230, "N15 GPIO0 21"),
 395         PINCTRL_PIN(231, "N16 GPIO0 22"),
 396         PINCTRL_PIN(232, "N17 GPIO0 23"),
 397         PINCTRL_PIN(233, "N18 GPIO0 24"),
 398         /* Row P (for some reason O is skipped) */
 399         PINCTRL_PIN(234, "P1 IDE DD4"),
 400         PINCTRL_PIN(235, "P2 IDE DD10"),
 401         PINCTRL_PIN(236, "P3 IDE DD5"),
 402         PINCTRL_PIN(237, "P4 IDE DD9"),
 403         PINCTRL_PIN(238, "P5 GND"),
 404         PINCTRL_PIN(239, "P6 USB XSCO"),
 405         PINCTRL_PIN(240, "P7 GMAC0 TXD3"),
 406         PINCTRL_PIN(241, "P8 GMAC0 TXEN"),
 407         PINCTRL_PIN(242, "P9 GMAC0 RXD2"),
 408         PINCTRL_PIN(243, "P10 GMAC1 TXC"),
 409         PINCTRL_PIN(244, "P11 GMAC1 RXD1"),
 410         PINCTRL_PIN(245, "P12 MODE SEL 1"),
 411         PINCTRL_PIN(246, "P13 GPIO1 28"),
 412         PINCTRL_PIN(247, "P14 GND"),
 413         PINCTRL_PIN(248, "P15 GPIO0 5"),
 414         PINCTRL_PIN(249, "P16 GPIO0 17"),
 415         PINCTRL_PIN(250, "P17 GPIO0 18"),
 416         PINCTRL_PIN(251, "P18 GPIO0 19"),
 417         /* Row R (for some reason Q is skipped) */
 418         PINCTRL_PIN(252, "R1 IDE DD6"),
 419         PINCTRL_PIN(253, "R2 IDE DD8"),
 420         PINCTRL_PIN(254, "R3 IDE DD7"),
 421         PINCTRL_PIN(255, "R4 IDE RESET N"),
 422         PINCTRL_PIN(256, "R5 ICE0 DBGACK"),
 423         PINCTRL_PIN(257, "R6 USB XSCI"),
 424         PINCTRL_PIN(258, "R7 GMAC0 TXD2"),
 425         PINCTRL_PIN(259, "R8 GMAC0 RXDV"),
 426         PINCTRL_PIN(260, "R9 GMAC0 RXD3"),
 427         PINCTRL_PIN(261, "R10 GMAC1 TXD0"),
 428         PINCTRL_PIN(262, "R11 GMAC1 RXD0"),
 429         PINCTRL_PIN(263, "R12 MODE SEL 0"),
 430         PINCTRL_PIN(264, "R13 MODE SEL 3"),
 431         PINCTRL_PIN(265, "R14 GPIO0 0"),
 432         PINCTRL_PIN(266, "R15 GPIO0 4"),
 433         PINCTRL_PIN(267, "R16 GPIO0 9"),
 434         PINCTRL_PIN(268, "R17 GPIO0 15"),
 435         PINCTRL_PIN(269, "R18 GPIO0 16"),
 436         /* Row T (for some reason S is skipped) */
 437         PINCTRL_PIN(270, "T1 ICE0 DBGRQ"),
 438         PINCTRL_PIN(271, "T2 ICE0 IDO"),
 439         PINCTRL_PIN(272, "T3 ICE0 ICK"),
 440         PINCTRL_PIN(273, "T4 ICE0 IMS"),
 441         PINCTRL_PIN(274, "T5 ICE0 IDI"),
 442         PINCTRL_PIN(275, "T6 USB RREF"),
 443         PINCTRL_PIN(276, "T7 GMAC0 TXD1"),
 444         PINCTRL_PIN(277, "T8 GMAC0 RXC"),
 445         PINCTRL_PIN(278, "T9 GMAC0 CRS"),
 446         PINCTRL_PIN(279, "T10 GMAC1 TXD1"),
 447         PINCTRL_PIN(280, "T11 GMAC1 RXC"),
 448         PINCTRL_PIN(281, "T12 GMAC1 CRS"),
 449         PINCTRL_PIN(282, "T13 EXT CLK"),
 450         PINCTRL_PIN(283, "T14 GPIO1 31"),
 451         PINCTRL_PIN(284, "T15 GPIO0 3"),
 452         PINCTRL_PIN(285, "T16 GPIO0 8"),
 453         PINCTRL_PIN(286, "T17 GPIO0 12"),
 454         PINCTRL_PIN(287, "T18 GPIO0 14"),
 455         /* Row U */
 456         PINCTRL_PIN(288, "U1 ICE0 IRST N"),
 457         PINCTRL_PIN(289, "U2 USB0 VCCHSRT"),
 458         PINCTRL_PIN(290, "U3 USB0 DP"),
 459         PINCTRL_PIN(291, "U4 USB VCCA U20"),
 460         PINCTRL_PIN(292, "U5 USB1 DP"),
 461         PINCTRL_PIN(293, "U6 USB1 GNDHSRT 1"),
 462         PINCTRL_PIN(294, "U7 GMAC0 TXD0"),
 463         PINCTRL_PIN(295, "U8 GMAC0 RXD0"),
 464         PINCTRL_PIN(296, "U9 GMAC1 COL"),
 465         PINCTRL_PIN(297, "U10 GMAC1 TXD2"),
 466         PINCTRL_PIN(298, "U11 GMAC1 RXDV"),
 467         PINCTRL_PIN(299, "U12 GMAC1 RXD3"),
 468         PINCTRL_PIN(300, "U13 MODE SEL 2"),
 469         PINCTRL_PIN(301, "U14 GPIO1 30"),
 470         PINCTRL_PIN(302, "U15 GPIO0 2"),
 471         PINCTRL_PIN(303, "U16 GPIO0 7"),
 472         PINCTRL_PIN(304, "U17 GPIO0 11"),
 473         PINCTRL_PIN(305, "U18 GPIO0 13"),
 474         /* Row V */
 475         PINCTRL_PIN(306, "V1 USB0 GNDHSRT"),
 476         PINCTRL_PIN(307, "V2 USB0 DM"),
 477         PINCTRL_PIN(308, "V3 USB GNDA U20"),
 478         PINCTRL_PIN(309, "V4 USB1 DM"),
 479         PINCTRL_PIN(310, "V5 USB1 VCCHSRT1"),
 480         PINCTRL_PIN(311, "V6 GMAC0 COL"),
 481         PINCTRL_PIN(312, "V7 GMAC0 TXC"),
 482         PINCTRL_PIN(313, "V8 GMAC0 RXD1"),
 483         PINCTRL_PIN(314, "V9 REF CLK"),
 484         PINCTRL_PIN(315, "V10 GMAC1 TXD3"),
 485         PINCTRL_PIN(316, "V11 GMAC1 TXEN"),
 486         PINCTRL_PIN(317, "V12 GMAC1 RXD2"),
 487         PINCTRL_PIN(318, "V13 M30 CLK"),
 488         PINCTRL_PIN(319, "V14 GPIO1 29"),
 489         PINCTRL_PIN(320, "V15 GPIO0 1"),
 490         PINCTRL_PIN(321, "V16 GPIO0 6"),
 491         PINCTRL_PIN(322, "V17 GPIO0 10"),
 492         PINCTRL_PIN(323, "V18 SYS RESET N"),
 493 };
 494
 495
 496 /* Digital ground */
 497 static const unsigned int gnd_3512_pins[] = {
 498         76, 85, 95, 102, 114, 119, 133, 134, 135, 136, 151, 152, 153, 154, 169,
 499         170, 171, 172, 187, 188, 189, 190, 204, 209, 221, 228, 238, 247
 500 };
 501
 502 static const unsigned int dram_3512_pins[] = {
 503         2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 21, 22, 23, 24, 25, 26, 27, 28, 29,
 504         30, 40, 41, 42, 43, 44, 45, 46, 47, 58, 59, 60, 61, 62, 63, 64, 65, 77,
 505         78, 79, 80, 81, 82
 506 };
 507
 508 static const unsigned int rtc_3512_pins[] = { 57, 20, 39 };
 509
 510 static const unsigned int power_3512_pins[] = { 19, 38, 36, 55, 37, 56, 54, 72 };
 511
 512 static const unsigned int system_3512_pins[] = {
 513         318, 264, 300, 245, 263, 282, 314, 323, 49,
 514 };
 515
 516 static const unsigned int vcontrol_3512_pins[] = { 18, 0, 1 };
 517
 518 static const unsigned int ice_3512_pins[] = { 256, 270, 271, 272, 273, 274, 288 };
 519
 520 static const unsigned int ide_3512_pins[] = {
 521         162, 163, 165, 166, 148, 180, 181, 182, 183, 184, 198, 199, 200, 201, 202,
 522         216, 217, 218, 219, 220, 234, 235, 236, 237, 252, 253, 254, 255
 523 };
 524
 525 static const unsigned int sata_3512_pins[] = {
 526         75, 74, 73, 93, 94, 131, 112, 130, 92, 91, 90, 111, 110, 109, 108, 129,
 527         128, 127, 126, 147, 146, 145, 144, 164
 528 };
 529
 530 static const unsigned int usb_3512_pins[] = {
 531         306, 289, 307, 290, 239, 257, 275, 308, 291, 309, 292, 310, 293
 532 };
 533
 534 /* GMII, ethernet pins */
 535 static const unsigned int gmii_gmac0_3512_pins[] = {
 536         240, 241, 242, 258, 259, 260, 276, 277, 278, 294, 295, 311, 312, 313
 537 };
 538
 539 static const unsigned int gmii_gmac1_3512_pins[] = {
 540         243, 244, 261, 262, 279, 280, 281, 296, 297, 298, 299, 315, 316, 317
 541 };
 542
 543 static const unsigned int pci_3512_pins[] = {
 544         13, 14, 15, 16, 17, 31, 32, 33, 34, 35, 48, 50, 51, 52, 53, 66, 67, 68, 69,
 545         70, 71, 83, 84, 86, 87, 88, 89, 103, 104, 105, 106, 107, 121, 122, 123,
 546         124, 125, 139, 140, 141, 142, 143, 157, 158, 159, 160, 161, 175, 176, 177,
 547         178, 179, 195, 196, 197
 548 };
 549
 550 /*
 551  * Apparently the LPC interface is using the PCICLK for the clocking so
 552  * PCI needs to be active at the same time.
 553  */
 554 static const unsigned int lpc_3512_pins[] = {
 555         285, /* LPC_LAD[0] */
 556         304, /* LPC_SERIRQ */
 557         286, /* LPC_LAD[2] */
 558         305, /* LPC_LFRAME# */
 559         287, /* LPC_LAD[3] */
 560         268, /* LPC_LAD[1] */
 561 };
 562
 563 /* Character LCD */
 564 static const unsigned int lcd_3512_pins[] = {
 565         262, 244, 317, 299, 246, 319, 301, 283, 269, 233, 211
 566 };
 567
 568 static const unsigned int ssp_3512_pins[] = {
 569         285, /* SSP_97RST# SSP AC97 Reset, active low */
 570         304, /* SSP_FSC */
 571         286, /* SSP_ECLK */
 572         305, /* SSP_TXD */
 573         287, /* SSP_RXD */
 574         268, /* SSP_SCLK */
 575 };
 576
 577 static const unsigned int uart_rxtx_3512_pins[] = {
 578         267, /* UART_SIN serial input, RX */
 579         322, /* UART_SOUT serial output, TX */
 580 };
 581
 582 static const unsigned int uart_modem_3512_pins[] = {
 583         285, /* UART_NDCD DCD carrier detect */
 584         304, /* UART_NDTR DTR data terminal ready */
 585         286, /* UART_NDSR DSR data set ready */
 586         305, /* UART_NRTS RTS request to send */
 587         287, /* UART_NCTS CTS clear to send */
 588         268, /* UART_NRI RI ring indicator */
 589 };
 590
 591 static const unsigned int tvc_3512_pins[] = {
 592         246, /* TVC_DATA[0] */
 593         319, /* TVC_DATA[1] */
 594         301, /* TVC_DATA[2] */
 595         283, /* TVC_DATA[3] */
 596         320, /* TVC_DATA[4] */
 597         302, /* TVC_DATA[5] */
 598         284, /* TVC_DATA[6] */
 599         266, /* TVC_DATA[7] */
 600 };
 601
 602 static const unsigned int tvc_clk_3512_pins[] = {
 603         265, /* TVC_CLK */
 604 };
 605
 606 /* NAND flash pins */
 607 static const unsigned int nflash_3512_pins[] = {
 608         199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237, 252,
 609         253, 254, 249, 250, 232, 233, 211, 193, 194
 610 };
 611
 612 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
 613 static const unsigned int pflash_3512_pins[] = {
 614         162, 163, 165, 166, 148, 199, 200, 201, 202, 216, 217, 218, 219, 220,
 615         234, 235, 236, 237, 252, 253, 254, 251, 229, 232, 233, 211, 212, 213,
 616         214, 215, 193, 194
 617 };
 618
 619 /*
 620  * The parallel flash can be set up in a 26-bit address bus mode exposing
 621  * A[0-15] (A[15] takes the place of ALE), but it has the
 622  * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be
 623  * used at the same time.
 624  */
 625 static const unsigned int pflash_3512_pins_extended[] = {
 626         162, 163, 165, 166, 148, 199, 200, 201, 202, 216, 217, 218, 219, 220,
 627         234, 235, 236, 237, 252, 253, 254, 251, 229, 232, 233, 211, 212, 213,
 628         214, 215, 193, 194,
 629         /* The extra pins */
 630         296, 315, 297, 279, 261, 243, 316, 298, 280, 262, 244, 317, 299, 281,
 631         265,
 632 };
 633
 634 /* Serial flash pins CE0, CE1, DI, DO, CK */
 635 static const unsigned int sflash_3512_pins[] = { 230, 231, 232, 233, 211 };
 636
 637 /* The GPIO0A (0) pin overlap with TVC CLK and extended parallel flash */
 638 static const unsigned int gpio0a_3512_pins[] = { 265 };
 639
 640 /* The GPIO0B (1-4) pins overlap with TVC and ICE */
 641 static const unsigned int gpio0b_3512_pins[] = { 320, 302, 284, 266 };
 642
 643 /* The GPIO0C (5-7) pins overlap with ICE */
 644 static const unsigned int gpio0c_3512_pins[] = { 248, 321, 303 };
 645
 646 /* The GPIO0D (9,10) pins overlap with UART RX/TX */
 647 static const unsigned int gpio0d_3512_pins[] = { 267, 322 };
 648
 649 /* The GPIO0E (8,11-15) pins overlap with LPC, UART modem pins, SSP */
 650 static const unsigned int gpio0e_3512_pins[] = { 285, 304, 286, 305, 287, 268 };
 651
 652 /* The GPIO0F (16) pins overlap with LCD */
 653 static const unsigned int gpio0f_3512_pins[] = { 269 };
 654
 655 /* The GPIO0G (17,18) pins overlap with NAND flash CE0, CE1 */
 656 static const unsigned int gpio0g_3512_pins[] = { 249, 250 };
 657
 658 /* The GPIO0H (19,20) pins overlap with parallel flash CE0, CE1 */
 659 static const unsigned int gpio0h_3512_pins[] = { 251, 229 };
 660
 661 /* The GPIO0I (21,22) pins overlap with serial flash CE0, CE1 */
 662 static const unsigned int gpio0i_3512_pins[] = { 230, 231 };
 663
 664 /* The GPIO0J (23) pins overlap with all flash */
 665 static const unsigned int gpio0j_3512_pins[] = { 232 };
 666
 667 /* The GPIO0K (24,25) pins overlap with all flash and LCD */
 668 static const unsigned int gpio0k_3512_pins[] = { 233, 211 };
 669
 670 /* The GPIO0L (26-29) pins overlap with parallel flash */
 671 static const unsigned int gpio0l_3512_pins[] = { 212, 213, 214, 215 };
 672
 673 /* The GPIO0M (30,31) pins overlap with parallel flash and NAND flash */
 674 static const unsigned int gpio0m_3512_pins[] = { 193, 194 };
 675
 676 /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
 677 static const unsigned int gpio1a_3512_pins[] = { 162, 163, 165, 166, 148 };
 678
 679 /* The GPIO1B (5-10, 27) pins overlap with just IDE */
 680 static const unsigned int gpio1b_3512_pins[] = {
 681         180, 181, 182, 183, 184, 198, 255
 682 };
 683
 684 /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */
 685 static const unsigned int gpio1c_3512_pins[] = {
 686         199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237,
 687         252, 253, 254
 688 };
 689
 690 /* The GPIO1D (28-31) pins overlap with LCD and TVC */
 691 static const unsigned int gpio1d_3512_pins[] = { 246, 319, 301, 283 };
 692
 693 /* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
 694 static const unsigned int gpio2a_3512_pins[] = { 315, 297, 279, 261 };
 695
 696 /* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
 697 static const unsigned int gpio2b_3512_pins[] = { 262, 244, 317, 299 };
 698
 699 /* The GPIO2C (8-31) pins overlap with PCI */
 700 static const unsigned int gpio2c_3512_pins[] = {
 701         17, 34, 35, 51, 52, 53, 68, 69, 71, 86, 87, 88, 89, 103, 104, 105,
 702         140, 141, 142, 143, 157, 158, 159, 160
 703 };
 704
 705 /* Groups for the 3512 SoC/package */
 706 static const struct gemini_pin_group gemini_3512_pin_groups[] = {
 707         {
 708                 .name = "gndgrp",
 709                 .pins = gnd_3512_pins,
 710                 .num_pins = ARRAY_SIZE(gnd_3512_pins),
 711         },
 712         {
 713                 .name = "dramgrp",
 714                 .pins = dram_3512_pins,
 715                 .num_pins = ARRAY_SIZE(dram_3512_pins),
 716                 .mask = DRAM_PADS_POWERDOWN,
 717         },
 718         {
 719                 .name = "rtcgrp",
 720                 .pins = rtc_3512_pins,
 721                 .num_pins = ARRAY_SIZE(rtc_3512_pins),
 722         },
 723         {
 724                 .name = "powergrp",
 725                 .pins = power_3512_pins,
 726                 .num_pins = ARRAY_SIZE(power_3512_pins),
 727         },
 728         {
 729                 .name = "systemgrp",
 730                 .pins = system_3512_pins,
 731                 .num_pins = ARRAY_SIZE(system_3512_pins),
 732         },
 733         {
 734                 .name = "vcontrolgrp",
 735                 .pins = vcontrol_3512_pins,
 736                 .num_pins = ARRAY_SIZE(vcontrol_3512_pins),
 737         },
 738         {
 739                 .name = "icegrp",
 740                 .pins = ice_3512_pins,
 741                 .num_pins = ARRAY_SIZE(ice_3512_pins),
 742                 /* Conflict with some GPIO groups */
 743         },
 744         {
 745                 .name = "idegrp",
 746                 .pins = ide_3512_pins,
 747                 .num_pins = ARRAY_SIZE(ide_3512_pins),
 748                 /* Conflict with all flash usage */
 749                 .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE |
 750                         PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
 751                 .driving_mask = GENMASK(21, 20),
 752         },
 753         {
 754                 .name = "satagrp",
 755                 .pins = sata_3512_pins,
 756                 .num_pins = ARRAY_SIZE(sata_3512_pins),
 757         },
 758         {
 759                 .name = "usbgrp",
 760                 .pins = usb_3512_pins,
 761                 .num_pins = ARRAY_SIZE(usb_3512_pins),
 762         },
 763         {
 764                 .name = "gmii_gmac0_grp",
 765                 .pins = gmii_gmac0_3512_pins,
 766                 .num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins),
 767                 .driving_mask = GENMASK(17, 16),
 768         },
 769         {
 770                 .name = "gmii_gmac1_grp",
 771                 .pins = gmii_gmac1_3512_pins,
 772                 .num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins),
 773                 /* Bring out RGMII on the GMAC1 pins */
 774                 .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
 775                 .driving_mask = GENMASK(19, 18),
 776         },
 777         {
 778                 .name = "pcigrp",
 779                 .pins = pci_3512_pins,
 780                 .num_pins = ARRAY_SIZE(pci_3512_pins),
 781                 /* Conflict only with GPIO2 */
 782                 .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE,
 783                 .driving_mask = GENMASK(23, 22),
 784         },
 785         {
 786                 .name = "lpcgrp",
 787                 .pins = lpc_3512_pins,
 788                 .num_pins = ARRAY_SIZE(lpc_3512_pins),
 789                 /* Conflict with SSP and UART modem pins */
 790                 .mask = SSP_PADS_ENABLE,
 791                 .value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE,
 792         },
 793         {
 794                 .name = "lcdgrp",
 795                 .pins = lcd_3512_pins,
 796                 .num_pins = ARRAY_SIZE(lcd_3512_pins),
 797                 /* Conflict with TVC and ICE */
 798                 .mask = TVC_PADS_ENABLE,
 799                 .value = LCD_PADS_ENABLE,
 800         },
 801         {
 802                 .name = "sspgrp",
 803                 .pins = ssp_3512_pins,
 804                 .num_pins = ARRAY_SIZE(ssp_3512_pins),
 805                 /* Conflict with LPC and UART modem pins */
 806                 .mask = LPC_PADS_ENABLE,
 807                 .value = SSP_PADS_ENABLE,
 808         },
 809         {
 810                 .name = "uartrxtxgrp",
 811                 .pins = uart_rxtx_3512_pins,
 812                 .num_pins = ARRAY_SIZE(uart_rxtx_3512_pins),
 813                 /* No conflicts except GPIO */
 814         },
 815         {
 816                 .name = "uartmodemgrp",
 817                 .pins = uart_modem_3512_pins,
 818                 .num_pins = ARRAY_SIZE(uart_modem_3512_pins),
 819                 /*
 820                  * Conflict with LPC and SSP,
 821                  * so when those are both disabled, modem UART can thrive.
 822                  */
 823                 .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
 824         },
 825         {
 826                 .name = "tvcgrp",
 827                 .pins = tvc_3512_pins,
 828                 .num_pins = ARRAY_SIZE(tvc_3512_pins),
 829                 /* Conflict with character LCD and ICE */
 830                 .mask = LCD_PADS_ENABLE,
 831                 .value = TVC_PADS_ENABLE,
 832         },
 833         {
 834                 .name = "tvcclkgrp",
 835                 .pins = tvc_clk_3512_pins,
 836                 .num_pins = ARRAY_SIZE(tvc_clk_3512_pins),
 837                 .value = TVC_CLK_PAD_ENABLE,
 838         },
 839         /*
 840          * The construction is done such that it is possible to use a serial
 841          * flash together with a NAND or parallel (NOR) flash, but it is not
 842          * possible to use NAND and parallel flash together. To use serial
 843          * flash with one of the two others, the muxbits need to be flipped
 844          * around before any access.
 845          */
 846         {
 847                 .name = "nflashgrp",
 848                 .pins = nflash_3512_pins,
 849                 .num_pins = ARRAY_SIZE(nflash_3512_pins),
 850                 /* Conflict with IDE, parallel and serial flash */
 851                 .mask = NAND_PADS_DISABLE | IDE_PADS_ENABLE,
 852                 .value = PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
 853         },
 854         {
 855                 .name = "pflashgrp",
 856                 .pins = pflash_3512_pins,
 857                 .num_pins = ARRAY_SIZE(pflash_3512_pins),
 858                 /* Conflict with IDE, NAND and serial flash */
 859                 .mask = PFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
 860                 .value = NAND_PADS_DISABLE | SFLASH_PADS_DISABLE,
 861         },
 862         {
 863                 .name = "sflashgrp",
 864                 .pins = sflash_3512_pins,
 865                 .num_pins = ARRAY_SIZE(sflash_3512_pins),
 866                 /* Conflict with IDE, NAND and parallel flash */
 867                 .mask = SFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
 868                 .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
 869         },
 870         {
 871                 .name = "gpio0agrp",
 872                 .pins = gpio0a_3512_pins,
 873                 .num_pins = ARRAY_SIZE(gpio0a_3512_pins),
 874                 /* Conflict with TVC CLK */
 875                 .mask = TVC_CLK_PAD_ENABLE,
 876         },
 877         {
 878                 .name = "gpio0bgrp",
 879                 .pins = gpio0b_3512_pins,
 880                 .num_pins = ARRAY_SIZE(gpio0b_3512_pins),
 881                 /* Conflict with TVC and ICE */
 882                 .mask = TVC_PADS_ENABLE,
 883         },
 884         {
 885                 .name = "gpio0cgrp",
 886                 .pins = gpio0c_3512_pins,
 887                 .num_pins = ARRAY_SIZE(gpio0c_3512_pins),
 888                 /* Conflict with ICE */
 889         },
 890         {
 891                 .name = "gpio0dgrp",
 892                 .pins = gpio0d_3512_pins,
 893                 .num_pins = ARRAY_SIZE(gpio0d_3512_pins),
 894                 /* Conflict with UART RX/TX */
 895         },
 896         {
 897                 .name = "gpio0egrp",
 898                 .pins = gpio0e_3512_pins,
 899                 .num_pins = ARRAY_SIZE(gpio0e_3512_pins),
 900                 /* Conflict with LPC, UART modem pins, SSP */
 901                 .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
 902         },
 903         {
 904                 .name = "gpio0fgrp",
 905                 .pins = gpio0f_3512_pins,
 906                 .num_pins = ARRAY_SIZE(gpio0f_3512_pins),
 907                 /* Conflict with LCD */
 908                 .mask = LCD_PADS_ENABLE,
 909         },
 910         {
 911                 .name = "gpio0ggrp",
 912                 .pins = gpio0g_3512_pins,
 913                 .num_pins = ARRAY_SIZE(gpio0g_3512_pins),
 914                 /* Conflict with NAND flash */
 915                 .value = NAND_PADS_DISABLE,
 916         },
 917         {
 918                 .name = "gpio0hgrp",
 919                 .pins = gpio0h_3512_pins,
 920                 .num_pins = ARRAY_SIZE(gpio0h_3512_pins),
 921                 /* Conflict with parallel flash */
 922                 .value = PFLASH_PADS_DISABLE,
 923         },
 924         {
 925                 .name = "gpio0igrp",
 926                 .pins = gpio0i_3512_pins,
 927                 .num_pins = ARRAY_SIZE(gpio0i_3512_pins),
 928                 /* Conflict with serial flash */
 929                 .value = SFLASH_PADS_DISABLE,
 930         },
 931         {
 932                 .name = "gpio0jgrp",
 933                 .pins = gpio0j_3512_pins,
 934                 .num_pins = ARRAY_SIZE(gpio0j_3512_pins),
 935                 /* Conflict with all flash */
 936                 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
 937                         SFLASH_PADS_DISABLE,
 938         },
 939         {
 940                 .name = "gpio0kgrp",
 941                 .pins = gpio0k_3512_pins,
 942                 .num_pins = ARRAY_SIZE(gpio0k_3512_pins),
 943                 /* Conflict with all flash and LCD */
 944                 .mask = LCD_PADS_ENABLE,
 945                 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
 946                         SFLASH_PADS_DISABLE,
 947         },
 948         {
 949                 .name = "gpio0lgrp",
 950                 .pins = gpio0l_3512_pins,
 951                 .num_pins = ARRAY_SIZE(gpio0l_3512_pins),
 952                 /* Conflict with parallel flash */
 953                 .value = PFLASH_PADS_DISABLE,
 954         },
 955         {
 956                 .name = "gpio0mgrp",
 957                 .pins = gpio0m_3512_pins,
 958                 .num_pins = ARRAY_SIZE(gpio0m_3512_pins),
 959                 /* Conflict with parallel and NAND flash */
 960                 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE,
 961         },
 962         {
 963                 .name = "gpio1agrp",
 964                 .pins = gpio1a_3512_pins,
 965                 .num_pins = ARRAY_SIZE(gpio1a_3512_pins),
 966                 /* Conflict with IDE and parallel flash */
 967                 .mask = IDE_PADS_ENABLE,
 968                 .value = PFLASH_PADS_DISABLE,
 969         },
 970         {
 971                 .name = "gpio1bgrp",
 972                 .pins = gpio1b_3512_pins,
 973                 .num_pins = ARRAY_SIZE(gpio1b_3512_pins),
 974                 /* Conflict with IDE only */
 975                 .mask = IDE_PADS_ENABLE,
 976         },
 977         {
 978                 .name = "gpio1cgrp",
 979                 .pins = gpio1c_3512_pins,
 980                 .num_pins = ARRAY_SIZE(gpio1c_3512_pins),
 981                 /* Conflict with IDE, parallel and NAND flash */
 982                 .mask = IDE_PADS_ENABLE,
 983                 .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
 984         },
 985         {
 986                 .name = "gpio1dgrp",
 987                 .pins = gpio1d_3512_pins,
 988                 .num_pins = ARRAY_SIZE(gpio1d_3512_pins),
 989                 /* Conflict with LCD and TVC */
 990                 .mask = LCD_PADS_ENABLE | TVC_PADS_ENABLE,
 991         },
 992         {
 993                 .name = "gpio2agrp",
 994                 .pins = gpio2a_3512_pins,
 995                 .num_pins = ARRAY_SIZE(gpio2a_3512_pins),
 996                 .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
 997                 /* Conflict with GMII GMAC1 and extended parallel flash */
 998         },
 999         {
1000                 .name = "gpio2bgrp",
1001                 .pins = gpio2b_3512_pins,
1002                 .num_pins = ARRAY_SIZE(gpio2b_3512_pins),
1003                 /* Conflict with GMII GMAC1, extended parallel flash and LCD */
1004                 .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
1005         },
1006         {
1007                 .name = "gpio2cgrp",
1008                 .pins = gpio2c_3512_pins,
1009                 .num_pins = ARRAY_SIZE(gpio2c_3512_pins),
1010                 /* Conflict with PCI */
1011                 .mask = PCI_PADS_ENABLE,
1012         },
1013 };
1014
1015 /* Pin names for the pinmux subsystem, 3516 variant */
1016 static const struct pinctrl_pin_desc gemini_3516_pins[] = {
1017         /* Row A */
1018         PINCTRL_PIN(0, "A1 AVCC3IOHA"),
1019         PINCTRL_PIN(1, "A2 DRAM CK N"),
1020         PINCTRL_PIN(2, "A3 DRAM CK"),
1021         PINCTRL_PIN(3, "A4 DRAM DQM1"),
1022         PINCTRL_PIN(4, "A5 DRAM DQ9"),
1023         PINCTRL_PIN(5, "A6 DRAM DQ13"),
1024         PINCTRL_PIN(6, "A7 DRAM DQ1"),
1025         PINCTRL_PIN(7, "A8 DRAM DQ2"),
1026         PINCTRL_PIN(8, "A9 DRAM DQ4"),
1027         PINCTRL_PIN(9, "A10 DRAM VREF"),
1028         PINCTRL_PIN(10, "A11 DRAM DQ24"),
1029         PINCTRL_PIN(11, "A12 DRAM DQ28"),
1030         PINCTRL_PIN(12, "A13 DRAM DQ30"),
1031         PINCTRL_PIN(13, "A14 DRAM DQ18"),
1032         PINCTRL_PIN(14, "A15 DRAM DQ21"),
1033         PINCTRL_PIN(15, "A16 DRAM CAS_N"),
1034         PINCTRL_PIN(16, "A17 DRAM BA1"),
1035         PINCTRL_PIN(17, "A18 PCI INTA N"),
1036         PINCTRL_PIN(18, "A19 PCI INTB N"),
1037         PINCTRL_PIN(19, "A20 PCI INTC N"),
1038         /* Row B */
1039         PINCTRL_PIN(20, "B1 PWR EN"),
1040         PINCTRL_PIN(21, "B2 GND"),
1041         PINCTRL_PIN(22, "B3 RTC CLKO"),
1042         PINCTRL_PIN(23, "B4 DRAM A5"),
1043         PINCTRL_PIN(24, "B5 DRAM A6"),
1044         PINCTRL_PIN(25, "B6 DRAM DQS1"),
1045         PINCTRL_PIN(26, "B7 DRAM DQ11"),
1046         PINCTRL_PIN(27, "B8 DRAM DQ0"),
1047         PINCTRL_PIN(28, "B9 DRAM DQS0"),
1048         PINCTRL_PIN(29, "B10 DRAM DQ7"),
1049         PINCTRL_PIN(30, "B11 DRAM DQS3"),
1050         PINCTRL_PIN(31, "B12 DRAM DQ27"),
1051         PINCTRL_PIN(32, "B13 DRAM DQ31"),
1052         PINCTRL_PIN(33, "B14 DRAM DQ20"),
1053         PINCTRL_PIN(34, "B15 DRAM DQS2"),
1054         PINCTRL_PIN(35, "B16 DRAM WE N"),
1055         PINCTRL_PIN(36, "B17 DRAM A10"),
1056         PINCTRL_PIN(37, "B18 DRAM A2"),
1057         PINCTRL_PIN(38, "B19 GND"),
1058         PINCTRL_PIN(39, "B20 PCI GNT0 N"),
1059         /* Row C */
1060         PINCTRL_PIN(40, "C1 AGNDIOHA"),
1061         PINCTRL_PIN(41, "C2 XTALI"),
1062         PINCTRL_PIN(42, "C3 GND"),
1063         PINCTRL_PIN(43, "C4 RTC CLKI"),
1064         PINCTRL_PIN(44, "C5 DRAM A12"),
1065         PINCTRL_PIN(45, "C6 DRAM A11"),
1066         PINCTRL_PIN(46, "C7 DRAM DQ8"),
1067         PINCTRL_PIN(47, "C8 DRAM DQ10"),
1068         PINCTRL_PIN(48, "C9 DRAM DQ3"),
1069         PINCTRL_PIN(49, "C10 DRAM DQ6"),
1070         PINCTRL_PIN(50, "C11 DRAM DQM0"),
1071         PINCTRL_PIN(51, "C12 DRAM DQ26"),
1072         PINCTRL_PIN(52, "C13 DRAM DQ16"),
1073         PINCTRL_PIN(53, "C14 DRAM DQ22"),
1074         PINCTRL_PIN(54, "C15 DRAM DQM2"),
1075         PINCTRL_PIN(55, "C16 DRAM BA0"),
1076         PINCTRL_PIN(56, "C17 DRAM A3"),
1077         PINCTRL_PIN(57, "C18 GND"),
1078         PINCTRL_PIN(58, "C19 PCI GNT1 N"),
1079         PINCTRL_PIN(59, "C20 PCI REQ2 N"),
1080         /* Row D */
1081         PINCTRL_PIN(60, "D1 AVCC3IOAHA"),
1082         PINCTRL_PIN(61, "D2 AVCCKHA"),
1083         PINCTRL_PIN(62, "D3 XTALO"),
1084         PINCTRL_PIN(63, "D4 GND"),
1085         PINCTRL_PIN(64, "D5 CIR RXD"),
1086         PINCTRL_PIN(65, "D6 DRAM A7"),
1087         PINCTRL_PIN(66, "D7 DRAM A4"),
1088         PINCTRL_PIN(67, "D8 DRAM A8"),
1089         PINCTRL_PIN(68, "D9 DRAM CKE"),
1090         PINCTRL_PIN(69, "D10 DRAM DQ14"),
1091         PINCTRL_PIN(70, "D11 DRAM DQ5"),
1092         PINCTRL_PIN(71, "D12 DRAM DQ25"),
1093         PINCTRL_PIN(72, "D13 DRAM DQ17"),
1094         PINCTRL_PIN(73, "D14 DRAM DQ23"),
1095         PINCTRL_PIN(74, "D15 DRAM RAS N"),
1096         PINCTRL_PIN(75, "D16 DRAM A1"),
1097         PINCTRL_PIN(76, "D17 GND"),
1098         PINCTRL_PIN(77, "D18 EXT RESET N"),
1099         PINCTRL_PIN(78, "D19 PCI REQ1 N"),
1100         PINCTRL_PIN(79, "D20 PCI REQ3 N"),
1101         /* Row E */
1102         PINCTRL_PIN(80, "E1 VCC2IO CTRL"),
1103         PINCTRL_PIN(81, "E2 VREF CTRL"),
1104         PINCTRL_PIN(82, "E3 CIR RST N"),
1105         PINCTRL_PIN(83, "E4 PWR BTN"),
1106         PINCTRL_PIN(84, "E5 GND"),
1107         PINCTRL_PIN(85, "E6 CIR TXD"),
1108         PINCTRL_PIN(86, "E7 VCCK CTRL"),
1109         PINCTRL_PIN(87, "E8 DRAM A9"),
1110         PINCTRL_PIN(88, "E9 DRAM DQ12"),
1111         PINCTRL_PIN(89, "E10 DRAM DQ15"),
1112         PINCTRL_PIN(90, "E11 DRAM DQM3"),
1113         PINCTRL_PIN(91, "E12 DRAM DQ29"),
1114         PINCTRL_PIN(92, "E13 DRAM DQ19"),
1115         PINCTRL_PIN(93, "E14 DRAM A13"),
1116         PINCTRL_PIN(94, "E15 DRAM A0"),
1117         PINCTRL_PIN(95, "E16 GND"),
1118         PINCTRL_PIN(96, "E17 PCI INTD N"),
1119         PINCTRL_PIN(97, "E18 PCI GNT3 N"),
1120         PINCTRL_PIN(98, "E19 PCI AD29"),
1121         PINCTRL_PIN(99, "E20 PCI AD28"),
1122         /* Row F */
1123         PINCTRL_PIN(100, "F1 AVCCKHB"),
1124         PINCTRL_PIN(101, "F2 AVCCK P"),
1125         PINCTRL_PIN(102, "F3 EBG"),
1126         PINCTRL_PIN(103, "F4 REXT"),
1127         PINCTRL_PIN(104, "F5 AVCC3IOHB"),
1128         PINCTRL_PIN(105, "F6 GND"),
1129         PINCTRL_PIN(106, "F7 VCC2IOHA 2"),
1130         PINCTRL_PIN(107, "F8 VCC2IOHA 2"),
1131         PINCTRL_PIN(108, "F9 VCC2IOHA 2"),
1132         PINCTRL_PIN(109, "F10 V1"),
1133         PINCTRL_PIN(110, "F11 V1"),
1134         PINCTRL_PIN(111, "F12 VCC2IOHA 2"),
1135         PINCTRL_PIN(112, "F13 VCC2IOHA 2"),
1136         PINCTRL_PIN(113, "F14 VCC2IOHA 2"),
1137         PINCTRL_PIN(114, "F15 GND"),
1138         PINCTRL_PIN(115, "F16 PCI CLK"),
1139         PINCTRL_PIN(116, "F17 PCI GNT2 N"),
1140         PINCTRL_PIN(117, "F18 PCI AD31"),
1141         PINCTRL_PIN(118, "F19 PCI AD26"),
1142         PINCTRL_PIN(119, "F20 PCI CBE3 N"),
1143         /* Row G */
1144         PINCTRL_PIN(120, "G1 SATA0 RXDP"),
1145         PINCTRL_PIN(121, "G2 SATA0 RXDN"),
1146         PINCTRL_PIN(122, "G3 AGNDK 0"),
1147         PINCTRL_PIN(123, "G4 AVCCK S"),
1148         PINCTRL_PIN(124, "G5 AVCC3 S"),
1149         PINCTRL_PIN(125, "G6 VCC2IOHA 2"),
1150         PINCTRL_PIN(126, "G7 GND"),
1151         PINCTRL_PIN(127, "G8 VCC2IOHA 2"),
1152         PINCTRL_PIN(128, "G9 V1"),
1153         PINCTRL_PIN(129, "G10 V1"),
1154         PINCTRL_PIN(130, "G11 V1"),
1155         PINCTRL_PIN(131, "G12 V1"),
1156         PINCTRL_PIN(132, "G13 VCC2IOHA 2"),
1157         PINCTRL_PIN(133, "G14 GND"),
1158         PINCTRL_PIN(134, "G15 VCC3IOHA"),
1159         PINCTRL_PIN(135, "G16 PCI REQ0 N"),
1160         PINCTRL_PIN(136, "G17 PCI AD30"),
1161         PINCTRL_PIN(137, "G18 PCI AD24"),
1162         PINCTRL_PIN(138, "G19 PCI AD23"),
1163         PINCTRL_PIN(139, "G20 PCI AD21"),
1164         /* Row H */
1165         PINCTRL_PIN(140, "H1 SATA0 TXDP"),
1166         PINCTRL_PIN(141, "H2 SATA0 TXDN"),
1167         PINCTRL_PIN(142, "H3 AGNDK 1"),
1168         PINCTRL_PIN(143, "H4 AVCCK 0"),
1169         PINCTRL_PIN(144, "H5 TEST CLKOUT"),
1170         PINCTRL_PIN(145, "H6 AGND"),
1171         PINCTRL_PIN(146, "H7 VCC2IOHA 2"),
1172         PINCTRL_PIN(147, "H8 GND"),
1173         PINCTRL_PIN(148, "H9 GND"),
1174         PINCTRL_PIN(149, "H10 GDN"),
1175         PINCTRL_PIN(150, "H11 GND"),
1176         PINCTRL_PIN(151, "H12 GND"),
1177         PINCTRL_PIN(152, "H13 GND"),
1178         PINCTRL_PIN(153, "H14 VCC3IOHA"),
1179         PINCTRL_PIN(154, "H15 VCC3IOHA"),
1180         PINCTRL_PIN(155, "H16 PCI AD27"),
1181         PINCTRL_PIN(156, "H17 PCI AD25"),
1182         PINCTRL_PIN(157, "H18 PCI AD22"),
1183         PINCTRL_PIN(158, "H19 PCI AD18"),
1184         PINCTRL_PIN(159, "H20 PCI AD17"),
1185         /* Row J (for some reason I is skipped) */
1186         PINCTRL_PIN(160, "J1 SATA1 TXDP"),
1187         PINCTRL_PIN(161, "J2 SATA1 TXDN"),
1188         PINCTRL_PIN(162, "J3 AGNDK 2"),
1189         PINCTRL_PIN(163, "J4 AVCCK 1"),
1190         PINCTRL_PIN(164, "J5 AGND"),
1191         PINCTRL_PIN(165, "J6 AGND"),
1192         PINCTRL_PIN(166, "J7 V1"),
1193         PINCTRL_PIN(167, "J8 GND"),
1194         PINCTRL_PIN(168, "J9 GND"),
1195         PINCTRL_PIN(169, "J10 GND"),
1196         PINCTRL_PIN(170, "J11 GND"),
1197         PINCTRL_PIN(171, "J12 GND"),
1198         PINCTRL_PIN(172, "J13 GND"),
1199         PINCTRL_PIN(173, "J14 V1"),
1200         PINCTRL_PIN(174, "J15 VCC3IOHA"),
1201         PINCTRL_PIN(175, "J16 PCI AD19"),
1202         PINCTRL_PIN(176, "J17 PCI AD20"),
1203         PINCTRL_PIN(177, "J18 PCI AD16"),
1204         PINCTRL_PIN(178, "J19 PCI CBE2 N"),
1205         PINCTRL_PIN(179, "J20 PCI FRAME N"),
1206         /* Row K */
1207         PINCTRL_PIN(180, "K1 SATA1 RXDP"),
1208         PINCTRL_PIN(181, "K2 SATA1 RXDN"),
1209         PINCTRL_PIN(182, "K3 AGNDK 3"),
1210         PINCTRL_PIN(183, "K4 AVCCK 2"),
1211         PINCTRL_PIN(184, "K5 AGND"),
1212         PINCTRL_PIN(185, "K6 V1"),
1213         PINCTRL_PIN(186, "K7 V1"),
1214         PINCTRL_PIN(187, "K8 GND"),
1215         PINCTRL_PIN(188, "K9 GND"),
1216         PINCTRL_PIN(189, "K10 GND"),
1217         PINCTRL_PIN(190, "K11 GND"),
1218         PINCTRL_PIN(191, "K12 GND"),
1219         PINCTRL_PIN(192, "K13 GND"),
1220         PINCTRL_PIN(193, "K14 V1"),
1221         PINCTRL_PIN(194, "K15 V1"),
1222         PINCTRL_PIN(195, "K16 PCI TRDY N"),
1223         PINCTRL_PIN(196, "K17 PCI IRDY N"),
1224         PINCTRL_PIN(197, "K18 PCI DEVSEL N"),
1225         PINCTRL_PIN(198, "K19 PCI STOP N"),
1226         PINCTRL_PIN(199, "K20 PCI PAR"),
1227         /* Row L */
1228         PINCTRL_PIN(200, "L1 IDE CS0 N"),
1229         PINCTRL_PIN(201, "L2 IDE DA0"),
1230         PINCTRL_PIN(202, "L3 AVCCK 3"),
1231         PINCTRL_PIN(203, "L4 AGND"),
1232         PINCTRL_PIN(204, "L5 IDE DIOR N"),
1233         PINCTRL_PIN(205, "L6 V1"),
1234         PINCTRL_PIN(206, "L7 V1"),
1235         PINCTRL_PIN(207, "L8 GND"),
1236         PINCTRL_PIN(208, "L9 GND"),
1237         PINCTRL_PIN(209, "L10 GND"),
1238         PINCTRL_PIN(210, "L11 GND"),
1239         PINCTRL_PIN(211, "L12 GND"),
1240         PINCTRL_PIN(212, "L13 GND"),
1241         PINCTRL_PIN(213, "L14 V1"),
1242         PINCTRL_PIN(214, "L15 V1"),
1243         PINCTRL_PIN(215, "L16 PCI AD12"),
1244         PINCTRL_PIN(216, "L17 PCI AD13"),
1245         PINCTRL_PIN(217, "L18 PCI AD14"),
1246         PINCTRL_PIN(218, "L19 PCI AD15"),
1247         PINCTRL_PIN(219, "L20 PCI CBE1 N"),
1248         /* Row M */
1249         PINCTRL_PIN(220, "M1 IDE DA1"),
1250         PINCTRL_PIN(221, "M2 IDE CS1 N"),
1251         PINCTRL_PIN(222, "M3 IDE DA2"),
1252         PINCTRL_PIN(223, "M4 IDE DMACK N"),
1253         PINCTRL_PIN(224, "M5 IDE DD1"),
1254         PINCTRL_PIN(225, "M6 VCC3IOHA"),
1255         PINCTRL_PIN(226, "M7 V1"),
1256         PINCTRL_PIN(227, "M8 GND"),
1257         PINCTRL_PIN(228, "M9 GND"),
1258         PINCTRL_PIN(229, "M10 GND"),
1259         PINCTRL_PIN(230, "M11 GND"),
1260         PINCTRL_PIN(231, "M12 GND"),
1261         PINCTRL_PIN(232, "M13 GND"),
1262         PINCTRL_PIN(233, "M14 V1"),
1263         PINCTRL_PIN(234, "M15 VCC3IOHA"),
1264         PINCTRL_PIN(235, "M16 PCI AD7"),
1265         PINCTRL_PIN(236, "M17 PCI AD6"),
1266         PINCTRL_PIN(237, "M18 PCI AD9"),
1267         PINCTRL_PIN(238, "M19 PCI AD10"),
1268         PINCTRL_PIN(239, "M20 PCI AD11"),
1269         /* Row N */
1270         PINCTRL_PIN(240, "N1 IDE IORDY"),
1271         PINCTRL_PIN(241, "N2 IDE INTRQ"),
1272         PINCTRL_PIN(242, "N3 IDE DIOW N"),
1273         PINCTRL_PIN(243, "N4 IDE DD15"),
1274         PINCTRL_PIN(244, "N5 IDE DMARQ"),
1275         PINCTRL_PIN(245, "N6 VCC3IOHA"),
1276         PINCTRL_PIN(246, "N7 VCC3IOHA"),
1277         PINCTRL_PIN(247, "N8 GND"),
1278         PINCTRL_PIN(248, "N9 GND"),
1279         PINCTRL_PIN(249, "N10 GND"),
1280         PINCTRL_PIN(250, "N11 GND"),
1281         PINCTRL_PIN(251, "N12 GND"),
1282         PINCTRL_PIN(252, "N13 GND"),
1283         PINCTRL_PIN(253, "N14 VCC3IOHA"),
1284         PINCTRL_PIN(254, "N15 VCC3IOHA"),
1285         PINCTRL_PIN(255, "N16 PCI CLKRUN N"),
1286         PINCTRL_PIN(256, "N17 PCI AD0"),
1287         PINCTRL_PIN(257, "N18 PCI AD4"),
1288         PINCTRL_PIN(258, "N19 PCI CBE0 N"),
1289         PINCTRL_PIN(259, "N20 PCI AD8"),
1290         /* Row P (for some reason O is skipped) */
1291         PINCTRL_PIN(260, "P1 IDE DD0"),
1292         PINCTRL_PIN(261, "P2 IDE DD14"),
1293         PINCTRL_PIN(262, "P3 IDE DD2"),
1294         PINCTRL_PIN(263, "P4 IDE DD4"),
1295         PINCTRL_PIN(264, "P5 IDE DD3"),
1296         PINCTRL_PIN(265, "P6 VCC3IOHA"),
1297         PINCTRL_PIN(266, "P7 GND"),
1298         PINCTRL_PIN(267, "P8 VCC2IOHA 1"),
1299         PINCTRL_PIN(268, "P9 V1"),
1300         PINCTRL_PIN(269, "P10 V1"),
1301         PINCTRL_PIN(270, "P11 V1"),
1302         PINCTRL_PIN(271, "P12 V1"),
1303         PINCTRL_PIN(272, "P13 VCC3IOHA"),
1304         PINCTRL_PIN(273, "P14 GND"),
1305         PINCTRL_PIN(274, "P15 VCC3IOHA"),
1306         PINCTRL_PIN(275, "P16 GPIO0 30"),
1307         PINCTRL_PIN(276, "P17 GPIO0 28"),
1308         PINCTRL_PIN(277, "P18 PCI AD1"),
1309         PINCTRL_PIN(278, "P19 PCI AD3"),
1310         PINCTRL_PIN(279, "P20 PCI AD5"),
1311         /* Row R (for some reason Q is skipped) */
1312         PINCTRL_PIN(280, "R1 IDE DD13"),
1313         PINCTRL_PIN(281, "R2 IDE DD12"),
1314         PINCTRL_PIN(282, "R3 IDE DD10"),
1315         PINCTRL_PIN(283, "R4 IDE DD6"),
1316         PINCTRL_PIN(284, "R5 ICE0 IDI"),
1317         PINCTRL_PIN(285, "R6 GND"),
1318         PINCTRL_PIN(286, "R7 VCC2IOHA 1"),
1319         PINCTRL_PIN(287, "R8 VCC2IOHA 1"),
1320         PINCTRL_PIN(288, "R9 VCC2IOHA 1"),
1321         PINCTRL_PIN(289, "R10 V1"),
1322         PINCTRL_PIN(290, "R11 V1"),
1323         PINCTRL_PIN(291, "R12 VCC3IOHA"),
1324         PINCTRL_PIN(292, "R13 VCC3IOHA"),
1325         PINCTRL_PIN(293, "R14 VCC3IOHA"),
1326         PINCTRL_PIN(294, "R15 GND"),
1327         PINCTRL_PIN(295, "R16 GPIO0 23"),
1328         PINCTRL_PIN(296, "R17 GPIO0 21"),
1329         PINCTRL_PIN(297, "R18 GPIO0 26"),
1330         PINCTRL_PIN(298, "R19 GPIO0 31"),
1331         PINCTRL_PIN(299, "R20 PCI AD2"),
1332         /* Row T (for some reason S is skipped) */
1333         PINCTRL_PIN(300, "T1 IDE DD11"),
1334         PINCTRL_PIN(301, "T2 IDE DD5"),
1335         PINCTRL_PIN(302, "T3 IDE DD8"),
1336         PINCTRL_PIN(303, "T4 ICE0 IDO"),
1337         PINCTRL_PIN(304, "T5 GND"),
1338         PINCTRL_PIN(305, "T6 USB GNDA U20"),
1339         PINCTRL_PIN(306, "T7 GMAC0 TXD0"),
1340         PINCTRL_PIN(307, "T8 GMAC0 TXEN"),
1341         PINCTRL_PIN(308, "T9 GMAC1 TXD3"),
1342         PINCTRL_PIN(309, "T10 GMAC1 RXDV"),
1343         PINCTRL_PIN(310, "T11 GMAC1 RXD2"),
1344         PINCTRL_PIN(311, "T12 GPIO1 29"),
1345         PINCTRL_PIN(312, "T13 GPIO0 3"),
1346         PINCTRL_PIN(313, "T14 GPIO0 9"),
1347         PINCTRL_PIN(314, "T15 GPIO0 16"),
1348         PINCTRL_PIN(315, "T16 GND"),
1349         PINCTRL_PIN(316, "T17 GPIO0 14"),
1350         PINCTRL_PIN(317, "T18 GPIO0 19"),
1351         PINCTRL_PIN(318, "T19 GPIO0 27"),
1352         PINCTRL_PIN(319, "T20 GPIO0 29"),
1353         /* Row U */
1354         PINCTRL_PIN(320, "U1 IDE DD9"),
1355         PINCTRL_PIN(321, "U2 IDE DD7"),
1356         PINCTRL_PIN(322, "U3 ICE0 ICK"),
1357         PINCTRL_PIN(323, "U4 GND"),
1358         PINCTRL_PIN(324, "U5 USB XSCO"),
1359         PINCTRL_PIN(325, "U6 GMAC0 TXD1"),
1360         PINCTRL_PIN(326, "U7 GMAC0 TXD3"),
1361         PINCTRL_PIN(327, "U8 GMAC0 TXC"),
1362         PINCTRL_PIN(328, "U9 GMAC0 RXD3"),
1363         PINCTRL_PIN(329, "U10 GMAC1 TXD0"),
1364         PINCTRL_PIN(330, "U11 GMAC1 CRS"),
1365         PINCTRL_PIN(331, "U12 EXT CLK"),
1366         PINCTRL_PIN(332, "U13 DEV DEF"),
1367         PINCTRL_PIN(333, "U14 GPIO0 0"),
1368         PINCTRL_PIN(334, "U15 GPIO0 4"),
1369         PINCTRL_PIN(335, "U16 GPIO0 10"),
1370         PINCTRL_PIN(336, "U17 GND"),
1371         PINCTRL_PIN(337, "U18 GPIO0 17"),
1372         PINCTRL_PIN(338, "U19 GPIO0 22"),
1373         PINCTRL_PIN(339, "U20 GPIO0 25"),
1374         /* Row V */
1375         PINCTRL_PIN(340, "V1 ICE0 DBGACK"),
1376         PINCTRL_PIN(341, "V2 ICE0 DBGRQ"),
1377         PINCTRL_PIN(342, "V3 GND"),
1378         PINCTRL_PIN(343, "V4 ICE0 IRST N"),
1379         PINCTRL_PIN(344, "V5 USB XSCI"),
1380         PINCTRL_PIN(345, "V6 GMAC0 COL"),
1381         PINCTRL_PIN(346, "V7 GMAC0 TXD2"),
1382         PINCTRL_PIN(347, "V8 GMAC0 RXDV"),
1383         PINCTRL_PIN(348, "V9 GMAC0 RXD1"),
1384         PINCTRL_PIN(349, "V10 GMAC1 COL"),
1385         PINCTRL_PIN(350, "V11 GMAC1 TXC"),
1386         PINCTRL_PIN(351, "V12 GMAC1 RXD1"),
1387         PINCTRL_PIN(352, "V13 MODE SEL1"),
1388         PINCTRL_PIN(353, "V14 GPIO1 28"),
1389         PINCTRL_PIN(354, "V15 GPIO0 1"),
1390         PINCTRL_PIN(355, "V16 GPIO0 8"),
1391         PINCTRL_PIN(356, "V17 GPIO0 11"),
1392         PINCTRL_PIN(357, "V18 GND"),
1393         PINCTRL_PIN(358, "V19 GPIO0 18"),
1394         PINCTRL_PIN(359, "V20 GPIO0 24"),
1395         /* Row W */
1396         PINCTRL_PIN(360, "W1 IDE RESET N"),
1397         PINCTRL_PIN(361, "W2 GND"),
1398         PINCTRL_PIN(362, "W3 USB0 VCCHSRT"),
1399         PINCTRL_PIN(363, "W4 USB0 DP"),
1400         PINCTRL_PIN(364, "W5 USB VCCA U20"),
1401         PINCTRL_PIN(365, "W6 USB1 DP"),
1402         PINCTRL_PIN(366, "W7 USB1 GNDHSRT"),
1403         PINCTRL_PIN(367, "W8 GMAC0 RXD0"),
1404         PINCTRL_PIN(368, "W9 GMAC0 CRS"),
1405         PINCTRL_PIN(369, "W10 GMAC1 TXD2"),
1406         PINCTRL_PIN(370, "W11 GMAC1 TXEN"),
1407         PINCTRL_PIN(371, "W12 GMAC1 RXD3"),
1408         PINCTRL_PIN(372, "W13 MODE SEL0"),
1409         PINCTRL_PIN(373, "W14 MODE SEL3"),
1410         PINCTRL_PIN(374, "W15 GPIO1 31"),
1411         PINCTRL_PIN(375, "W16 GPIO0 5"),
1412         PINCTRL_PIN(376, "W17 GPIO0 7"),
1413         PINCTRL_PIN(377, "W18 GPIO0 12"),
1414         PINCTRL_PIN(378, "W19 GND"),
1415         PINCTRL_PIN(379, "W20 GPIO0 20"),
1416         /* Row Y */
1417         PINCTRL_PIN(380, "Y1 ICE0 IMS"),
1418         PINCTRL_PIN(381, "Y2 USB0 GNDHSRT"),
1419         PINCTRL_PIN(382, "Y3 USB0 DM"),
1420         PINCTRL_PIN(383, "Y4 USB RREF"),
1421         PINCTRL_PIN(384, "Y5 USB1 DM"),
1422         PINCTRL_PIN(385, "Y6 USB1 VCCHSRT"),
1423         PINCTRL_PIN(386, "Y7 GMAC0 RXC"),
1424         PINCTRL_PIN(387, "Y8 GMAC0 RXD2"),
1425         PINCTRL_PIN(388, "Y9 REF CLK"),
1426         PINCTRL_PIN(389, "Y10 GMAC1 TXD1"),
1427         PINCTRL_PIN(390, "Y11 GMAC1 RXC"),
1428         PINCTRL_PIN(391, "Y12 GMAC1 RXD0"),
1429         PINCTRL_PIN(392, "Y13 M30 CLK"),
1430         PINCTRL_PIN(393, "Y14 MODE SEL2"),
1431         PINCTRL_PIN(394, "Y15 GPIO1 30"),
1432         PINCTRL_PIN(395, "Y16 GPIO0 2"),
1433         PINCTRL_PIN(396, "Y17 GPIO0 6"),
1434         PINCTRL_PIN(397, "Y18 SYS RESET N"),
1435         PINCTRL_PIN(398, "Y19 GPIO0 13"),
1436         PINCTRL_PIN(399, "Y20 GPIO0 15"),
1437 };
1438
1439 /* Digital ground */
1440 static const unsigned int gnd_3516_pins[] = {
1441         21, 38, 42, 57, 63, 76, 84, 95, 105, 114, 126, 133, 147, 148, 149, 150,
1442         151, 152, 167, 168, 169, 170, 171, 172, 187, 188, 189, 190, 191, 192,
1443         207, 208, 209, 210, 211, 212, 227, 228, 229, 230, 231, 232, 247, 248,
1444         249, 250, 251, 252, 266, 273, 285, 294, 304, 315, 323, 336, 342, 357,
1445         361, 378
1446 };
1447
1448 static const unsigned int dram_3516_pins[] = {
1449         1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 23, 24, 25, 26,
1450         27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 44, 45, 46, 47, 48, 49, 50,
1451         51, 52, 53, 54, 55, 56, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
1452         87, 88, 89, 90, 91, 92, 93, 94
1453 };
1454
1455 static const unsigned int rtc_3516_pins[] = { 0, 43, 22 };
1456
1457 static const unsigned int power_3516_pins[] = { 20, 83, 40, 41, 60, 61, 62 };
1458
1459 static const unsigned int cir_3516_pins[] = { 85, 64, 82 };
1460
1461 static const unsigned int system_3516_pins[] = {
1462         332, 392, 372, 373, 393, 352, 331, 388, 397, 77
1463 };
1464
1465 static const unsigned int vcontrol_3516_pins[] = { 86, 81, 80 };
1466
1467 static const unsigned int ice_3516_pins[] = { 340, 341, 303, 322, 380, 284, 343 };
1468
1469 static const unsigned int ide_3516_pins[] = {
1470         200, 201, 204, 220, 221, 222, 223, 224, 240, 241, 242, 243, 244, 260,
1471         261, 262, 263, 264, 280, 281, 282, 283, 300, 301, 302, 320, 321, 360
1472 };
1473
1474 static const unsigned int sata_3516_pins[] = {
1475         100, 101, 102, 103, 104, 120, 121, 122, 123, 124, 140, 141, 142, 143,
1476         144, 160, 161, 162, 163, 180, 181, 182, 183, 202
1477 };
1478
1479 static const unsigned int usb_3516_pins[] = {
1480         305, 324, 344, 362, 363, 364, 365, 366, 381, 382, 383, 384, 385
1481 };
1482
1483 /* GMII, ethernet pins */
1484 static const unsigned int gmii_gmac0_3516_pins[] = {
1485         306, 307, 325, 326, 327, 328, 345, 346, 347, 348, 367, 368, 386, 387
1486 };
1487
1488 static const unsigned int gmii_gmac1_3516_pins[] = {
1489         308, 309, 310, 329, 330, 349, 350, 351, 369, 370, 371, 389, 390, 391
1490 };
1491
1492 static const unsigned int pci_3516_pins[] = {
1493         17, 18, 19, 39, 58, 59, 78, 79, 96, 97, 98, 99, 115, 116, 117, 118,
1494         119, 135, 136, 137, 138, 139, 155, 156, 157, 158, 159, 175, 176, 177,
1495         178, 179, 195, 196, 197, 198, 199, 215, 216, 217, 218, 219, 235, 236,
1496         237, 238, 239, 255, 256, 257, 258, 259, 277, 278, 279, 299
1497 };
1498
1499 /*
1500  * Apparently the LPC interface is using the PCICLK for the clocking so
1501  * PCI needs to be active at the same time.
1502  */
1503 static const unsigned int lpc_3516_pins[] = {
1504         355, /* LPC_LAD[0] */
1505         356, /* LPC_SERIRQ */
1506         377, /* LPC_LAD[2] */
1507         398, /* LPC_LFRAME# */
1508         316, /* LPC_LAD[3] */
1509         399, /* LPC_LAD[1] */
1510 };
1511
1512 /* Character LCD */
1513 static const unsigned int lcd_3516_pins[] = {
1514         391, 351, 310, 371, 353, 311, 394, 374, 314, 359, 339
1515 };
1516
1517 static const unsigned int ssp_3516_pins[] = {
1518         355, /* SSP_97RST# SSP AC97 Reset, active low */
1519         356, /* SSP_FSC */
1520         377, /* SSP_ECLK */
1521         398, /* SSP_TXD */
1522         316, /* SSP_RXD */
1523         399, /* SSP_SCLK */
1524 };
1525
1526 static const unsigned int uart_rxtx_3516_pins[] = {
1527         313, /* UART_SIN serial input, RX */
1528         335, /* UART_SOUT serial output, TX */
1529 };
1530
1531 static const unsigned int uart_modem_3516_pins[] = {
1532         355, /* UART_NDCD DCD carrier detect */
1533         356, /* UART_NDTR DTR data terminal ready */
1534         377, /* UART_NDSR DSR data set ready */
1535         398, /* UART_NRTS RTS request to send */
1536         316, /* UART_NCTS CTS clear to send */
1537         399, /* UART_NRI RI ring indicator */
1538 };
1539
1540 static const unsigned int tvc_3516_pins[] = {
1541         353, /* TVC_DATA[0] */
1542         311, /* TVC_DATA[1] */
1543         394, /* TVC_DATA[2] */
1544         374, /* TVC_DATA[3] */
1545         354, /* TVC_DATA[4] */
1546         395, /* TVC_DATA[5] */
1547         312, /* TVC_DATA[6] */
1548         334, /* TVC_DATA[7] */
1549 };
1550
1551 static const unsigned int tvc_clk_3516_pins[] = {
1552         333, /* TVC_CLK */
1553 };
1554
1555 /* NAND flash pins */
1556 static const unsigned int nflash_3516_pins[] = {
1557         243, 260, 261, 224, 280, 262, 281, 264, 300, 263, 282, 301, 320, 283,
1558         302, 321, 337, 358, 295, 359, 339, 275, 298
1559 };
1560
1561 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
1562 static const unsigned int pflash_3516_pins[] = {
1563         221, 200, 222, 201, 220, 243, 260, 261, 224, 280, 262, 281, 264, 300,
1564         263, 282, 301, 320, 283, 302, 321, 317, 379, 295, 359, 339, 297, 318,
1565         276, 319, 275, 298
1566 };
1567
1568 /*
1569  * The parallel flash can be set up in a 26-bit address bus mode exposing
1570  * A[0-15] (A[15] takes the place of ALE), but it has the
1571  * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be
1572  * used at the same time.
1573  */
1574 static const unsigned int pflash_3516_pins_extended[] = {
1575         221, 200, 222, 201, 220, 243, 260, 261, 224, 280, 262, 281, 264, 300,
1576         263, 282, 301, 320, 283, 302, 321, 317, 379, 295, 359, 339, 297, 318,
1577         276, 319, 275, 298,
1578         /* The extra pins */
1579         349, 308, 369, 389, 329, 350, 370, 309, 390, 391, 351, 310, 371, 330,
1580         333
1581 };
1582
1583 /* Serial flash pins CE0, CE1, DI, DO, CK */
1584 static const unsigned int sflash_3516_pins[] = { 296, 338, 295, 359, 339 };
1585
1586 /* The GPIO0A (0-4) pins overlap with TVC and extended parallel flash */
1587 static const unsigned int gpio0a_3516_pins[] = { 354, 395, 312, 334 };
1588
1589 /* The GPIO0B (5-7) pins overlap with ICE */
1590 static const unsigned int gpio0b_3516_pins[] = { 375, 396, 376 };
1591
1592 /* The GPIO0C (8,11-15) pins overlap with LPC, UART and SSP */
1593 static const unsigned int gpio0c_3516_pins[] = { 355, 356, 377, 398, 316, 399 };
1594
1595 /* The GPIO0D (9,10) pins overlap with UART RX/TX */
1596 static const unsigned int gpio0d_3516_pins[] = { 313, 335 };
1597
1598 /* The GPIO0E (16) pins overlap with LCD */
1599 static const unsigned int gpio0e_3516_pins[] = { 314 };
1600
1601 /* The GPIO0F (17,18) pins overlap with NAND flash CE0, CE1 */
1602 static const unsigned int gpio0f_3516_pins[] = { 337, 358 };
1603
1604 /* The GPIO0G (19,20,26-29) pins overlap with parallel flash */
1605 static const unsigned int gpio0g_3516_pins[] = { 317, 379, 297, 318, 276, 319 };
1606
1607 /* The GPIO0H (21,22) pins overlap with serial flash CE0, CE1 */
1608 static const unsigned int gpio0h_3516_pins[] = { 296, 338 };
1609
1610 /* The GPIO0I (23) pins overlap with all flash */
1611 static const unsigned int gpio0i_3516_pins[] = { 295 };
1612
1613 /* The GPIO0J (24,25) pins overlap with all flash and LCD */
1614 static const unsigned int gpio0j_3516_pins[] = { 359, 339 };
1615
1616 /* The GPIO0K (30,31) pins overlap with NAND flash */
1617 static const unsigned int gpio0k_3516_pins[] = { 275, 298 };
1618
1619 /* The GPIO0L (0) pins overlap with TVC_CLK */
1620 static const unsigned int gpio0l_3516_pins[] = { 333 };
1621
1622 /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
1623 static const unsigned int gpio1a_3516_pins[] = { 221, 200, 222, 201, 220 };
1624
1625 /* The GPIO1B (5-10,27) pins overlap with just IDE */
1626 static const unsigned int gpio1b_3516_pins[] = { 241, 223, 240, 204, 242, 244, 360 };
1627
1628 /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */
1629 static const unsigned int gpio1c_3516_pins[] = {
1630         243, 260, 261, 224, 280, 262, 281, 264, 300, 263, 282, 301, 320, 283,
1631         302, 321
1632 };
1633
1634 /* The GPIO1D (28-31) pins overlap with TVC */
1635 static const unsigned int gpio1d_3516_pins[] = { 353, 311, 394, 374 };
1636
1637 /* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
1638 static const unsigned int gpio2a_3516_pins[] = { 308, 369, 389, 329 };
1639
1640 /* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
1641 static const unsigned int gpio2b_3516_pins[] = { 391, 351, 310, 371 };
1642
1643 /* The GPIO2C (8-31) pins overlap with PCI */
1644 static const unsigned int gpio2c_3516_pins[] = {
1645         259, 237, 238, 239, 215, 216, 217, 218, 177, 159, 158, 175, 176, 139,
1646         157, 138, 137, 156, 118, 155, 99, 98, 136, 117
1647 };
1648
1649 /* Groups for the 3516 SoC/package */
1650 static const struct gemini_pin_group gemini_3516_pin_groups[] = {
1651         {
1652                 .name = "gndgrp",
1653                 .pins = gnd_3516_pins,
1654                 .num_pins = ARRAY_SIZE(gnd_3516_pins),
1655         },
1656         {
1657                 .name = "dramgrp",
1658                 .pins = dram_3516_pins,
1659                 .num_pins = ARRAY_SIZE(dram_3516_pins),
1660                 .mask = DRAM_PADS_POWERDOWN,
1661         },
1662         {
1663                 .name = "rtcgrp",
1664                 .pins = rtc_3516_pins,
1665                 .num_pins = ARRAY_SIZE(rtc_3516_pins),
1666         },
1667         {
1668                 .name = "powergrp",
1669                 .pins = power_3516_pins,
1670                 .num_pins = ARRAY_SIZE(power_3516_pins),
1671         },
1672         {
1673                 .name = "cirgrp",
1674                 .pins = cir_3516_pins,
1675                 .num_pins = ARRAY_SIZE(cir_3516_pins),
1676         },
1677         {
1678                 .name = "systemgrp",
1679                 .pins = system_3516_pins,
1680                 .num_pins = ARRAY_SIZE(system_3516_pins),
1681         },
1682         {
1683                 .name = "vcontrolgrp",
1684                 .pins = vcontrol_3516_pins,
1685                 .num_pins = ARRAY_SIZE(vcontrol_3516_pins),
1686         },
1687         {
1688                 .name = "icegrp",
1689                 .pins = ice_3516_pins,
1690                 .num_pins = ARRAY_SIZE(ice_3516_pins),
1691                 /* Conflict with some GPIO groups */
1692         },
1693         {
1694                 .name = "idegrp",
1695                 .pins = ide_3516_pins,
1696                 .num_pins = ARRAY_SIZE(ide_3516_pins),
1697                 /* Conflict with all flash usage */
1698                 .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE |
1699                         PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
1700                 .driving_mask = GENMASK(21, 20),
1701         },
1702         {
1703                 .name = "satagrp",
1704                 .pins = sata_3516_pins,
1705                 .num_pins = ARRAY_SIZE(sata_3516_pins),
1706         },
1707         {
1708                 .name = "usbgrp",
1709                 .pins = usb_3516_pins,
1710                 .num_pins = ARRAY_SIZE(usb_3516_pins),
1711         },
1712         {
1713                 .name = "gmii_gmac0_grp",
1714                 .pins = gmii_gmac0_3516_pins,
1715                 .num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins),
1716                 .mask = GEMINI_GMAC_IOSEL_MASK,
1717                 .driving_mask = GENMASK(17, 16),
1718         },
1719         {
1720                 .name = "gmii_gmac1_grp",
1721                 .pins = gmii_gmac1_3516_pins,
1722                 .num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins),
1723                 /* Bring out RGMII on the GMAC1 pins */
1724                 .mask = GEMINI_GMAC_IOSEL_MASK,
1725                 .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
1726                 .driving_mask = GENMASK(19, 18),
1727         },
1728         {
1729                 .name = "pcigrp",
1730                 .pins = pci_3516_pins,
1731                 .num_pins = ARRAY_SIZE(pci_3516_pins),
1732                 /* Conflict only with GPIO2 */
1733                 .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE,
1734                 .driving_mask = GENMASK(23, 22),
1735         },
1736         {
1737                 .name = "lpcgrp",
1738                 .pins = lpc_3516_pins,
1739                 .num_pins = ARRAY_SIZE(lpc_3516_pins),
1740                 /* Conflict with SSP */
1741                 .mask = SSP_PADS_ENABLE,
1742                 .value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE,
1743         },
1744         {
1745                 .name = "lcdgrp",
1746                 .pins = lcd_3516_pins,
1747                 .num_pins = ARRAY_SIZE(lcd_3516_pins),
1748                 .mask = TVC_PADS_ENABLE,
1749                 .value = LCD_PADS_ENABLE,
1750         },
1751         {
1752                 .name = "sspgrp",
1753                 .pins = ssp_3516_pins,
1754                 .num_pins = ARRAY_SIZE(ssp_3516_pins),
1755                 /* Conflict with LPC */
1756                 .mask = LPC_PADS_ENABLE,
1757                 .value = SSP_PADS_ENABLE,
1758         },
1759         {
1760                 .name = "uartrxtxgrp",
1761                 .pins = uart_rxtx_3516_pins,
1762                 .num_pins = ARRAY_SIZE(uart_rxtx_3516_pins),
1763                 /* No conflicts except GPIO */
1764         },
1765         {
1766                 .name = "uartmodemgrp",
1767                 .pins = uart_modem_3516_pins,
1768                 .num_pins = ARRAY_SIZE(uart_modem_3516_pins),
1769                 /*
1770                  * Conflict with LPC and SSP,
1771                  * so when those are both disabled, modem UART can thrive.
1772                  */
1773                 .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
1774         },
1775         {
1776                 .name = "tvcgrp",
1777                 .pins = tvc_3516_pins,
1778                 .num_pins = ARRAY_SIZE(tvc_3516_pins),
1779                 /* Conflict with character LCD */
1780                 .mask = LCD_PADS_ENABLE,
1781                 .value = TVC_PADS_ENABLE,
1782         },
1783         {
1784                 .name = "tvcclkgrp",
1785                 .pins = tvc_clk_3516_pins,
1786                 .num_pins = ARRAY_SIZE(tvc_clk_3516_pins),
1787                 .value = TVC_CLK_PAD_ENABLE,
1788         },
1789         /*
1790          * The construction is done such that it is possible to use a serial
1791          * flash together with a NAND or parallel (NOR) flash, but it is not
1792          * possible to use NAND and parallel flash together. To use serial
1793          * flash with one of the two others, the muxbits need to be flipped
1794          * around before any access.
1795          */
1796         {
1797                 .name = "nflashgrp",
1798                 .pins = nflash_3516_pins,
1799                 .num_pins = ARRAY_SIZE(nflash_3516_pins),
1800                 /* Conflict with IDE, parallel and serial flash */
1801                 .mask = NAND_PADS_DISABLE | IDE_PADS_ENABLE,
1802                 .value = PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
1803         },
1804         {
1805                 .name = "pflashgrp",
1806                 .pins = pflash_3516_pins,
1807                 .num_pins = ARRAY_SIZE(pflash_3516_pins),
1808                 /* Conflict with IDE, NAND and serial flash */
1809                 .mask = PFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
1810                 .value = NAND_PADS_DISABLE | SFLASH_PADS_DISABLE,
1811         },
1812         {
1813                 .name = "sflashgrp",
1814                 .pins = sflash_3516_pins,
1815                 .num_pins = ARRAY_SIZE(sflash_3516_pins),
1816                 /* Conflict with IDE, NAND and parallel flash */
1817                 .mask = SFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
1818                 .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
1819         },
1820         {
1821                 .name = "gpio0agrp",
1822                 .pins = gpio0a_3516_pins,
1823                 .num_pins = ARRAY_SIZE(gpio0a_3516_pins),
1824                 /* Conflict with TVC and ICE */
1825                 .mask = TVC_PADS_ENABLE,
1826         },
1827         {
1828                 .name = "gpio0bgrp",
1829                 .pins = gpio0b_3516_pins,
1830                 .num_pins = ARRAY_SIZE(gpio0b_3516_pins),
1831                 /* Conflict with ICE */
1832         },
1833         {
1834                 .name = "gpio0cgrp",
1835                 .pins = gpio0c_3516_pins,
1836                 .num_pins = ARRAY_SIZE(gpio0c_3516_pins),
1837                 /* Conflict with LPC, UART and SSP */
1838                 .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
1839         },
1840         {
1841                 .name = "gpio0dgrp",
1842                 .pins = gpio0d_3516_pins,
1843                 .num_pins = ARRAY_SIZE(gpio0d_3516_pins),
1844                 /* Conflict with UART */
1845         },
1846         {
1847                 .name = "gpio0egrp",
1848                 .pins = gpio0e_3516_pins,
1849                 .num_pins = ARRAY_SIZE(gpio0e_3516_pins),
1850                 /* Conflict with LCD */
1851                 .mask = LCD_PADS_ENABLE,
1852         },
1853         {
1854                 .name = "gpio0fgrp",
1855                 .pins = gpio0f_3516_pins,
1856                 .num_pins = ARRAY_SIZE(gpio0f_3516_pins),
1857                 /* Conflict with NAND flash */
1858                 .value = NAND_PADS_DISABLE,
1859         },
1860         {
1861                 .name = "gpio0ggrp",
1862                 .pins = gpio0g_3516_pins,
1863                 .num_pins = ARRAY_SIZE(gpio0g_3516_pins),
1864                 /* Conflict with parallel flash */
1865                 .value = PFLASH_PADS_DISABLE,
1866         },
1867         {
1868                 .name = "gpio0hgrp",
1869                 .pins = gpio0h_3516_pins,
1870                 .num_pins = ARRAY_SIZE(gpio0h_3516_pins),
1871                 /* Conflict with serial flash */
1872                 .value = SFLASH_PADS_DISABLE,
1873         },
1874         {
1875                 .name = "gpio0igrp",
1876                 .pins = gpio0i_3516_pins,
1877                 .num_pins = ARRAY_SIZE(gpio0i_3516_pins),
1878                 /* Conflict with all flash */
1879                 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
1880                         SFLASH_PADS_DISABLE,
1881         },
1882         {
1883                 .name = "gpio0jgrp",
1884                 .pins = gpio0j_3516_pins,
1885                 .num_pins = ARRAY_SIZE(gpio0j_3516_pins),
1886                 /* Conflict with all flash and LCD */
1887                 .mask = LCD_PADS_ENABLE,
1888                 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
1889                         SFLASH_PADS_DISABLE,
1890         },
1891         {
1892                 .name = "gpio0kgrp",
1893                 .pins = gpio0k_3516_pins,
1894                 .num_pins = ARRAY_SIZE(gpio0k_3516_pins),
1895                 /* Conflict with parallel and NAND flash */
1896                 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE,
1897         },
1898         {
1899                 .name = "gpio0lgrp",
1900                 .pins = gpio0l_3516_pins,
1901                 .num_pins = ARRAY_SIZE(gpio0l_3516_pins),
1902                 /* Conflict with TVE CLK */
1903                 .mask = TVC_CLK_PAD_ENABLE,
1904         },
1905         {
1906                 .name = "gpio1agrp",
1907                 .pins = gpio1a_3516_pins,
1908                 .num_pins = ARRAY_SIZE(gpio1a_3516_pins),
1909                 /* Conflict with IDE and parallel flash */
1910                 .mask = IDE_PADS_ENABLE,
1911                 .value = PFLASH_PADS_DISABLE,
1912         },
1913         {
1914                 .name = "gpio1bgrp",
1915                 .pins = gpio1b_3516_pins,
1916                 .num_pins = ARRAY_SIZE(gpio1b_3516_pins),
1917                 /* Conflict with IDE only */
1918                 .mask = IDE_PADS_ENABLE,
1919         },
1920         {
1921                 .name = "gpio1cgrp",
1922                 .pins = gpio1c_3516_pins,
1923                 .num_pins = ARRAY_SIZE(gpio1c_3516_pins),
1924                 /* Conflict with IDE, parallel and NAND flash */
1925                 .mask = IDE_PADS_ENABLE,
1926                 .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
1927         },
1928         {
1929                 .name = "gpio1dgrp",
1930                 .pins = gpio1d_3516_pins,
1931                 .num_pins = ARRAY_SIZE(gpio1d_3516_pins),
1932                 /* Conflict with TVC */
1933                 .mask = TVC_PADS_ENABLE,
1934         },
1935         {
1936                 .name = "gpio2agrp",
1937                 .pins = gpio2a_3516_pins,
1938                 .num_pins = ARRAY_SIZE(gpio2a_3516_pins),
1939                 .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
1940                 /* Conflict with GMII GMAC1 and extended parallel flash */
1941         },
1942         {
1943                 .name = "gpio2bgrp",
1944                 .pins = gpio2b_3516_pins,
1945                 .num_pins = ARRAY_SIZE(gpio2b_3516_pins),
1946                 /* Conflict with GMII GMAC1, extended parallel flash and LCD */
1947                 .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
1948         },
1949         {
1950                 .name = "gpio2cgrp",
1951                 .pins = gpio2c_3516_pins,
1952                 .num_pins = ARRAY_SIZE(gpio2c_3516_pins),
1953                 /* Conflict with PCI */
1954                 .mask = PCI_PADS_ENABLE,
1955         },
1956 };
1957
1958 static int gemini_get_groups_count(struct pinctrl_dev *pctldev)
1959 {
1960         struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1961
1962         if (pmx->is_3512)
1963                 return ARRAY_SIZE(gemini_3512_pin_groups);
1964         if (pmx->is_3516)
1965                 return ARRAY_SIZE(gemini_3516_pin_groups);
1966         return 0;
1967 }
1968
1969 static const char *gemini_get_group_name(struct pinctrl_dev *pctldev,
1970                                          unsigned int selector)
1971 {
1972         struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1973
1974         if (pmx->is_3512)
1975                 return gemini_3512_pin_groups[selector].name;
1976         if (pmx->is_3516)
1977                 return gemini_3516_pin_groups[selector].name;
1978         return NULL;
1979 }
1980
1981 static int gemini_get_group_pins(struct pinctrl_dev *pctldev,
1982                                  unsigned int selector,
1983                                  const unsigned int **pins,
1984                                  unsigned int *num_pins)
1985 {
1986         struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1987
1988         /* The special case with the 3516 flash pin */
1989         if (pmx->flash_pin &&
1990             pmx->is_3512 &&
1991             !strcmp(gemini_3512_pin_groups[selector].name, "pflashgrp")) {
1992                 *pins = pflash_3512_pins_extended;
1993                 *num_pins = ARRAY_SIZE(pflash_3512_pins_extended);
1994                 return 0;
1995         }
1996         if (pmx->flash_pin &&
1997             pmx->is_3516 &&
1998             !strcmp(gemini_3516_pin_groups[selector].name, "pflashgrp")) {
1999                 *pins = pflash_3516_pins_extended;
2000                 *num_pins = ARRAY_SIZE(pflash_3516_pins_extended);
2001                 return 0;
2002         }
2003         if (pmx->is_3512) {
2004                 *pins = gemini_3512_pin_groups[selector].pins;
2005                 *num_pins = gemini_3512_pin_groups[selector].num_pins;
2006         }
2007         if (pmx->is_3516) {
2008                 *pins = gemini_3516_pin_groups[selector].pins;
2009                 *num_pins = gemini_3516_pin_groups[selector].num_pins;
2010         }
2011         return 0;
2012 }
2013
2014 static void gemini_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
2015                                 unsigned int offset)
2016 {
2017         seq_printf(s, " " DRIVER_NAME);
2018 }
2019
2020 static const struct pinctrl_ops gemini_pctrl_ops = {
2021         .get_groups_count = gemini_get_groups_count,
2022         .get_group_name = gemini_get_group_name,
2023         .get_group_pins = gemini_get_group_pins,
2024         .pin_dbg_show = gemini_pin_dbg_show,
2025         .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
2026         .dt_free_map = pinconf_generic_dt_free_map,
2027 };
2028
2029 /**
2030  * struct gemini_pmx_func - describes Gemini pinmux functions
2031  * @name: the name of this specific function
2032  * @groups: corresponding pin groups
2033  */
2034 struct gemini_pmx_func {
2035         const char *name;
2036         const char * const *groups;
2037         const unsigned int num_groups;
2038 };
2039
2040 static const char * const dramgrps[] = { "dramgrp" };
2041 static const char * const rtcgrps[] = { "rtcgrp" };
2042 static const char * const powergrps[] = { "powergrp" };
2043 static const char * const cirgrps[] = { "cirgrp" };
2044 static const char * const systemgrps[] = { "systemgrp" };
2045 static const char * const vcontrolgrps[] = { "vcontrolgrp" };
2046 static const char * const icegrps[] = { "icegrp" };
2047 static const char * const idegrps[] = { "idegrp" };
2048 static const char * const satagrps[] = { "satagrp" };
2049 static const char * const usbgrps[] = { "usbgrp" };
2050 static const char * const gmiigrps[] = { "gmii_gmac0_grp", "gmii_gmac1_grp" };
2051 static const char * const pcigrps[] = { "pcigrp" };
2052 static const char * const lpcgrps[] = { "lpcgrp" };
2053 static const char * const lcdgrps[] = { "lcdgrp" };
2054 static const char * const sspgrps[] = { "sspgrp" };
2055 static const char * const uartgrps[] = { "uartrxtxgrp", "uartmodemgrp" };
2056 static const char * const tvcgrps[] = { "tvcgrp" };
2057 static const char * const nflashgrps[] = { "nflashgrp" };
2058 static const char * const pflashgrps[] = { "pflashgrp", "pflashextgrp" };
2059 static const char * const sflashgrps[] = { "sflashgrp" };
2060 static const char * const gpio0grps[] = { "gpio0agrp", "gpio0bgrp", "gpio0cgrp",
2061                                           "gpio0dgrp", "gpio0egrp", "gpio0fgrp",
2062                                           "gpio0ggrp", "gpio0hgrp", "gpio0igrp",
2063                                           "gpio0jgrp", "gpio0kgrp", "gpio0lgrp",
2064                                           "gpio0mgrp" };
2065 static const char * const gpio1grps[] = { "gpio1agrp", "gpio1bgrp", "gpio1cgrp",
2066                                           "gpio1dgrp" };
2067 static const char * const gpio2grps[] = { "gpio2agrp", "gpio2bgrp", "gpio2cgrp" };
2068
2069 static const struct gemini_pmx_func gemini_pmx_functions[] = {
2070         {
2071                 .name = "dram",
2072                 .groups = dramgrps,
2073                 .num_groups = ARRAY_SIZE(idegrps),
2074         },
2075         {
2076                 .name = "rtc",
2077                 .groups = rtcgrps,
2078                 .num_groups = ARRAY_SIZE(rtcgrps),
2079         },
2080         {
2081                 .name = "power",
2082                 .groups = powergrps,
2083                 .num_groups = ARRAY_SIZE(powergrps),
2084         },
2085         {
2086                 /* This function is strictly unavailable on 3512 */
2087                 .name = "cir",
2088                 .groups = cirgrps,
2089                 .num_groups = ARRAY_SIZE(cirgrps),
2090         },
2091         {
2092                 .name = "system",
2093                 .groups = systemgrps,
2094                 .num_groups = ARRAY_SIZE(systemgrps),
2095         },
2096         {
2097                 .name = "vcontrol",
2098                 .groups = vcontrolgrps,
2099                 .num_groups = ARRAY_SIZE(vcontrolgrps),
2100         },
2101         {
2102                 .name = "ice",
2103                 .groups = icegrps,
2104                 .num_groups = ARRAY_SIZE(icegrps),
2105         },
2106         {
2107                 .name = "ide",
2108                 .groups = idegrps,
2109                 .num_groups = ARRAY_SIZE(idegrps),
2110         },
2111         {
2112                 .name = "sata",
2113                 .groups = satagrps,
2114                 .num_groups = ARRAY_SIZE(satagrps),
2115         },
2116         {
2117                 .name = "usb",
2118                 .groups = usbgrps,
2119                 .num_groups = ARRAY_SIZE(usbgrps),
2120         },
2121         {
2122                 .name = "gmii",
2123                 .groups = gmiigrps,
2124                 .num_groups = ARRAY_SIZE(gmiigrps),
2125         },
2126         {
2127                 .name = "pci",
2128                 .groups = pcigrps,
2129                 .num_groups = ARRAY_SIZE(pcigrps),
2130         },
2131         {
2132                 .name = "lpc",
2133                 .groups = lpcgrps,
2134                 .num_groups = ARRAY_SIZE(lpcgrps),
2135         },
2136         {
2137                 .name = "lcd",
2138                 .groups = lcdgrps,
2139                 .num_groups = ARRAY_SIZE(lcdgrps),
2140         },
2141         {
2142                 .name = "ssp",
2143                 .groups = sspgrps,
2144                 .num_groups = ARRAY_SIZE(sspgrps),
2145         },
2146         {
2147                 .name = "uart",
2148                 .groups = uartgrps,
2149                 .num_groups = ARRAY_SIZE(uartgrps),
2150         },
2151         {
2152                 .name = "tvc",
2153                 .groups = tvcgrps,
2154                 .num_groups = ARRAY_SIZE(tvcgrps),
2155         },
2156         {
2157                 .name = "nflash",
2158                 .groups = nflashgrps,
2159                 .num_groups = ARRAY_SIZE(nflashgrps),
2160         },
2161         {
2162                 .name = "pflash",
2163                 .groups = pflashgrps,
2164                 .num_groups = ARRAY_SIZE(pflashgrps),
2165         },
2166         {
2167                 .name = "sflash",
2168                 .groups = sflashgrps,
2169                 .num_groups = ARRAY_SIZE(sflashgrps),
2170         },
2171         {
2172                 .name = "gpio0",
2173                 .groups = gpio0grps,
2174                 .num_groups = ARRAY_SIZE(gpio0grps),
2175         },
2176         {
2177                 .name = "gpio1",
2178                 .groups = gpio1grps,
2179                 .num_groups = ARRAY_SIZE(gpio1grps),
2180         },
2181         {
2182                 .name = "gpio2",
2183                 .groups = gpio2grps,
2184                 .num_groups = ARRAY_SIZE(gpio2grps),
2185         },
2186 };
2187
2188
2189 static int gemini_pmx_set_mux(struct pinctrl_dev *pctldev,
2190                               unsigned int selector,
2191                               unsigned int group)
2192 {
2193         struct gemini_pmx *pmx;
2194         const struct gemini_pmx_func *func;
2195         const struct gemini_pin_group *grp;
2196         u32 before, after, expected;
2197         unsigned long tmp;
2198         int i;
2199
2200         pmx = pinctrl_dev_get_drvdata(pctldev);
2201
2202         func = &gemini_pmx_functions[selector];
2203         if (pmx->is_3512)
2204                 grp = &gemini_3512_pin_groups[group];
2205         else if (pmx->is_3516)
2206                 grp = &gemini_3516_pin_groups[group];
2207         else {
2208                 dev_err(pmx->dev, "invalid SoC type\n");
2209                 return -ENODEV;
2210         }
2211
2212         dev_dbg(pmx->dev,
2213                 "ACTIVATE function \"%s\" with group \"%s\"\n",
2214                 func->name, grp->name);
2215
2216         regmap_read(pmx->map, GLOBAL_MISC_CTRL, &before);
2217         regmap_update_bits(pmx->map, GLOBAL_MISC_CTRL,
2218                            grp->mask | grp->value,
2219                            grp->value);
2220         regmap_read(pmx->map, GLOBAL_MISC_CTRL, &after);
2221
2222         /* Which bits changed */
2223         before &= PADS_MASK;
2224         after &= PADS_MASK;
2225         expected = before &= ~grp->mask;
2226         expected |= grp->value;
2227         expected &= PADS_MASK;
2228
2229         /* Print changed states */
2230         tmp = grp->mask;
2231         for_each_set_bit(i, &tmp, PADS_MAXBIT) {
2232                 bool enabled = !(i > 3);
2233
2234                 /* Did not go low though it should */
2235                 if (after & BIT(i)) {
2236                         dev_err(pmx->dev,
2237                                 "pin group %s could not be %s: "
2238                                 "probably a hardware limitation\n",
2239                                 gemini_padgroups[i],
2240                                 enabled ? "enabled" : "disabled");
2241                         dev_err(pmx->dev,
2242                                 "GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n",
2243                                 before, after, expected);
2244                 } else {
2245                         dev_dbg(pmx->dev,
2246                                 "padgroup %s %s\n",
2247                                 gemini_padgroups[i],
2248                                 enabled ? "enabled" : "disabled");
2249                 }
2250         }
2251
2252         tmp = grp->value;
2253         for_each_set_bit(i, &tmp, PADS_MAXBIT) {
2254                 bool enabled = (i > 3);
2255
2256                 /* Did not go high though it should */
2257                 if (!(after & BIT(i))) {
2258                         dev_err(pmx->dev,
2259                                 "pin group %s could not be %s: "
2260                                 "probably a hardware limitation\n",
2261                                 gemini_padgroups[i],
2262                                 enabled ? "enabled" : "disabled");
2263                         dev_err(pmx->dev,
2264                                 "GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n",
2265                                 before, after, expected);
2266                 } else {
2267                         dev_dbg(pmx->dev,
2268                                 "padgroup %s %s\n",
2269                                 gemini_padgroups[i],
2270                                 enabled ? "enabled" : "disabled");
2271                 }
2272         }
2273
2274         return 0;
2275 }
2276
2277 static int gemini_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2278 {
2279         return ARRAY_SIZE(gemini_pmx_functions);
2280 }
2281
2282 static const char *gemini_pmx_get_func_name(struct pinctrl_dev *pctldev,
2283                                             unsigned int selector)
2284 {
2285         return gemini_pmx_functions[selector].name;
2286 }
2287
2288 static int gemini_pmx_get_groups(struct pinctrl_dev *pctldev,
2289                                  unsigned int selector,
2290                                  const char * const **groups,
2291                                  unsigned int * const num_groups)
2292 {
2293         *groups = gemini_pmx_functions[selector].groups;
2294         *num_groups = gemini_pmx_functions[selector].num_groups;
2295         return 0;
2296 }
2297
2298 static const struct pinmux_ops gemini_pmx_ops = {
2299         .get_functions_count = gemini_pmx_get_funcs_count,
2300         .get_function_name = gemini_pmx_get_func_name,
2301         .get_function_groups = gemini_pmx_get_groups,
2302         .set_mux = gemini_pmx_set_mux,
2303 };
2304
2305 #define GEMINI_CFGPIN(_n, _r, _lb, _hb) {       \
2306         .pin = _n,                              \
2307         .reg = _r,                              \
2308         .mask = GENMASK(_hb, _lb)               \
2309 }
2310
2311 static const struct gemini_pin_conf gemini_confs_3512[] = {
2312         GEMINI_CFGPIN(259, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */
2313         GEMINI_CFGPIN(277, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */
2314         GEMINI_CFGPIN(241, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */
2315         GEMINI_CFGPIN(312, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */
2316         GEMINI_CFGPIN(298, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */
2317         GEMINI_CFGPIN(280, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */
2318         GEMINI_CFGPIN(316, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */
2319         GEMINI_CFGPIN(243, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */
2320         GEMINI_CFGPIN(295, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */
2321         GEMINI_CFGPIN(313, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */
2322         GEMINI_CFGPIN(242, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */
2323         GEMINI_CFGPIN(260, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */
2324         GEMINI_CFGPIN(294, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */
2325         GEMINI_CFGPIN(276, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */
2326         GEMINI_CFGPIN(258, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */
2327         GEMINI_CFGPIN(240, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */
2328         GEMINI_CFGPIN(262, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */
2329         GEMINI_CFGPIN(244, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */
2330         GEMINI_CFGPIN(317, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */
2331         GEMINI_CFGPIN(299, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */
2332         GEMINI_CFGPIN(261, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */
2333         GEMINI_CFGPIN(279, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */
2334         GEMINI_CFGPIN(297, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */
2335         GEMINI_CFGPIN(315, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */
2336 };
2337
2338 static const struct gemini_pin_conf gemini_confs_3516[] = {
2339         GEMINI_CFGPIN(347, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */
2340         GEMINI_CFGPIN(386, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */
2341         GEMINI_CFGPIN(307, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */
2342         GEMINI_CFGPIN(327, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */
2343         GEMINI_CFGPIN(309, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */
2344         GEMINI_CFGPIN(390, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */
2345         GEMINI_CFGPIN(370, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */
2346         GEMINI_CFGPIN(350, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */
2347         GEMINI_CFGPIN(367, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */
2348         GEMINI_CFGPIN(348, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */
2349         GEMINI_CFGPIN(387, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */
2350         GEMINI_CFGPIN(328, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */
2351         GEMINI_CFGPIN(306, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */
2352         GEMINI_CFGPIN(325, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */
2353         GEMINI_CFGPIN(346, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */
2354         GEMINI_CFGPIN(326, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */
2355         GEMINI_CFGPIN(391, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */
2356         GEMINI_CFGPIN(351, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */
2357         GEMINI_CFGPIN(310, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */
2358         GEMINI_CFGPIN(371, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */
2359         GEMINI_CFGPIN(329, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */
2360         GEMINI_CFGPIN(389, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */
2361         GEMINI_CFGPIN(369, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */
2362         GEMINI_CFGPIN(308, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */
2363 };
2364
2365 static const struct gemini_pin_conf *gemini_get_pin_conf(struct gemini_pmx *pmx,
2366                                                          unsigned int pin)
2367 {
2368         const struct gemini_pin_conf *retconf;
2369         int i;
2370
2371         for (i = 0; i < pmx->nconfs; i++) {
2372                 retconf = &pmx->confs[i];
2373                 if (retconf->pin == pin)
2374                         return retconf;
2375         }
2376         return NULL;
2377 }
2378
2379 static int gemini_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2380                               unsigned long *config)
2381 {
2382         struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
2383         enum pin_config_param param = pinconf_to_config_param(*config);
2384         const struct gemini_pin_conf *conf;
2385         u32 val;
2386
2387         switch (param) {
2388         case PIN_CONFIG_SKEW_DELAY:
2389                 conf = gemini_get_pin_conf(pmx, pin);
2390                 if (!conf)
2391                         return -ENOTSUPP;
2392                 regmap_read(pmx->map, conf->reg, &val);
2393                 val &= conf->mask;
2394                 val >>= (ffs(conf->mask) - 1);
2395                 *config = pinconf_to_config_packed(PIN_CONFIG_SKEW_DELAY, val);
2396                 break;
2397         default:
2398                 return -ENOTSUPP;
2399         }
2400
2401         return 0;
2402 }
2403
2404 static int gemini_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2405                               unsigned long *configs, unsigned int num_configs)
2406 {
2407         struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
2408         const struct gemini_pin_conf *conf;
2409         enum pin_config_param param;
2410         u32 arg;
2411         int ret = 0;
2412         int i;
2413
2414         for (i = 0; i < num_configs; i++) {
2415                 param = pinconf_to_config_param(configs[i]);
2416                 arg = pinconf_to_config_argument(configs[i]);
2417
2418                 switch (param) {
2419                 case PIN_CONFIG_SKEW_DELAY:
2420                         if (arg > 0xf)
2421                                 return -EINVAL;
2422                         conf = gemini_get_pin_conf(pmx, pin);
2423                         if (!conf) {
2424                                 dev_err(pmx->dev,
2425                                         "invalid pin for skew delay %d\n", pin);
2426                                 return -ENOTSUPP;
2427                         }
2428                         arg <<= (ffs(conf->mask) - 1);
2429                         dev_dbg(pmx->dev,
2430                                 "set pin %d to skew delay mask %08x, val %08x\n",
2431                                 pin, conf->mask, arg);
2432                         regmap_update_bits(pmx->map, conf->reg, conf->mask, arg);
2433                         break;
2434                 default:
2435                         dev_err(pmx->dev, "Invalid config param %04x\n", param);
2436                         return -ENOTSUPP;
2437                 }
2438         }
2439
2440         return ret;
2441 }
2442
2443 static int gemini_pinconf_group_set(struct pinctrl_dev *pctldev,
2444                                     unsigned selector,
2445                                     unsigned long *configs,
2446                                     unsigned num_configs)
2447 {
2448         struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
2449         const struct gemini_pin_group *grp = NULL;
2450         enum pin_config_param param;
2451         u32 arg;
2452         u32 val;
2453         int i;
2454
2455         if (pmx->is_3512)
2456                 grp = &gemini_3512_pin_groups[selector];
2457         if (pmx->is_3516)
2458                 grp = &gemini_3516_pin_groups[selector];
2459
2460         /* First figure out if this group supports configs */
2461         if (!grp->driving_mask) {
2462                 dev_err(pmx->dev, "pin config group \"%s\" does "
2463                         "not support drive strength setting\n",
2464                         grp->name);
2465                 return -EINVAL;
2466         }
2467
2468         for (i = 0; i < num_configs; i++) {
2469                 param = pinconf_to_config_param(configs[i]);
2470                 arg = pinconf_to_config_argument(configs[i]);
2471
2472                 switch (param) {
2473                 case PIN_CONFIG_DRIVE_STRENGTH:
2474                         switch (arg) {
2475                         case 4:
2476                                 val = 0;
2477                                 break;
2478                         case 8:
2479                                 val = 1;
2480                                 break;
2481                         case 12:
2482                                 val = 2;
2483                                 break;
2484                         case 16:
2485                                 val = 3;
2486                                 break;
2487                         default:
2488                                 dev_err(pmx->dev,
2489                                         "invalid drive strength %d mA\n",
2490                                         arg);
2491                                 return -ENOTSUPP;
2492                         }
2493                         val <<= (ffs(grp->driving_mask) - 1);
2494                         regmap_update_bits(pmx->map, GLOBAL_IODRIVE,
2495                                            grp->driving_mask,
2496                                            val);
2497                         dev_dbg(pmx->dev,
2498                                 "set group %s to %d mA drive strength mask %08x val %08x\n",
2499                                 grp->name, arg, grp->driving_mask, val);
2500                         break;
2501                 default:
2502                         dev_err(pmx->dev, "invalid config param %04x\n", param);
2503                         return -ENOTSUPP;
2504                 }
2505         }
2506
2507         return 0;
2508 }
2509
2510 static const struct pinconf_ops gemini_pinconf_ops = {
2511         .pin_config_get = gemini_pinconf_get,
2512         .pin_config_set = gemini_pinconf_set,
2513         .pin_config_group_set = gemini_pinconf_group_set,
2514         .is_generic = true,
2515 };
2516
2517 static struct pinctrl_desc gemini_pmx_desc = {
2518         .name = DRIVER_NAME,
2519         .pctlops = &gemini_pctrl_ops,
2520         .pmxops = &gemini_pmx_ops,
2521         .confops = &gemini_pinconf_ops,
2522         .owner = THIS_MODULE,
2523 };
2524
2525 static int gemini_pmx_probe(struct platform_device *pdev)
2526 {
2527         struct gemini_pmx *pmx;
2528         struct regmap *map;
2529         struct device *dev = &pdev->dev;
2530         struct device *parent;
2531         unsigned long tmp;
2532         u32 val;
2533         int ret;
2534         int i;
2535
2536         /* Create state holders etc for this driver */
2537         pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
2538         if (!pmx)
2539                 return -ENOMEM;
2540
2541         pmx->dev = &pdev->dev;
2542         parent = dev->parent;
2543         if (!parent) {
2544                 dev_err(dev, "no parent to pin controller\n");
2545                 return -ENODEV;
2546         }
2547         map = syscon_node_to_regmap(parent->of_node);
2548         if (IS_ERR(map)) {
2549                 dev_err(dev, "no syscon regmap\n");
2550                 return PTR_ERR(map);
2551         }
2552         pmx->map = map;
2553
2554         /* Check that regmap works at first call, then no more */
2555         ret = regmap_read(map, GLOBAL_WORD_ID, &val);
2556         if (ret) {
2557                 dev_err(dev, "cannot access regmap\n");
2558                 return ret;
2559         }
2560         val >>= 8;
2561         val &= 0xffff;
2562         if (val == 0x3512) {
2563                 pmx->is_3512 = true;
2564                 pmx->confs = gemini_confs_3512;
2565                 pmx->nconfs = ARRAY_SIZE(gemini_confs_3512);
2566                 gemini_pmx_desc.pins = gemini_3512_pins;
2567                 gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3512_pins);
2568                 dev_info(dev, "detected 3512 chip variant\n");
2569         } else if (val == 0x3516) {
2570                 pmx->is_3516 = true;
2571                 pmx->confs = gemini_confs_3516;
2572                 pmx->nconfs = ARRAY_SIZE(gemini_confs_3516);
2573                 gemini_pmx_desc.pins = gemini_3516_pins;
2574                 gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3516_pins);
2575                 dev_info(dev, "detected 3516 chip variant\n");
2576         } else {
2577                 dev_err(dev, "unknown chip ID: %04x\n", val);
2578                 return -ENODEV;
2579         }
2580
2581         ret = regmap_read(map, GLOBAL_MISC_CTRL, &val);
2582         dev_info(dev, "GLOBAL MISC CTRL at boot: 0x%08x\n", val);
2583         /* Mask off relevant pads */
2584         val &= PADS_MASK;
2585         /* Invert the meaning of the DRAM+flash pads */
2586         val ^= 0x0f;
2587         /* Print initial state */
2588         tmp = val;
2589         for_each_set_bit(i, &tmp, PADS_MAXBIT) {
2590                 dev_dbg(dev, "pad group %s %s\n", gemini_padgroups[i],
2591                         (val & BIT(i)) ? "enabled" : "disabled");
2592         }
2593
2594         /* Check if flash pin is set */
2595         regmap_read(map, GLOBAL_STATUS, &val);
2596         pmx->flash_pin = !!(val & GLOBAL_STATUS_FLPIN);
2597         dev_info(dev, "flash pin is %s\n", pmx->flash_pin ? "set" : "not set");
2598
2599         pmx->pctl = devm_pinctrl_register(dev, &gemini_pmx_desc, pmx);
2600         if (IS_ERR(pmx->pctl)) {
2601                 dev_err(dev, "could not register pinmux driver\n");
2602                 return PTR_ERR(pmx->pctl);
2603         }
2604
2605         dev_info(dev, "initialized Gemini pin control driver\n");
2606
2607         return 0;
2608 }
2609
2610 static const struct of_device_id gemini_pinctrl_match[] = {
2611         { .compatible = "cortina,gemini-pinctrl" },
2612         {},
2613 };
2614
2615 static struct platform_driver gemini_pmx_driver = {
2616         .driver = {
2617                 .name = DRIVER_NAME,
2618                 .of_match_table = gemini_pinctrl_match,
2619         },
2620         .probe = gemini_pmx_probe,
2621 };
2622
2623 static int __init gemini_pmx_init(void)
2624 {
2625         return platform_driver_register(&gemini_pmx_driver);
2626 }
2627 arch_initcall(gemini_pmx_init);