2 * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2012 Linaro Ltd
7 * http://www.linaro.org
9 * Author: Thomas Abraham <thomas.ab@samsung.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This file contains the Samsung Exynos specific information required by the
17 * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
18 * external gpio and wakeup interrupt support.
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/irqdomain.h>
25 #include <linux/irq.h>
26 #include <linux/of_irq.h>
28 #include <linux/slab.h>
29 #include <linux/err.h>
31 #include <asm/mach/irq.h>
33 #include "pinctrl-samsung.h"
34 #include "pinctrl-exynos.h"
36 /* list of external wakeup controllers supported */
37 static const struct of_device_id exynos_wkup_irq_ids[] = {
38 { .compatible = "samsung,exynos4210-wakeup-eint", },
42 static void exynos_gpio_irq_unmask(struct irq_data *irqd)
44 struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
45 struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
46 unsigned long reg_mask = d->ctrl->geint_mask + edata->eint_offset;
49 mask = readl(d->virt_base + reg_mask);
50 mask &= ~(1 << edata->pin);
51 writel(mask, d->virt_base + reg_mask);
54 static void exynos_gpio_irq_mask(struct irq_data *irqd)
56 struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
57 struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
58 unsigned long reg_mask = d->ctrl->geint_mask + edata->eint_offset;
61 mask = readl(d->virt_base + reg_mask);
62 mask |= 1 << edata->pin;
63 writel(mask, d->virt_base + reg_mask);
66 static void exynos_gpio_irq_ack(struct irq_data *irqd)
68 struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
69 struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
70 unsigned long reg_pend = d->ctrl->geint_pend + edata->eint_offset;
72 writel(1 << edata->pin, d->virt_base + reg_pend);
75 static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
77 struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
78 struct samsung_pin_ctrl *ctrl = d->ctrl;
79 struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
80 struct samsung_pin_bank *bank = edata->bank;
81 unsigned int shift = EXYNOS_EINT_CON_LEN * edata->pin;
82 unsigned int con, trig_type;
83 unsigned long reg_con = ctrl->geint_con + edata->eint_offset;
87 case IRQ_TYPE_EDGE_RISING:
88 trig_type = EXYNOS_EINT_EDGE_RISING;
90 case IRQ_TYPE_EDGE_FALLING:
91 trig_type = EXYNOS_EINT_EDGE_FALLING;
93 case IRQ_TYPE_EDGE_BOTH:
94 trig_type = EXYNOS_EINT_EDGE_BOTH;
96 case IRQ_TYPE_LEVEL_HIGH:
97 trig_type = EXYNOS_EINT_LEVEL_HIGH;
99 case IRQ_TYPE_LEVEL_LOW:
100 trig_type = EXYNOS_EINT_LEVEL_LOW;
103 pr_err("unsupported external interrupt type\n");
107 if (type & IRQ_TYPE_EDGE_BOTH)
108 __irq_set_handler_locked(irqd->irq, handle_edge_irq);
110 __irq_set_handler_locked(irqd->irq, handle_level_irq);
112 con = readl(d->virt_base + reg_con);
113 con &= ~(EXYNOS_EINT_CON_MASK << shift);
114 con |= trig_type << shift;
115 writel(con, d->virt_base + reg_con);
117 reg_con = bank->pctl_offset;
118 shift = edata->pin * bank->func_width;
119 mask = (1 << bank->func_width) - 1;
121 con = readl(d->virt_base + reg_con);
122 con &= ~(mask << shift);
123 con |= EXYNOS_EINT_FUNC << shift;
124 writel(con, d->virt_base + reg_con);
130 * irq_chip for gpio interrupts.
132 static struct irq_chip exynos_gpio_irq_chip = {
133 .name = "exynos_gpio_irq_chip",
134 .irq_unmask = exynos_gpio_irq_unmask,
135 .irq_mask = exynos_gpio_irq_mask,
136 .irq_ack = exynos_gpio_irq_ack,
137 .irq_set_type = exynos_gpio_irq_set_type,
141 * given a controller-local external gpio interrupt number, prepare the handler
144 static struct exynos_geint_data *exynos_get_eint_data(irq_hw_number_t hw,
145 struct samsung_pinctrl_drv_data *d)
147 struct samsung_pin_bank *bank = d->ctrl->pin_banks;
148 struct exynos_geint_data *eint_data;
149 unsigned int nr_banks = d->ctrl->nr_banks, idx;
150 unsigned int irq_base = 0, eint_offset = 0;
152 if (hw >= d->ctrl->nr_gint) {
153 dev_err(d->dev, "unsupported ext-gpio interrupt\n");
157 for (idx = 0; idx < nr_banks; idx++, bank++) {
158 if (bank->eint_type != EINT_TYPE_GPIO)
160 if ((hw >= irq_base) && (hw < (irq_base + bank->nr_pins)))
162 irq_base += bank->nr_pins;
166 if (idx == nr_banks) {
167 dev_err(d->dev, "pin bank not found for ext-gpio interrupt\n");
171 eint_data = devm_kzalloc(d->dev, sizeof(*eint_data), GFP_KERNEL);
173 dev_err(d->dev, "no memory for eint-gpio data\n");
177 eint_data->bank = bank;
178 eint_data->pin = hw - irq_base;
179 eint_data->eint_offset = eint_offset;
183 static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq,
186 struct samsung_pinctrl_drv_data *d = h->host_data;
187 struct exynos_geint_data *eint_data;
189 eint_data = exynos_get_eint_data(hw, d);
193 irq_set_handler_data(virq, eint_data);
194 irq_set_chip_data(virq, h->host_data);
195 irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip,
197 set_irq_flags(virq, IRQF_VALID);
201 static void exynos_gpio_irq_unmap(struct irq_domain *h, unsigned int virq)
203 struct samsung_pinctrl_drv_data *d = h->host_data;
204 struct exynos_geint_data *eint_data;
206 eint_data = irq_get_handler_data(virq);
207 devm_kfree(d->dev, eint_data);
211 * irq domain callbacks for external gpio interrupt controller.
213 static const struct irq_domain_ops exynos_gpio_irqd_ops = {
214 .map = exynos_gpio_irq_map,
215 .unmap = exynos_gpio_irq_unmap,
216 .xlate = irq_domain_xlate_twocell,
219 static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
221 struct samsung_pinctrl_drv_data *d = data;
222 struct samsung_pin_ctrl *ctrl = d->ctrl;
223 struct samsung_pin_bank *bank = ctrl->pin_banks;
224 unsigned int svc, group, pin, virq;
226 svc = readl(d->virt_base + ctrl->svc);
227 group = EXYNOS_SVC_GROUP(svc);
228 pin = svc & EXYNOS_SVC_NUM_MASK;
234 virq = irq_linear_revmap(d->gpio_irqd, bank->irq_base + pin);
237 generic_handle_irq(virq);
242 * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
243 * @d: driver data of samsung pinctrl driver.
245 static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
247 struct device *dev = d->dev;
251 dev_err(dev, "irq number not available\n");
255 ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq,
256 0, dev_name(dev), d);
258 dev_err(dev, "irq request failed\n");
262 d->gpio_irqd = irq_domain_add_linear(dev->of_node, d->ctrl->nr_gint,
263 &exynos_gpio_irqd_ops, d);
265 dev_err(dev, "gpio irq domain allocation failed\n");
272 static void exynos_wkup_irq_unmask(struct irq_data *irqd)
274 struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
275 unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
276 unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
277 unsigned long reg_mask = d->ctrl->weint_mask + (bank << 2);
280 mask = readl(d->virt_base + reg_mask);
282 writel(mask, d->virt_base + reg_mask);
285 static void exynos_wkup_irq_mask(struct irq_data *irqd)
287 struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
288 unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
289 unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
290 unsigned long reg_mask = d->ctrl->weint_mask + (bank << 2);
293 mask = readl(d->virt_base + reg_mask);
295 writel(mask, d->virt_base + reg_mask);
298 static void exynos_wkup_irq_ack(struct irq_data *irqd)
300 struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
301 unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
302 unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
303 unsigned long pend = d->ctrl->weint_pend + (bank << 2);
305 writel(1 << pin, d->virt_base + pend);
308 static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type)
310 struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
311 unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
312 unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
313 unsigned long reg_con = d->ctrl->weint_con + (bank << 2);
314 unsigned long shift = EXYNOS_EINT_CON_LEN * pin;
315 unsigned long con, trig_type;
318 case IRQ_TYPE_EDGE_RISING:
319 trig_type = EXYNOS_EINT_EDGE_RISING;
321 case IRQ_TYPE_EDGE_FALLING:
322 trig_type = EXYNOS_EINT_EDGE_FALLING;
324 case IRQ_TYPE_EDGE_BOTH:
325 trig_type = EXYNOS_EINT_EDGE_BOTH;
327 case IRQ_TYPE_LEVEL_HIGH:
328 trig_type = EXYNOS_EINT_LEVEL_HIGH;
330 case IRQ_TYPE_LEVEL_LOW:
331 trig_type = EXYNOS_EINT_LEVEL_LOW;
334 pr_err("unsupported external interrupt type\n");
338 if (type & IRQ_TYPE_EDGE_BOTH)
339 __irq_set_handler_locked(irqd->irq, handle_edge_irq);
341 __irq_set_handler_locked(irqd->irq, handle_level_irq);
343 con = readl(d->virt_base + reg_con);
344 con &= ~(EXYNOS_EINT_CON_MASK << shift);
345 con |= trig_type << shift;
346 writel(con, d->virt_base + reg_con);
351 * irq_chip for wakeup interrupts
353 static struct irq_chip exynos_wkup_irq_chip = {
354 .name = "exynos_wkup_irq_chip",
355 .irq_unmask = exynos_wkup_irq_unmask,
356 .irq_mask = exynos_wkup_irq_mask,
357 .irq_ack = exynos_wkup_irq_ack,
358 .irq_set_type = exynos_wkup_irq_set_type,
361 /* interrupt handler for wakeup interrupts 0..15 */
362 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
364 struct exynos_weint_data *eintd = irq_get_handler_data(irq);
365 struct irq_chip *chip = irq_get_chip(irq);
368 chained_irq_enter(chip, desc);
369 chip->irq_mask(&desc->irq_data);
372 chip->irq_ack(&desc->irq_data);
374 eint_irq = irq_linear_revmap(eintd->domain, eintd->irq);
375 generic_handle_irq(eint_irq);
376 chip->irq_unmask(&desc->irq_data);
377 chained_irq_exit(chip, desc);
380 static inline void exynos_irq_demux_eint(int irq_base, unsigned long pend,
381 struct irq_domain *domain)
387 generic_handle_irq(irq_find_mapping(domain, irq_base + irq));
392 /* interrupt handler for wakeup interrupt 16 */
393 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
395 struct irq_chip *chip = irq_get_chip(irq);
396 struct exynos_weint_data *eintd = irq_get_handler_data(irq);
397 struct samsung_pinctrl_drv_data *d = eintd->domain->host_data;
401 chained_irq_enter(chip, desc);
402 pend = readl(d->virt_base + d->ctrl->weint_pend + 0x8);
403 mask = readl(d->virt_base + d->ctrl->weint_mask + 0x8);
404 exynos_irq_demux_eint(16, pend & ~mask, eintd->domain);
405 pend = readl(d->virt_base + d->ctrl->weint_pend + 0xC);
406 mask = readl(d->virt_base + d->ctrl->weint_mask + 0xC);
407 exynos_irq_demux_eint(24, pend & ~mask, eintd->domain);
408 chained_irq_exit(chip, desc);
411 static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
414 irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip, handle_level_irq);
415 irq_set_chip_data(virq, h->host_data);
416 set_irq_flags(virq, IRQF_VALID);
421 * irq domain callbacks for external wakeup interrupt controller.
423 static const struct irq_domain_ops exynos_wkup_irqd_ops = {
424 .map = exynos_wkup_irq_map,
425 .xlate = irq_domain_xlate_twocell,
429 * exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
430 * @d: driver data of samsung pinctrl driver.
432 static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
434 struct device *dev = d->dev;
435 struct device_node *wkup_np = NULL;
436 struct device_node *np;
437 struct exynos_weint_data *weint_data;
440 for_each_child_of_node(dev->of_node, np) {
441 if (of_match_node(exynos_wkup_irq_ids, np)) {
449 d->wkup_irqd = irq_domain_add_linear(wkup_np, d->ctrl->nr_wint,
450 &exynos_wkup_irqd_ops, d);
452 dev_err(dev, "wakeup irq domain allocation failed\n");
456 weint_data = devm_kzalloc(dev, sizeof(*weint_data) * 17, GFP_KERNEL);
458 dev_err(dev, "could not allocate memory for weint_data\n");
462 irq = irq_of_parse_and_map(wkup_np, 16);
464 weint_data[16].domain = d->wkup_irqd;
465 irq_set_chained_handler(irq, exynos_irq_demux_eint16_31);
466 irq_set_handler_data(irq, &weint_data[16]);
468 dev_err(dev, "irq number for EINT16-32 not found\n");
471 for (idx = 0; idx < 16; idx++) {
472 weint_data[idx].domain = d->wkup_irqd;
473 weint_data[idx].irq = idx;
475 irq = irq_of_parse_and_map(wkup_np, idx);
477 irq_set_handler_data(irq, &weint_data[idx]);
478 irq_set_chained_handler(irq, exynos_irq_eint0_15);
480 dev_err(dev, "irq number for eint-%x not found\n", idx);
486 /* pin banks of exynos4210 pin-controller 0 */
487 static struct samsung_pin_bank exynos4210_pin_banks0[] = {
488 EXYNOS_PIN_BANK_EINTG(0x000, EXYNOS4210_GPIO_A0, "gpa0"),
489 EXYNOS_PIN_BANK_EINTG(0x020, EXYNOS4210_GPIO_A1, "gpa1"),
490 EXYNOS_PIN_BANK_EINTG(0x040, EXYNOS4210_GPIO_B, "gpb"),
491 EXYNOS_PIN_BANK_EINTG(0x060, EXYNOS4210_GPIO_C0, "gpc0"),
492 EXYNOS_PIN_BANK_EINTG(0x080, EXYNOS4210_GPIO_C1, "gpc1"),
493 EXYNOS_PIN_BANK_EINTG(0x0A0, EXYNOS4210_GPIO_D0, "gpd0"),
494 EXYNOS_PIN_BANK_EINTG(0x0C0, EXYNOS4210_GPIO_D1, "gpd1"),
495 EXYNOS_PIN_BANK_EINTG(0x0E0, EXYNOS4210_GPIO_E0, "gpe0"),
496 EXYNOS_PIN_BANK_EINTG(0x100, EXYNOS4210_GPIO_E1, "gpe1"),
497 EXYNOS_PIN_BANK_EINTG(0x120, EXYNOS4210_GPIO_E2, "gpe2"),
498 EXYNOS_PIN_BANK_EINTG(0x140, EXYNOS4210_GPIO_E3, "gpe3"),
499 EXYNOS_PIN_BANK_EINTG(0x160, EXYNOS4210_GPIO_E4, "gpe4"),
500 EXYNOS_PIN_BANK_EINTG(0x180, EXYNOS4210_GPIO_F0, "gpf0"),
501 EXYNOS_PIN_BANK_EINTG(0x1A0, EXYNOS4210_GPIO_F1, "gpf1"),
502 EXYNOS_PIN_BANK_EINTG(0x1C0, EXYNOS4210_GPIO_F2, "gpf2"),
503 EXYNOS_PIN_BANK_EINTG(0x1E0, EXYNOS4210_GPIO_F3, "gpf3"),
506 /* pin banks of exynos4210 pin-controller 1 */
507 static struct samsung_pin_bank exynos4210_pin_banks1[] = {
508 EXYNOS_PIN_BANK_EINTG(0x000, EXYNOS4210_GPIO_J0, "gpj0"),
509 EXYNOS_PIN_BANK_EINTG(0x020, EXYNOS4210_GPIO_J1, "gpj1"),
510 EXYNOS_PIN_BANK_EINTG(0x040, EXYNOS4210_GPIO_K0, "gpk0"),
511 EXYNOS_PIN_BANK_EINTG(0x060, EXYNOS4210_GPIO_K1, "gpk1"),
512 EXYNOS_PIN_BANK_EINTG(0x080, EXYNOS4210_GPIO_K2, "gpk2"),
513 EXYNOS_PIN_BANK_EINTG(0x0A0, EXYNOS4210_GPIO_K3, "gpk3"),
514 EXYNOS_PIN_BANK_EINTG(0x0C0, EXYNOS4210_GPIO_L0, "gpl0"),
515 EXYNOS_PIN_BANK_EINTG(0x0E0, EXYNOS4210_GPIO_L1, "gpl1"),
516 EXYNOS_PIN_BANK_EINTG(0x100, EXYNOS4210_GPIO_L2, "gpl2"),
517 EXYNOS_PIN_BANK_EINTN(0x120, EXYNOS4210_GPIO_Y0, "gpy0"),
518 EXYNOS_PIN_BANK_EINTN(0x140, EXYNOS4210_GPIO_Y1, "gpy1"),
519 EXYNOS_PIN_BANK_EINTN(0x160, EXYNOS4210_GPIO_Y2, "gpy2"),
520 EXYNOS_PIN_BANK_EINTN(0x180, EXYNOS4210_GPIO_Y3, "gpy3"),
521 EXYNOS_PIN_BANK_EINTN(0x1A0, EXYNOS4210_GPIO_Y4, "gpy4"),
522 EXYNOS_PIN_BANK_EINTN(0x1C0, EXYNOS4210_GPIO_Y5, "gpy5"),
523 EXYNOS_PIN_BANK_EINTN(0x1E0, EXYNOS4210_GPIO_Y6, "gpy6"),
524 EXYNOS_PIN_BANK_EINTN(0xC00, EXYNOS4210_GPIO_X0, "gpx0"),
525 EXYNOS_PIN_BANK_EINTN(0xC20, EXYNOS4210_GPIO_X1, "gpx1"),
526 EXYNOS_PIN_BANK_EINTN(0xC40, EXYNOS4210_GPIO_X2, "gpx2"),
527 EXYNOS_PIN_BANK_EINTN(0xC60, EXYNOS4210_GPIO_X3, "gpx3"),
530 /* pin banks of exynos4210 pin-controller 2 */
531 static struct samsung_pin_bank exynos4210_pin_banks2[] = {
532 EXYNOS_PIN_BANK_EINTN(0x000, EXYNOS4210_GPIO_Z, "gpz"),
536 * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
537 * three gpio/pin-mux/pinconfig controllers.
539 struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
541 /* pin-controller instance 0 data */
542 .pin_banks = exynos4210_pin_banks0,
543 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0),
544 .base = EXYNOS4210_GPIO_A0_START,
545 .nr_pins = EXYNOS4210_GPIOA_NR_PINS,
546 .nr_gint = EXYNOS4210_GPIOA_NR_GINT,
547 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
548 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
549 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
550 .svc = EXYNOS_SVC_OFFSET,
551 .eint_gpio_init = exynos_eint_gpio_init,
552 .label = "exynos4210-gpio-ctrl0",
554 /* pin-controller instance 1 data */
555 .pin_banks = exynos4210_pin_banks1,
556 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1),
557 .base = EXYNOS4210_GPIOA_NR_PINS,
558 .nr_pins = EXYNOS4210_GPIOB_NR_PINS,
559 .nr_gint = EXYNOS4210_GPIOB_NR_GINT,
561 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
562 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
563 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
564 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
565 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
566 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
567 .svc = EXYNOS_SVC_OFFSET,
568 .eint_gpio_init = exynos_eint_gpio_init,
569 .eint_wkup_init = exynos_eint_wkup_init,
570 .label = "exynos4210-gpio-ctrl1",
572 /* pin-controller instance 2 data */
573 .pin_banks = exynos4210_pin_banks2,
574 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2),
575 .base = EXYNOS4210_GPIOA_NR_PINS +
576 EXYNOS4210_GPIOB_NR_PINS,
577 .nr_pins = EXYNOS4210_GPIOC_NR_PINS,
578 .label = "exynos4210-gpio-ctrl2",