1 // SPDX-License-Identifier: GPL-2.0-only
3 * CY8C95X0 20/40/60 pin I2C GPIO port expander with interrupt support
5 * Copyright (C) 2022 9elements GmbH
6 * Authors: Patrick Rudolph <patrick.rudolph@9elements.com>
7 * Naresh Solanki <Naresh.Solanki@9elements.com>
10 #include <linux/acpi.h>
11 #include <linux/bitmap.h>
12 #include <linux/dmi.h>
13 #include <linux/gpio/driver.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/i2c.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/mod_devicetable.h>
19 #include <linux/module.h>
20 #include <linux/property.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/seq_file.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/pinctrl/pinconf.h>
27 #include <linux/pinctrl/pinconf-generic.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
31 /* Fast access registers */
32 #define CY8C95X0_INPUT 0x00
33 #define CY8C95X0_OUTPUT 0x08
34 #define CY8C95X0_INTSTATUS 0x10
36 #define CY8C95X0_INPUT_(x) (CY8C95X0_INPUT + (x))
37 #define CY8C95X0_OUTPUT_(x) (CY8C95X0_OUTPUT + (x))
38 #define CY8C95X0_INTSTATUS_(x) (CY8C95X0_INTSTATUS + (x))
40 /* Port Select configures the port */
41 #define CY8C95X0_PORTSEL 0x18
42 /* Port settings, write PORTSEL first */
43 #define CY8C95X0_INTMASK 0x19
44 #define CY8C95X0_PWMSEL 0x1A
45 #define CY8C95X0_INVERT 0x1B
46 #define CY8C95X0_DIRECTION 0x1C
47 /* Drive mode register change state on writing '1' */
48 #define CY8C95X0_DRV_PU 0x1D
49 #define CY8C95X0_DRV_PD 0x1E
50 #define CY8C95X0_DRV_ODH 0x1F
51 #define CY8C95X0_DRV_ODL 0x20
52 #define CY8C95X0_DRV_PP_FAST 0x21
53 #define CY8C95X0_DRV_PP_SLOW 0x22
54 #define CY8C95X0_DRV_HIZ 0x23
55 #define CY8C95X0_DEVID 0x2E
56 #define CY8C95X0_WATCHDOG 0x2F
57 #define CY8C95X0_COMMAND 0x30
59 #define CY8C95X0_PIN_TO_OFFSET(x) (((x) >= 20) ? ((x) + 4) : (x))
61 #define CY8C95X0_MUX_REGMAP_TO_PORT(x) ((x) / MUXED_STRIDE)
62 #define CY8C95X0_MUX_REGMAP_TO_REG(x) (((x) % MUXED_STRIDE) + CY8C95X0_INTMASK)
63 #define CY8C95X0_MUX_REGMAP_TO_OFFSET(x, p) ((x) - CY8C95X0_INTMASK + (p) * MUXED_STRIDE)
65 static const struct i2c_device_id cy8c95x0_id[] = {
71 MODULE_DEVICE_TABLE(i2c, cy8c95x0_id);
73 #define OF_CY8C95X(__nrgpio) ((void *)(__nrgpio))
75 static const struct of_device_id cy8c95x0_dt_ids[] = {
76 { .compatible = "cypress,cy8c9520", .data = OF_CY8C95X(20), },
77 { .compatible = "cypress,cy8c9540", .data = OF_CY8C95X(40), },
78 { .compatible = "cypress,cy8c9560", .data = OF_CY8C95X(60), },
81 MODULE_DEVICE_TABLE(of, cy8c95x0_dt_ids);
83 static const struct acpi_gpio_params cy8c95x0_irq_gpios = { 0, 0, true };
85 static const struct acpi_gpio_mapping cy8c95x0_acpi_irq_gpios[] = {
86 { "irq-gpios", &cy8c95x0_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
90 static int cy8c95x0_acpi_get_irq(struct device *dev)
94 ret = devm_acpi_dev_add_driver_gpios(dev, cy8c95x0_acpi_irq_gpios);
96 dev_warn(dev, "can't add GPIO ACPI mapping\n");
98 ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq-gpios", 0);
102 dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret);
106 static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = {
109 * On Intel Galileo Gen 1 board the IRQ pin is provided
110 * as an absolute number instead of being relative.
111 * Since first controller (gpio-sch.c) and second
112 * (gpio-dwapb.c) are at the fixed bases, we may safely
113 * refer to the number in the global space to get an IRQ
117 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
125 #define MAX_LINE (MAX_BANK * BANK_SZ)
126 #define MUXED_STRIDE 16
127 #define CY8C95X0_GPIO_MASK GENMASK(7, 0)
130 * struct cy8c95x0_pinctrl - driver data
131 * @regmap: Device's regmap. Only direct access registers.
132 * @muxed_regmap: Regmap for all muxed registers.
133 * @irq_lock: IRQ bus lock
134 * @i2c_lock: Mutex for the device internal mux register
135 * @irq_mask: I/O bits affected by interrupts
136 * @irq_trig_raise: I/O bits affected by raising voltage level
137 * @irq_trig_fall: I/O bits affected by falling voltage level
138 * @irq_trig_low: I/O bits affected by a low voltage level
139 * @irq_trig_high: I/O bits affected by a high voltage level
140 * @push_pull: I/O bits configured as push pull driver
141 * @shiftmask: Mask used to compensate for Gport2 width
142 * @nport: Number of Gports in this chip
143 * @gpio_chip: gpiolib chip
144 * @driver_data: private driver data
145 * @regulator: Pointer to the regulator for the IC
146 * @dev: struct device
147 * @pctldev: pin controller device
148 * @pinctrl_desc: pin controller description
149 * @name: Chip controller name
150 * @tpin: Total number of pins
151 * @gpio_reset: GPIO line handler that can reset the IC
153 struct cy8c95x0_pinctrl {
154 struct regmap *regmap;
155 struct regmap *muxed_regmap;
156 struct mutex irq_lock;
157 struct mutex i2c_lock;
158 DECLARE_BITMAP(irq_mask, MAX_LINE);
159 DECLARE_BITMAP(irq_trig_raise, MAX_LINE);
160 DECLARE_BITMAP(irq_trig_fall, MAX_LINE);
161 DECLARE_BITMAP(irq_trig_low, MAX_LINE);
162 DECLARE_BITMAP(irq_trig_high, MAX_LINE);
163 DECLARE_BITMAP(push_pull, MAX_LINE);
164 DECLARE_BITMAP(shiftmask, MAX_LINE);
166 struct gpio_chip gpio_chip;
167 unsigned long driver_data;
168 struct regulator *regulator;
170 struct pinctrl_dev *pctldev;
171 struct pinctrl_desc pinctrl_desc;
174 struct gpio_desc *gpio_reset;
177 static const struct pinctrl_pin_desc cy8c9560_pins[] = {
178 PINCTRL_PIN(0, "gp00"),
179 PINCTRL_PIN(1, "gp01"),
180 PINCTRL_PIN(2, "gp02"),
181 PINCTRL_PIN(3, "gp03"),
182 PINCTRL_PIN(4, "gp04"),
183 PINCTRL_PIN(5, "gp05"),
184 PINCTRL_PIN(6, "gp06"),
185 PINCTRL_PIN(7, "gp07"),
187 PINCTRL_PIN(8, "gp10"),
188 PINCTRL_PIN(9, "gp11"),
189 PINCTRL_PIN(10, "gp12"),
190 PINCTRL_PIN(11, "gp13"),
191 PINCTRL_PIN(12, "gp14"),
192 PINCTRL_PIN(13, "gp15"),
193 PINCTRL_PIN(14, "gp16"),
194 PINCTRL_PIN(15, "gp17"),
196 PINCTRL_PIN(16, "gp20"),
197 PINCTRL_PIN(17, "gp21"),
198 PINCTRL_PIN(18, "gp22"),
199 PINCTRL_PIN(19, "gp23"),
201 PINCTRL_PIN(20, "gp30"),
202 PINCTRL_PIN(21, "gp31"),
203 PINCTRL_PIN(22, "gp32"),
204 PINCTRL_PIN(23, "gp33"),
205 PINCTRL_PIN(24, "gp34"),
206 PINCTRL_PIN(25, "gp35"),
207 PINCTRL_PIN(26, "gp36"),
208 PINCTRL_PIN(27, "gp37"),
210 PINCTRL_PIN(28, "gp40"),
211 PINCTRL_PIN(29, "gp41"),
212 PINCTRL_PIN(30, "gp42"),
213 PINCTRL_PIN(31, "gp43"),
214 PINCTRL_PIN(32, "gp44"),
215 PINCTRL_PIN(33, "gp45"),
216 PINCTRL_PIN(34, "gp46"),
217 PINCTRL_PIN(35, "gp47"),
219 PINCTRL_PIN(36, "gp50"),
220 PINCTRL_PIN(37, "gp51"),
221 PINCTRL_PIN(38, "gp52"),
222 PINCTRL_PIN(39, "gp53"),
223 PINCTRL_PIN(40, "gp54"),
224 PINCTRL_PIN(41, "gp55"),
225 PINCTRL_PIN(42, "gp56"),
226 PINCTRL_PIN(43, "gp57"),
228 PINCTRL_PIN(44, "gp60"),
229 PINCTRL_PIN(45, "gp61"),
230 PINCTRL_PIN(46, "gp62"),
231 PINCTRL_PIN(47, "gp63"),
232 PINCTRL_PIN(48, "gp64"),
233 PINCTRL_PIN(49, "gp65"),
234 PINCTRL_PIN(50, "gp66"),
235 PINCTRL_PIN(51, "gp67"),
237 PINCTRL_PIN(52, "gp70"),
238 PINCTRL_PIN(53, "gp71"),
239 PINCTRL_PIN(54, "gp72"),
240 PINCTRL_PIN(55, "gp73"),
241 PINCTRL_PIN(56, "gp74"),
242 PINCTRL_PIN(57, "gp75"),
243 PINCTRL_PIN(58, "gp76"),
244 PINCTRL_PIN(59, "gp77"),
247 static const char * const cy8c95x0_groups[] = {
317 static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip,
318 unsigned int pin, bool input);
320 static inline u8 cypress_get_port(struct cy8c95x0_pinctrl *chip, unsigned int pin)
322 /* Account for GPORT2 which only has 4 bits */
323 return CY8C95X0_PIN_TO_OFFSET(pin) / BANK_SZ;
326 static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin)
328 /* Account for GPORT2 which only has 4 bits */
329 return BIT(CY8C95X0_PIN_TO_OFFSET(pin) % BANK_SZ);
332 static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg)
342 static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg)
345 case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
356 static bool cy8c95x0_volatile_register(struct device *dev, unsigned int reg)
359 case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
360 case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
361 case CY8C95X0_INTMASK:
362 case CY8C95X0_INVERT:
363 case CY8C95X0_PWMSEL:
364 case CY8C95X0_DIRECTION:
365 case CY8C95X0_DRV_PU:
366 case CY8C95X0_DRV_PD:
367 case CY8C95X0_DRV_ODH:
368 case CY8C95X0_DRV_ODL:
369 case CY8C95X0_DRV_PP_FAST:
370 case CY8C95X0_DRV_PP_SLOW:
371 case CY8C95X0_DRV_HIZ:
378 static bool cy8c95x0_precious_register(struct device *dev, unsigned int reg)
381 case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
388 static bool cy8c95x0_muxed_register(unsigned int reg)
391 case CY8C95X0_INTMASK:
392 case CY8C95X0_PWMSEL:
393 case CY8C95X0_INVERT:
394 case CY8C95X0_DIRECTION:
395 case CY8C95X0_DRV_PU:
396 case CY8C95X0_DRV_PD:
397 case CY8C95X0_DRV_ODH:
398 case CY8C95X0_DRV_ODL:
399 case CY8C95X0_DRV_PP_FAST:
400 case CY8C95X0_DRV_PP_SLOW:
401 case CY8C95X0_DRV_HIZ:
408 static bool cy8c95x0_wc_register(unsigned int reg)
411 case CY8C95X0_DRV_PU:
412 case CY8C95X0_DRV_PD:
413 case CY8C95X0_DRV_ODH:
414 case CY8C95X0_DRV_ODL:
415 case CY8C95X0_DRV_PP_FAST:
416 case CY8C95X0_DRV_PP_SLOW:
417 case CY8C95X0_DRV_HIZ:
424 static bool cy8c95x0_quick_path_register(unsigned int reg)
427 case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
428 case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
429 case CY8C95X0_OUTPUT_(0) ... CY8C95X0_OUTPUT_(7):
436 static const struct reg_default cy8c95x0_reg_defaults[] = {
437 { CY8C95X0_OUTPUT_(0), GENMASK(7, 0) },
438 { CY8C95X0_OUTPUT_(1), GENMASK(7, 0) },
439 { CY8C95X0_OUTPUT_(2), GENMASK(7, 0) },
440 { CY8C95X0_OUTPUT_(3), GENMASK(7, 0) },
441 { CY8C95X0_OUTPUT_(4), GENMASK(7, 0) },
442 { CY8C95X0_OUTPUT_(5), GENMASK(7, 0) },
443 { CY8C95X0_OUTPUT_(6), GENMASK(7, 0) },
444 { CY8C95X0_OUTPUT_(7), GENMASK(7, 0) },
445 { CY8C95X0_PORTSEL, 0 },
446 { CY8C95X0_PWMSEL, 0 },
450 cy8c95x0_mux_reg_read(void *context, unsigned int off, unsigned int *val)
452 struct cy8c95x0_pinctrl *chip = context;
453 u8 port = CY8C95X0_MUX_REGMAP_TO_PORT(off);
454 int ret, reg = CY8C95X0_MUX_REGMAP_TO_REG(off);
456 mutex_lock(&chip->i2c_lock);
457 /* Select the correct bank */
458 ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
463 * Read the register through direct access regmap. The target range
464 * is marked volatile.
466 ret = regmap_read(chip->regmap, reg, val);
468 mutex_unlock(&chip->i2c_lock);
474 cy8c95x0_mux_reg_write(void *context, unsigned int off, unsigned int val)
476 struct cy8c95x0_pinctrl *chip = context;
477 u8 port = CY8C95X0_MUX_REGMAP_TO_PORT(off);
478 int ret, reg = CY8C95X0_MUX_REGMAP_TO_REG(off);
480 mutex_lock(&chip->i2c_lock);
481 /* Select the correct bank */
482 ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
487 * Write the register through direct access regmap. The target range
488 * is marked volatile.
490 ret = regmap_write(chip->regmap, reg, val);
492 mutex_unlock(&chip->i2c_lock);
497 static bool cy8c95x0_mux_accessible_register(struct device *dev, unsigned int off)
499 struct i2c_client *i2c = to_i2c_client(dev);
500 struct cy8c95x0_pinctrl *chip = i2c_get_clientdata(i2c);
501 u8 port = CY8C95X0_MUX_REGMAP_TO_PORT(off);
502 u8 reg = CY8C95X0_MUX_REGMAP_TO_REG(off);
504 if (port >= chip->nport)
507 return cy8c95x0_muxed_register(reg);
510 static struct regmap_bus cy8c95x0_regmap_bus = {
511 .reg_read = cy8c95x0_mux_reg_read,
512 .reg_write = cy8c95x0_mux_reg_write,
515 /* Regmap for muxed registers CY8C95X0_INTMASK - CY8C95X0_DRV_HIZ */
516 static const struct regmap_config cy8c95x0_muxed_regmap = {
520 .cache_type = REGCACHE_FLAT,
521 .use_single_read = true,
522 .use_single_write = true,
523 .max_register = MUXED_STRIDE * BANK_SZ,
524 .num_reg_defaults_raw = MUXED_STRIDE * BANK_SZ,
525 .readable_reg = cy8c95x0_mux_accessible_register,
526 .writeable_reg = cy8c95x0_mux_accessible_register,
529 /* Direct access regmap */
530 static const struct regmap_config cy8c95x0_i2c_regmap = {
535 .reg_defaults = cy8c95x0_reg_defaults,
536 .num_reg_defaults = ARRAY_SIZE(cy8c95x0_reg_defaults),
538 .readable_reg = cy8c95x0_readable_register,
539 .writeable_reg = cy8c95x0_writeable_register,
540 .volatile_reg = cy8c95x0_volatile_register,
541 .precious_reg = cy8c95x0_precious_register,
543 .cache_type = REGCACHE_FLAT,
544 .max_register = CY8C95X0_COMMAND,
547 static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip,
552 bool *change, bool async,
555 struct regmap *regmap;
556 int ret, off, i, read_val;
558 /* Caller should never modify PORTSEL directly */
559 if (reg == CY8C95X0_PORTSEL)
562 /* Registers behind the PORTSEL mux have their own regmap */
563 if (cy8c95x0_muxed_register(reg)) {
564 regmap = chip->muxed_regmap;
565 off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port);
567 regmap = chip->regmap;
568 /* Quick path direct access registers honor the port argument */
569 if (cy8c95x0_quick_path_register(reg))
575 ret = regmap_update_bits_base(regmap, off, mask, val, change, async, force);
579 /* Update the cache when a WC bit is written */
580 if (cy8c95x0_wc_register(reg) && (mask & val)) {
581 for (i = CY8C95X0_DRV_PU; i <= CY8C95X0_DRV_HIZ; i++) {
584 off = CY8C95X0_MUX_REGMAP_TO_OFFSET(i, port);
586 ret = regmap_read(regmap, off, &read_val);
590 if (!(read_val & mask & val))
593 regcache_cache_only(regmap, true);
594 regmap_update_bits(regmap, off, mask & val, 0);
595 regcache_cache_only(regmap, false);
603 * cy8c95x0_regmap_write_bits() - writes a register using the regmap cache
604 * @chip: The pinctrl to work on
605 * @reg: The register to write to. Can be direct access or muxed register.
606 * MUST NOT be the PORTSEL register.
607 * @port: The port to be used for muxed registers or quick path direct access
608 * registers. Otherwise unused.
609 * @mask: Bitmask to change
610 * @val: New value for bitmask
612 * This function handles the register writes to the direct access registers and
613 * the muxed registers while caching all register accesses, internally handling
614 * the correct state of the PORTSEL register and protecting the access to muxed
616 * The caller must only use this function to change registers behind the PORTSEL mux.
618 * Return: 0 for successful request, else a corresponding error value
620 static int cy8c95x0_regmap_write_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg,
621 unsigned int port, unsigned int mask, unsigned int val)
623 return cy8c95x0_regmap_update_bits_base(chip, reg, port, mask, val, NULL, false, true);
627 * cy8c95x0_regmap_update_bits() - updates a register using the regmap cache
628 * @chip: The pinctrl to work on
629 * @reg: The register to write to. Can be direct access or muxed register.
630 * MUST NOT be the PORTSEL register.
631 * @port: The port to be used for muxed registers or quick path direct access
632 * registers. Otherwise unused.
633 * @mask: Bitmask to change
634 * @val: New value for bitmask
636 * This function handles the register updates to the direct access registers and
637 * the muxed registers while caching all register accesses, internally handling
638 * the correct state of the PORTSEL register and protecting the access to muxed
640 * The caller must only use this function to change registers behind the PORTSEL mux.
642 * Return: 0 for successful request, else a corresponding error value
644 static int cy8c95x0_regmap_update_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg,
645 unsigned int port, unsigned int mask, unsigned int val)
647 return cy8c95x0_regmap_update_bits_base(chip, reg, port, mask, val, NULL, false, false);
651 * cy8c95x0_regmap_read() - reads a register using the regmap cache
652 * @chip: The pinctrl to work on
653 * @reg: The register to read from. Can be direct access or muxed register.
654 * @port: The port to be used for muxed registers or quick path direct access
655 * registers. Otherwise unused.
656 * @read_val: Value read from hardware or cache
658 * This function handles the register reads from the direct access registers and
659 * the muxed registers while caching all register accesses, internally handling
660 * the correct state of the PORTSEL register and protecting the access to muxed
662 * The caller must only use this function to read registers behind the PORTSEL mux.
664 * Return: 0 for successful request, else a corresponding error value
666 static int cy8c95x0_regmap_read(struct cy8c95x0_pinctrl *chip, unsigned int reg,
667 unsigned int port, unsigned int *read_val)
669 struct regmap *regmap;
672 /* Registers behind the PORTSEL mux have their own regmap */
673 if (cy8c95x0_muxed_register(reg)) {
674 regmap = chip->muxed_regmap;
675 off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port);
677 regmap = chip->regmap;
678 /* Quick path direct access registers honor the port argument */
679 if (cy8c95x0_quick_path_register(reg))
685 return regmap_read(regmap, off, read_val);
688 static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
689 unsigned long *val, unsigned long *mask)
691 DECLARE_BITMAP(tmask, MAX_LINE);
692 DECLARE_BITMAP(tval, MAX_LINE);
698 /* Add the 4 bit gap of Gport2 */
699 bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE);
700 bitmap_shift_left(tmask, tmask, 4, MAX_LINE);
701 bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3);
703 bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE);
704 bitmap_shift_left(tval, tval, 4, MAX_LINE);
705 bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);
707 for (i = 0; i < chip->nport; i++) {
708 /* Skip over unused banks */
709 bits = bitmap_get_value8(tmask, i * BANK_SZ);
713 write_val = bitmap_get_value8(tval, i * BANK_SZ);
715 ret = cy8c95x0_regmap_update_bits(chip, reg, i, bits, write_val);
722 dev_err(chip->dev, "failed writing register %d, port %d: err %d\n", reg, i, ret);
727 static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
728 unsigned long *val, unsigned long *mask)
730 DECLARE_BITMAP(tmask, MAX_LINE);
731 DECLARE_BITMAP(tval, MAX_LINE);
732 DECLARE_BITMAP(tmp, MAX_LINE);
738 /* Add the 4 bit gap of Gport2 */
739 bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE);
740 bitmap_shift_left(tmask, tmask, 4, MAX_LINE);
741 bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3);
743 bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE);
744 bitmap_shift_left(tval, tval, 4, MAX_LINE);
745 bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);
747 for (i = 0; i < chip->nport; i++) {
748 /* Skip over unused banks */
749 bits = bitmap_get_value8(tmask, i * BANK_SZ);
753 ret = cy8c95x0_regmap_read(chip, reg, i, &read_val);
758 read_val |= bitmap_get_value8(tval, i * BANK_SZ) & ~bits;
759 bitmap_set_value8(tval, read_val, i * BANK_SZ);
762 /* Fill the 4 bit gap of Gport2 */
763 bitmap_shift_right(tmp, tval, 4, MAX_LINE);
764 bitmap_replace(val, tmp, tval, chip->shiftmask, MAX_LINE);
768 dev_err(chip->dev, "failed reading register %d, port %d: err %d\n", reg, i, ret);
773 static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off)
775 return pinctrl_gpio_direction_input(gc, off);
778 static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc,
779 unsigned int off, int val)
781 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
782 u8 port = cypress_get_port(chip, off);
783 u8 bit = cypress_get_pin_mask(chip, off);
786 /* Set output level */
787 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, val ? bit : 0);
791 return pinctrl_gpio_direction_output(gc, off);
794 static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off)
796 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
797 u8 port = cypress_get_port(chip, off);
798 u8 bit = cypress_get_pin_mask(chip, off);
802 ret = cy8c95x0_regmap_read(chip, CY8C95X0_INPUT, port, ®_val);
806 * Diagnostic already emitted; that's all we should
807 * do unless gpio_*_value_cansleep() calls become different
808 * from their nonsleeping siblings (and report faults).
813 return !!(reg_val & bit);
816 static void cy8c95x0_gpio_set_value(struct gpio_chip *gc, unsigned int off,
819 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
820 u8 port = cypress_get_port(chip, off);
821 u8 bit = cypress_get_pin_mask(chip, off);
823 cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, val ? bit : 0);
826 static int cy8c95x0_gpio_get_direction(struct gpio_chip *gc, unsigned int off)
828 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
829 u8 port = cypress_get_port(chip, off);
830 u8 bit = cypress_get_pin_mask(chip, off);
834 ret = cy8c95x0_regmap_read(chip, CY8C95X0_DIRECTION, port, ®_val);
839 return GPIO_LINE_DIRECTION_IN;
841 return GPIO_LINE_DIRECTION_OUT;
846 static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip,
848 unsigned long *config)
850 enum pin_config_param param = pinconf_to_config_param(*config);
851 u8 port = cypress_get_port(chip, off);
852 u8 bit = cypress_get_pin_mask(chip, off);
859 case PIN_CONFIG_BIAS_PULL_UP:
860 reg = CY8C95X0_DRV_PU;
862 case PIN_CONFIG_BIAS_PULL_DOWN:
863 reg = CY8C95X0_DRV_PD;
865 case PIN_CONFIG_BIAS_DISABLE:
866 reg = CY8C95X0_DRV_HIZ;
868 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
869 reg = CY8C95X0_DRV_ODL;
871 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
872 reg = CY8C95X0_DRV_ODH;
874 case PIN_CONFIG_DRIVE_PUSH_PULL:
875 reg = CY8C95X0_DRV_PP_FAST;
877 case PIN_CONFIG_INPUT_ENABLE:
878 reg = CY8C95X0_DIRECTION;
880 case PIN_CONFIG_MODE_PWM:
881 reg = CY8C95X0_PWMSEL;
883 case PIN_CONFIG_OUTPUT:
884 reg = CY8C95X0_OUTPUT;
886 case PIN_CONFIG_OUTPUT_ENABLE:
887 reg = CY8C95X0_DIRECTION;
890 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
891 case PIN_CONFIG_BIAS_BUS_HOLD:
892 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
893 case PIN_CONFIG_DRIVE_STRENGTH:
894 case PIN_CONFIG_DRIVE_STRENGTH_UA:
895 case PIN_CONFIG_INPUT_DEBOUNCE:
896 case PIN_CONFIG_INPUT_SCHMITT:
897 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
898 case PIN_CONFIG_MODE_LOW_POWER:
899 case PIN_CONFIG_PERSIST_STATE:
900 case PIN_CONFIG_POWER_SOURCE:
901 case PIN_CONFIG_SKEW_DELAY:
902 case PIN_CONFIG_SLEEP_HARDWARE_STATE:
903 case PIN_CONFIG_SLEW_RATE:
909 * Writing 1 to one of the drive mode registers will automatically
910 * clear conflicting set bits in the other drive mode registers.
912 ret = cy8c95x0_regmap_read(chip, reg, port, ®_val);
918 if (param == PIN_CONFIG_OUTPUT_ENABLE)
921 *config = pinconf_to_config_packed(param, (u16)arg);
926 static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip,
928 unsigned long config)
930 u8 port = cypress_get_port(chip, off);
931 u8 bit = cypress_get_pin_mask(chip, off);
932 unsigned long param = pinconf_to_config_param(config);
933 unsigned long arg = pinconf_to_config_argument(config);
938 case PIN_CONFIG_BIAS_PULL_UP:
939 __clear_bit(off, chip->push_pull);
940 reg = CY8C95X0_DRV_PU;
942 case PIN_CONFIG_BIAS_PULL_DOWN:
943 __clear_bit(off, chip->push_pull);
944 reg = CY8C95X0_DRV_PD;
946 case PIN_CONFIG_BIAS_DISABLE:
947 __clear_bit(off, chip->push_pull);
948 reg = CY8C95X0_DRV_HIZ;
950 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
951 __clear_bit(off, chip->push_pull);
952 reg = CY8C95X0_DRV_ODL;
954 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
955 __clear_bit(off, chip->push_pull);
956 reg = CY8C95X0_DRV_ODH;
958 case PIN_CONFIG_DRIVE_PUSH_PULL:
959 __set_bit(off, chip->push_pull);
960 reg = CY8C95X0_DRV_PP_FAST;
962 case PIN_CONFIG_MODE_PWM:
963 reg = CY8C95X0_PWMSEL;
965 case PIN_CONFIG_OUTPUT_ENABLE:
966 ret = cy8c95x0_pinmux_direction(chip, off, !arg);
968 case PIN_CONFIG_INPUT_ENABLE:
969 ret = cy8c95x0_pinmux_direction(chip, off, arg);
976 * Writing 1 to one of the drive mode registers will automatically
977 * clear conflicting set bits in the other drive mode registers.
979 ret = cy8c95x0_regmap_write_bits(chip, reg, port, bit, bit);
984 static int cy8c95x0_gpio_get_multiple(struct gpio_chip *gc,
985 unsigned long *mask, unsigned long *bits)
987 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
989 return cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, bits, mask);
992 static void cy8c95x0_gpio_set_multiple(struct gpio_chip *gc,
993 unsigned long *mask, unsigned long *bits)
995 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
997 cy8c95x0_write_regs_mask(chip, CY8C95X0_OUTPUT, bits, mask);
1000 static int cy8c95x0_add_pin_ranges(struct gpio_chip *gc)
1002 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
1003 struct device *dev = chip->dev;
1006 ret = gpiochip_add_pin_range(gc, dev_name(dev), 0, 0, chip->tpin);
1008 dev_err(dev, "failed to add GPIO pin range\n");
1013 static int cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl *chip)
1015 struct gpio_chip *gc = &chip->gpio_chip;
1017 gc->request = gpiochip_generic_request;
1018 gc->free = gpiochip_generic_free;
1019 gc->direction_input = cy8c95x0_gpio_direction_input;
1020 gc->direction_output = cy8c95x0_gpio_direction_output;
1021 gc->get = cy8c95x0_gpio_get_value;
1022 gc->set = cy8c95x0_gpio_set_value;
1023 gc->get_direction = cy8c95x0_gpio_get_direction;
1024 gc->get_multiple = cy8c95x0_gpio_get_multiple;
1025 gc->set_multiple = cy8c95x0_gpio_set_multiple;
1026 gc->set_config = gpiochip_generic_config;
1027 gc->can_sleep = true;
1028 gc->add_pin_ranges = cy8c95x0_add_pin_ranges;
1031 gc->ngpio = chip->tpin;
1033 gc->parent = chip->dev;
1034 gc->owner = THIS_MODULE;
1037 gc->label = dev_name(chip->dev);
1039 return devm_gpiochip_add_data(chip->dev, gc, chip);
1042 static void cy8c95x0_irq_mask(struct irq_data *d)
1044 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1045 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
1046 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1048 set_bit(hwirq, chip->irq_mask);
1049 gpiochip_disable_irq(gc, hwirq);
1052 static void cy8c95x0_irq_unmask(struct irq_data *d)
1054 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1055 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
1056 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1058 gpiochip_enable_irq(gc, hwirq);
1059 clear_bit(hwirq, chip->irq_mask);
1062 static void cy8c95x0_irq_bus_lock(struct irq_data *d)
1064 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1065 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
1067 mutex_lock(&chip->irq_lock);
1070 static void cy8c95x0_irq_bus_sync_unlock(struct irq_data *d)
1072 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1073 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
1074 DECLARE_BITMAP(ones, MAX_LINE);
1075 DECLARE_BITMAP(irq_mask, MAX_LINE);
1076 DECLARE_BITMAP(reg_direction, MAX_LINE);
1078 bitmap_fill(ones, MAX_LINE);
1080 cy8c95x0_write_regs_mask(chip, CY8C95X0_INTMASK, chip->irq_mask, ones);
1082 /* Switch direction to input if needed */
1083 cy8c95x0_read_regs_mask(chip, CY8C95X0_DIRECTION, reg_direction, chip->irq_mask);
1084 bitmap_or(irq_mask, chip->irq_mask, reg_direction, MAX_LINE);
1085 bitmap_complement(irq_mask, irq_mask, MAX_LINE);
1087 /* Look for any newly setup interrupt */
1088 cy8c95x0_write_regs_mask(chip, CY8C95X0_DIRECTION, ones, irq_mask);
1090 mutex_unlock(&chip->irq_lock);
1093 static int cy8c95x0_irq_set_type(struct irq_data *d, unsigned int type)
1095 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1096 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
1097 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1098 unsigned int trig_type;
1101 case IRQ_TYPE_EDGE_RISING:
1102 case IRQ_TYPE_EDGE_FALLING:
1103 case IRQ_TYPE_EDGE_BOTH:
1106 case IRQ_TYPE_LEVEL_HIGH:
1107 trig_type = IRQ_TYPE_EDGE_RISING;
1109 case IRQ_TYPE_LEVEL_LOW:
1110 trig_type = IRQ_TYPE_EDGE_FALLING;
1113 dev_err(chip->dev, "irq %d: unsupported type %d\n", d->irq, type);
1117 assign_bit(hwirq, chip->irq_trig_fall, trig_type & IRQ_TYPE_EDGE_FALLING);
1118 assign_bit(hwirq, chip->irq_trig_raise, trig_type & IRQ_TYPE_EDGE_RISING);
1119 assign_bit(hwirq, chip->irq_trig_low, type == IRQ_TYPE_LEVEL_LOW);
1120 assign_bit(hwirq, chip->irq_trig_high, type == IRQ_TYPE_LEVEL_HIGH);
1125 static void cy8c95x0_irq_shutdown(struct irq_data *d)
1127 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1128 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
1129 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1131 clear_bit(hwirq, chip->irq_trig_raise);
1132 clear_bit(hwirq, chip->irq_trig_fall);
1133 clear_bit(hwirq, chip->irq_trig_low);
1134 clear_bit(hwirq, chip->irq_trig_high);
1137 static const struct irq_chip cy8c95x0_irqchip = {
1138 .name = "cy8c95x0-irq",
1139 .irq_mask = cy8c95x0_irq_mask,
1140 .irq_unmask = cy8c95x0_irq_unmask,
1141 .irq_bus_lock = cy8c95x0_irq_bus_lock,
1142 .irq_bus_sync_unlock = cy8c95x0_irq_bus_sync_unlock,
1143 .irq_set_type = cy8c95x0_irq_set_type,
1144 .irq_shutdown = cy8c95x0_irq_shutdown,
1145 .flags = IRQCHIP_IMMUTABLE,
1146 GPIOCHIP_IRQ_RESOURCE_HELPERS,
1149 static bool cy8c95x0_irq_pending(struct cy8c95x0_pinctrl *chip, unsigned long *pending)
1151 DECLARE_BITMAP(ones, MAX_LINE);
1152 DECLARE_BITMAP(cur_stat, MAX_LINE);
1153 DECLARE_BITMAP(new_stat, MAX_LINE);
1154 DECLARE_BITMAP(trigger, MAX_LINE);
1156 bitmap_fill(ones, MAX_LINE);
1158 /* Read the current interrupt status from the device */
1159 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INTSTATUS, trigger, ones))
1162 /* Check latched inputs */
1163 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, cur_stat, trigger))
1166 /* Apply filter for rising/falling edge selection */
1167 bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise,
1168 cur_stat, MAX_LINE);
1170 bitmap_and(pending, new_stat, trigger, MAX_LINE);
1172 return !bitmap_empty(pending, MAX_LINE);
1175 static irqreturn_t cy8c95x0_irq_handler(int irq, void *devid)
1177 struct cy8c95x0_pinctrl *chip = devid;
1178 struct gpio_chip *gc = &chip->gpio_chip;
1179 DECLARE_BITMAP(pending, MAX_LINE);
1180 int nested_irq, level;
1183 ret = cy8c95x0_irq_pending(chip, pending);
1185 return IRQ_RETVAL(0);
1188 for_each_set_bit(level, pending, MAX_LINE) {
1189 /* Already accounted for 4bit gap in GPort2 */
1190 nested_irq = irq_find_mapping(gc->irq.domain, level);
1192 if (unlikely(nested_irq <= 0)) {
1193 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level);
1197 if (test_bit(level, chip->irq_trig_low))
1198 while (!cy8c95x0_gpio_get_value(gc, level))
1199 handle_nested_irq(nested_irq);
1200 else if (test_bit(level, chip->irq_trig_high))
1201 while (cy8c95x0_gpio_get_value(gc, level))
1202 handle_nested_irq(nested_irq);
1204 handle_nested_irq(nested_irq);
1209 return IRQ_RETVAL(ret);
1212 static int cy8c95x0_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
1214 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1219 static const char *cy8c95x0_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
1222 return cy8c95x0_groups[group];
1225 static int cy8c95x0_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
1227 const unsigned int **pins,
1228 unsigned int *num_pins)
1230 *pins = &cy8c9560_pins[group].number;
1235 static const char *cy8c95x0_get_fname(unsigned int selector)
1243 static void cy8c95x0_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1246 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1247 DECLARE_BITMAP(mask, MAX_LINE);
1248 DECLARE_BITMAP(pwm, MAX_LINE);
1250 bitmap_zero(mask, MAX_LINE);
1251 __set_bit(pin, mask);
1253 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_PWMSEL, pwm, mask)) {
1254 seq_puts(s, "not available");
1258 seq_printf(s, "MODE:%s", cy8c95x0_get_fname(test_bit(pin, pwm)));
1261 static const struct pinctrl_ops cy8c95x0_pinctrl_ops = {
1262 .get_groups_count = cy8c95x0_pinctrl_get_groups_count,
1263 .get_group_name = cy8c95x0_pinctrl_get_group_name,
1264 .get_group_pins = cy8c95x0_pinctrl_get_group_pins,
1266 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1267 .dt_free_map = pinconf_generic_dt_free_map,
1269 .pin_dbg_show = cy8c95x0_pin_dbg_show,
1272 static const char *cy8c95x0_get_function_name(struct pinctrl_dev *pctldev, unsigned int selector)
1274 return cy8c95x0_get_fname(selector);
1277 static int cy8c95x0_get_functions_count(struct pinctrl_dev *pctldev)
1282 static int cy8c95x0_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector,
1283 const char * const **groups,
1284 unsigned int * const num_groups)
1286 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1288 *groups = cy8c95x0_groups;
1289 *num_groups = chip->tpin;
1293 static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl *chip, unsigned int off, bool mode)
1295 u8 port = cypress_get_port(chip, off);
1296 u8 bit = cypress_get_pin_mask(chip, off);
1298 return cy8c95x0_regmap_write_bits(chip, CY8C95X0_PWMSEL, port, bit, mode ? bit : 0);
1301 static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip,
1302 unsigned int selector, unsigned int group)
1304 u8 port = cypress_get_port(chip, group);
1305 u8 bit = cypress_get_pin_mask(chip, group);
1308 ret = cy8c95x0_set_mode(chip, group, selector);
1315 /* Set direction to output & set output to 1 so that PWM can work */
1316 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, bit);
1320 return cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, bit);
1323 static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
1326 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1328 return cy8c95x0_pinmux_mode(chip, selector, group);
1331 static int cy8c95x0_gpio_request_enable(struct pinctrl_dev *pctldev,
1332 struct pinctrl_gpio_range *range,
1335 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1337 return cy8c95x0_set_mode(chip, pin, false);
1340 static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip,
1341 unsigned int pin, bool input)
1343 u8 port = cypress_get_port(chip, pin);
1344 u8 bit = cypress_get_pin_mask(chip, pin);
1347 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, input ? bit : 0);
1352 * Disable driving the pin by forcing it to HighZ. Only setting
1353 * the direction register isn't sufficient in Push-Pull mode.
1355 if (input && test_bit(pin, chip->push_pull)) {
1356 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DRV_HIZ, port, bit, bit);
1360 __clear_bit(pin, chip->push_pull);
1366 static int cy8c95x0_gpio_set_direction(struct pinctrl_dev *pctldev,
1367 struct pinctrl_gpio_range *range,
1368 unsigned int pin, bool input)
1370 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1372 return cy8c95x0_pinmux_direction(chip, pin, input);
1375 static const struct pinmux_ops cy8c95x0_pmxops = {
1376 .get_functions_count = cy8c95x0_get_functions_count,
1377 .get_function_name = cy8c95x0_get_function_name,
1378 .get_function_groups = cy8c95x0_get_function_groups,
1379 .set_mux = cy8c95x0_set_mux,
1380 .gpio_request_enable = cy8c95x0_gpio_request_enable,
1381 .gpio_set_direction = cy8c95x0_gpio_set_direction,
1385 static int cy8c95x0_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1386 unsigned long *config)
1388 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1390 return cy8c95x0_gpio_get_pincfg(chip, pin, config);
1393 static int cy8c95x0_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1394 unsigned long *configs, unsigned int num_configs)
1396 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1400 for (i = 0; i < num_configs; i++) {
1401 ret = cy8c95x0_gpio_set_pincfg(chip, pin, configs[i]);
1409 static const struct pinconf_ops cy8c95x0_pinconf_ops = {
1410 .pin_config_get = cy8c95x0_pinconf_get,
1411 .pin_config_set = cy8c95x0_pinconf_set,
1415 static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq)
1417 struct gpio_irq_chip *girq = &chip->gpio_chip.irq;
1418 DECLARE_BITMAP(pending_irqs, MAX_LINE);
1421 mutex_init(&chip->irq_lock);
1423 bitmap_zero(pending_irqs, MAX_LINE);
1425 /* Read IRQ status register to clear all pending interrupts */
1426 ret = cy8c95x0_irq_pending(chip, pending_irqs);
1428 dev_err(chip->dev, "failed to clear irq status register\n");
1432 /* Mask all interrupts */
1433 bitmap_fill(chip->irq_mask, MAX_LINE);
1435 gpio_irq_chip_set_chip(girq, &cy8c95x0_irqchip);
1437 /* This will let us handle the parent IRQ in the driver */
1438 girq->parent_handler = NULL;
1439 girq->num_parents = 0;
1440 girq->parents = NULL;
1441 girq->default_type = IRQ_TYPE_NONE;
1442 girq->handler = handle_simple_irq;
1443 girq->threaded = true;
1445 ret = devm_request_threaded_irq(chip->dev, irq,
1446 NULL, cy8c95x0_irq_handler,
1447 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_HIGH,
1448 dev_name(chip->dev), chip);
1450 dev_err(chip->dev, "failed to request irq %d\n", irq);
1453 dev_info(chip->dev, "Registered threaded IRQ\n");
1458 static int cy8c95x0_setup_pinctrl(struct cy8c95x0_pinctrl *chip)
1460 struct pinctrl_desc *pd = &chip->pinctrl_desc;
1462 pd->pctlops = &cy8c95x0_pinctrl_ops;
1463 pd->confops = &cy8c95x0_pinconf_ops;
1464 pd->pmxops = &cy8c95x0_pmxops;
1465 pd->name = dev_name(chip->dev);
1466 pd->pins = cy8c9560_pins;
1467 pd->npins = chip->tpin;
1468 pd->owner = THIS_MODULE;
1470 chip->pctldev = devm_pinctrl_register(chip->dev, pd, chip);
1471 if (IS_ERR(chip->pctldev))
1472 return dev_err_probe(chip->dev, PTR_ERR(chip->pctldev),
1473 "can't register controller\n");
1478 static int cy8c95x0_detect(struct i2c_client *client,
1479 struct i2c_board_info *info)
1481 struct i2c_adapter *adapter = client->adapter;
1485 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1488 ret = i2c_smbus_read_byte_data(client, CY8C95X0_DEVID);
1491 switch (ret & GENMASK(7, 4)) {
1493 name = cy8c95x0_id[0].name;
1496 name = cy8c95x0_id[1].name;
1499 name = cy8c95x0_id[2].name;
1505 dev_info(&client->dev, "Found a %s chip at 0x%02x.\n", name, client->addr);
1506 strscpy(info->type, name, I2C_NAME_SIZE);
1511 static int cy8c95x0_probe(struct i2c_client *client)
1513 struct cy8c95x0_pinctrl *chip;
1514 struct regulator *reg;
1517 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
1521 chip->dev = &client->dev;
1523 /* Set the device type */
1524 chip->driver_data = (uintptr_t)i2c_get_match_data(client);
1525 if (!chip->driver_data)
1528 i2c_set_clientdata(client, chip);
1530 chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK;
1531 chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ);
1533 switch (chip->tpin) {
1535 strscpy(chip->name, cy8c95x0_id[0].name, I2C_NAME_SIZE);
1538 strscpy(chip->name, cy8c95x0_id[1].name, I2C_NAME_SIZE);
1541 strscpy(chip->name, cy8c95x0_id[2].name, I2C_NAME_SIZE);
1547 reg = devm_regulator_get(&client->dev, "vdd");
1549 if (PTR_ERR(reg) == -EPROBE_DEFER)
1550 return -EPROBE_DEFER;
1552 ret = regulator_enable(reg);
1554 dev_err(&client->dev, "failed to enable regulator vdd: %d\n", ret);
1557 chip->regulator = reg;
1560 /* bring the chip out of reset if reset pin is provided */
1561 chip->gpio_reset = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_HIGH);
1562 if (IS_ERR(chip->gpio_reset)) {
1563 ret = dev_err_probe(chip->dev, PTR_ERR(chip->gpio_reset),
1564 "Failed to get GPIO 'reset'\n");
1566 } else if (chip->gpio_reset) {
1567 usleep_range(1000, 2000);
1568 gpiod_set_value_cansleep(chip->gpio_reset, 0);
1569 usleep_range(250000, 300000);
1571 gpiod_set_consumer_name(chip->gpio_reset, "CY8C95X0 RESET");
1574 /* Generic regmap for direct access registers */
1575 chip->regmap = devm_regmap_init_i2c(client, &cy8c95x0_i2c_regmap);
1576 if (IS_ERR(chip->regmap)) {
1577 ret = PTR_ERR(chip->regmap);
1581 /* Port specific regmap behind PORTSEL mux */
1582 chip->muxed_regmap = devm_regmap_init(&client->dev, &cy8c95x0_regmap_bus,
1583 chip, &cy8c95x0_muxed_regmap);
1584 if (IS_ERR(chip->muxed_regmap)) {
1585 ret = dev_err_probe(&client->dev, PTR_ERR(chip->muxed_regmap),
1586 "Failed to register muxed regmap\n");
1590 bitmap_zero(chip->push_pull, MAX_LINE);
1591 bitmap_zero(chip->shiftmask, MAX_LINE);
1592 bitmap_set(chip->shiftmask, 0, 20);
1593 mutex_init(&chip->i2c_lock);
1595 if (dmi_first_match(cy8c95x0_dmi_acpi_irq_info)) {
1596 ret = cy8c95x0_acpi_get_irq(&client->dev);
1602 ret = cy8c95x0_irq_setup(chip, client->irq);
1607 ret = cy8c95x0_setup_pinctrl(chip);
1611 ret = cy8c95x0_setup_gpiochip(chip);
1618 if (!IS_ERR_OR_NULL(chip->regulator))
1619 regulator_disable(chip->regulator);
1623 static void cy8c95x0_remove(struct i2c_client *client)
1625 struct cy8c95x0_pinctrl *chip = i2c_get_clientdata(client);
1627 if (!IS_ERR_OR_NULL(chip->regulator))
1628 regulator_disable(chip->regulator);
1631 static const struct acpi_device_id cy8c95x0_acpi_ids[] = {
1635 MODULE_DEVICE_TABLE(acpi, cy8c95x0_acpi_ids);
1637 static struct i2c_driver cy8c95x0_driver = {
1639 .name = "cy8c95x0-pinctrl",
1640 .of_match_table = cy8c95x0_dt_ids,
1641 .acpi_match_table = cy8c95x0_acpi_ids,
1643 .probe = cy8c95x0_probe,
1644 .remove = cy8c95x0_remove,
1645 .id_table = cy8c95x0_id,
1646 .detect = cy8c95x0_detect,
1648 module_i2c_driver(cy8c95x0_driver);
1650 MODULE_AUTHOR("Patrick Rudolph <patrick.rudolph@9elements.com>");
1651 MODULE_AUTHOR("Naresh Solanki <naresh.solanki@9elements.com>");
1652 MODULE_DESCRIPTION("Pinctrl driver for CY8C95X0");
1653 MODULE_LICENSE("GPL");