2 * at91 pinctrl driver based on at91 pinmux core
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 #include <linux/err.h>
11 #include <linux/init.h>
12 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/slab.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/irqdomain.h>
22 #include <linux/gpio.h>
23 #include <linux/pinctrl/machine.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinmux.h>
27 /* Since we request GPIOs from ourself */
28 #include <linux/pinctrl/consumer.h>
30 #include <asm/mach/irq.h>
32 #include <mach/hardware.h>
33 #include <mach/at91_pio.h>
37 #define MAX_NB_GPIO_PER_BANK 32
39 struct at91_pinctrl_mux_ops;
41 struct at91_gpio_chip {
42 struct gpio_chip chip;
43 struct pinctrl_gpio_range range;
44 struct at91_gpio_chip *next; /* Bank sharing same clock */
45 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
46 int pioc_virq; /* PIO bank Linux virtual interrupt */
47 int pioc_idx; /* PIO bank index */
48 void __iomem *regbase; /* PIO bank virtual address */
49 struct clk *clock; /* associated clock */
50 struct irq_domain *domain; /* associated irq domain */
51 struct at91_pinctrl_mux_ops *ops; /* ops */
54 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
56 static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
58 static int gpio_banks;
60 #define PULL_UP (1 << 0)
61 #define MULTI_DRIVE (1 << 1)
64 * struct at91_pmx_func - describes AT91 pinmux functions
65 * @name: the name of this specific function
66 * @groups: corresponding pin groups
67 * @ngroups: the number of groups
69 struct at91_pmx_func {
77 AT91_MUX_PERIPH_A = 1,
78 AT91_MUX_PERIPH_B = 2,
79 AT91_MUX_PERIPH_C = 3,
80 AT91_MUX_PERIPH_D = 4,
84 * struct at91_pmx_pin - describes an At91 pin mux
85 * @bank: the bank of the pin
86 * @pin: the pin number in the @bank
87 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
88 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
98 * struct at91_pin_group - describes an At91 pin group
99 * @name: the name of this specific pin group
100 * @pins_conf: the mux mode for each pin in this group. The size of this
101 * array is the same as pins.
102 * @pins: an array of discrete physical pins used in this group, taken
103 * from the driver-local pin enumeration space
104 * @npins: the number of pins in this group array, i.e. the number of
105 * elements in .pins so we can iterate over that array
107 struct at91_pin_group {
109 struct at91_pmx_pin *pins_conf;
115 * struct at91_pinctrl_mux_ops - describes an At91 mux ops group
116 * on new IP with support for periph C and D the way to mux in
117 * periph A and B has changed
118 * So provide the right call back
119 * if not present means the IP does not support it
120 * @get_periph: return the periph mode configured
121 * @mux_A_periph: mux as periph A
122 * @mux_B_periph: mux as periph B
123 * @mux_C_periph: mux as periph C
124 * @mux_D_periph: mux as periph D
125 * @irq_type: return irq type
127 struct at91_pinctrl_mux_ops {
128 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
129 void (*mux_A_periph)(void __iomem *pio, unsigned mask);
130 void (*mux_B_periph)(void __iomem *pio, unsigned mask);
131 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
132 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
134 int (*irq_type)(struct irq_data *d, unsigned type);
137 static int gpio_irq_type(struct irq_data *d, unsigned type);
138 static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
140 struct at91_pinctrl {
142 struct pinctrl_dev *pctl;
149 struct at91_pmx_func *functions;
152 struct at91_pin_group *groups;
155 struct at91_pinctrl_mux_ops *ops;
158 static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name(
159 const struct at91_pinctrl *info,
162 const struct at91_pin_group *grp = NULL;
165 for (i = 0; i < info->ngroups; i++) {
166 if (strcmp(info->groups[i].name, name))
169 grp = &info->groups[i];
170 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
177 static int at91_get_groups_count(struct pinctrl_dev *pctldev)
179 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
181 return info->ngroups;
184 static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
187 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
189 return info->groups[selector].name;
192 static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
193 const unsigned **pins,
196 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
198 if (selector >= info->ngroups)
201 *pins = info->groups[selector].pins;
202 *npins = info->groups[selector].npins;
207 static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
210 seq_printf(s, "%s", dev_name(pctldev->dev));
213 static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
214 struct device_node *np,
215 struct pinctrl_map **map, unsigned *num_maps)
217 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
218 const struct at91_pin_group *grp;
219 struct pinctrl_map *new_map;
220 struct device_node *parent;
223 struct at91_pmx_pin *pin;
226 * first find the group of this node and check if we need create
227 * config maps for pins
229 grp = at91_pinctrl_find_group_by_name(info, np->name);
231 dev_err(info->dev, "unable to find group for node %s\n",
236 map_num += grp->npins;
237 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL);
245 parent = of_get_parent(np);
250 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
251 new_map[0].data.mux.function = parent->name;
252 new_map[0].data.mux.group = np->name;
255 /* create config map */
257 for (i = 0; i < grp->npins; i++) {
258 pin = &grp->pins_conf[i];
260 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
261 new_map[i].data.configs.group_or_pin =
262 pin_get_name(pctldev, grp->pins[i]);
263 new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
264 new_map[i].data.configs.num_configs = 1;
267 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
268 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
273 static void at91_dt_free_map(struct pinctrl_dev *pctldev,
274 struct pinctrl_map *map, unsigned num_maps)
278 static struct pinctrl_ops at91_pctrl_ops = {
279 .get_groups_count = at91_get_groups_count,
280 .get_group_name = at91_get_group_name,
281 .get_group_pins = at91_get_group_pins,
282 .pin_dbg_show = at91_pin_dbg_show,
283 .dt_node_to_map = at91_dt_node_to_map,
284 .dt_free_map = at91_dt_free_map,
287 static void __iomem * pin_to_controller(struct at91_pinctrl *info,
290 return gpio_chips[bank]->regbase;
293 static inline int pin_to_bank(unsigned pin)
295 return pin /= MAX_NB_GPIO_PER_BANK;
298 static unsigned pin_to_mask(unsigned int pin)
303 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
305 writel_relaxed(mask, pio + PIO_IDR);
308 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
310 return (readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1;
313 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
315 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
318 static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
320 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
323 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
325 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
328 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
330 writel_relaxed(mask, pio + PIO_ASR);
333 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
335 writel_relaxed(mask, pio + PIO_BSR);
338 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
341 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
343 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
347 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
349 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
351 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
355 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
357 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
358 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
361 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
363 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
364 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
367 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
371 if (readl_relaxed(pio + PIO_PSR) & mask)
372 return AT91_MUX_GPIO;
374 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
375 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
380 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
384 if (readl_relaxed(pio + PIO_PSR) & mask)
385 return AT91_MUX_GPIO;
387 select = readl_relaxed(pio + PIO_ABSR) & mask;
392 static struct at91_pinctrl_mux_ops at91rm9200_ops = {
393 .get_periph = at91_mux_get_periph,
394 .mux_A_periph = at91_mux_set_A_periph,
395 .mux_B_periph = at91_mux_set_B_periph,
396 .irq_type = gpio_irq_type,
399 static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
400 .get_periph = at91_mux_pio3_get_periph,
401 .mux_A_periph = at91_mux_pio3_set_A_periph,
402 .mux_B_periph = at91_mux_pio3_set_B_periph,
403 .mux_C_periph = at91_mux_pio3_set_C_periph,
404 .mux_D_periph = at91_mux_pio3_set_D_periph,
405 .irq_type = alt_gpio_irq_type,
408 static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
411 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lu\n",
412 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
414 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lu\n",
415 pin->bank + 'A', pin->pin, pin->conf);
419 static int pin_check_config(struct at91_pinctrl *info, const char* name,
420 int index, const struct at91_pmx_pin *pin)
424 /* check if it's a valid config */
425 if (pin->bank >= info->nbanks) {
426 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
427 name, index, pin->bank, info->nbanks);
431 if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
432 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
433 name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
442 if (mux >= info->nmux) {
443 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
444 name, index, mux, info->nmux);
448 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
449 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
450 name, index, mux, pin->bank + 'A', pin->pin);
457 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
459 writel_relaxed(mask, pio + PIO_PDR);
462 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
464 writel_relaxed(mask, pio + PIO_PER);
465 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
468 static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
471 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
472 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
473 const struct at91_pmx_pin *pin;
474 uint32_t npins = info->groups[group].npins;
479 dev_dbg(info->dev, "enable function %s group %s\n",
480 info->functions[selector].name, info->groups[group].name);
482 /* first check that all the pins of the group are valid with a valid
484 for (i = 0; i < npins; i++) {
486 ret = pin_check_config(info, info->groups[group].name, i, pin);
491 for (i = 0; i < npins; i++) {
493 at91_pin_dbg(info->dev, pin);
494 pio = pin_to_controller(info, pin->bank);
495 mask = pin_to_mask(pin->pin);
496 at91_mux_disable_interrupt(pio, mask);
499 at91_mux_gpio_enable(pio, mask, 1);
501 case AT91_MUX_PERIPH_A:
502 info->ops->mux_A_periph(pio, mask);
504 case AT91_MUX_PERIPH_B:
505 info->ops->mux_B_periph(pio, mask);
507 case AT91_MUX_PERIPH_C:
508 if (!info->ops->mux_C_periph)
510 info->ops->mux_C_periph(pio, mask);
512 case AT91_MUX_PERIPH_D:
513 if (!info->ops->mux_D_periph)
515 info->ops->mux_D_periph(pio, mask);
519 at91_mux_gpio_disable(pio, mask);
525 static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
528 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
529 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
530 const struct at91_pmx_pin *pin;
531 uint32_t npins = info->groups[group].npins;
536 for (i = 0; i < npins; i++) {
538 at91_pin_dbg(info->dev, pin);
539 pio = pin_to_controller(info, pin->bank);
540 mask = pin_to_mask(pin->pin);
541 at91_mux_gpio_enable(pio, mask, 1);
545 static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
547 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
549 return info->nfunctions;
552 static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
555 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
557 return info->functions[selector].name;
560 static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
561 const char * const **groups,
562 unsigned * const num_groups)
564 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
566 *groups = info->functions[selector].groups;
567 *num_groups = info->functions[selector].ngroups;
572 int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
573 struct pinctrl_gpio_range *range,
576 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
577 struct at91_gpio_chip *at91_chip;
578 struct gpio_chip *chip;
582 dev_err(npct->dev, "invalid range\n");
586 dev_err(npct->dev, "missing GPIO chip in range\n");
590 at91_chip = container_of(chip, struct at91_gpio_chip, chip);
592 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
594 mask = 1 << (offset - chip->base);
596 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
597 offset, 'A' + range->id, offset - chip->base, mask);
599 writel_relaxed(mask, at91_chip->regbase + PIO_PER);
604 void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
605 struct pinctrl_gpio_range *range,
608 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
610 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
611 /* Set the pin to some default state, GPIO is usually default */
614 static struct pinmux_ops at91_pmx_ops = {
615 .get_functions_count = at91_pmx_get_funcs_count,
616 .get_function_name = at91_pmx_get_func_name,
617 .get_function_groups = at91_pmx_get_groups,
618 .enable = at91_pmx_enable,
619 .disable = at91_pmx_disable,
620 .gpio_request_enable = at91_gpio_request_enable,
621 .gpio_disable_free = at91_gpio_disable_free,
624 static int at91_pinconf_get(struct pinctrl_dev *pctldev,
625 unsigned pin_id, unsigned long *config)
627 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
631 dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, *config);
632 pio = pin_to_controller(info, pin_to_bank(pin_id));
633 pin = pin_id % MAX_NB_GPIO_PER_BANK;
635 if (at91_mux_get_multidrive(pio, pin))
636 *config |= MULTI_DRIVE;
638 if (at91_mux_get_pullup(pio, pin))
644 static int at91_pinconf_set(struct pinctrl_dev *pctldev,
645 unsigned pin_id, unsigned long config)
647 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
651 dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, config);
652 pio = pin_to_controller(info, pin_to_bank(pin_id));
653 mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK);
655 at91_mux_set_pullup(pio, mask, config & PULL_UP);
656 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
660 static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
661 struct seq_file *s, unsigned pin_id)
666 static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
667 struct seq_file *s, unsigned group)
671 struct pinconf_ops at91_pinconf_ops = {
672 .pin_config_get = at91_pinconf_get,
673 .pin_config_set = at91_pinconf_set,
674 .pin_config_dbg_show = at91_pinconf_dbg_show,
675 .pin_config_group_dbg_show = at91_pinconf_group_dbg_show,
678 static struct pinctrl_desc at91_pinctrl_desc = {
679 .pctlops = &at91_pctrl_ops,
680 .pmxops = &at91_pmx_ops,
681 .confops = &at91_pinconf_ops,
682 .owner = THIS_MODULE,
685 static const char *gpio_compat = "atmel,at91rm9200-gpio";
687 static void __devinit at91_pinctrl_child_count(struct at91_pinctrl *info,
688 struct device_node *np)
690 struct device_node *child;
692 for_each_child_of_node(np, child) {
693 if (of_device_is_compatible(child, gpio_compat)) {
697 info->ngroups += of_get_child_count(child);
702 static int __devinit at91_pinctrl_mux_mask(struct at91_pinctrl *info,
703 struct device_node *np)
707 const const __be32 *list;
709 list = of_get_property(np, "atmel,mux-mask", &size);
711 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
715 size /= sizeof(*list);
716 if (!size || size % info->nbanks) {
717 dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks);
720 info->nmux = size / info->nbanks;
722 info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
723 if (!info->mux_mask) {
724 dev_err(info->dev, "could not alloc mux_mask\n");
728 ret = of_property_read_u32_array(np, "atmel,mux-mask",
729 info->mux_mask, size);
731 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
735 static int __devinit at91_pinctrl_parse_groups(struct device_node *np,
736 struct at91_pin_group *grp,
737 struct at91_pinctrl *info,
740 struct at91_pmx_pin *pin;
742 const const __be32 *list;
745 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
747 /* Initialise group */
748 grp->name = np->name;
751 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
752 * do sanity check and calculate pins number
754 list = of_get_property(np, "atmel,pins", &size);
755 /* we do not check return since it's safe node passed down */
756 size /= sizeof(*list);
757 if (!size || size % 4) {
758 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
762 grp->npins = size / 4;
763 pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin),
765 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
767 if (!grp->pins_conf || !grp->pins)
770 for (i = 0, j = 0; i < size; i += 4, j++) {
771 pin->bank = be32_to_cpu(*list++);
772 pin->pin = be32_to_cpu(*list++);
773 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
774 pin->mux = be32_to_cpu(*list++);
775 pin->conf = be32_to_cpu(*list++);
777 at91_pin_dbg(info->dev, pin);
784 static int __devinit at91_pinctrl_parse_functions(struct device_node *np,
785 struct at91_pinctrl *info, u32 index)
787 struct device_node *child;
788 struct at91_pmx_func *func;
789 struct at91_pin_group *grp;
791 static u32 grp_index;
794 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
796 func = &info->functions[index];
798 /* Initialise function */
799 func->name = np->name;
800 func->ngroups = of_get_child_count(np);
801 if (func->ngroups <= 0) {
802 dev_err(info->dev, "no groups defined\n");
805 func->groups = devm_kzalloc(info->dev,
806 func->ngroups * sizeof(char *), GFP_KERNEL);
810 for_each_child_of_node(np, child) {
811 func->groups[i] = child->name;
812 grp = &info->groups[grp_index++];
813 ret = at91_pinctrl_parse_groups(child, grp, info, i++);
821 static struct of_device_id at91_pinctrl_of_match[] __devinitdata = {
822 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
823 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
827 static int __devinit at91_pinctrl_probe_dt(struct platform_device *pdev,
828 struct at91_pinctrl *info)
833 struct device_node *np = pdev->dev.of_node;
834 struct device_node *child;
839 info->dev = &pdev->dev;
840 info->ops = (struct at91_pinctrl_mux_ops*)
841 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
842 at91_pinctrl_child_count(info, np);
844 if (info->nbanks < 1) {
845 dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n");
849 ret = at91_pinctrl_mux_mask(info, np);
853 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
855 dev_dbg(&pdev->dev, "mux-mask\n");
856 tmp = info->mux_mask;
857 for (i = 0; i < info->nbanks; i++) {
858 for (j = 0; j < info->nmux; j++, tmp++) {
859 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
863 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
864 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
865 info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func),
867 if (!info->functions)
870 info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group),
875 dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks);
876 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
877 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
881 for_each_child_of_node(np, child) {
882 if (of_device_is_compatible(child, gpio_compat))
884 ret = at91_pinctrl_parse_functions(child, info, i++);
886 dev_err(&pdev->dev, "failed to parse function\n");
894 static int __devinit at91_pinctrl_probe(struct platform_device *pdev)
896 struct at91_pinctrl *info;
897 struct pinctrl_pin_desc *pdesc;
900 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
904 ret = at91_pinctrl_probe_dt(pdev, info);
909 * We need all the GPIO drivers to probe FIRST, or we will not be able
910 * to obtain references to the struct gpio_chip * for them, and we
911 * need this to proceed.
913 for (i = 0; i < info->nbanks; i++) {
914 if (!gpio_chips[i]) {
915 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
916 devm_kfree(&pdev->dev, info);
917 return -EPROBE_DEFER;
921 at91_pinctrl_desc.name = dev_name(&pdev->dev);
922 at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK;
923 at91_pinctrl_desc.pins = pdesc =
924 devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL);
926 if (!at91_pinctrl_desc.pins)
929 for (i = 0 , k = 0; i < info->nbanks; i++) {
930 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
932 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
937 platform_set_drvdata(pdev, info);
938 info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info);
941 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
946 /* We will handle a range of GPIO pins */
947 for (i = 0; i < info->nbanks; i++)
948 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
950 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
958 int __devexit at91_pinctrl_remove(struct platform_device *pdev)
960 struct at91_pinctrl *info = platform_get_drvdata(pdev);
962 pinctrl_unregister(info->pctl);
967 static int at91_gpio_request(struct gpio_chip *chip, unsigned offset)
970 * Map back to global GPIO space and request muxing, the direction
971 * parameter does not matter for this controller.
973 int gpio = chip->base + offset;
974 int bank = chip->base / chip->ngpio;
976 dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__,
977 'A' + bank, offset, gpio);
979 return pinctrl_request_gpio(gpio);
982 static void at91_gpio_free(struct gpio_chip *chip, unsigned offset)
984 int gpio = chip->base + offset;
986 pinctrl_free_gpio(gpio);
989 static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
991 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
992 void __iomem *pio = at91_gpio->regbase;
993 unsigned mask = 1 << offset;
995 writel_relaxed(mask, pio + PIO_ODR);
999 static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1001 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1002 void __iomem *pio = at91_gpio->regbase;
1003 unsigned mask = 1 << offset;
1006 pdsr = readl_relaxed(pio + PIO_PDSR);
1007 return (pdsr & mask) != 0;
1010 static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1013 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1014 void __iomem *pio = at91_gpio->regbase;
1015 unsigned mask = 1 << offset;
1017 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1020 static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1023 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1024 void __iomem *pio = at91_gpio->regbase;
1025 unsigned mask = 1 << offset;
1027 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1028 writel_relaxed(mask, pio + PIO_OER);
1033 static int at91_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1035 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1038 if (offset < chip->ngpio)
1039 virq = irq_create_mapping(at91_gpio->domain, offset);
1043 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
1044 chip->label, offset + chip->base, virq);
1048 #ifdef CONFIG_DEBUG_FS
1049 static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1053 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1054 void __iomem *pio = at91_gpio->regbase;
1056 for (i = 0; i < chip->ngpio; i++) {
1057 unsigned pin = chip->base + i;
1058 unsigned mask = pin_to_mask(pin);
1059 const char *gpio_label;
1062 gpio_label = gpiochip_is_requested(chip, i);
1065 mode = at91_gpio->ops->get_periph(pio, mask);
1066 seq_printf(s, "[%s] GPIO%s%d: ",
1067 gpio_label, chip->label, i);
1068 if (mode == AT91_MUX_GPIO) {
1069 pdsr = readl_relaxed(pio + PIO_PDSR);
1071 seq_printf(s, "[gpio] %s\n",
1075 seq_printf(s, "[periph %c]\n",
1081 #define at91_gpio_dbg_show NULL
1084 /* Several AIC controller irqs are dispatched through this GPIO handler.
1085 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1086 * at91_set_gpio_input() then maybe enable its glitch filter.
1087 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1089 * First implementation always triggers on rising and falling edges
1090 * whereas the newer PIO3 can be additionally configured to trigger on
1091 * level, edge with any polarity.
1093 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1094 * configuring them with at91_set_a_periph() or at91_set_b_periph().
1095 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1098 static void gpio_irq_mask(struct irq_data *d)
1100 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1101 void __iomem *pio = at91_gpio->regbase;
1102 unsigned mask = 1 << d->hwirq;
1105 writel_relaxed(mask, pio + PIO_IDR);
1108 static void gpio_irq_unmask(struct irq_data *d)
1110 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1111 void __iomem *pio = at91_gpio->regbase;
1112 unsigned mask = 1 << d->hwirq;
1115 writel_relaxed(mask, pio + PIO_IER);
1118 static int gpio_irq_type(struct irq_data *d, unsigned type)
1122 case IRQ_TYPE_EDGE_BOTH:
1129 /* Alternate irq type for PIO3 support */
1130 static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1132 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1133 void __iomem *pio = at91_gpio->regbase;
1134 unsigned mask = 1 << d->hwirq;
1137 case IRQ_TYPE_EDGE_RISING:
1138 writel_relaxed(mask, pio + PIO_ESR);
1139 writel_relaxed(mask, pio + PIO_REHLSR);
1141 case IRQ_TYPE_EDGE_FALLING:
1142 writel_relaxed(mask, pio + PIO_ESR);
1143 writel_relaxed(mask, pio + PIO_FELLSR);
1145 case IRQ_TYPE_LEVEL_LOW:
1146 writel_relaxed(mask, pio + PIO_LSR);
1147 writel_relaxed(mask, pio + PIO_FELLSR);
1149 case IRQ_TYPE_LEVEL_HIGH:
1150 writel_relaxed(mask, pio + PIO_LSR);
1151 writel_relaxed(mask, pio + PIO_REHLSR);
1153 case IRQ_TYPE_EDGE_BOTH:
1155 * disable additional interrupt modes:
1156 * fall back to default behavior
1158 writel_relaxed(mask, pio + PIO_AIMDR);
1162 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
1166 /* enable additional interrupt modes */
1167 writel_relaxed(mask, pio + PIO_AIMER);
1173 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1175 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1176 unsigned bank = at91_gpio->pioc_idx;
1178 if (unlikely(bank >= MAX_GPIO_BANKS))
1181 irq_set_irq_wake(at91_gpio->pioc_virq, state);
1186 #define gpio_irq_set_wake NULL
1189 static struct irq_chip gpio_irqchip = {
1191 .irq_disable = gpio_irq_mask,
1192 .irq_mask = gpio_irq_mask,
1193 .irq_unmask = gpio_irq_unmask,
1194 /* .irq_set_type is set dynamically */
1195 .irq_set_wake = gpio_irq_set_wake,
1198 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1200 struct irq_chip *chip = irq_desc_get_chip(desc);
1201 struct irq_data *idata = irq_desc_get_irq_data(desc);
1202 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
1203 void __iomem *pio = at91_gpio->regbase;
1207 chained_irq_enter(chip, desc);
1209 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
1210 * When there none are pending, we're finished unless we need
1211 * to process multiple banks (like ID_PIOCDE on sam9263).
1213 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1215 if (!at91_gpio->next)
1217 at91_gpio = at91_gpio->next;
1218 pio = at91_gpio->regbase;
1222 for_each_set_bit(n, &isr, BITS_PER_LONG) {
1223 generic_handle_irq(irq_find_mapping(at91_gpio->domain, n));
1226 chained_irq_exit(chip, desc);
1227 /* now it may re-trigger */
1231 * This lock class tells lockdep that GPIO irqs are in a different
1232 * category than their parents, so it won't report false recursion.
1234 static struct lock_class_key gpio_lock_class;
1236 static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
1239 struct at91_gpio_chip *at91_gpio = h->host_data;
1241 irq_set_lockdep_class(virq, &gpio_lock_class);
1244 * Can use the "simple" and not "edge" handler since it's
1245 * shorter, and the AIC handles interrupts sanely.
1247 irq_set_chip_and_handler(virq, &gpio_irqchip,
1249 set_irq_flags(virq, IRQF_VALID);
1250 irq_set_chip_data(virq, at91_gpio);
1255 int at91_gpio_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
1256 const u32 *intspec, unsigned int intsize,
1257 irq_hw_number_t *out_hwirq, unsigned int *out_type)
1259 struct at91_gpio_chip *at91_gpio = d->host_data;
1261 int pin = at91_gpio->chip.base + intspec[0];
1263 if (WARN_ON(intsize < 2))
1265 *out_hwirq = intspec[0];
1266 *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
1268 ret = gpio_request(pin, ctrlr->full_name);
1272 ret = gpio_direction_input(pin);
1279 static struct irq_domain_ops at91_gpio_ops = {
1280 .map = at91_gpio_irq_map,
1281 .xlate = at91_gpio_irq_domain_xlate,
1284 static int at91_gpio_of_irq_setup(struct device_node *node,
1285 struct at91_gpio_chip *at91_gpio)
1287 struct at91_gpio_chip *prev = NULL;
1288 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);
1290 at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1292 /* Setup proper .irq_set_type function */
1293 gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type;
1295 /* Disable irqs of this PIO controller */
1296 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1298 /* Setup irq domain */
1299 at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
1300 &at91_gpio_ops, at91_gpio);
1301 if (!at91_gpio->domain)
1302 panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
1303 at91_gpio->pioc_idx);
1305 /* Setup chained handler */
1306 if (at91_gpio->pioc_idx)
1307 prev = gpio_chips[at91_gpio->pioc_idx - 1];
1309 /* The toplevel handler handles one bank of GPIOs, except
1310 * on some SoC it can handles up to three...
1311 * We only set up the handler for the first of the list.
1313 if (prev && prev->next == at91_gpio)
1316 irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
1317 irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
1322 /* This structure is replicated for each GPIO block allocated at probe time */
1323 static struct gpio_chip at91_gpio_template = {
1324 .request = at91_gpio_request,
1325 .free = at91_gpio_free,
1326 .direction_input = at91_gpio_direction_input,
1327 .get = at91_gpio_get,
1328 .direction_output = at91_gpio_direction_output,
1329 .set = at91_gpio_set,
1330 .to_irq = at91_gpio_to_irq,
1331 .dbg_show = at91_gpio_dbg_show,
1333 .ngpio = MAX_NB_GPIO_PER_BANK,
1336 static void __devinit at91_gpio_probe_fixup(void)
1339 struct at91_gpio_chip *at91_gpio, *last = NULL;
1341 for (i = 0; i < gpio_banks; i++) {
1342 at91_gpio = gpio_chips[i];
1345 * GPIO controller are grouped on some SoC:
1346 * PIOC, PIOD and PIOE can share the same IRQ line
1348 if (last && last->pioc_virq == at91_gpio->pioc_virq)
1349 last->next = at91_gpio;
1354 static struct of_device_id at91_gpio_of_match[] __devinitdata = {
1355 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1356 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1360 static int __devinit at91_gpio_probe(struct platform_device *pdev)
1362 struct device_node *np = pdev->dev.of_node;
1363 struct resource *res;
1364 struct at91_gpio_chip *at91_chip = NULL;
1365 struct gpio_chip *chip;
1366 struct pinctrl_gpio_range *range;
1369 int alias_idx = of_alias_get_id(np, "gpio");
1372 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1373 if (gpio_chips[alias_idx]) {
1378 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1384 irq = platform_get_irq(pdev, 0);
1390 at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
1396 at91_chip->regbase = devm_request_and_ioremap(&pdev->dev, res);
1397 if (!at91_chip->regbase) {
1398 dev_err(&pdev->dev, "failed to map registers, ignoring.\n");
1403 at91_chip->ops = (struct at91_pinctrl_mux_ops*)
1404 of_match_device(at91_gpio_of_match, &pdev->dev)->data;
1405 at91_chip->pioc_virq = irq;
1406 at91_chip->pioc_idx = alias_idx;
1408 at91_chip->clock = clk_get(&pdev->dev, NULL);
1409 if (IS_ERR(at91_chip->clock)) {
1410 dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
1414 if (clk_prepare(at91_chip->clock))
1417 /* enable PIO controller's clock */
1418 if (clk_enable(at91_chip->clock)) {
1419 dev_err(&pdev->dev, "failed to enable clock, ignoring.\n");
1423 at91_chip->chip = at91_gpio_template;
1425 chip = &at91_chip->chip;
1427 chip->label = dev_name(&pdev->dev);
1428 chip->dev = &pdev->dev;
1429 chip->owner = THIS_MODULE;
1430 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1432 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1433 if (ngpio >= MAX_NB_GPIO_PER_BANK)
1434 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1435 alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1437 chip->ngpio = ngpio;
1440 range = &at91_chip->range;
1441 range->name = chip->label;
1442 range->id = alias_idx;
1443 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1445 range->npins = chip->ngpio;
1448 ret = gpiochip_add(chip);
1452 gpio_chips[alias_idx] = at91_chip;
1453 gpio_banks = max(gpio_banks, alias_idx + 1);
1455 at91_gpio_probe_fixup();
1457 at91_gpio_of_irq_setup(np, at91_chip);
1459 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1464 clk_unprepare(at91_chip->clock);
1466 clk_put(at91_chip->clock);
1468 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1473 static struct platform_driver at91_gpio_driver = {
1475 .name = "gpio-at91",
1476 .owner = THIS_MODULE,
1477 .of_match_table = of_match_ptr(at91_gpio_of_match),
1479 .probe = at91_gpio_probe,
1482 static struct platform_driver at91_pinctrl_driver = {
1484 .name = "pinctrl-at91",
1485 .owner = THIS_MODULE,
1486 .of_match_table = of_match_ptr(at91_pinctrl_of_match),
1488 .probe = at91_pinctrl_probe,
1489 .remove = __devexit_p(at91_pinctrl_remove),
1492 static int __init at91_pinctrl_init(void)
1496 ret = platform_driver_register(&at91_gpio_driver);
1499 return platform_driver_register(&at91_pinctrl_driver);
1501 arch_initcall(at91_pinctrl_init);
1503 static void __exit at91_pinctrl_exit(void)
1505 platform_driver_unregister(&at91_pinctrl_driver);
1508 module_exit(at91_pinctrl_exit);
1509 MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>");
1510 MODULE_DESCRIPTION("Atmel AT91 pinctrl driver");
1511 MODULE_LICENSE("GPL v2");