Merge branch 'pm-devfreq'
[linux-2.6-block.git] / drivers / pinctrl / pinctrl-at91-pio4.c
1 /*
2  * Driver for the Atmel PIO4 controller
3  *
4  * Copyright (C) 2015 Atmel,
5  *               2015 Ludovic Desroches <ludovic.desroches@atmel.com>
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16
17 #include <linux/clk.h>
18 #include <linux/gpio.h>
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/platform_device.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinconf-generic.h>
26 #include <linux/pinctrl/pinctrl.h>
27 #include <linux/pinctrl/pinmux.h>
28 #include <linux/slab.h>
29 #include "core.h"
30 #include "pinconf.h"
31 #include "pinctrl-utils.h"
32
33 /*
34  * Warning:
35  * In order to not introduce confusion between Atmel PIO groups and pinctrl
36  * framework groups, Atmel PIO groups will be called banks, line is kept to
37  * designed the pin id into this bank.
38  */
39
40 #define ATMEL_PIO_MSKR          0x0000
41 #define ATMEL_PIO_CFGR          0x0004
42 #define         ATMEL_PIO_CFGR_FUNC_MASK        GENMASK(2, 0)
43 #define         ATMEL_PIO_DIR_MASK              BIT(8)
44 #define         ATMEL_PIO_PUEN_MASK             BIT(9)
45 #define         ATMEL_PIO_PDEN_MASK             BIT(10)
46 #define         ATMEL_PIO_IFEN_MASK             BIT(12)
47 #define         ATMEL_PIO_IFSCEN_MASK           BIT(13)
48 #define         ATMEL_PIO_OPD_MASK              BIT(14)
49 #define         ATMEL_PIO_SCHMITT_MASK          BIT(15)
50 #define         ATMEL_PIO_CFGR_EVTSEL_MASK      GENMASK(26, 24)
51 #define         ATMEL_PIO_CFGR_EVTSEL_FALLING   (0 << 24)
52 #define         ATMEL_PIO_CFGR_EVTSEL_RISING    (1 << 24)
53 #define         ATMEL_PIO_CFGR_EVTSEL_BOTH      (2 << 24)
54 #define         ATMEL_PIO_CFGR_EVTSEL_LOW       (3 << 24)
55 #define         ATMEL_PIO_CFGR_EVTSEL_HIGH      (4 << 24)
56 #define ATMEL_PIO_PDSR          0x0008
57 #define ATMEL_PIO_LOCKSR        0x000C
58 #define ATMEL_PIO_SODR          0x0010
59 #define ATMEL_PIO_CODR          0x0014
60 #define ATMEL_PIO_ODSR          0x0018
61 #define ATMEL_PIO_IER           0x0020
62 #define ATMEL_PIO_IDR           0x0024
63 #define ATMEL_PIO_IMR           0x0028
64 #define ATMEL_PIO_ISR           0x002C
65 #define ATMEL_PIO_IOFR          0x003C
66
67 #define ATMEL_PIO_NPINS_PER_BANK        32
68 #define ATMEL_PIO_BANK(pin_id)          (pin_id / ATMEL_PIO_NPINS_PER_BANK)
69 #define ATMEL_PIO_LINE(pin_id)          (pin_id % ATMEL_PIO_NPINS_PER_BANK)
70 #define ATMEL_PIO_BANK_OFFSET           0x40
71
72 #define ATMEL_GET_PIN_NO(pinfunc)       ((pinfunc) & 0xff)
73 #define ATMEL_GET_PIN_FUNC(pinfunc)     ((pinfunc >> 16) & 0xf)
74 #define ATMEL_GET_PIN_IOSET(pinfunc)    ((pinfunc >> 20) & 0xf)
75
76 struct atmel_pioctrl_data {
77         unsigned nbanks;
78 };
79
80 struct atmel_group {
81         const char *name;
82         u32 pin;
83 };
84
85 struct atmel_pin {
86         unsigned pin_id;
87         unsigned mux;
88         unsigned ioset;
89         unsigned bank;
90         unsigned line;
91         const char *device;
92 };
93
94 /**
95  * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
96  * @reg_base: base address of the controller.
97  * @clk: clock of the controller.
98  * @nbanks: number of PIO groups, it can vary depending on the SoC.
99  * @pinctrl_dev: pinctrl device registered.
100  * @groups: groups table to provide group name and pin in the group to pinctrl.
101  * @group_names: group names table to provide all the group/pin names to
102  *     pinctrl or gpio.
103  * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line
104  *     fields are set at probe time. Other ones are set when parsing dt
105  *     pinctrl.
106  * @npins: number of pins.
107  * @gpio_chip: gpio chip registered.
108  * @irq_domain: irq domain for the gpio controller.
109  * @irqs: table containing the hw irq number of the bank. The index of the
110  *     table is the bank id.
111  * @dev: device entry for the Atmel PIO controller.
112  * @node: node of the Atmel PIO controller.
113  */
114 struct atmel_pioctrl {
115         void __iomem            *reg_base;
116         struct clk              *clk;
117         unsigned                nbanks;
118         struct pinctrl_dev      *pinctrl_dev;
119         struct atmel_group      *groups;
120         const char * const      *group_names;
121         struct atmel_pin        **pins;
122         unsigned                npins;
123         struct gpio_chip        *gpio_chip;
124         struct irq_domain       *irq_domain;
125         int                     *irqs;
126         unsigned                *pm_wakeup_sources;
127         unsigned                *pm_suspend_backup;
128         struct device           *dev;
129         struct device_node      *node;
130 };
131
132 static const char * const atmel_functions[] = {
133         "GPIO", "A", "B", "C", "D", "E", "F", "G"
134 };
135
136 /* --- GPIO --- */
137 static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl,
138                                     unsigned int bank, unsigned int reg)
139 {
140         return readl_relaxed(atmel_pioctrl->reg_base
141                              + ATMEL_PIO_BANK_OFFSET * bank + reg);
142 }
143
144 static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl,
145                              unsigned int bank, unsigned int reg,
146                              unsigned int val)
147 {
148         writel_relaxed(val, atmel_pioctrl->reg_base
149                        + ATMEL_PIO_BANK_OFFSET * bank + reg);
150 }
151
152 static void atmel_gpio_irq_ack(struct irq_data *d)
153 {
154         /*
155          * Nothing to do, interrupt is cleared when reading the status
156          * register.
157          */
158 }
159
160 static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type)
161 {
162         struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
163         struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
164         unsigned reg;
165
166         atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
167                          BIT(pin->line));
168         reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
169         reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK);
170
171         switch (type) {
172         case IRQ_TYPE_EDGE_RISING:
173                 irq_set_handler_locked(d, handle_edge_irq);
174                 reg |= ATMEL_PIO_CFGR_EVTSEL_RISING;
175                 break;
176         case IRQ_TYPE_EDGE_FALLING:
177                 irq_set_handler_locked(d, handle_edge_irq);
178                 reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING;
179                 break;
180         case IRQ_TYPE_EDGE_BOTH:
181                 irq_set_handler_locked(d, handle_edge_irq);
182                 reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH;
183                 break;
184         case IRQ_TYPE_LEVEL_LOW:
185                 irq_set_handler_locked(d, handle_level_irq);
186                 reg |= ATMEL_PIO_CFGR_EVTSEL_LOW;
187                 break;
188         case IRQ_TYPE_LEVEL_HIGH:
189                 irq_set_handler_locked(d, handle_level_irq);
190                 reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH;
191                 break;
192         case IRQ_TYPE_NONE:
193         default:
194                 return -EINVAL;
195         }
196
197         atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
198
199         return 0;
200 }
201
202 static void atmel_gpio_irq_mask(struct irq_data *d)
203 {
204         struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
205         struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
206
207         atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR,
208                          BIT(pin->line));
209 }
210
211 static void atmel_gpio_irq_unmask(struct irq_data *d)
212 {
213         struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
214         struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
215
216         atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER,
217                          BIT(pin->line));
218 }
219
220 #ifdef CONFIG_PM_SLEEP
221
222 static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
223 {
224         struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
225         int bank = ATMEL_PIO_BANK(d->hwirq);
226         int line = ATMEL_PIO_LINE(d->hwirq);
227
228         /* The gpio controller has one interrupt line per bank. */
229         irq_set_irq_wake(atmel_pioctrl->irqs[bank], on);
230
231         if (on)
232                 atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line);
233         else
234                 atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line));
235
236         return 0;
237 }
238 #else
239 #define atmel_gpio_irq_set_wake NULL
240 #endif /* CONFIG_PM_SLEEP */
241
242 static struct irq_chip atmel_gpio_irq_chip = {
243         .name           = "GPIO",
244         .irq_ack        = atmel_gpio_irq_ack,
245         .irq_mask       = atmel_gpio_irq_mask,
246         .irq_unmask     = atmel_gpio_irq_unmask,
247         .irq_set_type   = atmel_gpio_irq_set_type,
248         .irq_set_wake   = atmel_gpio_irq_set_wake,
249 };
250
251 static void atmel_gpio_irq_handler(struct irq_desc *desc)
252 {
253         unsigned int irq = irq_desc_get_irq(desc);
254         struct atmel_pioctrl *atmel_pioctrl = irq_desc_get_handler_data(desc);
255         struct irq_chip *chip = irq_desc_get_chip(desc);
256         unsigned long isr;
257         int n, bank = -1;
258
259         /* Find from which bank is the irq received. */
260         for (n = 0; n < atmel_pioctrl->nbanks; n++) {
261                 if (atmel_pioctrl->irqs[n] == irq) {
262                         bank = n;
263                         break;
264                 }
265         }
266
267         if (bank < 0) {
268                 dev_err(atmel_pioctrl->dev,
269                         "no bank associated to irq %u\n", irq);
270                 return;
271         }
272
273         chained_irq_enter(chip, desc);
274
275         for (;;) {
276                 isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
277                                                      ATMEL_PIO_ISR);
278                 isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
279                                                       ATMEL_PIO_IMR);
280                 if (!isr)
281                         break;
282
283                 for_each_set_bit(n, &isr, BITS_PER_LONG)
284                         generic_handle_irq(gpio_to_irq(bank *
285                                         ATMEL_PIO_NPINS_PER_BANK + n));
286         }
287
288         chained_irq_exit(chip, desc);
289 }
290
291 static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
292 {
293         struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev);
294         struct atmel_pin *pin = atmel_pioctrl->pins[offset];
295         unsigned reg;
296
297         atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
298                          BIT(pin->line));
299         reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
300         reg &= ~ATMEL_PIO_DIR_MASK;
301         atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
302
303         return 0;
304 }
305
306 static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset)
307 {
308         struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev);
309         struct atmel_pin *pin = atmel_pioctrl->pins[offset];
310         unsigned reg;
311
312         reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR);
313
314         return !!(reg & BIT(pin->line));
315 }
316
317 static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
318                                        int value)
319 {
320         struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev);
321         struct atmel_pin *pin = atmel_pioctrl->pins[offset];
322         unsigned reg;
323
324         atmel_gpio_write(atmel_pioctrl, pin->bank,
325                          value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
326                          BIT(pin->line));
327
328         atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
329                          BIT(pin->line));
330         reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
331         reg |= ATMEL_PIO_DIR_MASK;
332         atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
333
334         return 0;
335 }
336
337 static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
338 {
339         struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev);
340         struct atmel_pin *pin = atmel_pioctrl->pins[offset];
341
342         atmel_gpio_write(atmel_pioctrl, pin->bank,
343                          val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
344                          BIT(pin->line));
345 }
346
347 static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
348 {
349         struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev);
350
351         return irq_find_mapping(atmel_pioctrl->irq_domain, offset);
352 }
353
354 static struct gpio_chip atmel_gpio_chip = {
355         .direction_input        = atmel_gpio_direction_input,
356         .get                    = atmel_gpio_get,
357         .direction_output       = atmel_gpio_direction_output,
358         .set                    = atmel_gpio_set,
359         .to_irq                 = atmel_gpio_to_irq,
360         .base                   = 0,
361 };
362
363 /* --- PINCTRL --- */
364 static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev,
365                                           unsigned pin_id)
366 {
367         struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
368         unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
369         unsigned line = atmel_pioctrl->pins[pin_id]->line;
370         void __iomem *addr = atmel_pioctrl->reg_base
371                              + bank * ATMEL_PIO_BANK_OFFSET;
372
373         writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
374         /* Have to set MSKR first, to access the right pin CFGR. */
375         wmb();
376
377         return readl_relaxed(addr + ATMEL_PIO_CFGR);
378 }
379
380 static void atmel_pin_config_write(struct pinctrl_dev *pctldev,
381                                    unsigned pin_id, u32 conf)
382 {
383         struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
384         unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
385         unsigned line = atmel_pioctrl->pins[pin_id]->line;
386         void __iomem *addr = atmel_pioctrl->reg_base
387                              + bank * ATMEL_PIO_BANK_OFFSET;
388
389         writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
390         /* Have to set MSKR first, to access the right pin CFGR. */
391         wmb();
392         writel_relaxed(conf, addr + ATMEL_PIO_CFGR);
393 }
394
395 static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev)
396 {
397         struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
398
399         return atmel_pioctrl->npins;
400 }
401
402 static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev,
403                                              unsigned selector)
404 {
405         struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
406
407         return atmel_pioctrl->groups[selector].name;
408 }
409
410 static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev,
411                                      unsigned selector, const unsigned **pins,
412                                      unsigned *num_pins)
413 {
414         struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
415
416         *pins = (unsigned *)&atmel_pioctrl->groups[selector].pin;
417         *num_pins = 1;
418
419         return 0;
420 }
421
422 struct atmel_group *atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev,
423                                                  unsigned pin)
424 {
425         struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
426         int i;
427
428         for (i = 0; i < atmel_pioctrl->npins; i++) {
429                 struct atmel_group *grp = atmel_pioctrl->groups + i;
430
431                 if (grp->pin == pin)
432                         return grp;
433         }
434
435         return NULL;
436 }
437
438 static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev,
439                                     struct device_node *np,
440                                     u32 pinfunc, const char **grp_name,
441                                     const char **func_name)
442 {
443         struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
444         unsigned pin_id, func_id;
445         struct atmel_group *grp;
446
447         pin_id = ATMEL_GET_PIN_NO(pinfunc);
448         func_id = ATMEL_GET_PIN_FUNC(pinfunc);
449
450         if (func_id >= ARRAY_SIZE(atmel_functions))
451                 return -EINVAL;
452
453         *func_name = atmel_functions[func_id];
454
455         grp = atmel_pctl_find_group_by_pin(pctldev, pin_id);
456         if (!grp)
457                 return -EINVAL;
458         *grp_name = grp->name;
459
460         atmel_pioctrl->pins[pin_id]->mux = func_id;
461         atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc);
462         /* Want the device name not the group one. */
463         if (np->parent == atmel_pioctrl->node)
464                 atmel_pioctrl->pins[pin_id]->device = np->name;
465         else
466                 atmel_pioctrl->pins[pin_id]->device = np->parent->name;
467
468         return 0;
469 }
470
471 static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
472                                         struct device_node *np,
473                                         struct pinctrl_map **map,
474                                         unsigned *reserved_maps,
475                                         unsigned *num_maps)
476 {
477         unsigned num_pins, num_configs, reserve;
478         unsigned long *configs;
479         struct property *pins;
480         bool has_config;
481         u32 pinfunc;
482         int ret, i;
483
484         pins = of_find_property(np, "pinmux", NULL);
485         if (!pins)
486                 return -EINVAL;
487
488         ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
489                                               &num_configs);
490         if (ret < 0) {
491                 dev_err(pctldev->dev, "%s: could not parse node property\n",
492                         of_node_full_name(np));
493                 return ret;
494         }
495
496         if (num_configs)
497                 has_config = true;
498
499         num_pins = pins->length / sizeof(u32);
500         if (!num_pins) {
501                 dev_err(pctldev->dev, "no pins found in node %s\n",
502                         of_node_full_name(np));
503                 ret = -EINVAL;
504                 goto exit;
505         }
506
507         /*
508          * Reserve maps, at least there is a mux map and an optional conf
509          * map for each pin.
510          */
511         reserve = 1;
512         if (has_config && num_pins >= 1)
513                 reserve++;
514         reserve *= num_pins;
515         ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
516                                         reserve);
517         if (ret < 0)
518                 goto exit;
519
520         for (i = 0; i < num_pins; i++) {
521                 const char *group, *func;
522
523                 ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc);
524                 if (ret)
525                         goto exit;
526
527                 ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group,
528                                                &func);
529                 if (ret)
530                         goto exit;
531
532                 pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps,
533                                           group, func);
534
535                 if (has_config) {
536                         ret = pinctrl_utils_add_map_configs(pctldev, map,
537                                         reserved_maps, num_maps, group,
538                                         configs, num_configs,
539                                         PIN_MAP_TYPE_CONFIGS_GROUP);
540                         if (ret < 0)
541                                 goto exit;
542                 }
543         }
544
545 exit:
546         kfree(configs);
547         return ret;
548 }
549
550 static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
551                                      struct device_node *np_config,
552                                      struct pinctrl_map **map,
553                                      unsigned *num_maps)
554 {
555         struct device_node *np;
556         unsigned reserved_maps;
557         int ret;
558
559         *map = NULL;
560         *num_maps = 0;
561         reserved_maps = 0;
562
563         /*
564          * If all the pins of a device have the same configuration (or no one),
565          * it is useless to add a subnode, so directly parse node referenced by
566          * phandle.
567          */
568         ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map,
569                                            &reserved_maps, num_maps);
570         if (ret) {
571                 for_each_child_of_node(np_config, np) {
572                         ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map,
573                                                     &reserved_maps, num_maps);
574                         if (ret < 0)
575                                 break;
576                 }
577         }
578
579         if (ret < 0) {
580                 pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
581                 dev_err(pctldev->dev, "can't create maps for node %s\n",
582                         np_config->full_name);
583         }
584
585         return ret;
586 }
587
588 static const struct pinctrl_ops atmel_pctlops = {
589         .get_groups_count       = atmel_pctl_get_groups_count,
590         .get_group_name         = atmel_pctl_get_group_name,
591         .get_group_pins         = atmel_pctl_get_group_pins,
592         .dt_node_to_map         = atmel_pctl_dt_node_to_map,
593         .dt_free_map            = pinctrl_utils_dt_free_map,
594 };
595
596 static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev)
597 {
598         return ARRAY_SIZE(atmel_functions);
599 }
600
601 static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev,
602                                                unsigned selector)
603 {
604         return atmel_functions[selector];
605 }
606
607 static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev,
608                                          unsigned selector,
609                                          const char * const **groups,
610                                          unsigned * const num_groups)
611 {
612         struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
613
614         *groups = atmel_pioctrl->group_names;
615         *num_groups = atmel_pioctrl->npins;
616
617         return 0;
618 }
619
620 static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev,
621                              unsigned function,
622                              unsigned group)
623 {
624         struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
625         unsigned pin;
626         u32 conf;
627
628         dev_dbg(pctldev->dev, "enable function %s group %s\n",
629                 atmel_functions[function], atmel_pioctrl->groups[group].name);
630
631         pin = atmel_pioctrl->groups[group].pin;
632         conf = atmel_pin_config_read(pctldev, pin);
633         conf &= (~ATMEL_PIO_CFGR_FUNC_MASK);
634         conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK);
635         dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf);
636         atmel_pin_config_write(pctldev, pin, conf);
637
638         return 0;
639 }
640
641 static const struct pinmux_ops atmel_pmxops = {
642         .get_functions_count    = atmel_pmx_get_functions_count,
643         .get_function_name      = atmel_pmx_get_function_name,
644         .get_function_groups    = atmel_pmx_get_function_groups,
645         .set_mux                = atmel_pmx_set_mux,
646 };
647
648 static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
649                                            unsigned group,
650                                            unsigned long *config)
651 {
652         struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
653         unsigned param = pinconf_to_config_param(*config), arg = 0;
654         struct atmel_group *grp = atmel_pioctrl->groups + group;
655         unsigned pin_id = grp->pin;
656         u32 res;
657
658         res = atmel_pin_config_read(pctldev, pin_id);
659
660         switch (param) {
661         case PIN_CONFIG_BIAS_PULL_UP:
662                 if (!(res & ATMEL_PIO_PUEN_MASK))
663                         return -EINVAL;
664                 arg = 1;
665                 break;
666         case PIN_CONFIG_BIAS_PULL_DOWN:
667                 if ((res & ATMEL_PIO_PUEN_MASK) ||
668                     (!(res & ATMEL_PIO_PDEN_MASK)))
669                         return -EINVAL;
670                 arg = 1;
671                 break;
672         case PIN_CONFIG_BIAS_DISABLE:
673                 if ((res & ATMEL_PIO_PUEN_MASK) ||
674                     ((res & ATMEL_PIO_PDEN_MASK)))
675                         return -EINVAL;
676                 arg = 1;
677                 break;
678         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
679                 if (!(res & ATMEL_PIO_OPD_MASK))
680                         return -EINVAL;
681                 arg = 1;
682                 break;
683         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
684                 if (!(res & ATMEL_PIO_SCHMITT_MASK))
685                         return -EINVAL;
686                 arg = 1;
687                 break;
688         default:
689                 return -ENOTSUPP;
690         }
691
692         *config = pinconf_to_config_packed(param, arg);
693         return 0;
694 }
695
696 static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
697                                            unsigned group,
698                                            unsigned long *configs,
699                                            unsigned num_configs)
700 {
701         struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
702         struct atmel_group *grp = atmel_pioctrl->groups + group;
703         unsigned bank, pin, pin_id = grp->pin;
704         u32 mask, conf = 0;
705         int i;
706
707         conf = atmel_pin_config_read(pctldev, pin_id);
708
709         for (i = 0; i < num_configs; i++) {
710                 unsigned param = pinconf_to_config_param(configs[i]);
711                 unsigned arg = pinconf_to_config_argument(configs[i]);
712
713                 dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
714                         __func__, pin_id, configs[i]);
715
716                 switch (param) {
717                 case PIN_CONFIG_BIAS_DISABLE:
718                         conf &= (~ATMEL_PIO_PUEN_MASK);
719                         conf &= (~ATMEL_PIO_PDEN_MASK);
720                         break;
721                 case PIN_CONFIG_BIAS_PULL_UP:
722                         conf |= ATMEL_PIO_PUEN_MASK;
723                         break;
724                 case PIN_CONFIG_BIAS_PULL_DOWN:
725                         conf |= ATMEL_PIO_PDEN_MASK;
726                         break;
727                 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
728                         if (arg == 0)
729                                 conf &= (~ATMEL_PIO_OPD_MASK);
730                         else
731                                 conf |= ATMEL_PIO_OPD_MASK;
732                         break;
733                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
734                         if (arg == 0)
735                                 conf |= ATMEL_PIO_SCHMITT_MASK;
736                         else
737                                 conf &= (~ATMEL_PIO_SCHMITT_MASK);
738                         break;
739                 case PIN_CONFIG_INPUT_DEBOUNCE:
740                         if (arg == 0) {
741                                 conf &= (~ATMEL_PIO_IFEN_MASK);
742                                 conf &= (~ATMEL_PIO_IFSCEN_MASK);
743                         } else {
744                                 /*
745                                  * We don't care about the debounce value for several reasons:
746                                  * - can't have different debounce periods inside a same group,
747                                  * - the register to configure this period is a secure register.
748                                  * The debouncing filter can filter a pulse with a duration of less
749                                  * than 1/2 slow clock period.
750                                  */
751                                 conf |= ATMEL_PIO_IFEN_MASK;
752                                 conf |= ATMEL_PIO_IFSCEN_MASK;
753                         }
754                         break;
755                 case PIN_CONFIG_OUTPUT:
756                         conf |= ATMEL_PIO_DIR_MASK;
757                         bank = ATMEL_PIO_BANK(pin_id);
758                         pin = ATMEL_PIO_LINE(pin_id);
759                         mask = 1 << pin;
760
761                         if (arg == 0) {
762                                 writel_relaxed(mask, atmel_pioctrl->reg_base +
763                                         bank * ATMEL_PIO_BANK_OFFSET +
764                                         ATMEL_PIO_CODR);
765                         } else {
766                                 writel_relaxed(mask, atmel_pioctrl->reg_base +
767                                         bank * ATMEL_PIO_BANK_OFFSET +
768                                         ATMEL_PIO_SODR);
769                         }
770                         break;
771                 default:
772                         dev_warn(pctldev->dev,
773                                  "unsupported configuration parameter: %u\n",
774                                  param);
775                         continue;
776                 }
777         }
778
779         dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf);
780         atmel_pin_config_write(pctldev, pin_id, conf);
781
782         return 0;
783 }
784
785 static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
786                                            struct seq_file *s, unsigned pin_id)
787 {
788         struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
789         u32 conf;
790
791         if (!atmel_pioctrl->pins[pin_id]->device)
792                 return;
793
794         if (atmel_pioctrl->pins[pin_id])
795                 seq_printf(s, " (%s, ioset %u) ",
796                            atmel_pioctrl->pins[pin_id]->device,
797                            atmel_pioctrl->pins[pin_id]->ioset);
798
799         conf = atmel_pin_config_read(pctldev, pin_id);
800         if (conf & ATMEL_PIO_PUEN_MASK)
801                 seq_printf(s, "%s ", "pull-up");
802         if (conf & ATMEL_PIO_PDEN_MASK)
803                 seq_printf(s, "%s ", "pull-down");
804         if (conf & ATMEL_PIO_IFEN_MASK)
805                 seq_printf(s, "%s ", "debounce");
806         if (conf & ATMEL_PIO_OPD_MASK)
807                 seq_printf(s, "%s ", "open-drain");
808         if (conf & ATMEL_PIO_SCHMITT_MASK)
809                 seq_printf(s, "%s ", "schmitt");
810 }
811
812 static const struct pinconf_ops atmel_confops = {
813         .pin_config_group_get   = atmel_conf_pin_config_group_get,
814         .pin_config_group_set   = atmel_conf_pin_config_group_set,
815         .pin_config_dbg_show    = atmel_conf_pin_config_dbg_show,
816 };
817
818 static struct pinctrl_desc atmel_pinctrl_desc = {
819         .name           = "atmel_pinctrl",
820         .confops        = &atmel_confops,
821         .pctlops        = &atmel_pctlops,
822         .pmxops         = &atmel_pmxops,
823 };
824
825 static int atmel_pctrl_suspend(struct device *dev)
826 {
827         struct platform_device *pdev = to_platform_device(dev);
828         struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
829         int i;
830
831         /*
832          * For each bank, save IMR to restore it later and disable all GPIO
833          * interrupts excepting the ones marked as wakeup sources.
834          */
835         for (i = 0; i < atmel_pioctrl->nbanks; i++) {
836                 atmel_pioctrl->pm_suspend_backup[i] =
837                         atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR);
838                 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR,
839                                  ~atmel_pioctrl->pm_wakeup_sources[i]);
840         }
841
842         return 0;
843 }
844
845 static int atmel_pctrl_resume(struct device *dev)
846 {
847         struct platform_device *pdev = to_platform_device(dev);
848         struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
849         int i;
850
851         for (i = 0; i < atmel_pioctrl->nbanks; i++)
852                 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER,
853                                  atmel_pioctrl->pm_suspend_backup[i]);
854
855         return 0;
856 }
857
858 static const struct dev_pm_ops atmel_pctrl_pm_ops = {
859         SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume)
860 };
861
862 /*
863  * The number of banks can be different from a SoC to another one.
864  * We can have up to 16 banks.
865  */
866 static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
867         .nbanks         = 4,
868 };
869
870 static const struct of_device_id atmel_pctrl_of_match[] = {
871         {
872                 .compatible = "atmel,sama5d2-pinctrl",
873                 .data = &atmel_sama5d2_pioctrl_data,
874         }, {
875                 /* sentinel */
876         }
877 };
878 MODULE_DEVICE_TABLE(of, atmel_pctrl_of_match);
879
880 static int atmel_pinctrl_probe(struct platform_device *pdev)
881 {
882         struct device *dev = &pdev->dev;
883         struct pinctrl_pin_desc *pin_desc;
884         const char **group_names;
885         const struct of_device_id *match;
886         int i, ret;
887         struct resource *res;
888         struct atmel_pioctrl *atmel_pioctrl;
889         struct atmel_pioctrl_data *atmel_pioctrl_data;
890
891         atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL);
892         if (!atmel_pioctrl)
893                 return -ENOMEM;
894         atmel_pioctrl->dev = dev;
895         atmel_pioctrl->node = dev->of_node;
896         platform_set_drvdata(pdev, atmel_pioctrl);
897
898         match = of_match_node(atmel_pctrl_of_match, dev->of_node);
899         if (!match) {
900                 dev_err(dev, "unknown compatible string\n");
901                 return -ENODEV;
902         }
903         atmel_pioctrl_data = (struct atmel_pioctrl_data *)match->data;
904         atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;
905         atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;
906
907         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
908         if (!res) {
909                 dev_err(dev, "unable to get atmel pinctrl resource\n");
910                 return -EINVAL;
911         }
912         atmel_pioctrl->reg_base = devm_ioremap_resource(dev, res);
913         if (IS_ERR(atmel_pioctrl->reg_base))
914                 return -EINVAL;
915
916         atmel_pioctrl->clk = devm_clk_get(dev, NULL);
917         if (IS_ERR(atmel_pioctrl->clk)) {
918                 dev_err(dev, "failed to get clock\n");
919                 return PTR_ERR(atmel_pioctrl->clk);
920         }
921
922         atmel_pioctrl->pins = devm_kzalloc(dev, sizeof(*atmel_pioctrl->pins)
923                         * atmel_pioctrl->npins, GFP_KERNEL);
924         if (!atmel_pioctrl->pins)
925                 return -ENOMEM;
926
927         pin_desc = devm_kzalloc(dev, sizeof(*pin_desc)
928                         * atmel_pioctrl->npins, GFP_KERNEL);
929         if (!pin_desc)
930                 return -ENOMEM;
931         atmel_pinctrl_desc.pins = pin_desc;
932         atmel_pinctrl_desc.npins = atmel_pioctrl->npins;
933
934         /* One pin is one group since a pin can achieve all functions. */
935         group_names = devm_kzalloc(dev, sizeof(*group_names)
936                         * atmel_pioctrl->npins, GFP_KERNEL);
937         if (!group_names)
938                 return -ENOMEM;
939         atmel_pioctrl->group_names = group_names;
940
941         atmel_pioctrl->groups = devm_kzalloc(&pdev->dev,
942                         sizeof(*atmel_pioctrl->groups) * atmel_pioctrl->npins,
943                         GFP_KERNEL);
944         if (!atmel_pioctrl->groups)
945                 return -ENOMEM;
946         for (i = 0 ; i < atmel_pioctrl->npins; i++) {
947                 struct atmel_group *group = atmel_pioctrl->groups + i;
948                 unsigned bank = ATMEL_PIO_BANK(i);
949                 unsigned line = ATMEL_PIO_LINE(i);
950
951                 atmel_pioctrl->pins[i] = devm_kzalloc(dev,
952                                 sizeof(**atmel_pioctrl->pins), GFP_KERNEL);
953                 if (!atmel_pioctrl->pins[i])
954                         return -ENOMEM;
955
956                 atmel_pioctrl->pins[i]->pin_id = i;
957                 atmel_pioctrl->pins[i]->bank = bank;
958                 atmel_pioctrl->pins[i]->line = line;
959
960                 pin_desc[i].number = i;
961                 /* Pin naming convention: P(bank_name)(bank_pin_number). */
962                 pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
963                                              bank + 'A', line);
964
965                 group->name = group_names[i] = pin_desc[i].name;
966                 group->pin = pin_desc[i].number;
967
968                 dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line);
969         }
970
971         atmel_pioctrl->gpio_chip = &atmel_gpio_chip;
972         atmel_pioctrl->gpio_chip->of_node = dev->of_node;
973         atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins;
974         atmel_pioctrl->gpio_chip->label = dev_name(dev);
975         atmel_pioctrl->gpio_chip->dev = dev;
976         atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names;
977
978         atmel_pioctrl->pm_wakeup_sources = devm_kzalloc(dev,
979                         sizeof(*atmel_pioctrl->pm_wakeup_sources)
980                         * atmel_pioctrl->nbanks, GFP_KERNEL);
981         if (!atmel_pioctrl->pm_wakeup_sources)
982                 return -ENOMEM;
983
984         atmel_pioctrl->pm_suspend_backup = devm_kzalloc(dev,
985                         sizeof(*atmel_pioctrl->pm_suspend_backup)
986                         * atmel_pioctrl->nbanks, GFP_KERNEL);
987         if (!atmel_pioctrl->pm_suspend_backup)
988                 return -ENOMEM;
989
990         atmel_pioctrl->irqs = devm_kzalloc(dev, sizeof(*atmel_pioctrl->irqs)
991                         * atmel_pioctrl->nbanks, GFP_KERNEL);
992         if (!atmel_pioctrl->irqs)
993                 return -ENOMEM;
994
995         /* There is one controller but each bank has its own irq line. */
996         for (i = 0; i < atmel_pioctrl->nbanks; i++) {
997                 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
998                 if (!res) {
999                         dev_err(dev, "missing irq resource for group %c\n",
1000                                 'A' + i);
1001                         return -EINVAL;
1002                 }
1003                 atmel_pioctrl->irqs[i] = res->start;
1004                 irq_set_chained_handler(res->start, atmel_gpio_irq_handler);
1005                 irq_set_handler_data(res->start, atmel_pioctrl);
1006                 dev_dbg(dev, "bank %i: irq=%pr\n", i, res);
1007         }
1008
1009         atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node,
1010                         atmel_pioctrl->gpio_chip->ngpio,
1011                         &irq_domain_simple_ops, NULL);
1012         if (!atmel_pioctrl->irq_domain) {
1013                 dev_err(dev, "can't add the irq domain\n");
1014                 return -ENODEV;
1015         }
1016         atmel_pioctrl->irq_domain->name = "atmel gpio";
1017
1018         for (i = 0; i < atmel_pioctrl->npins; i++) {
1019                 int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i);
1020
1021                 irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip,
1022                                          handle_simple_irq);
1023                 irq_set_chip_data(irq, atmel_pioctrl);
1024                 dev_dbg(dev,
1025                         "atmel gpio irq domain: hwirq: %d, linux irq: %d\n",
1026                         i, irq);
1027         }
1028
1029         ret = clk_prepare_enable(atmel_pioctrl->clk);
1030         if (ret) {
1031                 dev_err(dev, "failed to prepare and enable clock\n");
1032                 goto clk_prepare_enable_error;
1033         }
1034
1035         atmel_pioctrl->pinctrl_dev = pinctrl_register(&atmel_pinctrl_desc,
1036                                                       &pdev->dev,
1037                                                       atmel_pioctrl);
1038         if (!atmel_pioctrl->pinctrl_dev) {
1039                 dev_err(dev, "pinctrl registration failed\n");
1040                 goto pinctrl_register_error;
1041         }
1042
1043         ret = gpiochip_add(atmel_pioctrl->gpio_chip);
1044         if (ret) {
1045                 dev_err(dev, "failed to add gpiochip\n");
1046                 goto gpiochip_add_error;
1047         }
1048
1049         ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev),
1050                                      0, 0, atmel_pioctrl->gpio_chip->ngpio);
1051         if (ret) {
1052                 dev_err(dev, "failed to add gpio pin range\n");
1053                 goto gpiochip_add_pin_range_error;
1054         }
1055
1056         dev_info(&pdev->dev, "atmel pinctrl initialized\n");
1057
1058         return 0;
1059
1060 clk_prepare_enable_error:
1061         irq_domain_remove(atmel_pioctrl->irq_domain);
1062 pinctrl_register_error:
1063         clk_disable_unprepare(atmel_pioctrl->clk);
1064 gpiochip_add_error:
1065         pinctrl_unregister(atmel_pioctrl->pinctrl_dev);
1066 gpiochip_add_pin_range_error:
1067         gpiochip_remove(atmel_pioctrl->gpio_chip);
1068
1069         return ret;
1070 }
1071
1072 int atmel_pinctrl_remove(struct platform_device *pdev)
1073 {
1074         struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
1075
1076         irq_domain_remove(atmel_pioctrl->irq_domain);
1077         clk_disable_unprepare(atmel_pioctrl->clk);
1078         pinctrl_unregister(atmel_pioctrl->pinctrl_dev);
1079         gpiochip_remove(atmel_pioctrl->gpio_chip);
1080
1081         return 0;
1082 }
1083
1084 static struct platform_driver atmel_pinctrl_driver = {
1085         .driver = {
1086                 .name = "pinctrl-at91-pio4",
1087                 .of_match_table = atmel_pctrl_of_match,
1088                 .pm = &atmel_pctrl_pm_ops,
1089         },
1090         .probe = atmel_pinctrl_probe,
1091         .remove = atmel_pinctrl_remove,
1092 };
1093 module_platform_driver(atmel_pinctrl_driver);
1094
1095 MODULE_AUTHOR(Ludovic Desroches <ludovic.desroches@atmel.com>);
1096 MODULE_DESCRIPTION("Atmel PIO4 pinctrl driver");
1097 MODULE_LICENSE("GPL v2");