2 * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver.
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/gpio/driver.h>
18 #include <linux/module.h>
20 #include <linux/of_address.h>
21 #include <linux/of_device.h>
22 #include <linux/of_irq.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pinctrl/machine.h>
25 #include <linux/pinctrl/pinconf.h>
26 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/platform_device.h>
30 #include <linux/slab.h>
31 #include <linux/bitops.h>
32 #include <linux/regmap.h>
33 #include <linux/mfd/syscon.h>
34 #include <linux/delay.h>
35 #include <linux/interrupt.h>
37 #include <dt-bindings/pinctrl/mt65xx.h>
40 #include "../pinconf.h"
41 #include "../pinctrl-utils.h"
42 #include "pinctrl-mtk-common.h"
44 #define MAX_GPIO_MODE_PER_REG 5
45 #define GPIO_MODE_BITS 3
46 #define GPIO_MODE_PREFIX "GPIO"
48 static const char * const mtk_gpio_functions[] = {
49 "func0", "func1", "func2", "func3",
50 "func4", "func5", "func6", "func7",
51 "func8", "func9", "func10", "func11",
52 "func12", "func13", "func14", "func15",
56 * There are two base address for pull related configuration
57 * in mt8135, and different GPIO pins use different base address.
58 * When pin number greater than type1_start and less than type1_end,
59 * should use the second base address.
61 static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl,
64 if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end)
69 static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin)
71 /* Different SoC has different mask and port shift. */
72 return ((pin >> 4) & pctl->devdata->port_mask)
73 << pctl->devdata->port_shf;
76 static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
77 struct pinctrl_gpio_range *range, unsigned offset,
80 unsigned int reg_addr;
82 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
84 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
85 bit = BIT(offset & 0xf);
87 if (pctl->devdata->spec_dir_set)
88 pctl->devdata->spec_dir_set(®_addr, offset);
91 /* Different SoC has different alignment offset. */
92 reg_addr = CLR_ADDR(reg_addr, pctl);
94 reg_addr = SET_ADDR(reg_addr, pctl);
96 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
100 static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
102 unsigned int reg_addr;
104 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
106 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset;
107 bit = BIT(offset & 0xf);
110 reg_addr = SET_ADDR(reg_addr, pctl);
112 reg_addr = CLR_ADDR(reg_addr, pctl);
114 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
117 static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
118 int value, enum pin_config_param arg)
120 unsigned int reg_addr, offset;
124 * Due to some soc are not support ies/smt config, add this special
125 * control to handle it.
127 if (!pctl->devdata->spec_ies_smt_set &&
128 pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT &&
129 arg == PIN_CONFIG_INPUT_ENABLE)
132 if (!pctl->devdata->spec_ies_smt_set &&
133 pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT &&
134 arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
138 * Due to some pins are irregular, their input enable and smt
139 * control register are discontinuous, so we need this special handle.
141 if (pctl->devdata->spec_ies_smt_set) {
142 return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
143 pin, pctl->devdata->port_align, value, arg);
146 bit = BIT(pin & 0xf);
148 if (arg == PIN_CONFIG_INPUT_ENABLE)
149 offset = pctl->devdata->ies_offset;
151 offset = pctl->devdata->smt_offset;
154 reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
156 reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
158 regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
162 int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
163 const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
164 unsigned int pin, unsigned char align, int value)
166 unsigned int i, reg_addr, bit;
168 for (i = 0; i < info_num; i++) {
169 if (pin >= ies_smt_infos[i].start &&
170 pin <= ies_smt_infos[i].end) {
179 reg_addr = ies_smt_infos[i].offset + align;
181 reg_addr = ies_smt_infos[i].offset + (align << 1);
183 bit = BIT(ies_smt_infos[i].bit);
184 regmap_write(regmap, reg_addr, bit);
188 static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin(
189 struct mtk_pinctrl *pctl, unsigned long pin) {
192 for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) {
193 const struct mtk_pin_drv_grp *pin_drv =
194 pctl->devdata->pin_drv_grp + i;
195 if (pin == pin_drv->pin)
202 static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl,
203 unsigned int pin, unsigned char driving)
205 const struct mtk_pin_drv_grp *pin_drv;
207 unsigned int bits, mask, shift;
208 const struct mtk_drv_group_desc *drv_grp;
210 if (pin >= pctl->devdata->npins)
213 pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin);
214 if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls)
217 drv_grp = pctl->devdata->grp_desc + pin_drv->grp;
218 if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv
219 && !(driving % drv_grp->step)) {
220 val = driving / drv_grp->step - 1;
221 bits = drv_grp->high_bit - drv_grp->low_bit + 1;
222 mask = BIT(bits) - 1;
223 shift = pin_drv->bit + drv_grp->low_bit;
226 return regmap_update_bits(mtk_get_regmap(pctl, pin),
227 pin_drv->offset, mask, val);
233 int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
234 const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
235 unsigned int info_num, unsigned int pin,
236 unsigned char align, bool isup, unsigned int r1r0)
239 unsigned int reg_pupd, reg_set, reg_rst;
240 unsigned int bit_pupd, bit_r0, bit_r1;
241 const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin;
244 for (i = 0; i < info_num; i++) {
245 if (pin == pupd_infos[i].pin) {
254 spec_pupd_pin = pupd_infos + i;
255 reg_set = spec_pupd_pin->offset + align;
256 reg_rst = spec_pupd_pin->offset + (align << 1);
263 bit_pupd = BIT(spec_pupd_pin->pupd_bit);
264 regmap_write(regmap, reg_pupd, bit_pupd);
266 bit_r0 = BIT(spec_pupd_pin->r0_bit);
267 bit_r1 = BIT(spec_pupd_pin->r1_bit);
270 case MTK_PUPD_SET_R1R0_00:
271 regmap_write(regmap, reg_rst, bit_r0);
272 regmap_write(regmap, reg_rst, bit_r1);
274 case MTK_PUPD_SET_R1R0_01:
275 regmap_write(regmap, reg_set, bit_r0);
276 regmap_write(regmap, reg_rst, bit_r1);
278 case MTK_PUPD_SET_R1R0_10:
279 regmap_write(regmap, reg_rst, bit_r0);
280 regmap_write(regmap, reg_set, bit_r1);
282 case MTK_PUPD_SET_R1R0_11:
283 regmap_write(regmap, reg_set, bit_r0);
284 regmap_write(regmap, reg_set, bit_r1);
293 static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
294 unsigned int pin, bool enable, bool isup, unsigned int arg)
297 unsigned int reg_pullen, reg_pullsel;
300 /* Some pins' pull setting are very different,
301 * they have separate pull up/down bit, R0 and R1
302 * resistor bit, so we need this special handle.
304 if (pctl->devdata->spec_pull_set) {
305 ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
306 pin, pctl->devdata->port_align, isup, arg);
311 /* For generic pull config, default arg value should be 0 or 1. */
312 if (arg != 0 && arg != 1) {
313 dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n",
318 bit = BIT(pin & 0xf);
320 reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
321 pctl->devdata->pullen_offset, pctl);
323 reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
324 pctl->devdata->pullen_offset, pctl);
327 reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
328 pctl->devdata->pullsel_offset, pctl);
330 reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
331 pctl->devdata->pullsel_offset, pctl);
333 regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
334 regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
338 static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
339 unsigned int pin, enum pin_config_param param,
340 enum pin_config_param arg)
343 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
346 case PIN_CONFIG_BIAS_DISABLE:
347 ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
349 case PIN_CONFIG_BIAS_PULL_UP:
350 ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
352 case PIN_CONFIG_BIAS_PULL_DOWN:
353 ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
355 case PIN_CONFIG_INPUT_ENABLE:
356 mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
357 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
359 case PIN_CONFIG_OUTPUT:
360 mtk_gpio_set(pctl->chip, pin, arg);
361 ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
363 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
364 mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
365 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
367 case PIN_CONFIG_DRIVE_STRENGTH:
368 ret = mtk_pconf_set_driving(pctl, pin, arg);
377 static int mtk_pconf_group_get(struct pinctrl_dev *pctldev,
379 unsigned long *config)
381 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
383 *config = pctl->groups[group].config;
388 static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
389 unsigned long *configs, unsigned num_configs)
391 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
392 struct mtk_pinctrl_group *g = &pctl->groups[group];
395 for (i = 0; i < num_configs; i++) {
396 ret = mtk_pconf_parse_conf(pctldev, g->pin,
397 pinconf_to_config_param(configs[i]),
398 pinconf_to_config_argument(configs[i]));
402 g->config = configs[i];
408 static const struct pinconf_ops mtk_pconf_ops = {
409 .pin_config_group_get = mtk_pconf_group_get,
410 .pin_config_group_set = mtk_pconf_group_set,
413 static struct mtk_pinctrl_group *
414 mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin)
418 for (i = 0; i < pctl->ngroups; i++) {
419 struct mtk_pinctrl_group *grp = pctl->groups + i;
428 static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin(
429 struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum)
431 const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num;
432 const struct mtk_desc_function *func = pin->functions;
434 while (func && func->name) {
435 if (func->muxval == fnum)
443 static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl,
444 u32 pin_num, u32 fnum)
448 for (i = 0; i < pctl->devdata->npins; i++) {
449 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
451 if (pin->pin.number == pin_num) {
452 const struct mtk_desc_function *func =
455 while (func && func->name) {
456 if (func->muxval == fnum)
468 static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
469 u32 pin, u32 fnum, struct mtk_pinctrl_group *grp,
470 struct pinctrl_map **map, unsigned *reserved_maps,
475 if (*num_maps == *reserved_maps)
478 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
479 (*map)[*num_maps].data.mux.group = grp->name;
481 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
483 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
488 (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
494 static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
495 struct device_node *node,
496 struct pinctrl_map **map,
497 unsigned *reserved_maps,
500 struct property *pins;
501 u32 pinfunc, pin, func;
502 int num_pins, num_funcs, maps_per_pin;
503 unsigned long *configs;
504 unsigned int num_configs;
507 unsigned reserve = 0;
508 struct mtk_pinctrl_group *grp;
509 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
511 pins = of_find_property(node, "pinmux", NULL);
513 dev_err(pctl->dev, "missing pins property in node %s .\n",
518 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
526 num_pins = pins->length / sizeof(u32);
527 num_funcs = num_pins;
531 if (has_config && num_pins >= 1)
534 if (!num_pins || !maps_per_pin) {
539 reserve = num_pins * maps_per_pin;
541 err = pinctrl_utils_reserve_map(pctldev, map,
542 reserved_maps, num_maps, reserve);
546 for (i = 0; i < num_pins; i++) {
547 err = of_property_read_u32_index(node, "pinmux",
552 pin = MTK_GET_PIN_NO(pinfunc);
553 func = MTK_GET_PIN_FUNC(pinfunc);
555 if (pin >= pctl->devdata->npins ||
556 func >= ARRAY_SIZE(mtk_gpio_functions)) {
557 dev_err(pctl->dev, "invalid pins value.\n");
562 grp = mtk_pctrl_find_group_by_pin(pctl, pin);
564 dev_err(pctl->dev, "unable to match pin %d to group\n",
570 err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
571 reserved_maps, num_maps);
576 err = pinctrl_utils_add_map_configs(pctldev, map,
577 reserved_maps, num_maps, grp->name,
578 configs, num_configs,
579 PIN_MAP_TYPE_CONFIGS_GROUP);
592 static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
593 struct device_node *np_config,
594 struct pinctrl_map **map, unsigned *num_maps)
596 struct device_node *np;
597 unsigned reserved_maps;
604 for_each_child_of_node(np_config, np) {
605 ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
606 &reserved_maps, num_maps);
608 pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
617 static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
619 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
621 return pctl->ngroups;
624 static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
627 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
629 return pctl->groups[group].name;
632 static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
634 const unsigned **pins,
637 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
639 *pins = (unsigned *)&pctl->groups[group].pin;
645 static const struct pinctrl_ops mtk_pctrl_ops = {
646 .dt_node_to_map = mtk_pctrl_dt_node_to_map,
647 .dt_free_map = pinctrl_utils_dt_free_map,
648 .get_groups_count = mtk_pctrl_get_groups_count,
649 .get_group_name = mtk_pctrl_get_group_name,
650 .get_group_pins = mtk_pctrl_get_group_pins,
653 static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
655 return ARRAY_SIZE(mtk_gpio_functions);
658 static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
661 return mtk_gpio_functions[selector];
664 static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
666 const char * const **groups,
667 unsigned * const num_groups)
669 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
671 *groups = pctl->grp_names;
672 *num_groups = pctl->ngroups;
677 static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
678 unsigned long pin, unsigned long mode)
680 unsigned int reg_addr;
683 unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
684 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
686 if (pctl->devdata->spec_pinmux_set)
687 pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin),
690 reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf)
691 + pctl->devdata->pinmux_offset;
694 bit = pin % MAX_GPIO_MODE_PER_REG;
695 mask <<= (GPIO_MODE_BITS * bit);
696 val = (mode << (GPIO_MODE_BITS * bit));
697 return regmap_update_bits(mtk_get_regmap(pctl, pin),
698 reg_addr, mask, val);
701 static const struct mtk_desc_pin *
702 mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num)
705 const struct mtk_desc_pin *pin;
707 for (i = 0; i < pctl->devdata->npins; i++) {
708 pin = pctl->devdata->pins + i;
709 if (pin->eint.eintnum == eint_num)
716 static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
721 const struct mtk_desc_function *desc;
722 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
723 struct mtk_pinctrl_group *g = pctl->groups + group;
725 ret = mtk_pctrl_is_function_valid(pctl, g->pin, function);
727 dev_err(pctl->dev, "invalid function %d on group %d .\n",
732 desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function);
735 mtk_pmx_set_mode(pctldev, g->pin, desc->muxval);
739 static int mtk_pmx_find_gpio_mode(struct mtk_pinctrl *pctl,
742 const struct mtk_desc_pin *pin = pctl->devdata->pins + offset;
743 const struct mtk_desc_function *func = pin->functions;
745 while (func && func->name) {
746 if (!strncmp(func->name, GPIO_MODE_PREFIX,
747 sizeof(GPIO_MODE_PREFIX)-1))
754 static int mtk_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
755 struct pinctrl_gpio_range *range,
759 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
761 muxval = mtk_pmx_find_gpio_mode(pctl, offset);
764 dev_err(pctl->dev, "invalid gpio pin %d.\n", offset);
768 mtk_pmx_set_mode(pctldev, offset, muxval);
769 mtk_pconf_set_ies_smt(pctl, offset, 1, PIN_CONFIG_INPUT_ENABLE);
774 static const struct pinmux_ops mtk_pmx_ops = {
775 .get_functions_count = mtk_pmx_get_funcs_cnt,
776 .get_function_name = mtk_pmx_get_func_name,
777 .get_function_groups = mtk_pmx_get_func_groups,
778 .set_mux = mtk_pmx_set_mux,
779 .gpio_set_direction = mtk_pmx_gpio_set_direction,
780 .gpio_request_enable = mtk_pmx_gpio_request_enable,
783 static int mtk_gpio_direction_input(struct gpio_chip *chip,
786 return pinctrl_gpio_direction_input(chip->base + offset);
789 static int mtk_gpio_direction_output(struct gpio_chip *chip,
790 unsigned offset, int value)
792 mtk_gpio_set(chip, offset, value);
793 return pinctrl_gpio_direction_output(chip->base + offset);
796 static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
798 unsigned int reg_addr;
800 unsigned int read_val = 0;
802 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
804 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
805 bit = BIT(offset & 0xf);
807 if (pctl->devdata->spec_dir_set)
808 pctl->devdata->spec_dir_set(®_addr, offset);
810 regmap_read(pctl->regmap1, reg_addr, &read_val);
811 return !(read_val & bit);
814 static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset)
816 unsigned int reg_addr;
818 unsigned int read_val = 0;
819 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
821 reg_addr = mtk_get_port(pctl, offset) +
822 pctl->devdata->din_offset;
824 bit = BIT(offset & 0xf);
825 regmap_read(pctl->regmap1, reg_addr, &read_val);
826 return !!(read_val & bit);
829 static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
831 const struct mtk_desc_pin *pin;
832 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
835 pin = pctl->devdata->pins + offset;
836 if (pin->eint.eintnum == NO_EINT_SUPPORT)
839 irq = irq_find_mapping(pctl->domain, pin->eint.eintnum);
846 static int mtk_pinctrl_irq_request_resources(struct irq_data *d)
848 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
849 const struct mtk_desc_pin *pin;
852 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
855 dev_err(pctl->dev, "Can not find pin\n");
859 ret = gpiochip_lock_as_irq(pctl->chip, pin->pin.number);
861 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
866 /* set mux to INT mode */
867 mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux);
868 /* set gpio direction to input */
869 mtk_pmx_gpio_set_direction(pctl->pctl_dev, NULL, pin->pin.number, true);
870 /* set input-enable */
871 mtk_pconf_set_ies_smt(pctl, pin->pin.number, 1, PIN_CONFIG_INPUT_ENABLE);
876 static void mtk_pinctrl_irq_release_resources(struct irq_data *d)
878 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
879 const struct mtk_desc_pin *pin;
881 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
884 dev_err(pctl->dev, "Can not find pin\n");
888 gpiochip_unlock_as_irq(pctl->chip, pin->pin.number);
891 static void __iomem *mtk_eint_get_offset(struct mtk_pinctrl *pctl,
892 unsigned int eint_num, unsigned int offset)
894 unsigned int eint_base = 0;
897 if (eint_num >= pctl->devdata->ap_num)
898 eint_base = pctl->devdata->ap_num;
900 reg = pctl->eint_reg_base + offset + ((eint_num - eint_base) / 32) * 4;
906 * mtk_can_en_debounce: Check the EINT number is able to enable debounce or not
907 * @eint_num: the EINT number to setmtk_pinctrl
909 static unsigned int mtk_eint_can_en_debounce(struct mtk_pinctrl *pctl,
910 unsigned int eint_num)
913 unsigned int bit = BIT(eint_num % 32);
914 const struct mtk_eint_offsets *eint_offsets =
915 &pctl->devdata->eint_offsets;
917 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
920 if (readl(reg) & bit)
921 sens = MT_LEVEL_SENSITIVE;
923 sens = MT_EDGE_SENSITIVE;
925 if ((eint_num < pctl->devdata->db_cnt) && (sens != MT_EDGE_SENSITIVE))
932 * mtk_eint_get_mask: To get the eint mask
933 * @eint_num: the EINT number to get
935 static unsigned int mtk_eint_get_mask(struct mtk_pinctrl *pctl,
936 unsigned int eint_num)
938 unsigned int bit = BIT(eint_num % 32);
939 const struct mtk_eint_offsets *eint_offsets =
940 &pctl->devdata->eint_offsets;
942 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
945 return !!(readl(reg) & bit);
948 static int mtk_eint_flip_edge(struct mtk_pinctrl *pctl, int hwirq)
950 int start_level, curr_level;
951 unsigned int reg_offset;
952 const struct mtk_eint_offsets *eint_offsets = &(pctl->devdata->eint_offsets);
953 u32 mask = BIT(hwirq & 0x1f);
954 u32 port = (hwirq >> 5) & eint_offsets->port_mask;
955 void __iomem *reg = pctl->eint_reg_base + (port << 2);
956 const struct mtk_desc_pin *pin;
958 pin = mtk_find_pin_by_eint_num(pctl, hwirq);
959 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
961 start_level = curr_level;
963 reg_offset = eint_offsets->pol_clr;
965 reg_offset = eint_offsets->pol_set;
966 writel(mask, reg + reg_offset);
968 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
969 } while (start_level != curr_level);
974 static void mtk_eint_mask(struct irq_data *d)
976 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
977 const struct mtk_eint_offsets *eint_offsets =
978 &pctl->devdata->eint_offsets;
979 u32 mask = BIT(d->hwirq & 0x1f);
980 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
981 eint_offsets->mask_set);
986 static void mtk_eint_unmask(struct irq_data *d)
988 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
989 const struct mtk_eint_offsets *eint_offsets =
990 &pctl->devdata->eint_offsets;
991 u32 mask = BIT(d->hwirq & 0x1f);
992 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
993 eint_offsets->mask_clr);
997 if (pctl->eint_dual_edges[d->hwirq])
998 mtk_eint_flip_edge(pctl, d->hwirq);
1001 static int mtk_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
1004 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->parent);
1005 int eint_num, virq, eint_offset;
1006 unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, dbnc;
1007 static const unsigned int dbnc_arr[] = {0 , 1, 16, 32, 64, 128, 256};
1008 const struct mtk_desc_pin *pin;
1011 pin = pctl->devdata->pins + offset;
1012 if (pin->eint.eintnum == NO_EINT_SUPPORT)
1015 eint_num = pin->eint.eintnum;
1016 virq = irq_find_mapping(pctl->domain, eint_num);
1017 eint_offset = (eint_num % 4) * 8;
1018 d = irq_get_irq_data(virq);
1020 set_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_set;
1021 clr_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_clr;
1022 if (!mtk_eint_can_en_debounce(pctl, eint_num))
1025 dbnc = ARRAY_SIZE(dbnc_arr);
1026 for (i = 0; i < ARRAY_SIZE(dbnc_arr); i++) {
1027 if (debounce <= dbnc_arr[i]) {
1033 if (!mtk_eint_get_mask(pctl, eint_num)) {
1040 clr_bit = 0xff << eint_offset;
1041 writel(clr_bit, pctl->eint_reg_base + clr_offset);
1043 bit = ((dbnc << EINT_DBNC_SET_DBNC_BITS) | EINT_DBNC_SET_EN) <<
1045 rst = EINT_DBNC_RST_BIT << eint_offset;
1046 writel(rst | bit, pctl->eint_reg_base + set_offset);
1048 /* Delay a while (more than 2T) to wait for hw debounce counter reset
1057 static struct gpio_chip mtk_gpio_chip = {
1058 .owner = THIS_MODULE,
1059 .request = gpiochip_generic_request,
1060 .free = gpiochip_generic_free,
1061 .get_direction = mtk_gpio_get_direction,
1062 .direction_input = mtk_gpio_direction_input,
1063 .direction_output = mtk_gpio_direction_output,
1064 .get = mtk_gpio_get,
1065 .set = mtk_gpio_set,
1066 .to_irq = mtk_gpio_to_irq,
1067 .set_debounce = mtk_gpio_set_debounce,
1068 .of_gpio_n_cells = 2,
1071 static int mtk_eint_set_type(struct irq_data *d,
1074 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1075 const struct mtk_eint_offsets *eint_offsets =
1076 &pctl->devdata->eint_offsets;
1077 u32 mask = BIT(d->hwirq & 0x1f);
1080 if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) ||
1081 ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) {
1082 dev_err(pctl->dev, "Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
1083 d->irq, d->hwirq, type);
1087 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1088 pctl->eint_dual_edges[d->hwirq] = 1;
1090 pctl->eint_dual_edges[d->hwirq] = 0;
1092 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
1093 reg = mtk_eint_get_offset(pctl, d->hwirq,
1094 eint_offsets->pol_clr);
1097 reg = mtk_eint_get_offset(pctl, d->hwirq,
1098 eint_offsets->pol_set);
1102 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1103 reg = mtk_eint_get_offset(pctl, d->hwirq,
1104 eint_offsets->sens_clr);
1107 reg = mtk_eint_get_offset(pctl, d->hwirq,
1108 eint_offsets->sens_set);
1112 if (pctl->eint_dual_edges[d->hwirq])
1113 mtk_eint_flip_edge(pctl, d->hwirq);
1118 static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on)
1120 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1121 int shift = d->hwirq & 0x1f;
1122 int reg = d->hwirq >> 5;
1125 pctl->wake_mask[reg] |= BIT(shift);
1127 pctl->wake_mask[reg] &= ~BIT(shift);
1132 static void mtk_eint_chip_write_mask(const struct mtk_eint_offsets *chip,
1133 void __iomem *eint_reg_base, u32 *buf)
1138 for (port = 0; port < chip->ports; port++) {
1139 reg = eint_reg_base + (port << 2);
1140 writel_relaxed(~buf[port], reg + chip->mask_set);
1141 writel_relaxed(buf[port], reg + chip->mask_clr);
1145 static void mtk_eint_chip_read_mask(const struct mtk_eint_offsets *chip,
1146 void __iomem *eint_reg_base, u32 *buf)
1151 for (port = 0; port < chip->ports; port++) {
1152 reg = eint_reg_base + chip->mask + (port << 2);
1153 buf[port] = ~readl_relaxed(reg);
1154 /* Mask is 0 when irq is enabled, and 1 when disabled. */
1158 static int mtk_eint_suspend(struct device *device)
1161 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1162 const struct mtk_eint_offsets *eint_offsets =
1163 &pctl->devdata->eint_offsets;
1165 reg = pctl->eint_reg_base;
1166 mtk_eint_chip_read_mask(eint_offsets, reg, pctl->cur_mask);
1167 mtk_eint_chip_write_mask(eint_offsets, reg, pctl->wake_mask);
1172 static int mtk_eint_resume(struct device *device)
1174 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1175 const struct mtk_eint_offsets *eint_offsets =
1176 &pctl->devdata->eint_offsets;
1178 mtk_eint_chip_write_mask(eint_offsets,
1179 pctl->eint_reg_base, pctl->cur_mask);
1184 const struct dev_pm_ops mtk_eint_pm_ops = {
1185 .suspend = mtk_eint_suspend,
1186 .resume = mtk_eint_resume,
1189 static void mtk_eint_ack(struct irq_data *d)
1191 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1192 const struct mtk_eint_offsets *eint_offsets =
1193 &pctl->devdata->eint_offsets;
1194 u32 mask = BIT(d->hwirq & 0x1f);
1195 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
1201 static struct irq_chip mtk_pinctrl_irq_chip = {
1203 .irq_disable = mtk_eint_mask,
1204 .irq_mask = mtk_eint_mask,
1205 .irq_unmask = mtk_eint_unmask,
1206 .irq_ack = mtk_eint_ack,
1207 .irq_set_type = mtk_eint_set_type,
1208 .irq_set_wake = mtk_eint_irq_set_wake,
1209 .irq_request_resources = mtk_pinctrl_irq_request_resources,
1210 .irq_release_resources = mtk_pinctrl_irq_release_resources,
1213 static unsigned int mtk_eint_init(struct mtk_pinctrl *pctl)
1215 const struct mtk_eint_offsets *eint_offsets =
1216 &pctl->devdata->eint_offsets;
1217 void __iomem *reg = pctl->eint_reg_base + eint_offsets->dom_en;
1220 for (i = 0; i < pctl->devdata->ap_num; i += 32) {
1221 writel(0xffffffff, reg);
1228 mtk_eint_debounce_process(struct mtk_pinctrl *pctl, int index)
1230 unsigned int rst, ctrl_offset;
1231 unsigned int bit, dbnc;
1232 const struct mtk_eint_offsets *eint_offsets =
1233 &pctl->devdata->eint_offsets;
1235 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_ctrl;
1236 dbnc = readl(pctl->eint_reg_base + ctrl_offset);
1237 bit = EINT_DBNC_SET_EN << ((index % 4) * 8);
1238 if ((bit & dbnc) > 0) {
1239 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_set;
1240 rst = EINT_DBNC_RST_BIT << ((index % 4) * 8);
1241 writel(rst, pctl->eint_reg_base + ctrl_offset);
1245 static void mtk_eint_irq_handler(struct irq_desc *desc)
1247 struct irq_chip *chip = irq_desc_get_chip(desc);
1248 struct mtk_pinctrl *pctl = irq_desc_get_handler_data(desc);
1249 unsigned int status, eint_num;
1250 int offset, index, virq;
1251 const struct mtk_eint_offsets *eint_offsets =
1252 &pctl->devdata->eint_offsets;
1253 void __iomem *reg = mtk_eint_get_offset(pctl, 0, eint_offsets->stat);
1254 int dual_edges, start_level, curr_level;
1255 const struct mtk_desc_pin *pin;
1257 chained_irq_enter(chip, desc);
1258 for (eint_num = 0; eint_num < pctl->devdata->ap_num; eint_num += 32) {
1259 status = readl(reg);
1262 offset = __ffs(status);
1263 index = eint_num + offset;
1264 virq = irq_find_mapping(pctl->domain, index);
1265 status &= ~BIT(offset);
1267 dual_edges = pctl->eint_dual_edges[index];
1269 /* Clear soft-irq in case we raised it
1271 writel(BIT(offset), reg - eint_offsets->stat +
1272 eint_offsets->soft_clr);
1274 pin = mtk_find_pin_by_eint_num(pctl, index);
1275 start_level = mtk_gpio_get(pctl->chip,
1279 generic_handle_irq(virq);
1282 curr_level = mtk_eint_flip_edge(pctl, index);
1284 /* If level changed, we might lost one edge
1285 interrupt, raised it through soft-irq */
1286 if (start_level != curr_level)
1287 writel(BIT(offset), reg -
1288 eint_offsets->stat +
1289 eint_offsets->soft_set);
1292 if (index < pctl->devdata->db_cnt)
1293 mtk_eint_debounce_process(pctl , index);
1296 chained_irq_exit(chip, desc);
1299 static int mtk_pctrl_build_state(struct platform_device *pdev)
1301 struct mtk_pinctrl *pctl = platform_get_drvdata(pdev);
1304 pctl->ngroups = pctl->devdata->npins;
1306 /* Allocate groups */
1307 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1308 sizeof(*pctl->groups), GFP_KERNEL);
1312 /* We assume that one pin is one group, use pin name as group name. */
1313 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1314 sizeof(*pctl->grp_names), GFP_KERNEL);
1315 if (!pctl->grp_names)
1318 for (i = 0; i < pctl->devdata->npins; i++) {
1319 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
1320 struct mtk_pinctrl_group *group = pctl->groups + i;
1322 group->name = pin->pin.name;
1323 group->pin = pin->pin.number;
1325 pctl->grp_names[i] = pin->pin.name;
1331 int mtk_pctrl_init(struct platform_device *pdev,
1332 const struct mtk_pinctrl_devdata *data,
1333 struct regmap *regmap)
1335 struct pinctrl_pin_desc *pins;
1336 struct mtk_pinctrl *pctl;
1337 struct device_node *np = pdev->dev.of_node, *node;
1338 struct property *prop;
1339 struct resource *res;
1340 int i, ret, irq, ports_buf;
1342 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1346 platform_set_drvdata(pdev, pctl);
1348 prop = of_find_property(np, "pins-are-numbered", NULL);
1350 dev_err(&pdev->dev, "only support pins-are-numbered format\n");
1354 node = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
1356 pctl->regmap1 = syscon_node_to_regmap(node);
1357 if (IS_ERR(pctl->regmap1))
1358 return PTR_ERR(pctl->regmap1);
1359 } else if (regmap) {
1360 pctl->regmap1 = regmap;
1362 dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n");
1366 /* Only 8135 has two base addr, other SoCs have only one. */
1367 node = of_parse_phandle(np, "mediatek,pctl-regmap", 1);
1369 pctl->regmap2 = syscon_node_to_regmap(node);
1370 if (IS_ERR(pctl->regmap2))
1371 return PTR_ERR(pctl->regmap2);
1374 pctl->devdata = data;
1375 ret = mtk_pctrl_build_state(pdev);
1377 dev_err(&pdev->dev, "build state failed: %d\n", ret);
1381 pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins),
1386 for (i = 0; i < pctl->devdata->npins; i++)
1387 pins[i] = pctl->devdata->pins[i].pin;
1389 pctl->pctl_desc.name = dev_name(&pdev->dev);
1390 pctl->pctl_desc.owner = THIS_MODULE;
1391 pctl->pctl_desc.pins = pins;
1392 pctl->pctl_desc.npins = pctl->devdata->npins;
1393 pctl->pctl_desc.confops = &mtk_pconf_ops;
1394 pctl->pctl_desc.pctlops = &mtk_pctrl_ops;
1395 pctl->pctl_desc.pmxops = &mtk_pmx_ops;
1396 pctl->dev = &pdev->dev;
1398 pctl->pctl_dev = pinctrl_register(&pctl->pctl_desc, &pdev->dev, pctl);
1399 if (IS_ERR(pctl->pctl_dev)) {
1400 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1401 return PTR_ERR(pctl->pctl_dev);
1404 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1410 *pctl->chip = mtk_gpio_chip;
1411 pctl->chip->ngpio = pctl->devdata->npins;
1412 pctl->chip->label = dev_name(&pdev->dev);
1413 pctl->chip->parent = &pdev->dev;
1414 pctl->chip->base = -1;
1416 ret = gpiochip_add_data(pctl->chip, pctl);
1422 /* Register the GPIO to pin mappings. */
1423 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1424 0, 0, pctl->devdata->npins);
1430 if (!of_property_read_bool(np, "interrupt-controller"))
1433 /* Get EINT register base from dts. */
1434 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1436 dev_err(&pdev->dev, "Unable to get Pinctrl resource\n");
1441 pctl->eint_reg_base = devm_ioremap_resource(&pdev->dev, res);
1442 if (IS_ERR(pctl->eint_reg_base)) {
1447 ports_buf = pctl->devdata->eint_offsets.ports;
1448 pctl->wake_mask = devm_kcalloc(&pdev->dev, ports_buf,
1449 sizeof(*pctl->wake_mask), GFP_KERNEL);
1450 if (!pctl->wake_mask) {
1455 pctl->cur_mask = devm_kcalloc(&pdev->dev, ports_buf,
1456 sizeof(*pctl->cur_mask), GFP_KERNEL);
1457 if (!pctl->cur_mask) {
1462 pctl->eint_dual_edges = devm_kcalloc(&pdev->dev, pctl->devdata->ap_num,
1463 sizeof(int), GFP_KERNEL);
1464 if (!pctl->eint_dual_edges) {
1469 irq = irq_of_parse_and_map(np, 0);
1471 dev_err(&pdev->dev, "couldn't parse and map irq\n");
1476 pctl->domain = irq_domain_add_linear(np,
1477 pctl->devdata->ap_num, &irq_domain_simple_ops, NULL);
1478 if (!pctl->domain) {
1479 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1484 mtk_eint_init(pctl);
1485 for (i = 0; i < pctl->devdata->ap_num; i++) {
1486 int virq = irq_create_mapping(pctl->domain, i);
1488 irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip,
1490 irq_set_chip_data(virq, pctl);
1493 irq_set_chained_handler_and_data(irq, mtk_eint_irq_handler, pctl);
1497 gpiochip_remove(pctl->chip);
1499 pinctrl_unregister(pctl->pctl_dev);
1503 MODULE_LICENSE("GPL");
1504 MODULE_DESCRIPTION("MediaTek Pinctrl Driver");
1505 MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");