1 // SPDX-License-Identifier: GPL-2.0-only
3 * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver.
4 * Copyright (c) 2014 MediaTek Inc.
5 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
9 #include <linux/gpio/driver.h>
11 #include <linux/of_address.h>
12 #include <linux/of_device.h>
13 #include <linux/of_irq.h>
14 #include <linux/pinctrl/consumer.h>
15 #include <linux/pinctrl/machine.h>
16 #include <linux/pinctrl/pinconf.h>
17 #include <linux/pinctrl/pinconf-generic.h>
18 #include <linux/pinctrl/pinctrl.h>
19 #include <linux/pinctrl/pinmux.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22 #include <linux/bitops.h>
23 #include <linux/regmap.h>
24 #include <linux/mfd/syscon.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
28 #include <dt-bindings/pinctrl/mt65xx.h>
31 #include "../pinconf.h"
32 #include "../pinctrl-utils.h"
34 #include "pinctrl-mtk-common.h"
36 #define GPIO_MODE_BITS 3
37 #define GPIO_MODE_PREFIX "GPIO"
39 static const char * const mtk_gpio_functions[] = {
40 "func0", "func1", "func2", "func3",
41 "func4", "func5", "func6", "func7",
42 "func8", "func9", "func10", "func11",
43 "func12", "func13", "func14", "func15",
47 * There are two base address for pull related configuration
48 * in mt8135, and different GPIO pins use different base address.
49 * When pin number greater than type1_start and less than type1_end,
50 * should use the second base address.
52 static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl,
55 if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end)
60 static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin)
62 /* Different SoC has different mask and port shift. */
63 return ((pin >> pctl->devdata->mode_shf) & pctl->devdata->port_mask)
64 << pctl->devdata->port_shf;
67 static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
68 struct pinctrl_gpio_range *range, unsigned offset,
71 unsigned int reg_addr;
73 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
75 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
76 bit = BIT(offset & pctl->devdata->mode_mask);
78 if (pctl->devdata->spec_dir_set)
79 pctl->devdata->spec_dir_set(®_addr, offset);
82 /* Different SoC has different alignment offset. */
83 reg_addr = CLR_ADDR(reg_addr, pctl);
85 reg_addr = SET_ADDR(reg_addr, pctl);
87 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
91 static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
93 unsigned int reg_addr;
95 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
97 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset;
98 bit = BIT(offset & pctl->devdata->mode_mask);
101 reg_addr = SET_ADDR(reg_addr, pctl);
103 reg_addr = CLR_ADDR(reg_addr, pctl);
105 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
108 static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
109 int value, enum pin_config_param arg)
111 unsigned int reg_addr, offset;
115 * Due to some soc are not support ies/smt config, add this special
116 * control to handle it.
118 if (!pctl->devdata->spec_ies_smt_set &&
119 pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT &&
120 arg == PIN_CONFIG_INPUT_ENABLE)
123 if (!pctl->devdata->spec_ies_smt_set &&
124 pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT &&
125 arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
129 * Due to some pins are irregular, their input enable and smt
130 * control register are discontinuous, so we need this special handle.
132 if (pctl->devdata->spec_ies_smt_set) {
133 return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
134 pctl->devdata, pin, value, arg);
137 if (arg == PIN_CONFIG_INPUT_ENABLE)
138 offset = pctl->devdata->ies_offset;
140 offset = pctl->devdata->smt_offset;
142 bit = BIT(offset & pctl->devdata->mode_mask);
145 reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
147 reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
149 regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
153 int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
154 const struct mtk_pinctrl_devdata *devdata,
155 unsigned int pin, int value, enum pin_config_param arg)
157 const struct mtk_pin_ies_smt_set *ies_smt_infos = NULL;
158 unsigned int i, info_num, reg_addr, bit;
161 case PIN_CONFIG_INPUT_ENABLE:
162 ies_smt_infos = devdata->spec_ies;
163 info_num = devdata->n_spec_ies;
165 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
166 ies_smt_infos = devdata->spec_smt;
167 info_num = devdata->n_spec_smt;
176 for (i = 0; i < info_num; i++) {
177 if (pin >= ies_smt_infos[i].start &&
178 pin <= ies_smt_infos[i].end) {
187 reg_addr = ies_smt_infos[i].offset + devdata->port_align;
189 reg_addr = ies_smt_infos[i].offset + (devdata->port_align << 1);
191 bit = BIT(ies_smt_infos[i].bit);
192 regmap_write(regmap, reg_addr, bit);
196 static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin(
197 struct mtk_pinctrl *pctl, unsigned long pin) {
200 for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) {
201 const struct mtk_pin_drv_grp *pin_drv =
202 pctl->devdata->pin_drv_grp + i;
203 if (pin == pin_drv->pin)
210 static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl,
211 unsigned int pin, unsigned char driving)
213 const struct mtk_pin_drv_grp *pin_drv;
215 unsigned int bits, mask, shift;
216 const struct mtk_drv_group_desc *drv_grp;
218 if (pin >= pctl->devdata->npins)
221 pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin);
222 if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls)
225 drv_grp = pctl->devdata->grp_desc + pin_drv->grp;
226 if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv
227 && !(driving % drv_grp->step)) {
228 val = driving / drv_grp->step - 1;
229 bits = drv_grp->high_bit - drv_grp->low_bit + 1;
230 mask = BIT(bits) - 1;
231 shift = pin_drv->bit + drv_grp->low_bit;
234 return regmap_update_bits(mtk_get_regmap(pctl, pin),
235 pin_drv->offset, mask, val);
241 int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
242 const struct mtk_pinctrl_devdata *devdata,
243 unsigned int pin, bool isup, unsigned int r1r0)
246 unsigned int reg_pupd, reg_set, reg_rst;
247 unsigned int bit_pupd, bit_r0, bit_r1;
248 const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin;
251 if (!devdata->spec_pupd)
254 for (i = 0; i < devdata->n_spec_pupd; i++) {
255 if (pin == devdata->spec_pupd[i].pin) {
264 spec_pupd_pin = devdata->spec_pupd + i;
265 reg_set = spec_pupd_pin->offset + devdata->port_align;
266 reg_rst = spec_pupd_pin->offset + (devdata->port_align << 1);
273 bit_pupd = BIT(spec_pupd_pin->pupd_bit);
274 regmap_write(regmap, reg_pupd, bit_pupd);
276 bit_r0 = BIT(spec_pupd_pin->r0_bit);
277 bit_r1 = BIT(spec_pupd_pin->r1_bit);
280 case MTK_PUPD_SET_R1R0_00:
281 regmap_write(regmap, reg_rst, bit_r0);
282 regmap_write(regmap, reg_rst, bit_r1);
284 case MTK_PUPD_SET_R1R0_01:
285 regmap_write(regmap, reg_set, bit_r0);
286 regmap_write(regmap, reg_rst, bit_r1);
288 case MTK_PUPD_SET_R1R0_10:
289 regmap_write(regmap, reg_rst, bit_r0);
290 regmap_write(regmap, reg_set, bit_r1);
292 case MTK_PUPD_SET_R1R0_11:
293 regmap_write(regmap, reg_set, bit_r0);
294 regmap_write(regmap, reg_set, bit_r1);
303 static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
304 unsigned int pin, bool enable, bool isup, unsigned int arg)
307 unsigned int reg_pullen, reg_pullsel, r1r0;
310 /* Some pins' pull setting are very different,
311 * they have separate pull up/down bit, R0 and R1
312 * resistor bit, so we need this special handle.
314 if (pctl->devdata->spec_pull_set) {
315 /* For special pins, bias-disable is set by R1R0,
316 * the parameter should be "MTK_PUPD_SET_R1R0_00".
318 r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00;
319 ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
320 pctl->devdata, pin, isup,
326 /* For generic pull config, default arg value should be 0 or 1. */
327 if (arg != 0 && arg != 1) {
328 dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n",
333 if (pctl->devdata->mt8365_set_clr_mode) {
334 bit = pin & pctl->devdata->mode_mask;
335 reg_pullen = mtk_get_port(pctl, pin) +
336 pctl->devdata->pullen_offset;
337 reg_pullsel = mtk_get_port(pctl, pin) +
338 pctl->devdata->pullsel_offset;
339 ret = pctl->devdata->mt8365_set_clr_mode(mtk_get_regmap(pctl, pin),
340 bit, reg_pullen, reg_pullsel,
348 bit = BIT(pin & pctl->devdata->mode_mask);
350 reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
351 pctl->devdata->pullen_offset, pctl);
353 reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
354 pctl->devdata->pullen_offset, pctl);
357 reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
358 pctl->devdata->pullsel_offset, pctl);
360 reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
361 pctl->devdata->pullsel_offset, pctl);
363 regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
364 regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
368 static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
369 unsigned int pin, enum pin_config_param param,
370 enum pin_config_param arg)
373 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
376 case PIN_CONFIG_BIAS_DISABLE:
377 ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
379 case PIN_CONFIG_BIAS_PULL_UP:
380 ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
382 case PIN_CONFIG_BIAS_PULL_DOWN:
383 ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
385 case PIN_CONFIG_INPUT_ENABLE:
386 mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
387 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
389 case PIN_CONFIG_OUTPUT:
390 mtk_gpio_set(pctl->chip, pin, arg);
391 ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
393 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
394 mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
395 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
397 case PIN_CONFIG_DRIVE_STRENGTH:
398 ret = mtk_pconf_set_driving(pctl, pin, arg);
407 static int mtk_pconf_group_get(struct pinctrl_dev *pctldev,
409 unsigned long *config)
411 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
413 *config = pctl->groups[group].config;
418 static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
419 unsigned long *configs, unsigned num_configs)
421 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
422 struct mtk_pinctrl_group *g = &pctl->groups[group];
425 for (i = 0; i < num_configs; i++) {
426 ret = mtk_pconf_parse_conf(pctldev, g->pin,
427 pinconf_to_config_param(configs[i]),
428 pinconf_to_config_argument(configs[i]));
432 g->config = configs[i];
438 static const struct pinconf_ops mtk_pconf_ops = {
439 .pin_config_group_get = mtk_pconf_group_get,
440 .pin_config_group_set = mtk_pconf_group_set,
443 static struct mtk_pinctrl_group *
444 mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin)
448 for (i = 0; i < pctl->ngroups; i++) {
449 struct mtk_pinctrl_group *grp = pctl->groups + i;
458 static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin(
459 struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum)
461 const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num;
462 const struct mtk_desc_function *func = pin->functions;
464 while (func && func->name) {
465 if (func->muxval == fnum)
473 static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl,
474 u32 pin_num, u32 fnum)
478 for (i = 0; i < pctl->devdata->npins; i++) {
479 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
481 if (pin->pin.number == pin_num) {
482 const struct mtk_desc_function *func =
485 while (func && func->name) {
486 if (func->muxval == fnum)
498 static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
499 u32 pin, u32 fnum, struct mtk_pinctrl_group *grp,
500 struct pinctrl_map **map, unsigned *reserved_maps,
505 if (*num_maps == *reserved_maps)
508 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
509 (*map)[*num_maps].data.mux.group = grp->name;
511 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
513 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
518 (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
524 static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
525 struct device_node *node,
526 struct pinctrl_map **map,
527 unsigned *reserved_maps,
530 struct property *pins;
531 u32 pinfunc, pin, func;
532 int num_pins, num_funcs, maps_per_pin;
533 unsigned long *configs;
534 unsigned int num_configs;
535 bool has_config = false;
537 unsigned reserve = 0;
538 struct mtk_pinctrl_group *grp;
539 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
541 pins = of_find_property(node, "pinmux", NULL);
543 dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
548 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
556 num_pins = pins->length / sizeof(u32);
557 num_funcs = num_pins;
561 if (has_config && num_pins >= 1)
564 if (!num_pins || !maps_per_pin) {
569 reserve = num_pins * maps_per_pin;
571 err = pinctrl_utils_reserve_map(pctldev, map,
572 reserved_maps, num_maps, reserve);
576 for (i = 0; i < num_pins; i++) {
577 err = of_property_read_u32_index(node, "pinmux",
582 pin = MTK_GET_PIN_NO(pinfunc);
583 func = MTK_GET_PIN_FUNC(pinfunc);
585 if (pin >= pctl->devdata->npins ||
586 func >= ARRAY_SIZE(mtk_gpio_functions)) {
587 dev_err(pctl->dev, "invalid pins value.\n");
592 grp = mtk_pctrl_find_group_by_pin(pctl, pin);
594 dev_err(pctl->dev, "unable to match pin %d to group\n",
600 err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
601 reserved_maps, num_maps);
606 err = pinctrl_utils_add_map_configs(pctldev, map,
607 reserved_maps, num_maps, grp->name,
608 configs, num_configs,
609 PIN_MAP_TYPE_CONFIGS_GROUP);
622 static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
623 struct device_node *np_config,
624 struct pinctrl_map **map, unsigned *num_maps)
626 struct device_node *np;
627 unsigned reserved_maps;
634 for_each_child_of_node(np_config, np) {
635 ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
636 &reserved_maps, num_maps);
638 pinctrl_utils_free_map(pctldev, *map, *num_maps);
647 static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
649 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
651 return pctl->ngroups;
654 static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
657 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
659 return pctl->groups[group].name;
662 static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
664 const unsigned **pins,
667 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
669 *pins = (unsigned *)&pctl->groups[group].pin;
675 static const struct pinctrl_ops mtk_pctrl_ops = {
676 .dt_node_to_map = mtk_pctrl_dt_node_to_map,
677 .dt_free_map = pinctrl_utils_free_map,
678 .get_groups_count = mtk_pctrl_get_groups_count,
679 .get_group_name = mtk_pctrl_get_group_name,
680 .get_group_pins = mtk_pctrl_get_group_pins,
683 static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
685 return ARRAY_SIZE(mtk_gpio_functions);
688 static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
691 return mtk_gpio_functions[selector];
694 static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
696 const char * const **groups,
697 unsigned * const num_groups)
699 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
701 *groups = pctl->grp_names;
702 *num_groups = pctl->ngroups;
707 static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
708 unsigned long pin, unsigned long mode)
710 unsigned int reg_addr;
713 unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
714 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
716 if (pctl->devdata->spec_pinmux_set)
717 pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin),
720 reg_addr = ((pin / pctl->devdata->mode_per_reg) << pctl->devdata->port_shf)
721 + pctl->devdata->pinmux_offset;
724 bit = pin % pctl->devdata->mode_per_reg;
725 mask <<= (GPIO_MODE_BITS * bit);
726 val = (mode << (GPIO_MODE_BITS * bit));
727 return regmap_update_bits(mtk_get_regmap(pctl, pin),
728 reg_addr, mask, val);
731 static const struct mtk_desc_pin *
732 mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num)
735 const struct mtk_desc_pin *pin;
737 for (i = 0; i < pctl->devdata->npins; i++) {
738 pin = pctl->devdata->pins + i;
739 if (pin->eint.eintnum == eint_num)
746 static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
751 const struct mtk_desc_function *desc;
752 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
753 struct mtk_pinctrl_group *g = pctl->groups + group;
755 ret = mtk_pctrl_is_function_valid(pctl, g->pin, function);
757 dev_err(pctl->dev, "invalid function %d on group %d .\n",
762 desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function);
765 mtk_pmx_set_mode(pctldev, g->pin, desc->muxval);
769 static int mtk_pmx_find_gpio_mode(struct mtk_pinctrl *pctl,
772 const struct mtk_desc_pin *pin = pctl->devdata->pins + offset;
773 const struct mtk_desc_function *func = pin->functions;
775 while (func && func->name) {
776 if (!strncmp(func->name, GPIO_MODE_PREFIX,
777 sizeof(GPIO_MODE_PREFIX)-1))
784 static int mtk_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
785 struct pinctrl_gpio_range *range,
789 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
791 muxval = mtk_pmx_find_gpio_mode(pctl, offset);
794 dev_err(pctl->dev, "invalid gpio pin %d.\n", offset);
798 mtk_pmx_set_mode(pctldev, offset, muxval);
799 mtk_pconf_set_ies_smt(pctl, offset, 1, PIN_CONFIG_INPUT_ENABLE);
804 static const struct pinmux_ops mtk_pmx_ops = {
805 .get_functions_count = mtk_pmx_get_funcs_cnt,
806 .get_function_name = mtk_pmx_get_func_name,
807 .get_function_groups = mtk_pmx_get_func_groups,
808 .set_mux = mtk_pmx_set_mux,
809 .gpio_set_direction = mtk_pmx_gpio_set_direction,
810 .gpio_request_enable = mtk_pmx_gpio_request_enable,
813 static int mtk_gpio_direction_input(struct gpio_chip *chip,
816 return pinctrl_gpio_direction_input(chip->base + offset);
819 static int mtk_gpio_direction_output(struct gpio_chip *chip,
820 unsigned offset, int value)
822 mtk_gpio_set(chip, offset, value);
823 return pinctrl_gpio_direction_output(chip->base + offset);
826 static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
828 unsigned int reg_addr;
830 unsigned int read_val = 0;
832 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
834 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
835 bit = BIT(offset & pctl->devdata->mode_mask);
837 if (pctl->devdata->spec_dir_set)
838 pctl->devdata->spec_dir_set(®_addr, offset);
840 regmap_read(pctl->regmap1, reg_addr, &read_val);
842 return GPIO_LINE_DIRECTION_OUT;
844 return GPIO_LINE_DIRECTION_IN;
847 static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset)
849 unsigned int reg_addr;
851 unsigned int read_val = 0;
852 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
854 reg_addr = mtk_get_port(pctl, offset) +
855 pctl->devdata->din_offset;
857 bit = BIT(offset & pctl->devdata->mode_mask);
858 regmap_read(pctl->regmap1, reg_addr, &read_val);
859 return !!(read_val & bit);
862 static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
864 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
865 const struct mtk_desc_pin *pin;
866 unsigned long eint_n;
868 pin = pctl->devdata->pins + offset;
869 if (pin->eint.eintnum == NO_EINT_SUPPORT)
872 eint_n = pin->eint.eintnum;
874 return mtk_eint_find_irq(pctl->eint, eint_n);
877 static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned offset,
878 unsigned long config)
880 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
881 const struct mtk_desc_pin *pin;
882 unsigned long eint_n;
885 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
888 pin = pctl->devdata->pins + offset;
889 if (pin->eint.eintnum == NO_EINT_SUPPORT)
892 debounce = pinconf_to_config_argument(config);
893 eint_n = pin->eint.eintnum;
895 return mtk_eint_set_debounce(pctl->eint, eint_n, debounce);
898 static const struct gpio_chip mtk_gpio_chip = {
899 .owner = THIS_MODULE,
900 .request = gpiochip_generic_request,
901 .free = gpiochip_generic_free,
902 .get_direction = mtk_gpio_get_direction,
903 .direction_input = mtk_gpio_direction_input,
904 .direction_output = mtk_gpio_direction_output,
907 .to_irq = mtk_gpio_to_irq,
908 .set_config = mtk_gpio_set_config,
911 static int mtk_eint_suspend(struct device *device)
913 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
915 return mtk_eint_do_suspend(pctl->eint);
918 static int mtk_eint_resume(struct device *device)
920 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
922 return mtk_eint_do_resume(pctl->eint);
925 const struct dev_pm_ops mtk_eint_pm_ops = {
926 .suspend_noirq = mtk_eint_suspend,
927 .resume_noirq = mtk_eint_resume,
930 static int mtk_pctrl_build_state(struct platform_device *pdev)
932 struct mtk_pinctrl *pctl = platform_get_drvdata(pdev);
935 pctl->ngroups = pctl->devdata->npins;
937 /* Allocate groups */
938 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
939 sizeof(*pctl->groups), GFP_KERNEL);
943 /* We assume that one pin is one group, use pin name as group name. */
944 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
945 sizeof(*pctl->grp_names), GFP_KERNEL);
946 if (!pctl->grp_names)
949 for (i = 0; i < pctl->devdata->npins; i++) {
950 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
951 struct mtk_pinctrl_group *group = pctl->groups + i;
953 group->name = pin->pin.name;
954 group->pin = pin->pin.number;
956 pctl->grp_names[i] = pin->pin.name;
963 mtk_xt_get_gpio_n(void *data, unsigned long eint_n, unsigned int *gpio_n,
964 struct gpio_chip **gpio_chip)
966 struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data;
967 const struct mtk_desc_pin *pin;
969 pin = mtk_find_pin_by_eint_num(pctl, eint_n);
973 *gpio_chip = pctl->chip;
974 *gpio_n = pin->pin.number;
979 static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n)
981 struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data;
982 const struct mtk_desc_pin *pin;
984 pin = mtk_find_pin_by_eint_num(pctl, eint_n);
988 return mtk_gpio_get(pctl->chip, pin->pin.number);
991 static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
993 struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data;
994 const struct mtk_desc_pin *pin;
996 pin = mtk_find_pin_by_eint_num(pctl, eint_n);
1000 /* set mux to INT mode */
1001 mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux);
1002 /* set gpio direction to input */
1003 mtk_pmx_gpio_set_direction(pctl->pctl_dev, NULL, pin->pin.number,
1005 /* set input-enable */
1006 mtk_pconf_set_ies_smt(pctl, pin->pin.number, 1,
1007 PIN_CONFIG_INPUT_ENABLE);
1012 static const struct mtk_eint_xt mtk_eint_xt = {
1013 .get_gpio_n = mtk_xt_get_gpio_n,
1014 .get_gpio_state = mtk_xt_get_gpio_state,
1015 .set_gpio_as_eint = mtk_xt_set_gpio_as_eint,
1018 static int mtk_eint_init(struct mtk_pinctrl *pctl, struct platform_device *pdev)
1020 struct device_node *np = pdev->dev.of_node;
1022 if (!of_property_read_bool(np, "interrupt-controller"))
1025 pctl->eint = devm_kzalloc(pctl->dev, sizeof(*pctl->eint), GFP_KERNEL);
1029 pctl->eint->base = devm_platform_ioremap_resource(pdev, 0);
1030 if (IS_ERR(pctl->eint->base))
1031 return PTR_ERR(pctl->eint->base);
1033 pctl->eint->irq = irq_of_parse_and_map(np, 0);
1034 if (!pctl->eint->irq)
1037 pctl->eint->dev = &pdev->dev;
1039 * If pctl->eint->regs == NULL, it would fall back into using a generic
1040 * register map in mtk_eint_do_init calls.
1042 pctl->eint->regs = pctl->devdata->eint_regs;
1043 pctl->eint->hw = &pctl->devdata->eint_hw;
1044 pctl->eint->pctl = pctl;
1045 pctl->eint->gpio_xlate = &mtk_eint_xt;
1047 return mtk_eint_do_init(pctl->eint);
1050 /* This is used as a common probe function */
1051 int mtk_pctrl_init(struct platform_device *pdev,
1052 const struct mtk_pinctrl_devdata *data,
1053 struct regmap *regmap)
1055 struct device *dev = &pdev->dev;
1056 struct pinctrl_pin_desc *pins;
1057 struct mtk_pinctrl *pctl;
1058 struct device_node *np = pdev->dev.of_node, *node;
1061 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1065 platform_set_drvdata(pdev, pctl);
1067 node = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
1069 pctl->regmap1 = syscon_node_to_regmap(node);
1071 if (IS_ERR(pctl->regmap1))
1072 return PTR_ERR(pctl->regmap1);
1073 } else if (regmap) {
1074 pctl->regmap1 = regmap;
1076 return dev_err_probe(dev, -EINVAL, "Cannot find pinctrl regmap.\n");
1079 /* Only 8135 has two base addr, other SoCs have only one. */
1080 node = of_parse_phandle(np, "mediatek,pctl-regmap", 1);
1082 pctl->regmap2 = syscon_node_to_regmap(node);
1084 if (IS_ERR(pctl->regmap2))
1085 return PTR_ERR(pctl->regmap2);
1088 pctl->devdata = data;
1089 ret = mtk_pctrl_build_state(pdev);
1091 return dev_err_probe(dev, ret, "build state failed\n");
1093 pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins),
1098 for (i = 0; i < pctl->devdata->npins; i++)
1099 pins[i] = pctl->devdata->pins[i].pin;
1101 pctl->pctl_desc.name = dev_name(&pdev->dev);
1102 pctl->pctl_desc.owner = THIS_MODULE;
1103 pctl->pctl_desc.pins = pins;
1104 pctl->pctl_desc.npins = pctl->devdata->npins;
1105 pctl->pctl_desc.confops = &mtk_pconf_ops;
1106 pctl->pctl_desc.pctlops = &mtk_pctrl_ops;
1107 pctl->pctl_desc.pmxops = &mtk_pmx_ops;
1108 pctl->dev = &pdev->dev;
1110 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1112 if (IS_ERR(pctl->pctl_dev))
1113 return dev_err_probe(dev, PTR_ERR(pctl->pctl_dev),
1114 "Couldn't register pinctrl driver\n");
1116 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1120 *pctl->chip = mtk_gpio_chip;
1121 pctl->chip->ngpio = pctl->devdata->npins;
1122 pctl->chip->label = dev_name(&pdev->dev);
1123 pctl->chip->parent = &pdev->dev;
1124 pctl->chip->base = -1;
1126 ret = gpiochip_add_data(pctl->chip, pctl);
1130 /* Register the GPIO to pin mappings. */
1131 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1132 0, 0, pctl->devdata->npins);
1138 ret = mtk_eint_init(pctl, pdev);
1145 gpiochip_remove(pctl->chip);
1149 int mtk_pctrl_common_probe(struct platform_device *pdev)
1151 struct device *dev = &pdev->dev;
1152 const struct mtk_pinctrl_devdata *data = device_get_match_data(dev);
1157 return mtk_pctrl_init(pdev, data, NULL);