2 * MediaTek MT7622 Pinctrl Driver
4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/gpio/driver.h>
18 #include <linux/init.h>
19 #include <linux/mfd/syscon.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_platform.h>
23 #include <linux/platform_device.h>
24 #include <linux/pinctrl/pinctrl.h>
25 #include <linux/pinctrl/pinmux.h>
26 #include <linux/pinctrl/pinconf.h>
27 #include <linux/pinctrl/pinconf-generic.h>
28 #include <linux/regmap.h>
31 #include "../pinconf.h"
32 #include "../pinmux.h"
35 #define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
36 #define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), }
37 #define PINCTRL_PIN_GROUP(name, id) \
41 ARRAY_SIZE(id##_pins), \
45 #define MTK_GPIO_MODE 1
51 /* Custom pinconf parameters */
52 #define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1)
53 #define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
55 /* List these attributes which could be modified for the pin */
67 PINCTRL_PIN_REG_TDSEL,
68 PINCTRL_PIN_REG_RDSEL,
72 /* struct mtk_pin_field - the structure that holds the information of the field
73 * used to describe the attribute for the pin
74 * @offset: the register offset relative to the base address
75 * @mask: the mask used to filter out the field from the register
76 * @bitpos: the start bit relative to the register
77 * @next: the indication that the field would be extended to the
80 struct mtk_pin_field {
87 /* struct mtk_pin_field_calc - the structure that holds the range providing
88 * the guide used to look up the relevant field
89 * @s_pin: the start pin within the range
90 * @e_pin: the end pin within the range
91 * @s_addr: the start address for the range
92 * @x_addrs: the address distance between two consecutive registers
94 * @s_bit: the start bit for the first register within the range
95 * @x_bits: the bit distance between two consecutive pins within
98 struct mtk_pin_field_calc {
107 /* struct mtk_pin_reg_calc - the structure that holds all ranges used to
108 * determine which register the pin would make use of
109 * for certain pin attribute.
110 * @range: the start address for the range
111 * @nranges: the number of items in the range
113 struct mtk_pin_reg_calc {
114 const struct mtk_pin_field_calc *range;
115 unsigned int nranges;
118 /* struct mtk_pin_soc - the structure that holds SoC-specific data */
120 const struct mtk_pin_reg_calc *reg_cal;
121 const struct pinctrl_pin_desc *pins;
123 const struct group_desc *grps;
125 const struct function_desc *funcs;
127 const struct mtk_eint_regs *eint_regs;
128 const struct mtk_eint_hw *eint_hw;
132 struct pinctrl_dev *pctrl;
135 struct gpio_chip chip;
136 const struct mtk_pin_soc *soc;
137 struct mtk_eint *eint;
140 static const struct mtk_pin_field_calc mt7622_pin_mode_range[] = {
141 {0, 0, 0x320, 0x10, 16, 4},
142 {1, 4, 0x3a0, 0x10, 16, 4},
143 {5, 5, 0x320, 0x10, 0, 4},
144 {6, 6, 0x300, 0x10, 4, 4},
145 {7, 7, 0x300, 0x10, 4, 4},
146 {8, 9, 0x350, 0x10, 20, 4},
147 {10, 10, 0x300, 0x10, 8, 4},
148 {11, 11, 0x300, 0x10, 8, 4},
149 {12, 12, 0x300, 0x10, 8, 4},
150 {13, 13, 0x300, 0x10, 8, 4},
151 {14, 15, 0x320, 0x10, 4, 4},
152 {16, 17, 0x320, 0x10, 20, 4},
153 {18, 21, 0x310, 0x10, 16, 4},
154 {22, 22, 0x380, 0x10, 16, 4},
155 {23, 23, 0x300, 0x10, 24, 4},
156 {24, 24, 0x300, 0x10, 24, 4},
157 {25, 25, 0x300, 0x10, 12, 4},
158 {25, 25, 0x300, 0x10, 12, 4},
159 {26, 26, 0x300, 0x10, 12, 4},
160 {27, 27, 0x300, 0x10, 12, 4},
161 {28, 28, 0x300, 0x10, 12, 4},
162 {29, 29, 0x300, 0x10, 12, 4},
163 {30, 30, 0x300, 0x10, 12, 4},
164 {31, 31, 0x300, 0x10, 12, 4},
165 {32, 32, 0x300, 0x10, 12, 4},
166 {33, 33, 0x300, 0x10, 12, 4},
167 {34, 34, 0x300, 0x10, 12, 4},
168 {35, 35, 0x300, 0x10, 12, 4},
169 {36, 36, 0x300, 0x10, 12, 4},
170 {37, 37, 0x300, 0x10, 20, 4},
171 {38, 38, 0x300, 0x10, 20, 4},
172 {39, 39, 0x300, 0x10, 20, 4},
173 {40, 40, 0x300, 0x10, 20, 4},
174 {41, 41, 0x300, 0x10, 20, 4},
175 {42, 42, 0x300, 0x10, 20, 4},
176 {43, 43, 0x300, 0x10, 20, 4},
177 {44, 44, 0x300, 0x10, 20, 4},
178 {45, 46, 0x300, 0x10, 20, 4},
179 {47, 47, 0x300, 0x10, 20, 4},
180 {48, 48, 0x300, 0x10, 20, 4},
181 {49, 49, 0x300, 0x10, 20, 4},
182 {50, 50, 0x300, 0x10, 20, 4},
183 {51, 70, 0x330, 0x10, 4, 4},
184 {71, 71, 0x300, 0x10, 16, 4},
185 {72, 72, 0x300, 0x10, 16, 4},
186 {73, 76, 0x310, 0x10, 0, 4},
187 {77, 77, 0x320, 0x10, 28, 4},
188 {78, 78, 0x320, 0x10, 12, 4},
189 {79, 82, 0x3a0, 0x10, 0, 4},
190 {83, 83, 0x350, 0x10, 28, 4},
191 {84, 84, 0x330, 0x10, 0, 4},
192 {85, 90, 0x360, 0x10, 4, 4},
193 {91, 94, 0x390, 0x10, 16, 4},
194 {95, 97, 0x380, 0x10, 20, 4},
195 {98, 101, 0x390, 0x10, 0, 4},
196 {102, 102, 0x360, 0x10, 0, 4},
199 static const struct mtk_pin_field_calc mt7622_pin_dir_range[] = {
200 {0, 102, 0x0, 0x10, 0, 1},
203 static const struct mtk_pin_field_calc mt7622_pin_di_range[] = {
204 {0, 102, 0x200, 0x10, 0, 1},
207 static const struct mtk_pin_field_calc mt7622_pin_do_range[] = {
208 {0, 102, 0x100, 0x10, 0, 1},
211 static const struct mtk_pin_field_calc mt7622_pin_sr_range[] = {
212 {0, 31, 0x910, 0x10, 0, 1},
213 {32, 50, 0xa10, 0x10, 0, 1},
214 {51, 70, 0x810, 0x10, 0, 1},
215 {71, 72, 0xb10, 0x10, 0, 1},
216 {73, 86, 0xb10, 0x10, 4, 1},
217 {87, 90, 0xc10, 0x10, 0, 1},
218 {91, 102, 0xb10, 0x10, 18, 1},
221 static const struct mtk_pin_field_calc mt7622_pin_smt_range[] = {
222 {0, 31, 0x920, 0x10, 0, 1},
223 {32, 50, 0xa20, 0x10, 0, 1},
224 {51, 70, 0x820, 0x10, 0, 1},
225 {71, 72, 0xb20, 0x10, 0, 1},
226 {73, 86, 0xb20, 0x10, 4, 1},
227 {87, 90, 0xc20, 0x10, 0, 1},
228 {91, 102, 0xb20, 0x10, 18, 1},
231 static const struct mtk_pin_field_calc mt7622_pin_pu_range[] = {
232 {0, 31, 0x930, 0x10, 0, 1},
233 {32, 50, 0xa30, 0x10, 0, 1},
234 {51, 70, 0x830, 0x10, 0, 1},
235 {71, 72, 0xb30, 0x10, 0, 1},
236 {73, 86, 0xb30, 0x10, 4, 1},
237 {87, 90, 0xc30, 0x10, 0, 1},
238 {91, 102, 0xb30, 0x10, 18, 1},
241 static const struct mtk_pin_field_calc mt7622_pin_pd_range[] = {
242 {0, 31, 0x940, 0x10, 0, 1},
243 {32, 50, 0xa40, 0x10, 0, 1},
244 {51, 70, 0x840, 0x10, 0, 1},
245 {71, 72, 0xb40, 0x10, 0, 1},
246 {73, 86, 0xb40, 0x10, 4, 1},
247 {87, 90, 0xc40, 0x10, 0, 1},
248 {91, 102, 0xb40, 0x10, 18, 1},
251 static const struct mtk_pin_field_calc mt7622_pin_e4_range[] = {
252 {0, 31, 0x960, 0x10, 0, 1},
253 {32, 50, 0xa60, 0x10, 0, 1},
254 {51, 70, 0x860, 0x10, 0, 1},
255 {71, 72, 0xb60, 0x10, 0, 1},
256 {73, 86, 0xb60, 0x10, 4, 1},
257 {87, 90, 0xc60, 0x10, 0, 1},
258 {91, 102, 0xb60, 0x10, 18, 1},
261 static const struct mtk_pin_field_calc mt7622_pin_e8_range[] = {
262 {0, 31, 0x970, 0x10, 0, 1},
263 {32, 50, 0xa70, 0x10, 0, 1},
264 {51, 70, 0x870, 0x10, 0, 1},
265 {71, 72, 0xb70, 0x10, 0, 1},
266 {73, 86, 0xb70, 0x10, 4, 1},
267 {87, 90, 0xc70, 0x10, 0, 1},
268 {91, 102, 0xb70, 0x10, 18, 1},
271 static const struct mtk_pin_field_calc mt7622_pin_tdsel_range[] = {
272 {0, 31, 0x980, 0x4, 0, 4},
273 {32, 50, 0xa80, 0x4, 0, 4},
274 {51, 70, 0x880, 0x4, 0, 4},
275 {71, 72, 0xb80, 0x4, 0, 4},
276 {73, 86, 0xb80, 0x4, 16, 4},
277 {87, 90, 0xc80, 0x4, 0, 4},
278 {91, 102, 0xb88, 0x4, 8, 4},
281 static const struct mtk_pin_field_calc mt7622_pin_rdsel_range[] = {
282 {0, 31, 0x990, 0x4, 0, 6},
283 {32, 50, 0xa90, 0x4, 0, 6},
284 {51, 58, 0x890, 0x4, 0, 6},
285 {59, 60, 0x894, 0x4, 28, 6},
286 {61, 62, 0x894, 0x4, 16, 6},
287 {63, 66, 0x898, 0x4, 8, 6},
288 {67, 68, 0x89c, 0x4, 12, 6},
289 {69, 70, 0x89c, 0x4, 0, 6},
290 {71, 72, 0xb90, 0x4, 0, 6},
291 {73, 86, 0xb90, 0x4, 24, 6},
292 {87, 90, 0xc90, 0x4, 0, 6},
293 {91, 102, 0xb9c, 0x4, 12, 6},
296 static const struct mtk_pin_reg_calc mt7622_reg_cals[PINCTRL_PIN_REG_MAX] = {
297 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7622_pin_mode_range),
298 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7622_pin_dir_range),
299 [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7622_pin_di_range),
300 [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7622_pin_do_range),
301 [PINCTRL_PIN_REG_SR] = MTK_RANGE(mt7622_pin_sr_range),
302 [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7622_pin_smt_range),
303 [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7622_pin_pu_range),
304 [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7622_pin_pd_range),
305 [PINCTRL_PIN_REG_E4] = MTK_RANGE(mt7622_pin_e4_range),
306 [PINCTRL_PIN_REG_E8] = MTK_RANGE(mt7622_pin_e8_range),
307 [PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt7622_pin_tdsel_range),
308 [PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt7622_pin_rdsel_range),
311 static const struct pinctrl_pin_desc mt7622_pins[] = {
312 PINCTRL_PIN(0, "GPIO_A"),
313 PINCTRL_PIN(1, "I2S1_IN"),
314 PINCTRL_PIN(2, "I2S1_OUT"),
315 PINCTRL_PIN(3, "I2S_BCLK"),
316 PINCTRL_PIN(4, "I2S_WS"),
317 PINCTRL_PIN(5, "I2S_MCLK"),
318 PINCTRL_PIN(6, "TXD0"),
319 PINCTRL_PIN(7, "RXD0"),
320 PINCTRL_PIN(8, "SPI_WP"),
321 PINCTRL_PIN(9, "SPI_HOLD"),
322 PINCTRL_PIN(10, "SPI_CLK"),
323 PINCTRL_PIN(11, "SPI_MOSI"),
324 PINCTRL_PIN(12, "SPI_MISO"),
325 PINCTRL_PIN(13, "SPI_CS"),
326 PINCTRL_PIN(14, "I2C_SDA"),
327 PINCTRL_PIN(15, "I2C_SCL"),
328 PINCTRL_PIN(16, "I2S2_IN"),
329 PINCTRL_PIN(17, "I2S3_IN"),
330 PINCTRL_PIN(18, "I2S4_IN"),
331 PINCTRL_PIN(19, "I2S2_OUT"),
332 PINCTRL_PIN(20, "I2S3_OUT"),
333 PINCTRL_PIN(21, "I2S4_OUT"),
334 PINCTRL_PIN(22, "GPIO_B"),
335 PINCTRL_PIN(23, "MDC"),
336 PINCTRL_PIN(24, "MDIO"),
337 PINCTRL_PIN(25, "G2_TXD0"),
338 PINCTRL_PIN(26, "G2_TXD1"),
339 PINCTRL_PIN(27, "G2_TXD2"),
340 PINCTRL_PIN(28, "G2_TXD3"),
341 PINCTRL_PIN(29, "G2_TXEN"),
342 PINCTRL_PIN(30, "G2_TXC"),
343 PINCTRL_PIN(31, "G2_RXD0"),
344 PINCTRL_PIN(32, "G2_RXD1"),
345 PINCTRL_PIN(33, "G2_RXD2"),
346 PINCTRL_PIN(34, "G2_RXD3"),
347 PINCTRL_PIN(35, "G2_RXDV"),
348 PINCTRL_PIN(36, "G2_RXC"),
349 PINCTRL_PIN(37, "NCEB"),
350 PINCTRL_PIN(38, "NWEB"),
351 PINCTRL_PIN(39, "NREB"),
352 PINCTRL_PIN(40, "NDL4"),
353 PINCTRL_PIN(41, "NDL5"),
354 PINCTRL_PIN(42, "NDL6"),
355 PINCTRL_PIN(43, "NDL7"),
356 PINCTRL_PIN(44, "NRB"),
357 PINCTRL_PIN(45, "NCLE"),
358 PINCTRL_PIN(46, "NALE"),
359 PINCTRL_PIN(47, "NDL0"),
360 PINCTRL_PIN(48, "NDL1"),
361 PINCTRL_PIN(49, "NDL2"),
362 PINCTRL_PIN(50, "NDL3"),
363 PINCTRL_PIN(51, "MDI_TP_P0"),
364 PINCTRL_PIN(52, "MDI_TN_P0"),
365 PINCTRL_PIN(53, "MDI_RP_P0"),
366 PINCTRL_PIN(54, "MDI_RN_P0"),
367 PINCTRL_PIN(55, "MDI_TP_P1"),
368 PINCTRL_PIN(56, "MDI_TN_P1"),
369 PINCTRL_PIN(57, "MDI_RP_P1"),
370 PINCTRL_PIN(58, "MDI_RN_P1"),
371 PINCTRL_PIN(59, "MDI_RP_P2"),
372 PINCTRL_PIN(60, "MDI_RN_P2"),
373 PINCTRL_PIN(61, "MDI_TP_P2"),
374 PINCTRL_PIN(62, "MDI_TN_P2"),
375 PINCTRL_PIN(63, "MDI_TP_P3"),
376 PINCTRL_PIN(64, "MDI_TN_P3"),
377 PINCTRL_PIN(65, "MDI_RP_P3"),
378 PINCTRL_PIN(66, "MDI_RN_P3"),
379 PINCTRL_PIN(67, "MDI_RP_P4"),
380 PINCTRL_PIN(68, "MDI_RN_P4"),
381 PINCTRL_PIN(69, "MDI_TP_P4"),
382 PINCTRL_PIN(70, "MDI_TN_P4"),
383 PINCTRL_PIN(71, "PMIC_SCL"),
384 PINCTRL_PIN(72, "PMIC_SDA"),
385 PINCTRL_PIN(73, "SPIC1_CLK"),
386 PINCTRL_PIN(74, "SPIC1_MOSI"),
387 PINCTRL_PIN(75, "SPIC1_MISO"),
388 PINCTRL_PIN(76, "SPIC1_CS"),
389 PINCTRL_PIN(77, "GPIO_D"),
390 PINCTRL_PIN(78, "WATCHDOG"),
391 PINCTRL_PIN(79, "RTS3_N"),
392 PINCTRL_PIN(80, "CTS3_N"),
393 PINCTRL_PIN(81, "TXD3"),
394 PINCTRL_PIN(82, "RXD3"),
395 PINCTRL_PIN(83, "PERST0_N"),
396 PINCTRL_PIN(84, "PERST1_N"),
397 PINCTRL_PIN(85, "WLED_N"),
398 PINCTRL_PIN(86, "EPHY_LED0_N"),
399 PINCTRL_PIN(87, "AUXIN0"),
400 PINCTRL_PIN(88, "AUXIN1"),
401 PINCTRL_PIN(89, "AUXIN2"),
402 PINCTRL_PIN(90, "AUXIN3"),
403 PINCTRL_PIN(91, "TXD4"),
404 PINCTRL_PIN(92, "RXD4"),
405 PINCTRL_PIN(93, "RTS4_N"),
406 PINCTRL_PIN(94, "CTS4_N"),
407 PINCTRL_PIN(95, "PWM1"),
408 PINCTRL_PIN(96, "PWM2"),
409 PINCTRL_PIN(97, "PWM3"),
410 PINCTRL_PIN(98, "PWM4"),
411 PINCTRL_PIN(99, "PWM5"),
412 PINCTRL_PIN(100, "PWM6"),
413 PINCTRL_PIN(101, "PWM7"),
414 PINCTRL_PIN(102, "GPIO_E"),
417 /* List all groups consisting of these pins dedicated to the enablement of
418 * certain hardware block and the corresponding mode for all of the pins. The
419 * hardware probably has multiple combinations of these pinouts.
423 static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, };
424 static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
426 static int mt7622_emmc_rst_pins[] = { 37, };
427 static int mt7622_emmc_rst_funcs[] = { 1, };
430 static int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, };
431 static int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, };
432 static int mt7622_ephy0_led_pins[] = { 86, };
433 static int mt7622_ephy0_led_funcs[] = { 0, };
434 static int mt7622_ephy1_led_pins[] = { 91, };
435 static int mt7622_ephy1_led_funcs[] = { 2, };
436 static int mt7622_ephy2_led_pins[] = { 92, };
437 static int mt7622_ephy2_led_funcs[] = { 2, };
438 static int mt7622_ephy3_led_pins[] = { 93, };
439 static int mt7622_ephy3_led_funcs[] = { 2, };
440 static int mt7622_ephy4_led_pins[] = { 94, };
441 static int mt7622_ephy4_led_funcs[] = { 2, };
443 /* Embedded Switch */
444 static int mt7622_esw_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
445 62, 63, 64, 65, 66, 67, 68, 69, 70, };
446 static int mt7622_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
447 0, 0, 0, 0, 0, 0, 0, 0, 0, };
448 static int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, };
449 static int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
450 static int mt7622_esw_p2_p3_p4_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 67,
452 static int mt7622_esw_p2_p3_p4_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
455 static int mt7622_rgmii_via_esw_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
457 static int mt7622_rgmii_via_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
460 /* RGMII via GMAC1 */
461 static int mt7622_rgmii_via_gmac1_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
463 static int mt7622_rgmii_via_gmac1_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
466 /* RGMII via GMAC2 */
467 static int mt7622_rgmii_via_gmac2_pins[] = { 25, 26, 27, 28, 29, 30, 31, 32,
469 static int mt7622_rgmii_via_gmac2_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
473 static int mt7622_i2c0_pins[] = { 14, 15, };
474 static int mt7622_i2c0_funcs[] = { 0, 0, };
475 static int mt7622_i2c1_0_pins[] = { 55, 56, };
476 static int mt7622_i2c1_0_funcs[] = { 0, 0, };
477 static int mt7622_i2c1_1_pins[] = { 73, 74, };
478 static int mt7622_i2c1_1_funcs[] = { 3, 3, };
479 static int mt7622_i2c1_2_pins[] = { 87, 88, };
480 static int mt7622_i2c1_2_funcs[] = { 0, 0, };
481 static int mt7622_i2c2_0_pins[] = { 57, 58, };
482 static int mt7622_i2c2_0_funcs[] = { 0, 0, };
483 static int mt7622_i2c2_1_pins[] = { 75, 76, };
484 static int mt7622_i2c2_1_funcs[] = { 3, 3, };
485 static int mt7622_i2c2_2_pins[] = { 89, 90, };
486 static int mt7622_i2c2_2_funcs[] = { 0, 0, };
489 static int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, };
490 static int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, };
491 static int mt7622_i2s1_in_data_pins[] = { 1, };
492 static int mt7622_i2s1_in_data_funcs[] = { 0, };
493 static int mt7622_i2s2_in_data_pins[] = { 16, };
494 static int mt7622_i2s2_in_data_funcs[] = { 0, };
495 static int mt7622_i2s3_in_data_pins[] = { 17, };
496 static int mt7622_i2s3_in_data_funcs[] = { 0, };
497 static int mt7622_i2s4_in_data_pins[] = { 18, };
498 static int mt7622_i2s4_in_data_funcs[] = { 0, };
499 static int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, };
500 static int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, };
501 static int mt7622_i2s1_out_data_pins[] = { 2, };
502 static int mt7622_i2s1_out_data_funcs[] = { 0, };
503 static int mt7622_i2s2_out_data_pins[] = { 19, };
504 static int mt7622_i2s2_out_data_funcs[] = { 0, };
505 static int mt7622_i2s3_out_data_pins[] = { 20, };
506 static int mt7622_i2s3_out_data_funcs[] = { 0, };
507 static int mt7622_i2s4_out_data_pins[] = { 21, };
508 static int mt7622_i2s4_out_data_funcs[] = { 0, };
511 static int mt7622_ir_0_tx_pins[] = { 16, };
512 static int mt7622_ir_0_tx_funcs[] = { 4, };
513 static int mt7622_ir_1_tx_pins[] = { 59, };
514 static int mt7622_ir_1_tx_funcs[] = { 5, };
515 static int mt7622_ir_2_tx_pins[] = { 99, };
516 static int mt7622_ir_2_tx_funcs[] = { 3, };
517 static int mt7622_ir_0_rx_pins[] = { 17, };
518 static int mt7622_ir_0_rx_funcs[] = { 4, };
519 static int mt7622_ir_1_rx_pins[] = { 60, };
520 static int mt7622_ir_1_rx_funcs[] = { 5, };
521 static int mt7622_ir_2_rx_pins[] = { 100, };
522 static int mt7622_ir_2_rx_funcs[] = { 3, };
525 static int mt7622_mdc_mdio_pins[] = { 23, 24, };
526 static int mt7622_mdc_mdio_funcs[] = { 0, 0, };
529 static int mt7622_pcie0_0_waken_pins[] = { 14, };
530 static int mt7622_pcie0_0_waken_funcs[] = { 2, };
531 static int mt7622_pcie0_0_clkreq_pins[] = { 15, };
532 static int mt7622_pcie0_0_clkreq_funcs[] = { 2, };
533 static int mt7622_pcie0_1_waken_pins[] = { 79, };
534 static int mt7622_pcie0_1_waken_funcs[] = { 4, };
535 static int mt7622_pcie0_1_clkreq_pins[] = { 80, };
536 static int mt7622_pcie0_1_clkreq_funcs[] = { 4, };
537 static int mt7622_pcie1_0_waken_pins[] = { 14, };
538 static int mt7622_pcie1_0_waken_funcs[] = { 3, };
539 static int mt7622_pcie1_0_clkreq_pins[] = { 15, };
540 static int mt7622_pcie1_0_clkreq_funcs[] = { 3, };
542 static int mt7622_pcie0_pad_perst_pins[] = { 83, };
543 static int mt7622_pcie0_pad_perst_funcs[] = { 0, };
544 static int mt7622_pcie1_pad_perst_pins[] = { 84, };
545 static int mt7622_pcie1_pad_perst_funcs[] = { 0, };
548 static int mt7622_pmic_bus_pins[] = { 71, 72, };
549 static int mt7622_pmic_bus_funcs[] = { 0, 0, };
552 static int mt7622_pnand_pins[] = { 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
554 static int mt7622_pnand_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
558 static int mt7622_pwm_ch1_0_pins[] = { 51, };
559 static int mt7622_pwm_ch1_0_funcs[] = { 3, };
560 static int mt7622_pwm_ch1_1_pins[] = { 73, };
561 static int mt7622_pwm_ch1_1_funcs[] = { 4, };
562 static int mt7622_pwm_ch1_2_pins[] = { 95, };
563 static int mt7622_pwm_ch1_2_funcs[] = { 0, };
564 static int mt7622_pwm_ch2_0_pins[] = { 52, };
565 static int mt7622_pwm_ch2_0_funcs[] = { 3, };
566 static int mt7622_pwm_ch2_1_pins[] = { 74, };
567 static int mt7622_pwm_ch2_1_funcs[] = { 4, };
568 static int mt7622_pwm_ch2_2_pins[] = { 96, };
569 static int mt7622_pwm_ch2_2_funcs[] = { 0, };
570 static int mt7622_pwm_ch3_0_pins[] = { 53, };
571 static int mt7622_pwm_ch3_0_funcs[] = { 3, };
572 static int mt7622_pwm_ch3_1_pins[] = { 75, };
573 static int mt7622_pwm_ch3_1_funcs[] = { 4, };
574 static int mt7622_pwm_ch3_2_pins[] = { 97, };
575 static int mt7622_pwm_ch3_2_funcs[] = { 0, };
576 static int mt7622_pwm_ch4_0_pins[] = { 54, };
577 static int mt7622_pwm_ch4_0_funcs[] = { 3, };
578 static int mt7622_pwm_ch4_1_pins[] = { 67, };
579 static int mt7622_pwm_ch4_1_funcs[] = { 3, };
580 static int mt7622_pwm_ch4_2_pins[] = { 76, };
581 static int mt7622_pwm_ch4_2_funcs[] = { 4, };
582 static int mt7622_pwm_ch4_3_pins[] = { 98, };
583 static int mt7622_pwm_ch4_3_funcs[] = { 0, };
584 static int mt7622_pwm_ch5_0_pins[] = { 68, };
585 static int mt7622_pwm_ch5_0_funcs[] = { 3, };
586 static int mt7622_pwm_ch5_1_pins[] = { 77, };
587 static int mt7622_pwm_ch5_1_funcs[] = { 4, };
588 static int mt7622_pwm_ch5_2_pins[] = { 99, };
589 static int mt7622_pwm_ch5_2_funcs[] = { 0, };
590 static int mt7622_pwm_ch6_0_pins[] = { 69, };
591 static int mt7622_pwm_ch6_0_funcs[] = { 3, };
592 static int mt7622_pwm_ch6_1_pins[] = { 78, };
593 static int mt7622_pwm_ch6_1_funcs[] = { 4, };
594 static int mt7622_pwm_ch6_2_pins[] = { 81, };
595 static int mt7622_pwm_ch6_2_funcs[] = { 4, };
596 static int mt7622_pwm_ch6_3_pins[] = { 100, };
597 static int mt7622_pwm_ch6_3_funcs[] = { 0, };
598 static int mt7622_pwm_ch7_0_pins[] = { 70, };
599 static int mt7622_pwm_ch7_0_funcs[] = { 3, };
600 static int mt7622_pwm_ch7_1_pins[] = { 82, };
601 static int mt7622_pwm_ch7_1_funcs[] = { 4, };
602 static int mt7622_pwm_ch7_2_pins[] = { 101, };
603 static int mt7622_pwm_ch7_2_funcs[] = { 0, };
606 static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, };
607 static int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, };
608 static int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, };
609 static int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, };
612 static int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, };
613 static int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, };
616 static int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 };
617 static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, };
620 static int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, };
621 static int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, };
622 static int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, };
623 static int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, };
624 static int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, };
625 static int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, };
626 static int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, };
627 static int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, };
628 static int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, };
629 static int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, };
630 static int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, };
631 static int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, };
634 static int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, };
635 static int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
636 static int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, };
637 static int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
638 static int mt7622_tdm_0_out_data_pins[] = { 20, };
639 static int mt7622_tdm_0_out_data_funcs[] = { 3, };
640 static int mt7622_tdm_0_in_data_pins[] = { 21, };
641 static int mt7622_tdm_0_in_data_funcs[] = { 3, };
642 static int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, };
643 static int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
644 static int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, };
645 static int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
646 static int mt7622_tdm_1_out_data_pins[] = { 55, };
647 static int mt7622_tdm_1_out_data_funcs[] = { 3, };
648 static int mt7622_tdm_1_in_data_pins[] = { 56, };
649 static int mt7622_tdm_1_in_data_funcs[] = { 3, };
652 static int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, };
653 static int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, };
654 static int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, };
655 static int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, };
656 static int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, };
657 static int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, };
658 static int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, };
659 static int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, };
660 static int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, };
661 static int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, };
662 static int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, };
663 static int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, };
664 static int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, };
665 static int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, };
666 static int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, };
667 static int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, };
668 static int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, };
669 static int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, };
670 static int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, };
671 static int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, };
672 static int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, };
673 static int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, };
674 static int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, };
675 static int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, };
676 static int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, };
677 static int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, };
678 static int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, };
679 static int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, };
680 static int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, };
681 static int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, };
682 static int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, };
683 static int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, };
684 static int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, };
685 static int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, };
686 static int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 };
687 static int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, };
688 static int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, };
689 static int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, };
690 static int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 };
691 static int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, };
694 static int mt7622_watchdog_pins[] = { 78, };
695 static int mt7622_watchdog_funcs[] = { 0, };
698 static int mt7622_wled_pins[] = { 85, };
699 static int mt7622_wled_funcs[] = { 0, };
701 static const struct group_desc mt7622_groups[] = {
702 PINCTRL_PIN_GROUP("emmc", mt7622_emmc),
703 PINCTRL_PIN_GROUP("emmc_rst", mt7622_emmc_rst),
704 PINCTRL_PIN_GROUP("ephy_leds", mt7622_ephy_leds),
705 PINCTRL_PIN_GROUP("ephy0_led", mt7622_ephy0_led),
706 PINCTRL_PIN_GROUP("ephy1_led", mt7622_ephy1_led),
707 PINCTRL_PIN_GROUP("ephy2_led", mt7622_ephy2_led),
708 PINCTRL_PIN_GROUP("ephy3_led", mt7622_ephy3_led),
709 PINCTRL_PIN_GROUP("ephy4_led", mt7622_ephy4_led),
710 PINCTRL_PIN_GROUP("esw", mt7622_esw),
711 PINCTRL_PIN_GROUP("esw_p0_p1", mt7622_esw_p0_p1),
712 PINCTRL_PIN_GROUP("esw_p2_p3_p4", mt7622_esw_p2_p3_p4),
713 PINCTRL_PIN_GROUP("rgmii_via_esw", mt7622_rgmii_via_esw),
714 PINCTRL_PIN_GROUP("rgmii_via_gmac1", mt7622_rgmii_via_gmac1),
715 PINCTRL_PIN_GROUP("rgmii_via_gmac2", mt7622_rgmii_via_gmac2),
716 PINCTRL_PIN_GROUP("i2c0", mt7622_i2c0),
717 PINCTRL_PIN_GROUP("i2c1_0", mt7622_i2c1_0),
718 PINCTRL_PIN_GROUP("i2c1_1", mt7622_i2c1_1),
719 PINCTRL_PIN_GROUP("i2c1_2", mt7622_i2c1_2),
720 PINCTRL_PIN_GROUP("i2c2_0", mt7622_i2c2_0),
721 PINCTRL_PIN_GROUP("i2c2_1", mt7622_i2c2_1),
722 PINCTRL_PIN_GROUP("i2c2_2", mt7622_i2c2_2),
723 PINCTRL_PIN_GROUP("i2s_out_mclk_bclk_ws", mt7622_i2s_out_mclk_bclk_ws),
724 PINCTRL_PIN_GROUP("i2s_in_mclk_bclk_ws", mt7622_i2s_in_mclk_bclk_ws),
725 PINCTRL_PIN_GROUP("i2s1_in_data", mt7622_i2s1_in_data),
726 PINCTRL_PIN_GROUP("i2s2_in_data", mt7622_i2s2_in_data),
727 PINCTRL_PIN_GROUP("i2s3_in_data", mt7622_i2s3_in_data),
728 PINCTRL_PIN_GROUP("i2s4_in_data", mt7622_i2s4_in_data),
729 PINCTRL_PIN_GROUP("i2s1_out_data", mt7622_i2s1_out_data),
730 PINCTRL_PIN_GROUP("i2s2_out_data", mt7622_i2s2_out_data),
731 PINCTRL_PIN_GROUP("i2s3_out_data", mt7622_i2s3_out_data),
732 PINCTRL_PIN_GROUP("i2s4_out_data", mt7622_i2s4_out_data),
733 PINCTRL_PIN_GROUP("ir_0_tx", mt7622_ir_0_tx),
734 PINCTRL_PIN_GROUP("ir_1_tx", mt7622_ir_1_tx),
735 PINCTRL_PIN_GROUP("ir_2_tx", mt7622_ir_2_tx),
736 PINCTRL_PIN_GROUP("ir_0_rx", mt7622_ir_0_rx),
737 PINCTRL_PIN_GROUP("ir_1_rx", mt7622_ir_1_rx),
738 PINCTRL_PIN_GROUP("ir_2_rx", mt7622_ir_2_rx),
739 PINCTRL_PIN_GROUP("mdc_mdio", mt7622_mdc_mdio),
740 PINCTRL_PIN_GROUP("pcie0_0_waken", mt7622_pcie0_0_waken),
741 PINCTRL_PIN_GROUP("pcie0_0_clkreq", mt7622_pcie0_0_clkreq),
742 PINCTRL_PIN_GROUP("pcie0_1_waken", mt7622_pcie0_1_waken),
743 PINCTRL_PIN_GROUP("pcie0_1_clkreq", mt7622_pcie0_1_clkreq),
744 PINCTRL_PIN_GROUP("pcie1_0_waken", mt7622_pcie1_0_waken),
745 PINCTRL_PIN_GROUP("pcie1_0_clkreq", mt7622_pcie1_0_clkreq),
746 PINCTRL_PIN_GROUP("pcie0_pad_perst", mt7622_pcie0_pad_perst),
747 PINCTRL_PIN_GROUP("pcie1_pad_perst", mt7622_pcie1_pad_perst),
748 PINCTRL_PIN_GROUP("par_nand", mt7622_pnand),
749 PINCTRL_PIN_GROUP("pmic_bus", mt7622_pmic_bus),
750 PINCTRL_PIN_GROUP("pwm_ch1_0", mt7622_pwm_ch1_0),
751 PINCTRL_PIN_GROUP("pwm_ch1_1", mt7622_pwm_ch1_1),
752 PINCTRL_PIN_GROUP("pwm_ch1_2", mt7622_pwm_ch1_2),
753 PINCTRL_PIN_GROUP("pwm_ch2_0", mt7622_pwm_ch2_0),
754 PINCTRL_PIN_GROUP("pwm_ch2_1", mt7622_pwm_ch2_1),
755 PINCTRL_PIN_GROUP("pwm_ch2_2", mt7622_pwm_ch2_2),
756 PINCTRL_PIN_GROUP("pwm_ch3_0", mt7622_pwm_ch3_0),
757 PINCTRL_PIN_GROUP("pwm_ch3_1", mt7622_pwm_ch3_1),
758 PINCTRL_PIN_GROUP("pwm_ch3_2", mt7622_pwm_ch3_2),
759 PINCTRL_PIN_GROUP("pwm_ch4_0", mt7622_pwm_ch4_0),
760 PINCTRL_PIN_GROUP("pwm_ch4_1", mt7622_pwm_ch4_1),
761 PINCTRL_PIN_GROUP("pwm_ch4_2", mt7622_pwm_ch4_2),
762 PINCTRL_PIN_GROUP("pwm_ch4_3", mt7622_pwm_ch4_3),
763 PINCTRL_PIN_GROUP("pwm_ch5_0", mt7622_pwm_ch5_0),
764 PINCTRL_PIN_GROUP("pwm_ch5_1", mt7622_pwm_ch5_1),
765 PINCTRL_PIN_GROUP("pwm_ch5_2", mt7622_pwm_ch5_2),
766 PINCTRL_PIN_GROUP("pwm_ch6_0", mt7622_pwm_ch6_0),
767 PINCTRL_PIN_GROUP("pwm_ch6_1", mt7622_pwm_ch6_1),
768 PINCTRL_PIN_GROUP("pwm_ch6_2", mt7622_pwm_ch6_2),
769 PINCTRL_PIN_GROUP("pwm_ch6_3", mt7622_pwm_ch6_3),
770 PINCTRL_PIN_GROUP("pwm_ch7_0", mt7622_pwm_ch7_0),
771 PINCTRL_PIN_GROUP("pwm_ch7_1", mt7622_pwm_ch7_1),
772 PINCTRL_PIN_GROUP("pwm_ch7_2", mt7622_pwm_ch7_2),
773 PINCTRL_PIN_GROUP("sd_0", mt7622_sd_0),
774 PINCTRL_PIN_GROUP("sd_1", mt7622_sd_1),
775 PINCTRL_PIN_GROUP("snfi", mt7622_snfi),
776 PINCTRL_PIN_GROUP("spi_nor", mt7622_spi),
777 PINCTRL_PIN_GROUP("spic0_0", mt7622_spic0_0),
778 PINCTRL_PIN_GROUP("spic0_1", mt7622_spic0_1),
779 PINCTRL_PIN_GROUP("spic1_0", mt7622_spic1_0),
780 PINCTRL_PIN_GROUP("spic1_1", mt7622_spic1_1),
781 PINCTRL_PIN_GROUP("spic2_0", mt7622_spic2_0),
782 PINCTRL_PIN_GROUP("spic2_0_wp_hold", mt7622_spic2_0_wp_hold),
783 PINCTRL_PIN_GROUP("tdm_0_out_mclk_bclk_ws",
784 mt7622_tdm_0_out_mclk_bclk_ws),
785 PINCTRL_PIN_GROUP("tdm_0_in_mclk_bclk_ws",
786 mt7622_tdm_0_in_mclk_bclk_ws),
787 PINCTRL_PIN_GROUP("tdm_0_out_data", mt7622_tdm_0_out_data),
788 PINCTRL_PIN_GROUP("tdm_0_in_data", mt7622_tdm_0_in_data),
789 PINCTRL_PIN_GROUP("tdm_1_out_mclk_bclk_ws",
790 mt7622_tdm_1_out_mclk_bclk_ws),
791 PINCTRL_PIN_GROUP("tdm_1_in_mclk_bclk_ws",
792 mt7622_tdm_1_in_mclk_bclk_ws),
793 PINCTRL_PIN_GROUP("tdm_1_out_data", mt7622_tdm_1_out_data),
794 PINCTRL_PIN_GROUP("tdm_1_in_data", mt7622_tdm_1_in_data),
795 PINCTRL_PIN_GROUP("uart0_0_tx_rx", mt7622_uart0_0_tx_rx),
796 PINCTRL_PIN_GROUP("uart1_0_tx_rx", mt7622_uart1_0_tx_rx),
797 PINCTRL_PIN_GROUP("uart1_0_rts_cts", mt7622_uart1_0_rts_cts),
798 PINCTRL_PIN_GROUP("uart1_1_tx_rx", mt7622_uart1_1_tx_rx),
799 PINCTRL_PIN_GROUP("uart1_1_rts_cts", mt7622_uart1_1_rts_cts),
800 PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7622_uart2_0_tx_rx),
801 PINCTRL_PIN_GROUP("uart2_0_rts_cts", mt7622_uart2_0_rts_cts),
802 PINCTRL_PIN_GROUP("uart2_1_tx_rx", mt7622_uart2_1_tx_rx),
803 PINCTRL_PIN_GROUP("uart2_1_rts_cts", mt7622_uart2_1_rts_cts),
804 PINCTRL_PIN_GROUP("uart2_2_tx_rx", mt7622_uart2_2_tx_rx),
805 PINCTRL_PIN_GROUP("uart2_2_rts_cts", mt7622_uart2_2_rts_cts),
806 PINCTRL_PIN_GROUP("uart2_3_tx_rx", mt7622_uart2_3_tx_rx),
807 PINCTRL_PIN_GROUP("uart3_0_tx_rx", mt7622_uart3_0_tx_rx),
808 PINCTRL_PIN_GROUP("uart3_1_tx_rx", mt7622_uart3_1_tx_rx),
809 PINCTRL_PIN_GROUP("uart3_1_rts_cts", mt7622_uart3_1_rts_cts),
810 PINCTRL_PIN_GROUP("uart4_0_tx_rx", mt7622_uart4_0_tx_rx),
811 PINCTRL_PIN_GROUP("uart4_1_tx_rx", mt7622_uart4_1_tx_rx),
812 PINCTRL_PIN_GROUP("uart4_1_rts_cts", mt7622_uart4_1_rts_cts),
813 PINCTRL_PIN_GROUP("uart4_2_tx_rx", mt7622_uart4_2_tx_rx),
814 PINCTRL_PIN_GROUP("uart4_2_rts_cts", mt7622_uart4_2_rts_cts),
815 PINCTRL_PIN_GROUP("watchdog", mt7622_watchdog),
816 PINCTRL_PIN_GROUP("wled", mt7622_wled),
819 /* Joint those groups owning the same capability in user point of view which
820 * allows that people tend to use through the device tree.
822 static const char *mt7622_emmc_groups[] = { "emmc", "emmc_rst", };
823 static const char *mt7622_ethernet_groups[] = { "esw", "esw_p0_p1",
824 "esw_p2_p3_p4", "mdc_mdio",
828 static const char *mt7622_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1",
829 "i2c1_2", "i2c2_0", "i2c2_1",
831 static const char *mt7622_i2s_groups[] = { "i2s_out_mclk_bclk_ws",
832 "i2s_in_mclk_bclk_ws",
833 "i2s1_in_data", "i2s2_in_data",
834 "i2s3_in_data", "i2s4_in_data",
835 "i2s1_out_data", "i2s2_out_data",
836 "i2s3_out_data", "i2s4_out_data", };
837 static const char *mt7622_ir_groups[] = { "ir_0_tx", "ir_1_tx", "ir_2_tx",
838 "ir_0_rx", "ir_1_rx", "ir_2_rx"};
839 static const char *mt7622_led_groups[] = { "ephy_leds", "ephy0_led",
840 "ephy1_led", "ephy2_led",
841 "ephy3_led", "ephy4_led",
843 static const char *mt7622_flash_groups[] = { "par_nand", "snfi", "spi_nor"};
844 static const char *mt7622_pcie_groups[] = { "pcie0_0_waken", "pcie0_0_clkreq",
845 "pcie0_1_waken", "pcie0_1_clkreq",
846 "pcie1_0_waken", "pcie1_0_clkreq",
848 "pcie1_pad_perst", };
849 static const char *mt7622_pmic_bus_groups[] = { "pmic_bus", };
850 static const char *mt7622_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1",
851 "pwm_ch1_2", "pwm_ch2_0",
852 "pwm_ch2_1", "pwm_ch2_2",
853 "pwm_ch3_0", "pwm_ch3_1",
854 "pwm_ch3_2", "pwm_ch4_0",
855 "pwm_ch4_1", "pwm_ch4_2",
856 "pwm_ch4_3", "pwm_ch5_0",
857 "pwm_ch5_1", "pwm_ch5_2",
858 "pwm_ch6_0", "pwm_ch6_1",
859 "pwm_ch6_2", "pwm_ch6_3",
860 "pwm_ch7_0", "pwm_ch7_1",
862 static const char *mt7622_sd_groups[] = { "sd_0", "sd_1", };
863 static const char *mt7622_spic_groups[] = { "spic0_0", "spic0_1", "spic1_0",
864 "spic1_1", "spic2_0",
865 "spic2_0_wp_hold", };
866 static const char *mt7622_tdm_groups[] = { "tdm_0_out_mclk_bclk_ws",
867 "tdm_0_in_mclk_bclk_ws",
870 "tdm_1_out_mclk_bclk_ws",
871 "tdm_1_in_mclk_bclk_ws",
875 static const char *mt7622_uart_groups[] = { "uart0_0_tx_rx",
876 "uart1_0_tx_rx", "uart1_0_rts_cts",
877 "uart1_1_tx_rx", "uart1_1_rts_cts",
878 "uart2_0_tx_rx", "uart2_0_rts_cts",
879 "uart2_1_tx_rx", "uart2_1_rts_cts",
880 "uart2_2_tx_rx", "uart2_2_rts_cts",
883 "uart3_1_tx_rx", "uart3_1_rts_cts",
885 "uart4_1_tx_rx", "uart4_1_rts_cts",
888 static const char *mt7622_wdt_groups[] = { "watchdog", };
890 static const struct function_desc mt7622_functions[] = {
891 {"emmc", mt7622_emmc_groups, ARRAY_SIZE(mt7622_emmc_groups)},
892 {"eth", mt7622_ethernet_groups, ARRAY_SIZE(mt7622_ethernet_groups)},
893 {"i2c", mt7622_i2c_groups, ARRAY_SIZE(mt7622_i2c_groups)},
894 {"i2s", mt7622_i2s_groups, ARRAY_SIZE(mt7622_i2s_groups)},
895 {"ir", mt7622_ir_groups, ARRAY_SIZE(mt7622_ir_groups)},
896 {"led", mt7622_led_groups, ARRAY_SIZE(mt7622_led_groups)},
897 {"flash", mt7622_flash_groups, ARRAY_SIZE(mt7622_flash_groups)},
898 {"pcie", mt7622_pcie_groups, ARRAY_SIZE(mt7622_pcie_groups)},
899 {"pmic", mt7622_pmic_bus_groups, ARRAY_SIZE(mt7622_pmic_bus_groups)},
900 {"pwm", mt7622_pwm_groups, ARRAY_SIZE(mt7622_pwm_groups)},
901 {"sd", mt7622_sd_groups, ARRAY_SIZE(mt7622_sd_groups)},
902 {"spi", mt7622_spic_groups, ARRAY_SIZE(mt7622_spic_groups)},
903 {"tdm", mt7622_tdm_groups, ARRAY_SIZE(mt7622_tdm_groups)},
904 {"uart", mt7622_uart_groups, ARRAY_SIZE(mt7622_uart_groups)},
905 {"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)},
908 static const struct pinconf_generic_params mtk_custom_bindings[] = {
909 {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
910 {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
913 #ifdef CONFIG_DEBUG_FS
914 static const struct pin_config_item mtk_conf_items[] = {
915 PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
916 PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
920 static const struct mtk_eint_hw mt7622_eint_hw = {
923 .ap_num = ARRAY_SIZE(mt7622_pins),
927 static const struct mtk_pin_soc mt7622_data = {
928 .reg_cal = mt7622_reg_cals,
930 .npins = ARRAY_SIZE(mt7622_pins),
931 .grps = mt7622_groups,
932 .ngrps = ARRAY_SIZE(mt7622_groups),
933 .funcs = mt7622_functions,
934 .nfuncs = ARRAY_SIZE(mt7622_functions),
935 .eint_hw = &mt7622_eint_hw,
938 static void mtk_w32(struct mtk_pinctrl *pctl, u32 reg, u32 val)
940 writel_relaxed(val, pctl->base + reg);
943 static u32 mtk_r32(struct mtk_pinctrl *pctl, u32 reg)
945 return readl_relaxed(pctl->base + reg);
948 static void mtk_rmw(struct mtk_pinctrl *pctl, u32 reg, u32 mask, u32 set)
952 val = mtk_r32(pctl, reg);
955 mtk_w32(pctl, reg, val);
958 static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw, int pin,
959 const struct mtk_pin_reg_calc *rc,
960 struct mtk_pin_field *pfd)
962 const struct mtk_pin_field_calc *c, *e;
969 if (pin >= c->s_pin && pin <= c->e_pin)
975 dev_err(hw->dev, "Out of range for pin = %d\n", pin);
979 /* Caculated bits as the overall offset the pin is located at */
980 bits = c->s_bit + (pin - c->s_pin) * (c->x_bits);
982 /* Fill pfd from bits and 32-bit register applied is assumed */
983 pfd->offset = c->s_addr + c->x_addrs * (bits / 32);
984 pfd->bitpos = bits % 32;
985 pfd->mask = (1 << c->x_bits) - 1;
987 /* pfd->next is used for indicating that bit wrapping-around happens
988 * which requires the manipulation for bit 0 starting in the next
989 * register to form the complete field read/write.
991 pfd->next = pfd->bitpos + c->x_bits - 1 > 31 ? c->x_addrs : 0;
996 static int mtk_hw_pin_field_get(struct mtk_pinctrl *hw, int pin,
997 int field, struct mtk_pin_field *pfd)
999 const struct mtk_pin_reg_calc *rc;
1001 if (field < 0 || field >= PINCTRL_PIN_REG_MAX) {
1002 dev_err(hw->dev, "Invalid Field %d\n", field);
1006 if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) {
1007 rc = &hw->soc->reg_cal[field];
1009 dev_err(hw->dev, "Undefined range for field %d\n", field);
1013 return mtk_hw_pin_field_lookup(hw, pin, rc, pfd);
1016 static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l)
1018 *l = 32 - pf->bitpos;
1019 *h = get_count_order(pf->mask) - *l;
1022 static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw,
1023 struct mtk_pin_field *pf, int value)
1025 int nbits_l, nbits_h;
1027 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
1029 mtk_rmw(hw, pf->offset, pf->mask << pf->bitpos,
1030 (value & pf->mask) << pf->bitpos);
1032 mtk_rmw(hw, pf->offset + pf->next, BIT(nbits_h) - 1,
1033 (value & pf->mask) >> nbits_l);
1036 static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw,
1037 struct mtk_pin_field *pf, int *value)
1039 int nbits_l, nbits_h, h, l;
1041 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
1043 l = (mtk_r32(hw, pf->offset) >> pf->bitpos) & (BIT(nbits_l) - 1);
1044 h = (mtk_r32(hw, pf->offset + pf->next)) & (BIT(nbits_h) - 1);
1046 *value = (h << nbits_l) | l;
1049 static int mtk_hw_set_value(struct mtk_pinctrl *hw, int pin, int field,
1052 struct mtk_pin_field pf;
1055 err = mtk_hw_pin_field_get(hw, pin, field, &pf);
1060 mtk_rmw(hw, pf.offset, pf.mask << pf.bitpos,
1061 (value & pf.mask) << pf.bitpos);
1063 mtk_hw_write_cross_field(hw, &pf, value);
1068 static int mtk_hw_get_value(struct mtk_pinctrl *hw, int pin, int field,
1071 struct mtk_pin_field pf;
1074 err = mtk_hw_pin_field_get(hw, pin, field, &pf);
1079 *value = (mtk_r32(hw, pf.offset) >> pf.bitpos) & pf.mask;
1081 mtk_hw_read_cross_field(hw, &pf, value);
1086 static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev,
1087 unsigned int selector, unsigned int group)
1089 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
1090 struct function_desc *func;
1091 struct group_desc *grp;
1094 func = pinmux_generic_get_function(pctldev, selector);
1098 grp = pinctrl_generic_get_group(pctldev, group);
1102 dev_dbg(pctldev->dev, "enable function %s group %s\n",
1103 func->name, grp->name);
1105 for (i = 0; i < grp->num_pins; i++) {
1106 int *pin_modes = grp->data;
1108 mtk_hw_set_value(hw, grp->pins[i], PINCTRL_PIN_REG_MODE,
1115 static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
1116 struct pinctrl_gpio_range *range,
1119 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
1121 return mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_MODE, MTK_GPIO_MODE);
1124 static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
1125 struct pinctrl_gpio_range *range,
1126 unsigned int pin, bool input)
1128 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
1130 /* hardware would take 0 as input direction */
1131 return mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DIR, !input);
1134 static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
1135 unsigned int pin, unsigned long *config)
1137 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
1138 u32 param = pinconf_to_config_param(*config);
1139 int val, val2, err, reg, ret = 1;
1142 case PIN_CONFIG_BIAS_DISABLE:
1143 err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_PU, &val);
1147 err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_PD, &val2);
1155 case PIN_CONFIG_BIAS_PULL_UP:
1156 case PIN_CONFIG_BIAS_PULL_DOWN:
1157 case PIN_CONFIG_SLEW_RATE:
1158 reg = (param == PIN_CONFIG_BIAS_PULL_UP) ?
1159 PINCTRL_PIN_REG_PU :
1160 (param == PIN_CONFIG_BIAS_PULL_DOWN) ?
1161 PINCTRL_PIN_REG_PD : PINCTRL_PIN_REG_SR;
1163 err = mtk_hw_get_value(hw, pin, reg, &val);
1171 case PIN_CONFIG_INPUT_ENABLE:
1172 case PIN_CONFIG_OUTPUT_ENABLE:
1173 err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_DIR, &val);
1177 /* HW takes input mode as zero; output mode as non-zero */
1178 if ((val && param == PIN_CONFIG_INPUT_ENABLE) ||
1179 (!val && param == PIN_CONFIG_OUTPUT_ENABLE))
1183 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1184 err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_DIR, &val);
1188 err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_SMT, &val2);
1196 case PIN_CONFIG_DRIVE_STRENGTH:
1197 err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_E4, &val);
1201 err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_E8, &val2);
1205 /* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1)
1206 * 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1)
1208 ret = ((val2 << 1) + val + 1) * 4;
1211 case MTK_PIN_CONFIG_TDSEL:
1212 case MTK_PIN_CONFIG_RDSEL:
1213 reg = (param == MTK_PIN_CONFIG_TDSEL) ?
1214 PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
1216 err = mtk_hw_get_value(hw, pin, reg, &val);
1227 *config = pinconf_to_config_packed(param, ret);
1232 static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1233 unsigned long *configs, unsigned int num_configs)
1235 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
1236 u32 reg, param, arg;
1239 for (cfg = 0; cfg < num_configs; cfg++) {
1240 param = pinconf_to_config_param(configs[cfg]);
1241 arg = pinconf_to_config_argument(configs[cfg]);
1244 case PIN_CONFIG_BIAS_DISABLE:
1245 case PIN_CONFIG_BIAS_PULL_UP:
1246 case PIN_CONFIG_BIAS_PULL_DOWN:
1247 arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
1248 (param == PIN_CONFIG_BIAS_PULL_UP) ? 1 : 2;
1250 err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_PU,
1255 err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_PD,
1260 case PIN_CONFIG_OUTPUT_ENABLE:
1261 err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_SMT,
1265 /* else: fall through */
1266 case PIN_CONFIG_INPUT_ENABLE:
1267 case PIN_CONFIG_SLEW_RATE:
1268 reg = (param == PIN_CONFIG_SLEW_RATE) ?
1269 PINCTRL_PIN_REG_SR : PINCTRL_PIN_REG_DIR;
1271 arg = (param == PIN_CONFIG_INPUT_ENABLE) ? 0 :
1272 (param == PIN_CONFIG_OUTPUT_ENABLE) ? 1 : arg;
1273 err = mtk_hw_set_value(hw, pin, reg, arg);
1278 case PIN_CONFIG_OUTPUT:
1279 err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DIR,
1284 err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DO,
1289 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1290 /* arg = 1: Input mode & SMT enable ;
1291 * arg = 0: Output mode & SMT disable
1294 err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DIR,
1299 err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_SMT,
1304 case PIN_CONFIG_DRIVE_STRENGTH:
1305 /* 4mA when (e8, e4) = (0, 0);
1306 * 8mA when (e8, e4) = (0, 1);
1307 * 12mA when (e8, e4) = (1, 0);
1308 * 16mA when (e8, e4) = (1, 1)
1310 if (!(arg % 4) && (arg >= 4 && arg <= 16)) {
1312 err = mtk_hw_set_value(hw, pin,
1318 err = mtk_hw_set_value(hw, pin,
1327 case MTK_PIN_CONFIG_TDSEL:
1328 case MTK_PIN_CONFIG_RDSEL:
1329 reg = (param == MTK_PIN_CONFIG_TDSEL) ?
1330 PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
1332 err = mtk_hw_set_value(hw, pin, reg, arg);
1344 static int mtk_pinconf_group_get(struct pinctrl_dev *pctldev,
1345 unsigned int group, unsigned long *config)
1347 const unsigned int *pins;
1348 unsigned int i, npins, old = 0;
1351 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
1355 for (i = 0; i < npins; i++) {
1356 if (mtk_pinconf_get(pctldev, pins[i], config))
1359 /* configs do not match between two pins */
1360 if (i && old != *config)
1369 static int mtk_pinconf_group_set(struct pinctrl_dev *pctldev,
1370 unsigned int group, unsigned long *configs,
1371 unsigned int num_configs)
1373 const unsigned int *pins;
1374 unsigned int i, npins;
1377 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
1381 for (i = 0; i < npins; i++) {
1382 ret = mtk_pinconf_set(pctldev, pins[i], configs, num_configs);
1390 static const struct pinctrl_ops mtk_pctlops = {
1391 .get_groups_count = pinctrl_generic_get_group_count,
1392 .get_group_name = pinctrl_generic_get_group_name,
1393 .get_group_pins = pinctrl_generic_get_group_pins,
1394 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
1395 .dt_free_map = pinconf_generic_dt_free_map,
1398 static const struct pinmux_ops mtk_pmxops = {
1399 .get_functions_count = pinmux_generic_get_function_count,
1400 .get_function_name = pinmux_generic_get_function_name,
1401 .get_function_groups = pinmux_generic_get_function_groups,
1402 .set_mux = mtk_pinmux_set_mux,
1403 .gpio_request_enable = mtk_pinmux_gpio_request_enable,
1404 .gpio_set_direction = mtk_pinmux_gpio_set_direction,
1408 static const struct pinconf_ops mtk_confops = {
1410 .pin_config_get = mtk_pinconf_get,
1411 .pin_config_set = mtk_pinconf_set,
1412 .pin_config_group_get = mtk_pinconf_group_get,
1413 .pin_config_group_set = mtk_pinconf_group_set,
1414 .pin_config_config_dbg_show = pinconf_generic_dump_config,
1417 static struct pinctrl_desc mtk_desc = {
1418 .name = PINCTRL_PINCTRL_DEV,
1419 .pctlops = &mtk_pctlops,
1420 .pmxops = &mtk_pmxops,
1421 .confops = &mtk_confops,
1422 .owner = THIS_MODULE,
1425 static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
1427 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
1430 err = mtk_hw_get_value(hw, gpio, PINCTRL_PIN_REG_DI, &value);
1437 static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
1439 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
1441 mtk_hw_set_value(hw, gpio, PINCTRL_PIN_REG_DO, !!value);
1444 static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
1446 return pinctrl_gpio_direction_input(chip->base + gpio);
1449 static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
1452 mtk_gpio_set(chip, gpio, value);
1454 return pinctrl_gpio_direction_output(chip->base + gpio);
1457 static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
1459 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
1460 unsigned long eint_n;
1467 return mtk_eint_find_irq(hw->eint, eint_n);
1470 static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
1471 unsigned long config)
1473 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
1474 unsigned long eint_n;
1478 pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
1481 debounce = pinconf_to_config_argument(config);
1484 return mtk_eint_set_debounce(hw->eint, eint_n, debounce);
1487 static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
1489 struct gpio_chip *chip = &hw->chip;
1492 chip->label = PINCTRL_PINCTRL_DEV;
1493 chip->parent = hw->dev;
1494 chip->request = gpiochip_generic_request;
1495 chip->free = gpiochip_generic_free;
1496 chip->direction_input = mtk_gpio_direction_input;
1497 chip->direction_output = mtk_gpio_direction_output;
1498 chip->get = mtk_gpio_get;
1499 chip->set = mtk_gpio_set;
1500 chip->to_irq = mtk_gpio_to_irq,
1501 chip->set_config = mtk_gpio_set_config,
1503 chip->ngpio = hw->soc->npins;
1505 chip->of_gpio_n_cells = 2;
1507 ret = gpiochip_add_data(chip, hw);
1511 /* Just for backward compatible for these old pinctrl nodes without
1512 * "gpio-ranges" property. Otherwise, called directly from a
1513 * DeviceTree-supported pinctrl driver is DEPRECATED.
1514 * Please see Section 2.1 of
1515 * Documentation/devicetree/bindings/gpio/gpio.txt on how to
1516 * bind pinctrl and gpio drivers via the "gpio-ranges" property.
1518 if (!of_find_property(np, "gpio-ranges", NULL)) {
1519 ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0,
1522 gpiochip_remove(chip);
1530 static int mtk_build_groups(struct mtk_pinctrl *hw)
1534 for (i = 0; i < hw->soc->ngrps; i++) {
1535 const struct group_desc *group = hw->soc->grps + i;
1537 err = pinctrl_generic_add_group(hw->pctrl, group->name,
1538 group->pins, group->num_pins,
1541 dev_err(hw->dev, "Failed to register group %s\n",
1550 static int mtk_build_functions(struct mtk_pinctrl *hw)
1554 for (i = 0; i < hw->soc->nfuncs ; i++) {
1555 const struct function_desc *func = hw->soc->funcs + i;
1557 err = pinmux_generic_add_function(hw->pctrl, func->name,
1559 func->num_group_names,
1562 dev_err(hw->dev, "Failed to register function %s\n",
1571 static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n,
1572 unsigned int *gpio_n,
1573 struct gpio_chip **gpio_chip)
1575 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
1577 *gpio_chip = &hw->chip;
1583 static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n)
1585 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
1586 struct gpio_chip *gpio_chip;
1587 unsigned int gpio_n;
1590 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
1594 return mtk_gpio_get(gpio_chip, gpio_n);
1597 static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
1599 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
1600 struct gpio_chip *gpio_chip;
1601 unsigned int gpio_n;
1604 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
1608 err = mtk_hw_set_value(hw, gpio_n, PINCTRL_PIN_REG_MODE,
1613 err = mtk_hw_set_value(hw, gpio_n, PINCTRL_PIN_REG_DIR, MTK_INPUT);
1617 err = mtk_hw_set_value(hw, gpio_n, PINCTRL_PIN_REG_SMT, MTK_ENABLE);
1624 static const struct mtk_eint_xt mtk_eint_xt = {
1625 .get_gpio_n = mtk_xt_get_gpio_n,
1626 .get_gpio_state = mtk_xt_get_gpio_state,
1627 .set_gpio_as_eint = mtk_xt_set_gpio_as_eint,
1631 mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev)
1633 struct device_node *np = pdev->dev.of_node;
1634 struct resource *res;
1636 if (!IS_ENABLED(CONFIG_EINT_MTK))
1639 if (!of_property_read_bool(np, "interrupt-controller"))
1642 hw->eint = devm_kzalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL);
1646 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eint");
1648 dev_err(&pdev->dev, "Unable to get eint resource\n");
1652 hw->eint->base = devm_ioremap_resource(&pdev->dev, res);
1653 if (IS_ERR(hw->eint->base))
1654 return PTR_ERR(hw->eint->base);
1656 hw->eint->irq = irq_of_parse_and_map(np, 0);
1660 hw->eint->dev = &pdev->dev;
1661 hw->eint->hw = hw->soc->eint_hw;
1662 hw->eint->pctl = hw;
1663 hw->eint->gpio_xlate = &mtk_eint_xt;
1665 return mtk_eint_do_init(hw->eint);
1668 static const struct of_device_id mtk_pinctrl_of_match[] = {
1669 { .compatible = "mediatek,mt7622-pinctrl", .data = &mt7622_data},
1673 static int mtk_pinctrl_probe(struct platform_device *pdev)
1675 struct resource *res;
1676 struct mtk_pinctrl *hw;
1677 const struct of_device_id *of_id =
1678 of_match_device(mtk_pinctrl_of_match, &pdev->dev);
1681 hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
1685 hw->soc = of_id->data;
1687 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1689 dev_err(&pdev->dev, "missing IO resource\n");
1693 hw->dev = &pdev->dev;
1694 hw->base = devm_ioremap_resource(&pdev->dev, res);
1695 if (IS_ERR(hw->base))
1696 return PTR_ERR(hw->base);
1698 /* Setup pins descriptions per SoC types */
1699 mtk_desc.pins = hw->soc->pins;
1700 mtk_desc.npins = hw->soc->npins;
1701 mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
1702 mtk_desc.custom_params = mtk_custom_bindings;
1703 #ifdef CONFIG_DEBUG_FS
1704 mtk_desc.custom_conf_items = mtk_conf_items;
1707 err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
1712 /* Setup groups descriptions per SoC types */
1713 err = mtk_build_groups(hw);
1715 dev_err(&pdev->dev, "Failed to build groups\n");
1719 /* Setup functions descriptions per SoC types */
1720 err = mtk_build_functions(hw);
1722 dev_err(&pdev->dev, "Failed to build functions\n");
1726 /* For able to make pinctrl_claim_hogs, we must not enable pinctrl
1727 * until all groups and functions are being added one.
1729 err = pinctrl_enable(hw->pctrl);
1733 err = mtk_build_eint(hw, pdev);
1735 dev_warn(&pdev->dev,
1736 "Failed to add EINT, but pinctrl still can work\n");
1738 /* Build gpiochip should be after pinctrl_enable is done */
1739 err = mtk_build_gpiochip(hw, pdev->dev.of_node);
1741 dev_err(&pdev->dev, "Failed to add gpio_chip\n");
1745 platform_set_drvdata(pdev, hw);
1750 static struct platform_driver mtk_pinctrl_driver = {
1752 .name = "mtk-pinctrl",
1753 .of_match_table = mtk_pinctrl_of_match,
1755 .probe = mtk_pinctrl_probe,
1758 static int __init mtk_pinctrl_init(void)
1760 return platform_driver_register(&mtk_pinctrl_driver);
1762 arch_initcall(mtk_pinctrl_init);