drivers/pinctrl/intel/pinctrl-intel.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel pinctrl/GPIO core driver.
   4  *
   5  * Copyright (C) 2015, Intel Corporation
   6  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
   7  *          Mika Westerberg <mika.westerberg@linux.intel.com>
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/cleanup.h>
  12 #include <linux/export.h>
  13 #include <linux/gpio/driver.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/log2.h>
  16 #include <linux/module.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/property.h>
  19 #include <linux/seq_file.h>
  20 #include <linux/string_helpers.h>
  21 #include <linux/time.h>
  22
  23 #include <linux/pinctrl/consumer.h>
  24 #include <linux/pinctrl/pinconf.h>
  25 #include <linux/pinctrl/pinconf-generic.h>
  26 #include <linux/pinctrl/pinctrl.h>
  27 #include <linux/pinctrl/pinmux.h>
  28
  29 #include <linux/platform_data/x86/pwm-lpss.h>
  30
  31 #include "../core.h"
  32 #include "pinctrl-intel.h"
  33
  34 /* Offset from regs */
  35 #define REVID                           0x000
  36 #define REVID_SHIFT                     16
  37 #define REVID_MASK                      GENMASK(31, 16)
  38
  39 #define CAPLIST                         0x004
  40 #define CAPLIST_ID_SHIFT                16
  41 #define CAPLIST_ID_MASK                 GENMASK(23, 16)
  42 #define CAPLIST_ID_GPIO_HW_INFO         1
  43 #define CAPLIST_ID_PWM                  2
  44 #define CAPLIST_ID_BLINK                3
  45 #define CAPLIST_ID_EXP                  4
  46 #define CAPLIST_NEXT_SHIFT              0
  47 #define CAPLIST_NEXT_MASK               GENMASK(15, 0)
  48
  49 #define PADBAR                          0x00c
  50
  51 #define PADOWN_BITS                     4
  52 #define PADOWN_SHIFT(p)                 ((p) % 8 * PADOWN_BITS)
  53 #define PADOWN_MASK(p)                  (GENMASK(3, 0) << PADOWN_SHIFT(p))
  54 #define PADOWN_GPP(p)                   ((p) / 8)
  55
  56 #define PWMC                            0x204
  57
  58 /* Offset from pad_regs */
  59 #define PADCFG0                         0x000
  60 #define PADCFG0_RXEVCFG_MASK            GENMASK(26, 25)
  61 #define PADCFG0_RXEVCFG_LEVEL           (0 << 25)
  62 #define PADCFG0_RXEVCFG_EDGE            (1 << 25)
  63 #define PADCFG0_RXEVCFG_DISABLED        (2 << 25)
  64 #define PADCFG0_RXEVCFG_EDGE_BOTH       (3 << 25)
  65 #define PADCFG0_PREGFRXSEL              BIT(24)
  66 #define PADCFG0_RXINV                   BIT(23)
  67 #define PADCFG0_GPIROUTIOXAPIC          BIT(20)
  68 #define PADCFG0_GPIROUTSCI              BIT(19)
  69 #define PADCFG0_GPIROUTSMI              BIT(18)
  70 #define PADCFG0_GPIROUTNMI              BIT(17)
  71 #define PADCFG0_PMODE_SHIFT             10
  72 #define PADCFG0_PMODE_MASK              GENMASK(13, 10)
  73 #define PADCFG0_PMODE_GPIO              0
  74 #define PADCFG0_GPIODIS_SHIFT           8
  75 #define PADCFG0_GPIODIS_MASK            GENMASK(9, 8)
  76 #define PADCFG0_GPIODIS_NONE            0
  77 #define PADCFG0_GPIODIS_OUTPUT          1
  78 #define PADCFG0_GPIODIS_INPUT           2
  79 #define PADCFG0_GPIODIS_FULL            3
  80 #define PADCFG0_GPIORXDIS               BIT(9)
  81 #define PADCFG0_GPIOTXDIS               BIT(8)
  82 #define PADCFG0_GPIORXSTATE             BIT(1)
  83 #define PADCFG0_GPIOTXSTATE             BIT(0)
  84
  85 #define PADCFG1                         0x004
  86 #define PADCFG1_TERM_UP                 BIT(13)
  87 #define PADCFG1_TERM_SHIFT              10
  88 #define PADCFG1_TERM_MASK               GENMASK(12, 10)
  89 /*
  90  * Bit 0  Bit 1  Bit 2                  Value, Ohms
  91  *
  92  *   0      0      0                    -
  93  *   0      0      1                    20000
  94  *   0      1      0                    5000
  95  *   0      1      1                    ~4000
  96  *   1      0      0                    1000 (if supported)
  97  *   1      0      1                    ~952 (if supported)
  98  *   1      1      0                    ~833 (if supported)
  99  *   1      1      1                    ~800 (if supported)
 100  */
 101 #define PADCFG1_TERM_20K                BIT(2)
 102 #define PADCFG1_TERM_5K                 BIT(1)
 103 #define PADCFG1_TERM_4K                 (BIT(2) | BIT(1))
 104 #define PADCFG1_TERM_1K                 BIT(0)
 105 #define PADCFG1_TERM_952                (BIT(2) | BIT(0))
 106 #define PADCFG1_TERM_833                (BIT(1) | BIT(0))
 107 #define PADCFG1_TERM_800                (BIT(2) | BIT(1) | BIT(0))
 108
 109 #define PADCFG2                         0x008
 110 #define PADCFG2_DEBOUNCE_SHIFT          1
 111 #define PADCFG2_DEBOUNCE_MASK           GENMASK(4, 1)
 112 #define PADCFG2_DEBEN                   BIT(0)
 113
 114 #define DEBOUNCE_PERIOD_NSEC            31250
 115
 116 struct intel_pad_context {
 117         u32 padcfg0;
 118         u32 padcfg1;
 119         u32 padcfg2;
 120 };
 121
 122 struct intel_community_context {
 123         u32 *intmask;
 124         u32 *hostown;
 125 };
 126
 127 #define pin_to_padno(c, p)      ((p) - (c)->pin_base)
 128 #define padgroup_offset(g, p)   ((p) - (g)->base)
 129
 130 #define for_each_intel_pin_community(pctrl, community)                                  \
 131         for (unsigned int __ci = 0;                                                     \
 132              __ci < pctrl->ncommunities && (community = &pctrl->communities[__ci]);     \
 133              __ci++)                                                                    \
 134
 135 #define for_each_intel_community_pad_group(community, grp)                      \
 136         for (unsigned int __gi = 0;                                             \
 137              __gi < community->ngpps && (grp = &community->gpps[__gi]);         \
 138              __gi++)                                                            \
 139
 140 #define for_each_intel_pad_group(pctrl, community, grp)                 \
 141         for_each_intel_pin_community(pctrl, community)                  \
 142                 for_each_intel_community_pad_group(community, grp)
 143
 144 #define for_each_intel_gpio_group(pctrl, community, grp)                \
 145         for_each_intel_pad_group(pctrl, community, grp)                 \
 146                 if (grp->gpio_base == INTEL_GPIO_BASE_NOMAP) {} else
 147
 148 const struct intel_community *intel_get_community(const struct intel_pinctrl *pctrl,
 149                                                   unsigned int pin)
 150 {
 151         const struct intel_community *community;
 152
 153         for_each_intel_pin_community(pctrl, community) {
 154                 if (pin >= community->pin_base &&
 155                     pin < community->pin_base + community->npins)
 156                         return community;
 157         }
 158
 159         dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
 160         return NULL;
 161 }
 162 EXPORT_SYMBOL_NS_GPL(intel_get_community, "PINCTRL_INTEL");
 163
 164 static const struct intel_padgroup *
 165 intel_community_get_padgroup(const struct intel_community *community,
 166                              unsigned int pin)
 167 {
 168         const struct intel_padgroup *padgrp;
 169
 170         for_each_intel_community_pad_group(community, padgrp) {
 171                 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
 172                         return padgrp;
 173         }
 174
 175         return NULL;
 176 }
 177
 178 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl,
 179                                       unsigned int pin, unsigned int reg)
 180 {
 181         const struct intel_community *community;
 182         unsigned int padno;
 183         size_t nregs;
 184
 185         community = intel_get_community(pctrl, pin);
 186         if (!community)
 187                 return NULL;
 188
 189         padno = pin_to_padno(community, pin);
 190         nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
 191
 192         if (reg >= nregs * 4)
 193                 return NULL;
 194
 195         return community->pad_regs + reg + padno * nregs * 4;
 196 }
 197
 198 static bool intel_pad_owned_by_host(const struct intel_pinctrl *pctrl, unsigned int pin)
 199 {
 200         const struct intel_community *community;
 201         const struct intel_padgroup *padgrp;
 202         unsigned int gpp, offset, gpp_offset;
 203         void __iomem *padown;
 204
 205         community = intel_get_community(pctrl, pin);
 206         if (!community)
 207                 return false;
 208         if (!community->padown_offset)
 209                 return true;
 210
 211         padgrp = intel_community_get_padgroup(community, pin);
 212         if (!padgrp)
 213                 return false;
 214
 215         gpp_offset = padgroup_offset(padgrp, pin);
 216         gpp = PADOWN_GPP(gpp_offset);
 217         offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
 218         padown = community->regs + offset;
 219
 220         return !(readl(padown) & PADOWN_MASK(gpp_offset));
 221 }
 222
 223 static bool intel_pad_acpi_mode(const struct intel_pinctrl *pctrl, unsigned int pin)
 224 {
 225         const struct intel_community *community;
 226         const struct intel_padgroup *padgrp;
 227         unsigned int offset, gpp_offset;
 228         void __iomem *hostown;
 229
 230         community = intel_get_community(pctrl, pin);
 231         if (!community)
 232                 return true;
 233         if (!community->hostown_offset)
 234                 return false;
 235
 236         padgrp = intel_community_get_padgroup(community, pin);
 237         if (!padgrp)
 238                 return true;
 239
 240         gpp_offset = padgroup_offset(padgrp, pin);
 241         offset = community->hostown_offset + padgrp->reg_num * 4;
 242         hostown = community->regs + offset;
 243
 244         return !(readl(hostown) & BIT(gpp_offset));
 245 }
 246
 247 /**
 248  * enum - Locking variants of the pad configuration
 249  * @PAD_UNLOCKED:       pad is fully controlled by the configuration registers
 250  * @PAD_LOCKED:         pad configuration registers, except TX state, are locked
 251  * @PAD_LOCKED_TX:      pad configuration TX state is locked
 252  * @PAD_LOCKED_FULL:    pad configuration registers are locked completely
 253  *
 254  * Locking is considered as read-only mode for corresponding registers and
 255  * their respective fields. That said, TX state bit is locked separately from
 256  * the main locking scheme.
 257  */
 258 enum {
 259         PAD_UNLOCKED    = 0,
 260         PAD_LOCKED      = 1,
 261         PAD_LOCKED_TX   = 2,
 262         PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX,
 263 };
 264
 265 static int intel_pad_locked(const struct intel_pinctrl *pctrl, unsigned int pin)
 266 {
 267         const struct intel_community *community;
 268         const struct intel_padgroup *padgrp;
 269         unsigned int offset, gpp_offset;
 270         u32 value;
 271         int ret = PAD_UNLOCKED;
 272
 273         community = intel_get_community(pctrl, pin);
 274         if (!community)
 275                 return PAD_LOCKED_FULL;
 276         if (!community->padcfglock_offset)
 277                 return PAD_UNLOCKED;
 278
 279         padgrp = intel_community_get_padgroup(community, pin);
 280         if (!padgrp)
 281                 return PAD_LOCKED_FULL;
 282
 283         gpp_offset = padgroup_offset(padgrp, pin);
 284
 285         /*
 286          * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
 287          * the pad is considered unlocked. Any other case means that it is
 288          * either fully or partially locked.
 289          */
 290         offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8;
 291         value = readl(community->regs + offset);
 292         if (value & BIT(gpp_offset))
 293                 ret |= PAD_LOCKED;
 294
 295         offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
 296         value = readl(community->regs + offset);
 297         if (value & BIT(gpp_offset))
 298                 ret |= PAD_LOCKED_TX;
 299
 300         return ret;
 301 }
 302
 303 static bool intel_pad_is_unlocked(const struct intel_pinctrl *pctrl, unsigned int pin)
 304 {
 305         return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED;
 306 }
 307
 308 static bool intel_pad_usable(const struct intel_pinctrl *pctrl, unsigned int pin)
 309 {
 310         return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin);
 311 }
 312
 313 int intel_get_groups_count(struct pinctrl_dev *pctldev)
 314 {
 315         const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 316
 317         return pctrl->soc->ngroups;
 318 }
 319 EXPORT_SYMBOL_NS_GPL(intel_get_groups_count, "PINCTRL_INTEL");
 320
 321 const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group)
 322 {
 323         const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 324
 325         return pctrl->soc->groups[group].grp.name;
 326 }
 327 EXPORT_SYMBOL_NS_GPL(intel_get_group_name, "PINCTRL_INTEL");
 328
 329 int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
 330                          const unsigned int **pins, unsigned int *npins)
 331 {
 332         const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 333
 334         *pins = pctrl->soc->groups[group].grp.pins;
 335         *npins = pctrl->soc->groups[group].grp.npins;
 336         return 0;
 337 }
 338 EXPORT_SYMBOL_NS_GPL(intel_get_group_pins, "PINCTRL_INTEL");
 339
 340 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 341                                unsigned int pin)
 342 {
 343         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 344         void __iomem *padcfg;
 345         u32 cfg0, cfg1, mode;
 346         int locked;
 347         bool acpi;
 348
 349         if (!intel_pad_owned_by_host(pctrl, pin)) {
 350                 seq_puts(s, "not available");
 351                 return;
 352         }
 353
 354         cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
 355         cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 356
 357         mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 358         if (mode == PADCFG0_PMODE_GPIO)
 359                 seq_puts(s, "GPIO ");
 360         else
 361                 seq_printf(s, "mode %d ", mode);
 362
 363         seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
 364
 365         /* Dump the additional PADCFG registers if available */
 366         padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
 367         if (padcfg)
 368                 seq_printf(s, " 0x%08x", readl(padcfg));
 369
 370         locked = intel_pad_locked(pctrl, pin);
 371         acpi = intel_pad_acpi_mode(pctrl, pin);
 372
 373         if (locked || acpi) {
 374                 seq_puts(s, " [");
 375                 if (locked)
 376                         seq_puts(s, "LOCKED");
 377                 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX)
 378                         seq_puts(s, " tx");
 379                 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL)
 380                         seq_puts(s, " full");
 381
 382                 if (locked && acpi)
 383                         seq_puts(s, ", ");
 384
 385                 if (acpi)
 386                         seq_puts(s, "ACPI");
 387                 seq_puts(s, "]");
 388         }
 389 }
 390
 391 static const struct pinctrl_ops intel_pinctrl_ops = {
 392         .get_groups_count = intel_get_groups_count,
 393         .get_group_name = intel_get_group_name,
 394         .get_group_pins = intel_get_group_pins,
 395         .pin_dbg_show = intel_pin_dbg_show,
 396 };
 397
 398 int intel_get_functions_count(struct pinctrl_dev *pctldev)
 399 {
 400         const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 401
 402         return pctrl->soc->nfunctions;
 403 }
 404 EXPORT_SYMBOL_NS_GPL(intel_get_functions_count, "PINCTRL_INTEL");
 405
 406 const char *intel_get_function_name(struct pinctrl_dev *pctldev, unsigned int function)
 407 {
 408         const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 409
 410         return pctrl->soc->functions[function].func.name;
 411 }
 412 EXPORT_SYMBOL_NS_GPL(intel_get_function_name, "PINCTRL_INTEL");
 413
 414 int intel_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function,
 415                               const char * const **groups, unsigned int * const ngroups)
 416 {
 417         const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 418
 419         *groups = pctrl->soc->functions[function].func.groups;
 420         *ngroups = pctrl->soc->functions[function].func.ngroups;
 421         return 0;
 422 }
 423 EXPORT_SYMBOL_NS_GPL(intel_get_function_groups, "PINCTRL_INTEL");
 424
 425 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
 426                                 unsigned int function, unsigned int group)
 427 {
 428         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 429         const struct intel_pingroup *grp = &pctrl->soc->groups[group];
 430         int i;
 431
 432         guard(raw_spinlock_irqsave)(&pctrl->lock);
 433
 434         /*
 435          * All pins in the groups needs to be accessible and writable
 436          * before we can enable the mux for this group.
 437          */
 438         for (i = 0; i < grp->grp.npins; i++) {
 439                 if (!intel_pad_usable(pctrl, grp->grp.pins[i]))
 440                         return -EBUSY;
 441         }
 442
 443         /* Now enable the mux setting for each pin in the group */
 444         for (i = 0; i < grp->grp.npins; i++) {
 445                 void __iomem *padcfg0;
 446                 u32 value, pmode;
 447
 448                 padcfg0 = intel_get_padcfg(pctrl, grp->grp.pins[i], PADCFG0);
 449
 450                 value = readl(padcfg0);
 451                 value &= ~PADCFG0_PMODE_MASK;
 452
 453                 if (grp->modes)
 454                         pmode = grp->modes[i];
 455                 else
 456                         pmode = grp->mode;
 457
 458                 value |= pmode << PADCFG0_PMODE_SHIFT;
 459                 writel(value, padcfg0);
 460         }
 461
 462         return 0;
 463 }
 464
 465 /**
 466  * enum - Possible pad physical connections
 467  * @PAD_CONNECT_NONE:   pad is fully disconnected
 468  * @PAD_CONNECT_INPUT:  pad is in input only mode
 469  * @PAD_CONNECT_OUTPUT: pad is in output only mode
 470  * @PAD_CONNECT_FULL:   pad is fully connected
 471  */
 472 enum {
 473         PAD_CONNECT_NONE        = 0,
 474         PAD_CONNECT_INPUT       = 1,
 475         PAD_CONNECT_OUTPUT      = 2,
 476         PAD_CONNECT_FULL        = PAD_CONNECT_INPUT | PAD_CONNECT_OUTPUT,
 477 };
 478
 479 static int __intel_gpio_get_direction(u32 value)
 480 {
 481         switch ((value & PADCFG0_GPIODIS_MASK) >> PADCFG0_GPIODIS_SHIFT) {
 482         case PADCFG0_GPIODIS_FULL:
 483                 return PAD_CONNECT_NONE;
 484         case PADCFG0_GPIODIS_OUTPUT:
 485                 return PAD_CONNECT_INPUT;
 486         case PADCFG0_GPIODIS_INPUT:
 487                 return PAD_CONNECT_OUTPUT;
 488         case PADCFG0_GPIODIS_NONE:
 489                 return PAD_CONNECT_FULL;
 490         default:
 491                 return -ENOTSUPP;
 492         };
 493 }
 494
 495 static u32 __intel_gpio_set_direction(u32 value, bool input, bool output)
 496 {
 497         if (input)
 498                 value &= ~PADCFG0_GPIORXDIS;
 499         else
 500                 value |= PADCFG0_GPIORXDIS;
 501
 502         if (output)
 503                 value &= ~PADCFG0_GPIOTXDIS;
 504         else
 505                 value |= PADCFG0_GPIOTXDIS;
 506
 507         return value;
 508 }
 509
 510 static int __intel_gpio_get_gpio_mode(u32 value)
 511 {
 512         return (value & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 513 }
 514
 515 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)
 516 {
 517         return __intel_gpio_get_gpio_mode(readl(padcfg0));
 518 }
 519
 520 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
 521 {
 522         u32 value;
 523
 524         value = readl(padcfg0);
 525
 526         /* Put the pad into GPIO mode */
 527         value &= ~PADCFG0_PMODE_MASK;
 528         value |= PADCFG0_PMODE_GPIO;
 529
 530         /* Disable TX buffer and enable RX (this will be input) */
 531         value = __intel_gpio_set_direction(value, true, false);
 532
 533         /* Disable SCI/SMI/NMI generation */
 534         value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
 535         value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
 536
 537         writel(value, padcfg0);
 538 }
 539
 540 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
 541                                      struct pinctrl_gpio_range *range,
 542                                      unsigned int pin)
 543 {
 544         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 545         void __iomem *padcfg0;
 546
 547         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 548
 549         guard(raw_spinlock_irqsave)(&pctrl->lock);
 550
 551         if (!intel_pad_owned_by_host(pctrl, pin))
 552                 return -EBUSY;
 553
 554         if (!intel_pad_is_unlocked(pctrl, pin))
 555                 return 0;
 556
 557         /*
 558          * If pin is already configured in GPIO mode, we assume that
 559          * firmware provides correct settings. In such case we avoid
 560          * potential glitches on the pin. Otherwise, for the pin in
 561          * alternative mode, consumer has to supply respective flags.
 562          */
 563         if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO)
 564                 return 0;
 565
 566         intel_gpio_set_gpio_mode(padcfg0);
 567
 568         return 0;
 569 }
 570
 571 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
 572                                     struct pinctrl_gpio_range *range,
 573                                     unsigned int pin, bool input)
 574 {
 575         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 576         void __iomem *padcfg0;
 577         u32 value;
 578
 579         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 580
 581         guard(raw_spinlock_irqsave)(&pctrl->lock);
 582
 583         value = readl(padcfg0);
 584         if (input)
 585                 value = __intel_gpio_set_direction(value, true, false);
 586         else
 587                 value = __intel_gpio_set_direction(value, false, true);
 588         writel(value, padcfg0);
 589
 590         return 0;
 591 }
 592
 593 static const struct pinmux_ops intel_pinmux_ops = {
 594         .get_functions_count = intel_get_functions_count,
 595         .get_function_name = intel_get_function_name,
 596         .get_function_groups = intel_get_function_groups,
 597         .set_mux = intel_pinmux_set_mux,
 598         .gpio_request_enable = intel_gpio_request_enable,
 599         .gpio_set_direction = intel_gpio_set_direction,
 600 };
 601
 602 static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin,
 603                                  enum pin_config_param param, u32 *arg)
 604 {
 605         void __iomem *padcfg1;
 606         u32 value, term;
 607
 608         padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
 609
 610         scoped_guard(raw_spinlock_irqsave, &pctrl->lock)
 611                 value = readl(padcfg1);
 612
 613         term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
 614
 615         switch (param) {
 616         case PIN_CONFIG_BIAS_DISABLE:
 617                 if (term)
 618                         return -EINVAL;
 619                 break;
 620
 621         case PIN_CONFIG_BIAS_PULL_UP:
 622                 if (!term || !(value & PADCFG1_TERM_UP))
 623                         return -EINVAL;
 624
 625                 switch (term) {
 626                 case PADCFG1_TERM_833:
 627                         *arg = 833;
 628                         break;
 629                 case PADCFG1_TERM_1K:
 630                         *arg = 1000;
 631                         break;
 632                 case PADCFG1_TERM_4K:
 633                         *arg = 4000;
 634                         break;
 635                 case PADCFG1_TERM_5K:
 636                         *arg = 5000;
 637                         break;
 638                 case PADCFG1_TERM_20K:
 639                         *arg = 20000;
 640                         break;
 641                 }
 642
 643                 break;
 644
 645         case PIN_CONFIG_BIAS_PULL_DOWN: {
 646                 const struct intel_community *community = intel_get_community(pctrl, pin);
 647
 648                 if (!term || value & PADCFG1_TERM_UP)
 649                         return -EINVAL;
 650
 651                 switch (term) {
 652                 case PADCFG1_TERM_833:
 653                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 654                                 return -EINVAL;
 655                         *arg = 833;
 656                         break;
 657                 case PADCFG1_TERM_1K:
 658                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 659                                 return -EINVAL;
 660                         *arg = 1000;
 661                         break;
 662                 case PADCFG1_TERM_4K:
 663                         *arg = 4000;
 664                         break;
 665                 case PADCFG1_TERM_5K:
 666                         *arg = 5000;
 667                         break;
 668                 case PADCFG1_TERM_20K:
 669                         *arg = 20000;
 670                         break;
 671                 }
 672
 673                 break;
 674         }
 675
 676         default:
 677                 return -EINVAL;
 678         }
 679
 680         return 0;
 681 }
 682
 683 static int intel_config_get_high_impedance(struct intel_pinctrl *pctrl, unsigned int pin,
 684                                            enum pin_config_param param, u32 *arg)
 685 {
 686         void __iomem *padcfg0;
 687         u32 value;
 688
 689         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 690
 691         scoped_guard(raw_spinlock_irqsave, &pctrl->lock)
 692                 value = readl(padcfg0);
 693
 694         if (__intel_gpio_get_direction(value) != PAD_CONNECT_NONE)
 695                 return -EINVAL;
 696
 697         return 0;
 698 }
 699
 700 static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin,
 701                                      enum pin_config_param param, u32 *arg)
 702 {
 703         void __iomem *padcfg2;
 704         unsigned long v;
 705         u32 value2;
 706
 707         padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 708         if (!padcfg2)
 709                 return -ENOTSUPP;
 710
 711         scoped_guard(raw_spinlock_irqsave, &pctrl->lock)
 712                 value2 = readl(padcfg2);
 713
 714         if (!(value2 & PADCFG2_DEBEN))
 715                 return -EINVAL;
 716
 717         v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
 718         *arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC;
 719
 720         return 0;
 721 }
 722
 723 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
 724                             unsigned long *config)
 725 {
 726         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 727         enum pin_config_param param = pinconf_to_config_param(*config);
 728         u32 arg = 0;
 729         int ret;
 730
 731         if (!intel_pad_owned_by_host(pctrl, pin))
 732                 return -ENOTSUPP;
 733
 734         switch (param) {
 735         case PIN_CONFIG_BIAS_DISABLE:
 736         case PIN_CONFIG_BIAS_PULL_UP:
 737         case PIN_CONFIG_BIAS_PULL_DOWN:
 738                 ret = intel_config_get_pull(pctrl, pin, param, &arg);
 739                 if (ret)
 740                         return ret;
 741                 break;
 742
 743         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 744                 ret = intel_config_get_high_impedance(pctrl, pin, param, &arg);
 745                 if (ret)
 746                         return ret;
 747                 break;
 748
 749         case PIN_CONFIG_INPUT_DEBOUNCE:
 750                 ret = intel_config_get_debounce(pctrl, pin, param, &arg);
 751                 if (ret)
 752                         return ret;
 753                 break;
 754
 755         default:
 756                 return -ENOTSUPP;
 757         }
 758
 759         *config = pinconf_to_config_packed(param, arg);
 760         return 0;
 761 }
 762
 763 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
 764                                  unsigned long config)
 765 {
 766         unsigned int param = pinconf_to_config_param(config);
 767         unsigned int arg = pinconf_to_config_argument(config);
 768         u32 term = 0, up = 0, value;
 769         void __iomem *padcfg1;
 770
 771         switch (param) {
 772         case PIN_CONFIG_BIAS_DISABLE:
 773                 break;
 774
 775         case PIN_CONFIG_BIAS_PULL_UP:
 776                 switch (arg) {
 777                 case 20000:
 778                         term = PADCFG1_TERM_20K;
 779                         break;
 780                 case 1: /* Set default strength value in case none is given */
 781                 case 5000:
 782                         term = PADCFG1_TERM_5K;
 783                         break;
 784                 case 4000:
 785                         term = PADCFG1_TERM_4K;
 786                         break;
 787                 case 1000:
 788                         term = PADCFG1_TERM_1K;
 789                         break;
 790                 case 833:
 791                         term = PADCFG1_TERM_833;
 792                         break;
 793                 default:
 794                         return -EINVAL;
 795                 }
 796
 797                 up = PADCFG1_TERM_UP;
 798                 break;
 799
 800         case PIN_CONFIG_BIAS_PULL_DOWN: {
 801                 const struct intel_community *community = intel_get_community(pctrl, pin);
 802
 803                 switch (arg) {
 804                 case 20000:
 805                         term = PADCFG1_TERM_20K;
 806                         break;
 807                 case 1: /* Set default strength value in case none is given */
 808                 case 5000:
 809                         term = PADCFG1_TERM_5K;
 810                         break;
 811                 case 4000:
 812                         term = PADCFG1_TERM_4K;
 813                         break;
 814                 case 1000:
 815                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 816                                 return -EINVAL;
 817                         term = PADCFG1_TERM_1K;
 818                         break;
 819                 case 833:
 820                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 821                                 return -EINVAL;
 822                         term = PADCFG1_TERM_833;
 823                         break;
 824                 default:
 825                         return -EINVAL;
 826                 }
 827
 828                 break;
 829         }
 830
 831         default:
 832                 return -EINVAL;
 833         }
 834
 835         padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
 836
 837         guard(raw_spinlock_irqsave)(&pctrl->lock);
 838
 839         value = readl(padcfg1);
 840         value = (value & ~PADCFG1_TERM_MASK) | (term << PADCFG1_TERM_SHIFT);
 841         value = (value & ~PADCFG1_TERM_UP) | up;
 842         writel(value, padcfg1);
 843
 844         return 0;
 845 }
 846
 847 static void intel_gpio_set_high_impedance(struct intel_pinctrl *pctrl, unsigned int pin)
 848 {
 849         void __iomem *padcfg0;
 850         u32 value;
 851
 852         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 853
 854         guard(raw_spinlock_irqsave)(&pctrl->lock);
 855
 856         value = readl(padcfg0);
 857         value = __intel_gpio_set_direction(value, false, false);
 858         writel(value, padcfg0);
 859 }
 860
 861 static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
 862                                      unsigned int pin, unsigned int debounce)
 863 {
 864         void __iomem *padcfg0, *padcfg2;
 865         u32 value0, value2;
 866         unsigned long v;
 867
 868         if (debounce) {
 869                 v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
 870                 if (v < 3 || v > 15)
 871                         return -EINVAL;
 872         } else {
 873                 v = 0;
 874         }
 875
 876         padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 877         if (!padcfg2)
 878                 return -ENOTSUPP;
 879
 880         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 881
 882         guard(raw_spinlock_irqsave)(&pctrl->lock);
 883
 884         value0 = readl(padcfg0);
 885         value2 = readl(padcfg2);
 886
 887         value2 = (value2 & ~PADCFG2_DEBOUNCE_MASK) | (v << PADCFG2_DEBOUNCE_SHIFT);
 888         if (v) {
 889                 /* Enable glitch filter and debouncer */
 890                 value0 |= PADCFG0_PREGFRXSEL;
 891                 value2 |= PADCFG2_DEBEN;
 892         } else {
 893                 /* Disable glitch filter and debouncer */
 894                 value0 &= ~PADCFG0_PREGFRXSEL;
 895                 value2 &= ~PADCFG2_DEBEN;
 896         }
 897
 898         writel(value0, padcfg0);
 899         writel(value2, padcfg2);
 900
 901         return 0;
 902 }
 903
 904 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
 905                           unsigned long *configs, unsigned int nconfigs)
 906 {
 907         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 908         int i, ret;
 909
 910         if (!intel_pad_usable(pctrl, pin))
 911                 return -ENOTSUPP;
 912
 913         for (i = 0; i < nconfigs; i++) {
 914                 switch (pinconf_to_config_param(configs[i])) {
 915                 case PIN_CONFIG_BIAS_DISABLE:
 916                 case PIN_CONFIG_BIAS_PULL_UP:
 917                 case PIN_CONFIG_BIAS_PULL_DOWN:
 918                         ret = intel_config_set_pull(pctrl, pin, configs[i]);
 919                         if (ret)
 920                                 return ret;
 921                         break;
 922
 923                 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 924                         intel_gpio_set_high_impedance(pctrl, pin);
 925                         break;
 926
 927                 case PIN_CONFIG_INPUT_DEBOUNCE:
 928                         ret = intel_config_set_debounce(pctrl, pin,
 929                                 pinconf_to_config_argument(configs[i]));
 930                         if (ret)
 931                                 return ret;
 932                         break;
 933
 934                 default:
 935                         return -ENOTSUPP;
 936                 }
 937         }
 938
 939         return 0;
 940 }
 941
 942 static const struct pinconf_ops intel_pinconf_ops = {
 943         .is_generic = true,
 944         .pin_config_get = intel_config_get,
 945         .pin_config_set = intel_config_set,
 946 };
 947
 948 static const struct pinctrl_desc intel_pinctrl_desc = {
 949         .pctlops = &intel_pinctrl_ops,
 950         .pmxops = &intel_pinmux_ops,
 951         .confops = &intel_pinconf_ops,
 952         .owner = THIS_MODULE,
 953 };
 954
 955 /**
 956  * intel_gpio_to_pin() - Translate from GPIO offset to pin number
 957  * @pctrl: Pinctrl structure
 958  * @offset: GPIO offset from gpiolib
 959  * @community: Community is filled here if not %NULL
 960  * @padgrp: Pad group is filled here if not %NULL
 961  *
 962  * When coming through gpiolib irqchip, the GPIO offset is not
 963  * automatically translated to pinctrl pin number. This function can be
 964  * used to find out the corresponding pinctrl pin.
 965  *
 966  * Return: a pin number and pointers to the community and pad group, which
 967  * the pin belongs to, or negative error code if translation can't be done.
 968  */
 969 static int intel_gpio_to_pin(const struct intel_pinctrl *pctrl, unsigned int offset,
 970                              const struct intel_community **community,
 971                              const struct intel_padgroup **padgrp)
 972 {
 973         const struct intel_community *comm;
 974         const struct intel_padgroup *grp;
 975
 976         for_each_intel_gpio_group(pctrl, comm, grp) {
 977                 if (offset >= grp->gpio_base && offset < grp->gpio_base + grp->size) {
 978                         if (community)
 979                                 *community = comm;
 980                         if (padgrp)
 981                                 *padgrp = grp;
 982
 983                         return grp->base + offset - grp->gpio_base;
 984                 }
 985         }
 986
 987         return -EINVAL;
 988 }
 989
 990 /**
 991  * intel_pin_to_gpio() - Translate from pin number to GPIO offset
 992  * @pctrl: Pinctrl structure
 993  * @pin: pin number
 994  *
 995  * Translate the pin number of pinctrl to GPIO offset
 996  *
 997  * Return: a GPIO offset, or negative error code if translation can't be done.
 998  */
 999 static int intel_pin_to_gpio(const struct intel_pinctrl *pctrl, int pin)
1000 {
1001         const struct intel_community *community;
1002         const struct intel_padgroup *padgrp;
1003
1004         community = intel_get_community(pctrl, pin);
1005         if (!community)
1006                 return -EINVAL;
1007
1008         padgrp = intel_community_get_padgroup(community, pin);
1009         if (!padgrp)
1010                 return -EINVAL;
1011
1012         return pin - padgrp->base + padgrp->gpio_base;
1013 }
1014
1015 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
1016 {
1017         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1018         void __iomem *reg;
1019         u32 padcfg0;
1020         int pin;
1021
1022         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
1023         if (pin < 0)
1024                 return -EINVAL;
1025
1026         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1027         if (!reg)
1028                 return -EINVAL;
1029
1030         padcfg0 = readl(reg);
1031         if (__intel_gpio_get_direction(padcfg0) & PAD_CONNECT_OUTPUT)
1032                 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
1033
1034         return !!(padcfg0 & PADCFG0_GPIORXSTATE);
1035 }
1036
1037 static int intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
1038                           int value)
1039 {
1040         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1041         void __iomem *reg;
1042         u32 padcfg0;
1043         int pin;
1044
1045         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
1046         if (pin < 0)
1047                 return -EINVAL;
1048
1049         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1050         if (!reg)
1051                 return -EINVAL;
1052
1053         guard(raw_spinlock_irqsave)(&pctrl->lock);
1054
1055         padcfg0 = readl(reg);
1056         if (value)
1057                 padcfg0 |= PADCFG0_GPIOTXSTATE;
1058         else
1059                 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
1060         writel(padcfg0, reg);
1061
1062         return 0;
1063 }
1064
1065 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1066 {
1067         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1068         void __iomem *reg;
1069         u32 padcfg0;
1070         int pin;
1071
1072         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
1073         if (pin < 0)
1074                 return -EINVAL;
1075
1076         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1077         if (!reg)
1078                 return -EINVAL;
1079
1080         scoped_guard(raw_spinlock_irqsave, &pctrl->lock)
1081                 padcfg0 = readl(reg);
1082
1083         if (padcfg0 & PADCFG0_PMODE_MASK)
1084                 return -EINVAL;
1085
1086         if (__intel_gpio_get_direction(padcfg0) & PAD_CONNECT_OUTPUT)
1087                 return GPIO_LINE_DIRECTION_OUT;
1088
1089         return GPIO_LINE_DIRECTION_IN;
1090 }
1091
1092 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1093 {
1094         return pinctrl_gpio_direction_input(chip, offset);
1095 }
1096
1097 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
1098                                        int value)
1099 {
1100         int ret;
1101
1102         ret = intel_gpio_set(chip, offset, value);
1103         if (ret)
1104                 return ret;
1105
1106         return pinctrl_gpio_direction_output(chip, offset);
1107 }
1108
1109 static const struct gpio_chip intel_gpio_chip = {
1110         .owner = THIS_MODULE,
1111         .request = gpiochip_generic_request,
1112         .free = gpiochip_generic_free,
1113         .get_direction = intel_gpio_get_direction,
1114         .direction_input = intel_gpio_direction_input,
1115         .direction_output = intel_gpio_direction_output,
1116         .get = intel_gpio_get,
1117         .set = intel_gpio_set,
1118         .set_config = gpiochip_generic_config,
1119 };
1120
1121 static void intel_gpio_irq_ack(struct irq_data *d)
1122 {
1123         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1124         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1125         const struct intel_community *community;
1126         const struct intel_padgroup *padgrp;
1127         int pin;
1128
1129         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
1130         if (pin >= 0) {
1131                 unsigned int gpp, gpp_offset;
1132                 void __iomem *is;
1133
1134                 gpp = padgrp->reg_num;
1135                 gpp_offset = padgroup_offset(padgrp, pin);
1136
1137                 is = community->regs + community->is_offset + gpp * 4;
1138
1139                 guard(raw_spinlock)(&pctrl->lock);
1140
1141                 writel(BIT(gpp_offset), is);
1142         }
1143 }
1144
1145 static void intel_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask)
1146 {
1147         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1148         const struct intel_community *community;
1149         const struct intel_padgroup *padgrp;
1150         int pin;
1151
1152         pin = intel_gpio_to_pin(pctrl, hwirq, &community, &padgrp);
1153         if (pin >= 0) {
1154                 unsigned int gpp, gpp_offset;
1155                 void __iomem *reg, *is;
1156                 u32 value;
1157
1158                 gpp = padgrp->reg_num;
1159                 gpp_offset = padgroup_offset(padgrp, pin);
1160
1161                 reg = community->regs + community->ie_offset + gpp * 4;
1162                 is = community->regs + community->is_offset + gpp * 4;
1163
1164                 guard(raw_spinlock_irqsave)(&pctrl->lock);
1165
1166                 /* Clear interrupt status first to avoid unexpected interrupt */
1167                 writel(BIT(gpp_offset), is);
1168
1169                 value = readl(reg);
1170                 if (mask)
1171                         value &= ~BIT(gpp_offset);
1172                 else
1173                         value |= BIT(gpp_offset);
1174                 writel(value, reg);
1175         }
1176 }
1177
1178 static void intel_gpio_irq_mask(struct irq_data *d)
1179 {
1180         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1181         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1182
1183         intel_gpio_irq_mask_unmask(gc, hwirq, true);
1184         gpiochip_disable_irq(gc, hwirq);
1185 }
1186
1187 static void intel_gpio_irq_unmask(struct irq_data *d)
1188 {
1189         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1190         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1191
1192         gpiochip_enable_irq(gc, hwirq);
1193         intel_gpio_irq_mask_unmask(gc, hwirq, false);
1194 }
1195
1196 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
1197 {
1198         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1199         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1200         unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1201         u32 rxevcfg, rxinv, value;
1202         void __iomem *reg;
1203
1204         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1205         if (!reg)
1206                 return -EINVAL;
1207
1208         /*
1209          * If the pin is in ACPI mode it is still usable as a GPIO but it
1210          * cannot be used as IRQ because GPI_IS status bit will not be
1211          * updated by the host controller hardware.
1212          */
1213         if (intel_pad_acpi_mode(pctrl, pin)) {
1214                 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
1215                 return -EPERM;
1216         }
1217
1218         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
1219                 rxevcfg = PADCFG0_RXEVCFG_EDGE_BOTH;
1220         } else if (type & IRQ_TYPE_EDGE_FALLING) {
1221                 rxevcfg = PADCFG0_RXEVCFG_EDGE;
1222         } else if (type & IRQ_TYPE_EDGE_RISING) {
1223                 rxevcfg = PADCFG0_RXEVCFG_EDGE;
1224         } else if (type & IRQ_TYPE_LEVEL_MASK) {
1225                 rxevcfg = PADCFG0_RXEVCFG_LEVEL;
1226         } else {
1227                 rxevcfg = PADCFG0_RXEVCFG_DISABLED;
1228         }
1229
1230         if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW)
1231                 rxinv = PADCFG0_RXINV;
1232         else
1233                 rxinv = 0;
1234
1235         guard(raw_spinlock_irqsave)(&pctrl->lock);
1236
1237         intel_gpio_set_gpio_mode(reg);
1238
1239         value = readl(reg);
1240
1241         value = (value & ~PADCFG0_RXEVCFG_MASK) | rxevcfg;
1242         value = (value & ~PADCFG0_RXINV) | rxinv;
1243
1244         writel(value, reg);
1245
1246         if (type & IRQ_TYPE_EDGE_BOTH)
1247                 irq_set_handler_locked(d, handle_edge_irq);
1248         else if (type & IRQ_TYPE_LEVEL_MASK)
1249                 irq_set_handler_locked(d, handle_level_irq);
1250
1251         return 0;
1252 }
1253
1254 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
1255 {
1256         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1257         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1258         unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1259
1260         if (on)
1261                 enable_irq_wake(pctrl->irq);
1262         else
1263                 disable_irq_wake(pctrl->irq);
1264
1265         dev_dbg(pctrl->dev, "%s wake for pin %u\n", str_enable_disable(on), pin);
1266         return 0;
1267 }
1268
1269 static const struct irq_chip intel_gpio_irq_chip = {
1270         .name = "intel-gpio",
1271         .irq_ack = intel_gpio_irq_ack,
1272         .irq_mask = intel_gpio_irq_mask,
1273         .irq_unmask = intel_gpio_irq_unmask,
1274         .irq_set_type = intel_gpio_irq_type,
1275         .irq_set_wake = intel_gpio_irq_wake,
1276         .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
1277         GPIOCHIP_IRQ_RESOURCE_HELPERS,
1278 };
1279
1280 static irqreturn_t intel_gpio_irq(int irq, void *data)
1281 {
1282         const struct intel_community *community;
1283         const struct intel_padgroup *padgrp;
1284         struct intel_pinctrl *pctrl = data;
1285         int ret = 0;
1286
1287         /* Need to check all communities for pending interrupts */
1288         for_each_intel_pad_group(pctrl, community, padgrp) {
1289                 struct gpio_chip *gc = &pctrl->chip;
1290                 unsigned long pending, enabled;
1291                 unsigned int gpp, gpp_offset;
1292                 void __iomem *reg, *is;
1293
1294                 gpp = padgrp->reg_num;
1295
1296                 reg = community->regs + community->ie_offset + gpp * 4;
1297                 is = community->regs + community->is_offset + gpp * 4;
1298
1299                 scoped_guard(raw_spinlock, &pctrl->lock) {
1300                         pending = readl(is);
1301                         enabled = readl(reg);
1302                 }
1303
1304                 /* Only interrupts that are enabled */
1305                 pending &= enabled;
1306
1307                 for_each_set_bit(gpp_offset, &pending, padgrp->size)
1308                         generic_handle_domain_irq(gc->irq.domain, padgrp->gpio_base + gpp_offset);
1309
1310                 ret += pending ? 1 : 0;
1311         }
1312
1313         return IRQ_RETVAL(ret);
1314 }
1315
1316 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1317 {
1318         const struct intel_community *community;
1319
1320         for_each_intel_pin_community(pctrl, community) {
1321                 void __iomem *reg, *is;
1322                 unsigned int gpp;
1323
1324                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1325                         reg = community->regs + community->ie_offset + gpp * 4;
1326                         is = community->regs + community->is_offset + gpp * 4;
1327
1328                         /* Mask and clear all interrupts */
1329                         writel(0, reg);
1330                         writel(0xffff, is);
1331                 }
1332         }
1333 }
1334
1335 static int intel_gpio_irq_init_hw(struct gpio_chip *gc)
1336 {
1337         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1338
1339         /*
1340          * Make sure the interrupt lines are in a proper state before
1341          * further configuration.
1342          */
1343         intel_gpio_irq_init(pctrl);
1344
1345         return 0;
1346 }
1347
1348 static int intel_gpio_add_pin_ranges(struct gpio_chip *gc)
1349 {
1350         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1351         const struct intel_community *community;
1352         const struct intel_padgroup *grp;
1353         int ret;
1354
1355         for_each_intel_gpio_group(pctrl, community, grp) {
1356                 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1357                                              grp->gpio_base, grp->base,
1358                                              grp->size);
1359                 if (ret) {
1360                         dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1361                         return ret;
1362                 }
1363         }
1364
1365         return 0;
1366 }
1367
1368 static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1369 {
1370         const struct intel_community *community;
1371         const struct intel_padgroup *grp;
1372         unsigned int ngpio = 0;
1373
1374         for_each_intel_gpio_group(pctrl, community, grp) {
1375                 if (grp->gpio_base + grp->size > ngpio)
1376                         ngpio = grp->gpio_base + grp->size;
1377         }
1378
1379         return ngpio;
1380 }
1381
1382 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1383 {
1384         int ret;
1385         struct gpio_irq_chip *girq;
1386
1387         pctrl->chip = intel_gpio_chip;
1388
1389         /* Setup GPIO chip */
1390         pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1391         pctrl->chip.label = dev_name(pctrl->dev);
1392         pctrl->chip.parent = pctrl->dev;
1393         pctrl->chip.base = -1;
1394         pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges;
1395         pctrl->irq = irq;
1396
1397         /*
1398          * On some platforms several GPIO controllers share the same interrupt
1399          * line.
1400          */
1401         ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1402                                IRQF_SHARED | IRQF_NO_THREAD,
1403                                dev_name(pctrl->dev), pctrl);
1404         if (ret) {
1405                 dev_err(pctrl->dev, "failed to request interrupt\n");
1406                 return ret;
1407         }
1408
1409         /* Setup IRQ chip */
1410         girq = &pctrl->chip.irq;
1411         gpio_irq_chip_set_chip(girq, &intel_gpio_irq_chip);
1412         /* This will let us handle the IRQ in the driver */
1413         girq->parent_handler = NULL;
1414         girq->num_parents = 0;
1415         girq->default_type = IRQ_TYPE_NONE;
1416         girq->handler = handle_bad_irq;
1417         girq->init_hw = intel_gpio_irq_init_hw;
1418
1419         ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1420         if (ret) {
1421                 dev_err(pctrl->dev, "failed to register gpiochip\n");
1422                 return ret;
1423         }
1424
1425         return 0;
1426 }
1427
1428 static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl,
1429                                                struct intel_community *community)
1430 {
1431         struct intel_padgroup *gpps;
1432         unsigned int padown_num = 0;
1433         size_t i, ngpps = community->ngpps;
1434
1435         gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1436         if (!gpps)
1437                 return -ENOMEM;
1438
1439         for (i = 0; i < ngpps; i++) {
1440                 gpps[i] = community->gpps[i];
1441
1442                 if (gpps[i].size > INTEL_PINCTRL_MAX_GPP_SIZE)
1443                         return -EINVAL;
1444
1445                 /* Special treatment for GPIO base */
1446                 switch (gpps[i].gpio_base) {
1447                         case INTEL_GPIO_BASE_MATCH:
1448                                 gpps[i].gpio_base = gpps[i].base;
1449                                 break;
1450                         case INTEL_GPIO_BASE_ZERO:
1451                                 gpps[i].gpio_base = 0;
1452                                 break;
1453                         case INTEL_GPIO_BASE_NOMAP:
1454                                 break;
1455                         default:
1456                                 break;
1457                 }
1458
1459                 gpps[i].padown_num = padown_num;
1460                 padown_num += DIV_ROUND_UP(gpps[i].size * 4, INTEL_PINCTRL_MAX_GPP_SIZE);
1461         }
1462
1463         community->gpps = gpps;
1464
1465         return 0;
1466 }
1467
1468 static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl,
1469                                                struct intel_community *community)
1470 {
1471         struct intel_padgroup *gpps;
1472         unsigned int npins = community->npins;
1473         unsigned int padown_num = 0;
1474         size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size);
1475
1476         if (community->gpp_size > INTEL_PINCTRL_MAX_GPP_SIZE)
1477                 return -EINVAL;
1478
1479         gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1480         if (!gpps)
1481                 return -ENOMEM;
1482
1483         for (i = 0; i < ngpps; i++) {
1484                 unsigned int gpp_size = community->gpp_size;
1485
1486                 gpps[i].reg_num = i;
1487                 gpps[i].base = community->pin_base + i * gpp_size;
1488                 gpps[i].size = min(gpp_size, npins);
1489                 npins -= gpps[i].size;
1490
1491                 gpps[i].gpio_base = gpps[i].base;
1492                 gpps[i].padown_num = padown_num;
1493
1494                 padown_num += community->gpp_num_padown_regs;
1495         }
1496
1497         community->ngpps = ngpps;
1498         community->gpps = gpps;
1499
1500         return 0;
1501 }
1502
1503 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1504 {
1505 #ifdef CONFIG_PM_SLEEP
1506         const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1507         struct intel_community_context *communities;
1508         struct intel_pad_context *pads;
1509         int i;
1510
1511         pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1512         if (!pads)
1513                 return -ENOMEM;
1514
1515         communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1516                                    sizeof(*communities), GFP_KERNEL);
1517         if (!communities)
1518                 return -ENOMEM;
1519
1520
1521         for (i = 0; i < pctrl->ncommunities; i++) {
1522                 struct intel_community *community = &pctrl->communities[i];
1523                 u32 *intmask, *hostown;
1524
1525                 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1526                                        sizeof(*intmask), GFP_KERNEL);
1527                 if (!intmask)
1528                         return -ENOMEM;
1529
1530                 communities[i].intmask = intmask;
1531
1532                 hostown = devm_kcalloc(pctrl->dev, community->ngpps,
1533                                        sizeof(*hostown), GFP_KERNEL);
1534                 if (!hostown)
1535                         return -ENOMEM;
1536
1537                 communities[i].hostown = hostown;
1538         }
1539
1540         pctrl->context.pads = pads;
1541         pctrl->context.communities = communities;
1542 #endif
1543
1544         return 0;
1545 }
1546
1547 static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl,
1548                                    struct intel_community *community)
1549 {
1550         static const struct pwm_lpss_boardinfo info = {
1551                 .clk_rate = 19200000,
1552                 .npwm = 1,
1553                 .base_unit_bits = 22,
1554         };
1555         struct pwm_chip *chip;
1556
1557         if (!(community->features & PINCTRL_FEATURE_PWM))
1558                 return 0;
1559
1560         if (!IS_REACHABLE(CONFIG_PWM_LPSS))
1561                 return 0;
1562
1563         chip = devm_pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info);
1564         return PTR_ERR_OR_ZERO(chip);
1565 }
1566
1567 int intel_pinctrl_probe(struct platform_device *pdev,
1568                         const struct intel_pinctrl_soc_data *soc_data)
1569 {
1570         struct device *dev = &pdev->dev;
1571         struct intel_pinctrl *pctrl;
1572         int i, ret, irq;
1573
1574         pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
1575         if (!pctrl)
1576                 return -ENOMEM;
1577
1578         pctrl->dev = dev;
1579         pctrl->soc = soc_data;
1580         raw_spin_lock_init(&pctrl->lock);
1581
1582         /*
1583          * Make a copy of the communities which we can use to hold pointers
1584          * to the registers.
1585          */
1586         pctrl->ncommunities = pctrl->soc->ncommunities;
1587         pctrl->communities = devm_kmemdup_array(dev, pctrl->soc->communities, pctrl->ncommunities,
1588                                                 sizeof(*pctrl->soc->communities), GFP_KERNEL);
1589         if (!pctrl->communities)
1590                 return -ENOMEM;
1591
1592         for (i = 0; i < pctrl->ncommunities; i++) {
1593                 struct intel_community *community = &pctrl->communities[i];
1594                 void __iomem *regs;
1595                 u32 offset;
1596                 u32 value;
1597
1598                 regs = devm_platform_ioremap_resource(pdev, community->barno);
1599                 if (IS_ERR(regs))
1600                         return PTR_ERR(regs);
1601
1602                 /*
1603                  * Determine community features based on the revision.
1604                  * A value of all ones means the device is not present.
1605                  */
1606                 value = readl(regs + REVID);
1607                 if (value == ~0u)
1608                         return -ENODEV;
1609                 if (((value & REVID_MASK) >> REVID_SHIFT) >= 0x94) {
1610                         community->features |= PINCTRL_FEATURE_DEBOUNCE;
1611                         community->features |= PINCTRL_FEATURE_1K_PD;
1612                 }
1613
1614                 /* Determine community features based on the capabilities */
1615                 offset = CAPLIST;
1616                 do {
1617                         value = readl(regs + offset);
1618                         switch ((value & CAPLIST_ID_MASK) >> CAPLIST_ID_SHIFT) {
1619                         case CAPLIST_ID_GPIO_HW_INFO:
1620                                 community->features |= PINCTRL_FEATURE_GPIO_HW_INFO;
1621                                 break;
1622                         case CAPLIST_ID_PWM:
1623                                 community->features |= PINCTRL_FEATURE_PWM;
1624                                 break;
1625                         case CAPLIST_ID_BLINK:
1626                                 community->features |= PINCTRL_FEATURE_BLINK;
1627                                 break;
1628                         case CAPLIST_ID_EXP:
1629                                 community->features |= PINCTRL_FEATURE_EXP;
1630                                 break;
1631                         default:
1632                                 break;
1633                         }
1634                         offset = (value & CAPLIST_NEXT_MASK) >> CAPLIST_NEXT_SHIFT;
1635                 } while (offset);
1636
1637                 dev_dbg(dev, "Community%d features: %#08x\n", i, community->features);
1638
1639                 /* Read offset of the pad configuration registers */
1640                 offset = readl(regs + PADBAR);
1641
1642                 community->regs = regs;
1643                 community->pad_regs = regs + offset;
1644
1645                 if (community->gpps)
1646                         ret = intel_pinctrl_add_padgroups_by_gpps(pctrl, community);
1647                 else
1648                         ret = intel_pinctrl_add_padgroups_by_size(pctrl, community);
1649                 if (ret)
1650                         return ret;
1651
1652                 ret = intel_pinctrl_probe_pwm(pctrl, community);
1653                 if (ret)
1654                         return ret;
1655         }
1656
1657         irq = platform_get_irq(pdev, 0);
1658         if (irq < 0)
1659                 return irq;
1660
1661         ret = intel_pinctrl_pm_init(pctrl);
1662         if (ret)
1663                 return ret;
1664
1665         pctrl->pctldesc = intel_pinctrl_desc;
1666         pctrl->pctldesc.name = dev_name(dev);
1667         pctrl->pctldesc.pins = pctrl->soc->pins;
1668         pctrl->pctldesc.npins = pctrl->soc->npins;
1669
1670         pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl);
1671         if (IS_ERR(pctrl->pctldev)) {
1672                 dev_err(dev, "failed to register pinctrl driver\n");
1673                 return PTR_ERR(pctrl->pctldev);
1674         }
1675
1676         ret = intel_gpio_probe(pctrl, irq);
1677         if (ret)
1678                 return ret;
1679
1680         platform_set_drvdata(pdev, pctrl);
1681
1682         return 0;
1683 }
1684 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe, "PINCTRL_INTEL");
1685
1686 int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
1687 {
1688         const struct intel_pinctrl_soc_data *data;
1689
1690         data = device_get_match_data(&pdev->dev);
1691         if (!data)
1692                 return -ENODATA;
1693
1694         return intel_pinctrl_probe(pdev, data);
1695 }
1696 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_hid, "PINCTRL_INTEL");
1697
1698 int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
1699 {
1700         const struct intel_pinctrl_soc_data *data;
1701
1702         data = intel_pinctrl_get_soc_data(pdev);
1703         if (IS_ERR(data))
1704                 return PTR_ERR(data);
1705
1706         return intel_pinctrl_probe(pdev, data);
1707 }
1708 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_uid, "PINCTRL_INTEL");
1709
1710 const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev)
1711 {
1712         const struct intel_pinctrl_soc_data * const *table;
1713         const struct intel_pinctrl_soc_data *data;
1714         struct device *dev = &pdev->dev;
1715
1716         table = device_get_match_data(dev);
1717         if (table) {
1718                 struct acpi_device *adev = ACPI_COMPANION(dev);
1719                 unsigned int i;
1720
1721                 for (i = 0; table[i]; i++) {
1722                         if (acpi_dev_uid_match(adev, table[i]->uid))
1723                                 break;
1724                 }
1725                 data = table[i];
1726         } else {
1727                 const struct platform_device_id *id;
1728
1729                 id = platform_get_device_id(pdev);
1730                 if (!id)
1731                         return ERR_PTR(-ENODEV);
1732
1733                 table = (const struct intel_pinctrl_soc_data * const *)id->driver_data;
1734                 data = table[pdev->id];
1735         }
1736
1737         return data ?: ERR_PTR(-ENODATA);
1738 }
1739 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_get_soc_data, "PINCTRL_INTEL");
1740
1741 static bool __intel_gpio_is_direct_irq(u32 value)
1742 {
1743         return (value & PADCFG0_GPIROUTIOXAPIC) &&
1744                (__intel_gpio_get_direction(value) == PAD_CONNECT_INPUT) &&
1745                (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO);
1746 }
1747
1748 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)
1749 {
1750         const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1751         u32 value;
1752
1753         if (!pd || !intel_pad_usable(pctrl, pin))
1754                 return false;
1755
1756         /*
1757          * Only restore the pin if it is actually in use by the kernel (or
1758          * by userspace). It is possible that some pins are used by the
1759          * BIOS during resume and those are not always locked down so leave
1760          * them alone.
1761          */
1762         if (pd->mux_owner || pd->gpio_owner ||
1763             gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin)))
1764                 return true;
1765
1766         /*
1767          * The firmware on some systems may configure GPIO pins to be
1768          * an interrupt source in so called "direct IRQ" mode. In such
1769          * cases the GPIO controller driver has no idea if those pins
1770          * are being used or not. At the same time, there is a known bug
1771          * in the firmwares that don't restore the pin settings correctly
1772          * after suspend, i.e. by an unknown reason the Rx value becomes
1773          * inverted.
1774          *
1775          * Hence, let's save and restore the pins that are configured
1776          * as GPIOs in the input mode with GPIROUTIOXAPIC bit set.
1777          *
1778          * See https://bugzilla.kernel.org/show_bug.cgi?id=214749.
1779          */
1780         value = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
1781         if (__intel_gpio_is_direct_irq(value))
1782                 return true;
1783
1784         return false;
1785 }
1786
1787 static int intel_pinctrl_suspend_noirq(struct device *dev)
1788 {
1789         struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1790         struct intel_community_context *communities;
1791         struct intel_pad_context *pads;
1792         int i;
1793
1794         pads = pctrl->context.pads;
1795         for (i = 0; i < pctrl->soc->npins; i++) {
1796                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1797                 void __iomem *padcfg;
1798                 u32 val;
1799
1800                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1801                         continue;
1802
1803                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1804                 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1805                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1806                 pads[i].padcfg1 = val;
1807
1808                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1809                 if (padcfg)
1810                         pads[i].padcfg2 = readl(padcfg);
1811         }
1812
1813         communities = pctrl->context.communities;
1814         for (i = 0; i < pctrl->ncommunities; i++) {
1815                 struct intel_community *community = &pctrl->communities[i];
1816                 void __iomem *base;
1817                 unsigned int gpp;
1818
1819                 base = community->regs + community->ie_offset;
1820                 for (gpp = 0; gpp < community->ngpps; gpp++)
1821                         communities[i].intmask[gpp] = readl(base + gpp * 4);
1822
1823                 base = community->regs + community->hostown_offset;
1824                 for (gpp = 0; gpp < community->ngpps; gpp++)
1825                         communities[i].hostown[gpp] = readl(base + gpp * 4);
1826         }
1827
1828         return 0;
1829 }
1830
1831 static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value)
1832 {
1833         u32 curr, updated;
1834
1835         curr = readl(reg);
1836
1837         updated = (curr & ~mask) | (value & mask);
1838         if (curr == updated)
1839                 return false;
1840
1841         writel(updated, reg);
1842         return true;
1843 }
1844
1845 static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c,
1846                                   void __iomem *base, unsigned int gpp, u32 saved)
1847 {
1848         const struct intel_community *community = &pctrl->communities[c];
1849         const struct intel_padgroup *padgrp = &community->gpps[gpp];
1850         struct device *dev = pctrl->dev;
1851         const char *dummy;
1852         u32 requested = 0;
1853         unsigned int i;
1854
1855         if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1856                 return;
1857
1858         for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy)
1859                 requested |= BIT(i);
1860
1861         if (!intel_gpio_update_reg(base + gpp * 4, requested, saved))
1862                 return;
1863
1864         dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1865 }
1866
1867 static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c,
1868                                   void __iomem *base, unsigned int gpp, u32 saved)
1869 {
1870         struct device *dev = pctrl->dev;
1871
1872         if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved))
1873                 return;
1874
1875         dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1876 }
1877
1878 static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin,
1879                                  unsigned int reg, u32 saved)
1880 {
1881         u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0;
1882         unsigned int n = reg / sizeof(u32);
1883         struct device *dev = pctrl->dev;
1884         void __iomem *padcfg;
1885
1886         padcfg = intel_get_padcfg(pctrl, pin, reg);
1887         if (!padcfg)
1888                 return;
1889
1890         if (!intel_gpio_update_reg(padcfg, ~mask, saved))
1891                 return;
1892
1893         dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg));
1894 }
1895
1896 static int intel_pinctrl_resume_noirq(struct device *dev)
1897 {
1898         struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1899         const struct intel_community_context *communities;
1900         const struct intel_pad_context *pads;
1901         int i;
1902
1903         /* Mask all interrupts */
1904         intel_gpio_irq_init(pctrl);
1905
1906         pads = pctrl->context.pads;
1907         for (i = 0; i < pctrl->soc->npins; i++) {
1908                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1909
1910                 if (!(intel_pinctrl_should_save(pctrl, desc->number) ||
1911                       /*
1912                        * If the firmware mangled the register contents too much,
1913                        * check the saved value for the Direct IRQ mode.
1914                        */
1915                       __intel_gpio_is_direct_irq(pads[i].padcfg0)))
1916                         continue;
1917
1918                 intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0);
1919                 intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1);
1920                 intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2);
1921         }
1922
1923         communities = pctrl->context.communities;
1924         for (i = 0; i < pctrl->ncommunities; i++) {
1925                 struct intel_community *community = &pctrl->communities[i];
1926                 void __iomem *base;
1927                 unsigned int gpp;
1928
1929                 base = community->regs + community->ie_offset;
1930                 for (gpp = 0; gpp < community->ngpps; gpp++)
1931                         intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]);
1932
1933                 base = community->regs + community->hostown_offset;
1934                 for (gpp = 0; gpp < community->ngpps; gpp++)
1935                         intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]);
1936         }
1937
1938         return 0;
1939 }
1940
1941 EXPORT_NS_GPL_DEV_SLEEP_PM_OPS(intel_pinctrl_pm_ops, PINCTRL_INTEL) = {
1942         NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend_noirq, intel_pinctrl_resume_noirq)
1943 };
1944
1945 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1946 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1947 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1948 MODULE_LICENSE("GPL v2");
1949 MODULE_IMPORT_NS("PWM_LPSS");