2 * Intel pinctrl/GPIO core driver.
4 * Copyright (C) 2015, Intel Corporation
5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
6 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/acpi.h>
17 #include <linux/gpio.h>
18 #include <linux/gpio/driver.h>
19 #include <linux/platform_device.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinconf-generic.h>
26 #include "pinctrl-intel.h"
28 /* Offset from regs */
31 #define GPI_GPE_STS 0x140
32 #define GPI_GPE_EN 0x160
35 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
36 #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
37 #define PADOWN_GPP(p) ((p) / 8)
39 /* Offset from pad_regs */
41 #define PADCFG0_RXEVCFG_SHIFT 25
42 #define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT)
43 #define PADCFG0_RXEVCFG_LEVEL 0
44 #define PADCFG0_RXEVCFG_EDGE 1
45 #define PADCFG0_RXEVCFG_DISABLED 2
46 #define PADCFG0_RXEVCFG_EDGE_BOTH 3
47 #define PADCFG0_RXINV BIT(23)
48 #define PADCFG0_GPIROUTIOXAPIC BIT(20)
49 #define PADCFG0_GPIROUTSCI BIT(19)
50 #define PADCFG0_GPIROUTSMI BIT(18)
51 #define PADCFG0_GPIROUTNMI BIT(17)
52 #define PADCFG0_PMODE_SHIFT 10
53 #define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT)
54 #define PADCFG0_GPIORXDIS BIT(9)
55 #define PADCFG0_GPIOTXDIS BIT(8)
56 #define PADCFG0_GPIORXSTATE BIT(1)
57 #define PADCFG0_GPIOTXSTATE BIT(0)
60 #define PADCFG1_TERM_UP BIT(13)
61 #define PADCFG1_TERM_SHIFT 10
62 #define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT)
63 #define PADCFG1_TERM_20K 4
64 #define PADCFG1_TERM_2K 3
65 #define PADCFG1_TERM_5K 2
66 #define PADCFG1_TERM_1K 1
68 struct intel_pad_context {
73 struct intel_community_context {
77 struct intel_pinctrl_context {
78 struct intel_pad_context *pads;
79 struct intel_community_context *communities;
83 * struct intel_pinctrl - Intel pinctrl private structure
84 * @dev: Pointer to the device structure
85 * @lock: Lock to serialize register access
86 * @pctldesc: Pin controller description
87 * @pctldev: Pointer to the pin controller device
88 * @chip: GPIO chip in this pin controller
89 * @soc: SoC/PCH specific pin configuration data
90 * @communities: All communities in this pin controller
91 * @ncommunities: Number of communities in this pin controller
92 * @context: Configuration saved over system sleep
94 struct intel_pinctrl {
97 struct pinctrl_desc pctldesc;
98 struct pinctrl_dev *pctldev;
99 struct gpio_chip chip;
100 const struct intel_pinctrl_soc_data *soc;
101 struct intel_community *communities;
103 struct intel_pinctrl_context context;
106 #define pin_to_padno(c, p) ((p) - (c)->pin_base)
108 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
111 struct intel_community *community;
114 for (i = 0; i < pctrl->ncommunities; i++) {
115 community = &pctrl->communities[i];
116 if (pin >= community->pin_base &&
117 pin < community->pin_base + community->npins)
121 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
125 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
128 const struct intel_community *community;
131 community = intel_get_community(pctrl, pin);
135 padno = pin_to_padno(community, pin);
136 return community->pad_regs + reg + padno * 8;
139 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
141 const struct intel_community *community;
142 unsigned padno, gpp, offset, group;
143 void __iomem *padown;
145 community = intel_get_community(pctrl, pin);
148 if (!community->padown_offset)
151 padno = pin_to_padno(community, pin);
152 group = padno / community->gpp_size;
153 gpp = PADOWN_GPP(padno % community->gpp_size);
154 offset = community->padown_offset + 0x10 * group + gpp * 4;
155 padown = community->regs + offset;
157 return !(readl(padown) & PADOWN_MASK(padno));
160 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
162 const struct intel_community *community;
163 unsigned padno, gpp, offset;
164 void __iomem *hostown;
166 community = intel_get_community(pctrl, pin);
169 if (!community->hostown_offset)
172 padno = pin_to_padno(community, pin);
173 gpp = padno / community->gpp_size;
174 offset = community->hostown_offset + gpp * 4;
175 hostown = community->regs + offset;
177 return !(readl(hostown) & BIT(padno % community->gpp_size));
180 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
182 struct intel_community *community;
183 unsigned padno, gpp, offset;
186 community = intel_get_community(pctrl, pin);
189 if (!community->padcfglock_offset)
192 padno = pin_to_padno(community, pin);
193 gpp = padno / community->gpp_size;
196 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
197 * the pad is considered unlocked. Any other case means that it is
198 * either fully or partially locked and we don't touch it.
200 offset = community->padcfglock_offset + gpp * 8;
201 value = readl(community->regs + offset);
202 if (value & BIT(pin % community->gpp_size))
205 offset = community->padcfglock_offset + 4 + gpp * 8;
206 value = readl(community->regs + offset);
207 if (value & BIT(pin % community->gpp_size))
213 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
215 return intel_pad_owned_by_host(pctrl, pin) &&
216 !intel_pad_locked(pctrl, pin);
219 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
221 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
223 return pctrl->soc->ngroups;
226 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
229 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
231 return pctrl->soc->groups[group].name;
234 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
235 const unsigned **pins, unsigned *npins)
237 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
239 *pins = pctrl->soc->groups[group].pins;
240 *npins = pctrl->soc->groups[group].npins;
244 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
247 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
248 u32 cfg0, cfg1, mode;
251 if (!intel_pad_owned_by_host(pctrl, pin)) {
252 seq_puts(s, "not available");
256 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
257 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
259 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
261 seq_puts(s, "GPIO ");
263 seq_printf(s, "mode %d ", mode);
265 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
267 locked = intel_pad_locked(pctrl, pin);
268 acpi = intel_pad_acpi_mode(pctrl, pin);
270 if (locked || acpi) {
273 seq_puts(s, "LOCKED");
283 static const struct pinctrl_ops intel_pinctrl_ops = {
284 .get_groups_count = intel_get_groups_count,
285 .get_group_name = intel_get_group_name,
286 .get_group_pins = intel_get_group_pins,
287 .pin_dbg_show = intel_pin_dbg_show,
290 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
292 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
294 return pctrl->soc->nfunctions;
297 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
300 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
302 return pctrl->soc->functions[function].name;
305 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
307 const char * const **groups,
308 unsigned * const ngroups)
310 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
312 *groups = pctrl->soc->functions[function].groups;
313 *ngroups = pctrl->soc->functions[function].ngroups;
317 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
320 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
321 const struct intel_pingroup *grp = &pctrl->soc->groups[group];
325 spin_lock_irqsave(&pctrl->lock, flags);
328 * All pins in the groups needs to be accessible and writable
329 * before we can enable the mux for this group.
331 for (i = 0; i < grp->npins; i++) {
332 if (!intel_pad_usable(pctrl, grp->pins[i])) {
333 spin_unlock_irqrestore(&pctrl->lock, flags);
338 /* Now enable the mux setting for each pin in the group */
339 for (i = 0; i < grp->npins; i++) {
340 void __iomem *padcfg0;
343 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
344 value = readl(padcfg0);
346 value &= ~PADCFG0_PMODE_MASK;
347 value |= grp->mode << PADCFG0_PMODE_SHIFT;
349 writel(value, padcfg0);
352 spin_unlock_irqrestore(&pctrl->lock, flags);
357 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
358 struct pinctrl_gpio_range *range,
361 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
362 void __iomem *padcfg0;
366 spin_lock_irqsave(&pctrl->lock, flags);
368 if (!intel_pad_usable(pctrl, pin)) {
369 spin_unlock_irqrestore(&pctrl->lock, flags);
373 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
374 /* Put the pad into GPIO mode */
375 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
376 /* Disable SCI/SMI/NMI generation */
377 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
378 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
379 /* Disable TX buffer and enable RX (this will be input) */
380 value &= ~PADCFG0_GPIORXDIS;
381 value |= PADCFG0_GPIOTXDIS;
382 writel(value, padcfg0);
384 spin_unlock_irqrestore(&pctrl->lock, flags);
389 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
390 struct pinctrl_gpio_range *range,
391 unsigned pin, bool input)
393 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
394 void __iomem *padcfg0;
398 spin_lock_irqsave(&pctrl->lock, flags);
400 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
402 value = readl(padcfg0);
404 value |= PADCFG0_GPIOTXDIS;
406 value &= ~PADCFG0_GPIOTXDIS;
407 writel(value, padcfg0);
409 spin_unlock_irqrestore(&pctrl->lock, flags);
414 static const struct pinmux_ops intel_pinmux_ops = {
415 .get_functions_count = intel_get_functions_count,
416 .get_function_name = intel_get_function_name,
417 .get_function_groups = intel_get_function_groups,
418 .set_mux = intel_pinmux_set_mux,
419 .gpio_request_enable = intel_gpio_request_enable,
420 .gpio_set_direction = intel_gpio_set_direction,
423 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
424 unsigned long *config)
426 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
427 enum pin_config_param param = pinconf_to_config_param(*config);
431 if (!intel_pad_owned_by_host(pctrl, pin))
434 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
435 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
438 case PIN_CONFIG_BIAS_DISABLE:
443 case PIN_CONFIG_BIAS_PULL_UP:
444 if (!term || !(value & PADCFG1_TERM_UP))
448 case PADCFG1_TERM_1K:
451 case PADCFG1_TERM_2K:
454 case PADCFG1_TERM_5K:
457 case PADCFG1_TERM_20K:
464 case PIN_CONFIG_BIAS_PULL_DOWN:
465 if (!term || value & PADCFG1_TERM_UP)
469 case PADCFG1_TERM_5K:
472 case PADCFG1_TERM_20K:
483 *config = pinconf_to_config_packed(param, arg);
487 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
488 unsigned long config)
490 unsigned param = pinconf_to_config_param(config);
491 unsigned arg = pinconf_to_config_argument(config);
492 void __iomem *padcfg1;
497 spin_lock_irqsave(&pctrl->lock, flags);
499 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
500 value = readl(padcfg1);
503 case PIN_CONFIG_BIAS_DISABLE:
504 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
507 case PIN_CONFIG_BIAS_PULL_UP:
508 value &= ~PADCFG1_TERM_MASK;
510 value |= PADCFG1_TERM_UP;
514 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
517 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
520 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
523 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
531 case PIN_CONFIG_BIAS_PULL_DOWN:
532 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
536 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
539 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
549 writel(value, padcfg1);
551 spin_unlock_irqrestore(&pctrl->lock, flags);
556 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
557 unsigned long *configs, unsigned nconfigs)
559 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
562 if (!intel_pad_usable(pctrl, pin))
565 for (i = 0; i < nconfigs; i++) {
566 switch (pinconf_to_config_param(configs[i])) {
567 case PIN_CONFIG_BIAS_DISABLE:
568 case PIN_CONFIG_BIAS_PULL_UP:
569 case PIN_CONFIG_BIAS_PULL_DOWN:
570 ret = intel_config_set_pull(pctrl, pin, configs[i]);
583 static const struct pinconf_ops intel_pinconf_ops = {
585 .pin_config_get = intel_config_get,
586 .pin_config_set = intel_config_set,
589 static const struct pinctrl_desc intel_pinctrl_desc = {
590 .pctlops = &intel_pinctrl_ops,
591 .pmxops = &intel_pinmux_ops,
592 .confops = &intel_pinconf_ops,
593 .owner = THIS_MODULE,
596 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
598 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
601 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
605 return !!(readl(reg) & PADCFG0_GPIORXSTATE);
608 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
610 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
613 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
618 spin_lock_irqsave(&pctrl->lock, flags);
619 padcfg0 = readl(reg);
621 padcfg0 |= PADCFG0_GPIOTXSTATE;
623 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
624 writel(padcfg0, reg);
625 spin_unlock_irqrestore(&pctrl->lock, flags);
629 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
631 return pinctrl_gpio_direction_input(chip->base + offset);
634 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
637 intel_gpio_set(chip, offset, value);
638 return pinctrl_gpio_direction_output(chip->base + offset);
641 static const struct gpio_chip intel_gpio_chip = {
642 .owner = THIS_MODULE,
643 .request = gpiochip_generic_request,
644 .free = gpiochip_generic_free,
645 .direction_input = intel_gpio_direction_input,
646 .direction_output = intel_gpio_direction_output,
647 .get = intel_gpio_get,
648 .set = intel_gpio_set,
651 static void intel_gpio_irq_ack(struct irq_data *d)
653 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
654 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
655 const struct intel_community *community;
656 unsigned pin = irqd_to_hwirq(d);
658 spin_lock(&pctrl->lock);
660 community = intel_get_community(pctrl, pin);
662 unsigned padno = pin_to_padno(community, pin);
663 unsigned gpp_offset = padno % community->gpp_size;
664 unsigned gpp = padno / community->gpp_size;
666 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
669 spin_unlock(&pctrl->lock);
672 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
674 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
675 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
676 const struct intel_community *community;
677 unsigned pin = irqd_to_hwirq(d);
680 spin_lock_irqsave(&pctrl->lock, flags);
682 community = intel_get_community(pctrl, pin);
684 unsigned padno = pin_to_padno(community, pin);
685 unsigned gpp_offset = padno % community->gpp_size;
686 unsigned gpp = padno / community->gpp_size;
690 reg = community->regs + community->ie_offset + gpp * 4;
693 value &= ~BIT(gpp_offset);
695 value |= BIT(gpp_offset);
699 spin_unlock_irqrestore(&pctrl->lock, flags);
702 static void intel_gpio_irq_mask(struct irq_data *d)
704 intel_gpio_irq_mask_unmask(d, true);
707 static void intel_gpio_irq_unmask(struct irq_data *d)
709 intel_gpio_irq_mask_unmask(d, false);
712 static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
714 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
715 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
716 unsigned pin = irqd_to_hwirq(d);
721 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
726 * If the pin is in ACPI mode it is still usable as a GPIO but it
727 * cannot be used as IRQ because GPI_IS status bit will not be
728 * updated by the host controller hardware.
730 if (intel_pad_acpi_mode(pctrl, pin)) {
731 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
735 spin_lock_irqsave(&pctrl->lock, flags);
739 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
741 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
742 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
743 } else if (type & IRQ_TYPE_EDGE_FALLING) {
744 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
745 value |= PADCFG0_RXINV;
746 } else if (type & IRQ_TYPE_EDGE_RISING) {
747 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
748 } else if (type & IRQ_TYPE_LEVEL_LOW) {
749 value |= PADCFG0_RXINV;
751 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
756 if (type & IRQ_TYPE_EDGE_BOTH)
757 irq_set_handler_locked(d, handle_edge_irq);
758 else if (type & IRQ_TYPE_LEVEL_MASK)
759 irq_set_handler_locked(d, handle_level_irq);
761 spin_unlock_irqrestore(&pctrl->lock, flags);
766 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
768 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
769 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
770 const struct intel_community *community;
771 unsigned pin = irqd_to_hwirq(d);
772 unsigned padno, gpp, gpp_offset;
775 community = intel_get_community(pctrl, pin);
779 padno = pin_to_padno(community, pin);
780 gpp = padno / community->gpp_size;
781 gpp_offset = padno % community->gpp_size;
783 /* Clear the existing wake status */
784 writel(BIT(gpp_offset), community->regs + GPI_GPE_STS + gpp * 4);
787 * The controller will generate wake when GPE of the corresponding
788 * pad is enabled and it is not routed to SCI (GPIROUTSCI is not
791 gpe_en = readl(community->regs + GPI_GPE_EN + gpp * 4);
793 gpe_en |= BIT(gpp_offset);
795 gpe_en &= ~BIT(gpp_offset);
796 writel(gpe_en, community->regs + GPI_GPE_EN + gpp * 4);
798 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
802 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
803 const struct intel_community *community)
805 struct gpio_chip *gc = &pctrl->chip;
806 irqreturn_t ret = IRQ_NONE;
809 for (gpp = 0; gpp < community->ngpps; gpp++) {
810 unsigned long pending, enabled, gpp_offset;
812 pending = readl(community->regs + GPI_IS + gpp * 4);
813 enabled = readl(community->regs + community->ie_offset +
816 /* Only interrupts that are enabled */
819 for_each_set_bit(gpp_offset, &pending, community->gpp_size) {
823 * The last group in community can have less pins
826 padno = gpp_offset + gpp * community->gpp_size;
827 if (padno >= community->npins)
830 irq = irq_find_mapping(gc->irqdomain,
831 community->pin_base + padno);
832 generic_handle_irq(irq);
841 static irqreturn_t intel_gpio_irq(int irq, void *data)
843 const struct intel_community *community;
844 struct intel_pinctrl *pctrl = data;
845 irqreturn_t ret = IRQ_NONE;
848 /* Need to check all communities for pending interrupts */
849 for (i = 0; i < pctrl->ncommunities; i++) {
850 community = &pctrl->communities[i];
851 ret |= intel_gpio_community_irq_handler(pctrl, community);
857 static struct irq_chip intel_gpio_irqchip = {
858 .name = "intel-gpio",
859 .irq_ack = intel_gpio_irq_ack,
860 .irq_mask = intel_gpio_irq_mask,
861 .irq_unmask = intel_gpio_irq_unmask,
862 .irq_set_type = intel_gpio_irq_type,
863 .irq_set_wake = intel_gpio_irq_wake,
866 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
870 pctrl->chip = intel_gpio_chip;
872 pctrl->chip.ngpio = pctrl->soc->npins;
873 pctrl->chip.label = dev_name(pctrl->dev);
874 pctrl->chip.parent = pctrl->dev;
875 pctrl->chip.base = -1;
877 ret = gpiochip_add_data(&pctrl->chip, pctrl);
879 dev_err(pctrl->dev, "failed to register gpiochip\n");
883 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
884 0, 0, pctrl->soc->npins);
886 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
891 * We need to request the interrupt here (instead of providing chip
892 * to the irq directly) because on some platforms several GPIO
893 * controllers share the same interrupt line.
895 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, IRQF_SHARED,
896 dev_name(pctrl->dev), pctrl);
898 dev_err(pctrl->dev, "failed to request interrupt\n");
902 ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
903 handle_simple_irq, IRQ_TYPE_NONE);
905 dev_err(pctrl->dev, "failed to add irqchip\n");
909 gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
914 gpiochip_remove(&pctrl->chip);
919 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
921 #ifdef CONFIG_PM_SLEEP
922 const struct intel_pinctrl_soc_data *soc = pctrl->soc;
923 struct intel_community_context *communities;
924 struct intel_pad_context *pads;
927 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
931 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
932 sizeof(*communities), GFP_KERNEL);
937 for (i = 0; i < pctrl->ncommunities; i++) {
938 struct intel_community *community = &pctrl->communities[i];
941 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
942 sizeof(*intmask), GFP_KERNEL);
946 communities[i].intmask = intmask;
949 pctrl->context.pads = pads;
950 pctrl->context.communities = communities;
956 int intel_pinctrl_probe(struct platform_device *pdev,
957 const struct intel_pinctrl_soc_data *soc_data)
959 struct intel_pinctrl *pctrl;
965 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
969 pctrl->dev = &pdev->dev;
970 pctrl->soc = soc_data;
971 spin_lock_init(&pctrl->lock);
974 * Make a copy of the communities which we can use to hold pointers
977 pctrl->ncommunities = pctrl->soc->ncommunities;
978 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
979 sizeof(*pctrl->communities), GFP_KERNEL);
980 if (!pctrl->communities)
983 for (i = 0; i < pctrl->ncommunities; i++) {
984 struct intel_community *community = &pctrl->communities[i];
985 struct resource *res;
989 *community = pctrl->soc->communities[i];
991 res = platform_get_resource(pdev, IORESOURCE_MEM,
993 regs = devm_ioremap_resource(&pdev->dev, res);
995 return PTR_ERR(regs);
997 /* Read offset of the pad configuration registers */
998 padbar = readl(regs + PADBAR);
1000 community->regs = regs;
1001 community->pad_regs = regs + padbar;
1002 community->ngpps = DIV_ROUND_UP(community->npins,
1003 community->gpp_size);
1006 irq = platform_get_irq(pdev, 0);
1008 dev_err(&pdev->dev, "failed to get interrupt number\n");
1012 ret = intel_pinctrl_pm_init(pctrl);
1016 pctrl->pctldesc = intel_pinctrl_desc;
1017 pctrl->pctldesc.name = dev_name(&pdev->dev);
1018 pctrl->pctldesc.pins = pctrl->soc->pins;
1019 pctrl->pctldesc.npins = pctrl->soc->npins;
1021 pctrl->pctldev = pinctrl_register(&pctrl->pctldesc, &pdev->dev, pctrl);
1022 if (IS_ERR(pctrl->pctldev)) {
1023 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1024 return PTR_ERR(pctrl->pctldev);
1027 ret = intel_gpio_probe(pctrl, irq);
1029 pinctrl_unregister(pctrl->pctldev);
1033 platform_set_drvdata(pdev, pctrl);
1037 EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1039 int intel_pinctrl_remove(struct platform_device *pdev)
1041 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1043 gpiochip_remove(&pctrl->chip);
1044 pinctrl_unregister(pctrl->pctldev);
1048 EXPORT_SYMBOL_GPL(intel_pinctrl_remove);
1050 #ifdef CONFIG_PM_SLEEP
1051 int intel_pinctrl_suspend(struct device *dev)
1053 struct platform_device *pdev = to_platform_device(dev);
1054 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1055 struct intel_community_context *communities;
1056 struct intel_pad_context *pads;
1059 pads = pctrl->context.pads;
1060 for (i = 0; i < pctrl->soc->npins; i++) {
1061 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1064 if (!intel_pad_usable(pctrl, desc->number))
1067 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1068 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1069 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1070 pads[i].padcfg1 = val;
1073 communities = pctrl->context.communities;
1074 for (i = 0; i < pctrl->ncommunities; i++) {
1075 struct intel_community *community = &pctrl->communities[i];
1079 base = community->regs + community->ie_offset;
1080 for (gpp = 0; gpp < community->ngpps; gpp++)
1081 communities[i].intmask[gpp] = readl(base + gpp * 4);
1086 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1088 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1092 for (i = 0; i < pctrl->ncommunities; i++) {
1093 const struct intel_community *community;
1097 community = &pctrl->communities[i];
1098 base = community->regs;
1100 for (gpp = 0; gpp < community->ngpps; gpp++) {
1101 /* Mask and clear all interrupts */
1102 writel(0, base + community->ie_offset + gpp * 4);
1103 writel(0xffff, base + GPI_IS + gpp * 4);
1108 int intel_pinctrl_resume(struct device *dev)
1110 struct platform_device *pdev = to_platform_device(dev);
1111 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1112 const struct intel_community_context *communities;
1113 const struct intel_pad_context *pads;
1116 /* Mask all interrupts */
1117 intel_gpio_irq_init(pctrl);
1119 pads = pctrl->context.pads;
1120 for (i = 0; i < pctrl->soc->npins; i++) {
1121 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1122 void __iomem *padcfg;
1125 if (!intel_pad_usable(pctrl, desc->number))
1128 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1129 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1130 if (val != pads[i].padcfg0) {
1131 writel(pads[i].padcfg0, padcfg);
1132 dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1133 desc->number, readl(padcfg));
1136 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1137 val = readl(padcfg);
1138 if (val != pads[i].padcfg1) {
1139 writel(pads[i].padcfg1, padcfg);
1140 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1141 desc->number, readl(padcfg));
1145 communities = pctrl->context.communities;
1146 for (i = 0; i < pctrl->ncommunities; i++) {
1147 struct intel_community *community = &pctrl->communities[i];
1151 base = community->regs + community->ie_offset;
1152 for (gpp = 0; gpp < community->ngpps; gpp++) {
1153 writel(communities[i].intmask[gpp], base + gpp * 4);
1154 dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1155 readl(base + gpp * 4));
1161 EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1164 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1165 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1166 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1167 MODULE_LICENSE("GPL v2");