2 * Intel pinctrl/GPIO core driver.
4 * Copyright (C) 2015, Intel Corporation
5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
6 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/platform_device.h>
17 #include <linux/pinctrl/pinctrl.h>
18 #include <linux/pinctrl/pinmux.h>
19 #include <linux/pinctrl/pinconf.h>
20 #include <linux/pinctrl/pinconf-generic.h>
23 #include "pinctrl-intel.h"
25 /* Offset from regs */
28 #define GPI_GPE_STS 0x140
29 #define GPI_GPE_EN 0x160
32 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
33 #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
34 #define PADOWN_GPP(p) ((p) / 8)
36 /* Offset from pad_regs */
38 #define PADCFG0_RXEVCFG_SHIFT 25
39 #define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT)
40 #define PADCFG0_RXEVCFG_LEVEL 0
41 #define PADCFG0_RXEVCFG_EDGE 1
42 #define PADCFG0_RXEVCFG_DISABLED 2
43 #define PADCFG0_RXEVCFG_EDGE_BOTH 3
44 #define PADCFG0_RXINV BIT(23)
45 #define PADCFG0_GPIROUTIOXAPIC BIT(20)
46 #define PADCFG0_GPIROUTSCI BIT(19)
47 #define PADCFG0_GPIROUTSMI BIT(18)
48 #define PADCFG0_GPIROUTNMI BIT(17)
49 #define PADCFG0_PMODE_SHIFT 10
50 #define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT)
51 #define PADCFG0_GPIORXDIS BIT(9)
52 #define PADCFG0_GPIOTXDIS BIT(8)
53 #define PADCFG0_GPIORXSTATE BIT(1)
54 #define PADCFG0_GPIOTXSTATE BIT(0)
57 #define PADCFG1_TERM_UP BIT(13)
58 #define PADCFG1_TERM_SHIFT 10
59 #define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT)
60 #define PADCFG1_TERM_20K 4
61 #define PADCFG1_TERM_2K 3
62 #define PADCFG1_TERM_5K 2
63 #define PADCFG1_TERM_1K 1
65 struct intel_pad_context {
70 struct intel_community_context {
74 struct intel_pinctrl_context {
75 struct intel_pad_context *pads;
76 struct intel_community_context *communities;
80 * struct intel_pinctrl - Intel pinctrl private structure
81 * @dev: Pointer to the device structure
82 * @lock: Lock to serialize register access
83 * @pctldesc: Pin controller description
84 * @pctldev: Pointer to the pin controller device
85 * @chip: GPIO chip in this pin controller
86 * @soc: SoC/PCH specific pin configuration data
87 * @communities: All communities in this pin controller
88 * @ncommunities: Number of communities in this pin controller
89 * @context: Configuration saved over system sleep
90 * @irq: pinctrl/GPIO chip irq number
92 struct intel_pinctrl {
95 struct pinctrl_desc pctldesc;
96 struct pinctrl_dev *pctldev;
97 struct gpio_chip chip;
98 const struct intel_pinctrl_soc_data *soc;
99 struct intel_community *communities;
101 struct intel_pinctrl_context context;
105 #define pin_to_padno(c, p) ((p) - (c)->pin_base)
107 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
110 struct intel_community *community;
113 for (i = 0; i < pctrl->ncommunities; i++) {
114 community = &pctrl->communities[i];
115 if (pin >= community->pin_base &&
116 pin < community->pin_base + community->npins)
120 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
124 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
127 const struct intel_community *community;
130 community = intel_get_community(pctrl, pin);
134 padno = pin_to_padno(community, pin);
135 return community->pad_regs + reg + padno * 8;
138 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
140 const struct intel_community *community;
141 unsigned padno, gpp, offset, group;
142 void __iomem *padown;
144 community = intel_get_community(pctrl, pin);
147 if (!community->padown_offset)
150 padno = pin_to_padno(community, pin);
151 group = padno / community->gpp_size;
152 gpp = PADOWN_GPP(padno % community->gpp_size);
153 offset = community->padown_offset + 0x10 * group + gpp * 4;
154 padown = community->regs + offset;
156 return !(readl(padown) & PADOWN_MASK(padno));
159 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
161 const struct intel_community *community;
162 unsigned padno, gpp, offset;
163 void __iomem *hostown;
165 community = intel_get_community(pctrl, pin);
168 if (!community->hostown_offset)
171 padno = pin_to_padno(community, pin);
172 gpp = padno / community->gpp_size;
173 offset = community->hostown_offset + gpp * 4;
174 hostown = community->regs + offset;
176 return !(readl(hostown) & BIT(padno % community->gpp_size));
179 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
181 struct intel_community *community;
182 unsigned padno, gpp, offset;
185 community = intel_get_community(pctrl, pin);
188 if (!community->padcfglock_offset)
191 padno = pin_to_padno(community, pin);
192 gpp = padno / community->gpp_size;
195 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
196 * the pad is considered unlocked. Any other case means that it is
197 * either fully or partially locked and we don't touch it.
199 offset = community->padcfglock_offset + gpp * 8;
200 value = readl(community->regs + offset);
201 if (value & BIT(pin % community->gpp_size))
204 offset = community->padcfglock_offset + 4 + gpp * 8;
205 value = readl(community->regs + offset);
206 if (value & BIT(pin % community->gpp_size))
212 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
214 return intel_pad_owned_by_host(pctrl, pin) &&
215 !intel_pad_locked(pctrl, pin);
218 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
220 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
222 return pctrl->soc->ngroups;
225 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
228 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
230 return pctrl->soc->groups[group].name;
233 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
234 const unsigned **pins, unsigned *npins)
236 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
238 *pins = pctrl->soc->groups[group].pins;
239 *npins = pctrl->soc->groups[group].npins;
243 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
246 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
247 u32 cfg0, cfg1, mode;
250 if (!intel_pad_owned_by_host(pctrl, pin)) {
251 seq_puts(s, "not available");
255 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
256 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
258 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
260 seq_puts(s, "GPIO ");
262 seq_printf(s, "mode %d ", mode);
264 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
266 locked = intel_pad_locked(pctrl, pin);
267 acpi = intel_pad_acpi_mode(pctrl, pin);
269 if (locked || acpi) {
272 seq_puts(s, "LOCKED");
282 static const struct pinctrl_ops intel_pinctrl_ops = {
283 .get_groups_count = intel_get_groups_count,
284 .get_group_name = intel_get_group_name,
285 .get_group_pins = intel_get_group_pins,
286 .pin_dbg_show = intel_pin_dbg_show,
289 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
291 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
293 return pctrl->soc->nfunctions;
296 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
299 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
301 return pctrl->soc->functions[function].name;
304 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
306 const char * const **groups,
307 unsigned * const ngroups)
309 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
311 *groups = pctrl->soc->functions[function].groups;
312 *ngroups = pctrl->soc->functions[function].ngroups;
316 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
319 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
320 const struct intel_pingroup *grp = &pctrl->soc->groups[group];
324 raw_spin_lock_irqsave(&pctrl->lock, flags);
327 * All pins in the groups needs to be accessible and writable
328 * before we can enable the mux for this group.
330 for (i = 0; i < grp->npins; i++) {
331 if (!intel_pad_usable(pctrl, grp->pins[i])) {
332 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
337 /* Now enable the mux setting for each pin in the group */
338 for (i = 0; i < grp->npins; i++) {
339 void __iomem *padcfg0;
342 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
343 value = readl(padcfg0);
345 value &= ~PADCFG0_PMODE_MASK;
346 value |= grp->mode << PADCFG0_PMODE_SHIFT;
348 writel(value, padcfg0);
351 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
356 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
357 struct pinctrl_gpio_range *range,
360 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
361 void __iomem *padcfg0;
365 raw_spin_lock_irqsave(&pctrl->lock, flags);
367 if (!intel_pad_usable(pctrl, pin)) {
368 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
372 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
373 /* Put the pad into GPIO mode */
374 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
375 /* Disable SCI/SMI/NMI generation */
376 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
377 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
378 /* Disable TX buffer and enable RX (this will be input) */
379 value &= ~PADCFG0_GPIORXDIS;
380 value |= PADCFG0_GPIOTXDIS;
381 writel(value, padcfg0);
383 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
388 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
389 struct pinctrl_gpio_range *range,
390 unsigned pin, bool input)
392 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
393 void __iomem *padcfg0;
397 raw_spin_lock_irqsave(&pctrl->lock, flags);
399 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
401 value = readl(padcfg0);
403 value |= PADCFG0_GPIOTXDIS;
405 value &= ~PADCFG0_GPIOTXDIS;
406 writel(value, padcfg0);
408 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
413 static const struct pinmux_ops intel_pinmux_ops = {
414 .get_functions_count = intel_get_functions_count,
415 .get_function_name = intel_get_function_name,
416 .get_function_groups = intel_get_function_groups,
417 .set_mux = intel_pinmux_set_mux,
418 .gpio_request_enable = intel_gpio_request_enable,
419 .gpio_set_direction = intel_gpio_set_direction,
422 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
423 unsigned long *config)
425 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
426 enum pin_config_param param = pinconf_to_config_param(*config);
430 if (!intel_pad_owned_by_host(pctrl, pin))
433 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
434 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
437 case PIN_CONFIG_BIAS_DISABLE:
442 case PIN_CONFIG_BIAS_PULL_UP:
443 if (!term || !(value & PADCFG1_TERM_UP))
447 case PADCFG1_TERM_1K:
450 case PADCFG1_TERM_2K:
453 case PADCFG1_TERM_5K:
456 case PADCFG1_TERM_20K:
463 case PIN_CONFIG_BIAS_PULL_DOWN:
464 if (!term || value & PADCFG1_TERM_UP)
468 case PADCFG1_TERM_5K:
471 case PADCFG1_TERM_20K:
482 *config = pinconf_to_config_packed(param, arg);
486 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
487 unsigned long config)
489 unsigned param = pinconf_to_config_param(config);
490 unsigned arg = pinconf_to_config_argument(config);
491 void __iomem *padcfg1;
496 raw_spin_lock_irqsave(&pctrl->lock, flags);
498 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
499 value = readl(padcfg1);
502 case PIN_CONFIG_BIAS_DISABLE:
503 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
506 case PIN_CONFIG_BIAS_PULL_UP:
507 value &= ~PADCFG1_TERM_MASK;
509 value |= PADCFG1_TERM_UP;
513 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
516 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
519 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
522 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
530 case PIN_CONFIG_BIAS_PULL_DOWN:
531 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
535 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
538 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
548 writel(value, padcfg1);
550 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
555 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
556 unsigned long *configs, unsigned nconfigs)
558 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
561 if (!intel_pad_usable(pctrl, pin))
564 for (i = 0; i < nconfigs; i++) {
565 switch (pinconf_to_config_param(configs[i])) {
566 case PIN_CONFIG_BIAS_DISABLE:
567 case PIN_CONFIG_BIAS_PULL_UP:
568 case PIN_CONFIG_BIAS_PULL_DOWN:
569 ret = intel_config_set_pull(pctrl, pin, configs[i]);
582 static const struct pinconf_ops intel_pinconf_ops = {
584 .pin_config_get = intel_config_get,
585 .pin_config_set = intel_config_set,
588 static const struct pinctrl_desc intel_pinctrl_desc = {
589 .pctlops = &intel_pinctrl_ops,
590 .pmxops = &intel_pinmux_ops,
591 .confops = &intel_pinconf_ops,
592 .owner = THIS_MODULE,
595 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
597 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
600 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
604 return !!(readl(reg) & PADCFG0_GPIORXSTATE);
607 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
609 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
612 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
617 raw_spin_lock_irqsave(&pctrl->lock, flags);
618 padcfg0 = readl(reg);
620 padcfg0 |= PADCFG0_GPIOTXSTATE;
622 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
623 writel(padcfg0, reg);
624 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
628 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
630 return pinctrl_gpio_direction_input(chip->base + offset);
633 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
636 intel_gpio_set(chip, offset, value);
637 return pinctrl_gpio_direction_output(chip->base + offset);
640 static const struct gpio_chip intel_gpio_chip = {
641 .owner = THIS_MODULE,
642 .request = gpiochip_generic_request,
643 .free = gpiochip_generic_free,
644 .direction_input = intel_gpio_direction_input,
645 .direction_output = intel_gpio_direction_output,
646 .get = intel_gpio_get,
647 .set = intel_gpio_set,
650 static void intel_gpio_irq_ack(struct irq_data *d)
652 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
653 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
654 const struct intel_community *community;
655 unsigned pin = irqd_to_hwirq(d);
657 raw_spin_lock(&pctrl->lock);
659 community = intel_get_community(pctrl, pin);
661 unsigned padno = pin_to_padno(community, pin);
662 unsigned gpp_offset = padno % community->gpp_size;
663 unsigned gpp = padno / community->gpp_size;
665 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
668 raw_spin_unlock(&pctrl->lock);
671 static void intel_gpio_irq_enable(struct irq_data *d)
673 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
674 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
675 const struct intel_community *community;
676 unsigned pin = irqd_to_hwirq(d);
679 raw_spin_lock_irqsave(&pctrl->lock, flags);
681 community = intel_get_community(pctrl, pin);
683 unsigned padno = pin_to_padno(community, pin);
684 unsigned gpp_size = community->gpp_size;
685 unsigned gpp_offset = padno % gpp_size;
686 unsigned gpp = padno / gpp_size;
689 /* Clear interrupt status first to avoid unexpected interrupt */
690 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
692 value = readl(community->regs + community->ie_offset + gpp * 4);
693 value |= BIT(gpp_offset);
694 writel(value, community->regs + community->ie_offset + gpp * 4);
697 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
700 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
702 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
703 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
704 const struct intel_community *community;
705 unsigned pin = irqd_to_hwirq(d);
708 raw_spin_lock_irqsave(&pctrl->lock, flags);
710 community = intel_get_community(pctrl, pin);
712 unsigned padno = pin_to_padno(community, pin);
713 unsigned gpp_offset = padno % community->gpp_size;
714 unsigned gpp = padno / community->gpp_size;
718 reg = community->regs + community->ie_offset + gpp * 4;
721 value &= ~BIT(gpp_offset);
723 value |= BIT(gpp_offset);
727 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
730 static void intel_gpio_irq_mask(struct irq_data *d)
732 intel_gpio_irq_mask_unmask(d, true);
735 static void intel_gpio_irq_unmask(struct irq_data *d)
737 intel_gpio_irq_mask_unmask(d, false);
740 static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
742 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
743 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
744 unsigned pin = irqd_to_hwirq(d);
749 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
754 * If the pin is in ACPI mode it is still usable as a GPIO but it
755 * cannot be used as IRQ because GPI_IS status bit will not be
756 * updated by the host controller hardware.
758 if (intel_pad_acpi_mode(pctrl, pin)) {
759 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
763 raw_spin_lock_irqsave(&pctrl->lock, flags);
767 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
769 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
770 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
771 } else if (type & IRQ_TYPE_EDGE_FALLING) {
772 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
773 value |= PADCFG0_RXINV;
774 } else if (type & IRQ_TYPE_EDGE_RISING) {
775 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
776 } else if (type & IRQ_TYPE_LEVEL_MASK) {
777 if (type & IRQ_TYPE_LEVEL_LOW)
778 value |= PADCFG0_RXINV;
780 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
785 if (type & IRQ_TYPE_EDGE_BOTH)
786 irq_set_handler_locked(d, handle_edge_irq);
787 else if (type & IRQ_TYPE_LEVEL_MASK)
788 irq_set_handler_locked(d, handle_level_irq);
790 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
795 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
797 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
798 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
799 unsigned pin = irqd_to_hwirq(d);
802 enable_irq_wake(pctrl->irq);
804 disable_irq_wake(pctrl->irq);
806 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
810 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
811 const struct intel_community *community)
813 struct gpio_chip *gc = &pctrl->chip;
814 irqreturn_t ret = IRQ_NONE;
817 for (gpp = 0; gpp < community->ngpps; gpp++) {
818 unsigned long pending, enabled, gpp_offset;
820 pending = readl(community->regs + GPI_IS + gpp * 4);
821 enabled = readl(community->regs + community->ie_offset +
824 /* Only interrupts that are enabled */
827 for_each_set_bit(gpp_offset, &pending, community->gpp_size) {
831 * The last group in community can have less pins
834 padno = gpp_offset + gpp * community->gpp_size;
835 if (padno >= community->npins)
838 irq = irq_find_mapping(gc->irqdomain,
839 community->pin_base + padno);
840 generic_handle_irq(irq);
849 static irqreturn_t intel_gpio_irq(int irq, void *data)
851 const struct intel_community *community;
852 struct intel_pinctrl *pctrl = data;
853 irqreturn_t ret = IRQ_NONE;
856 /* Need to check all communities for pending interrupts */
857 for (i = 0; i < pctrl->ncommunities; i++) {
858 community = &pctrl->communities[i];
859 ret |= intel_gpio_community_irq_handler(pctrl, community);
865 static struct irq_chip intel_gpio_irqchip = {
866 .name = "intel-gpio",
867 .irq_enable = intel_gpio_irq_enable,
868 .irq_ack = intel_gpio_irq_ack,
869 .irq_mask = intel_gpio_irq_mask,
870 .irq_unmask = intel_gpio_irq_unmask,
871 .irq_set_type = intel_gpio_irq_type,
872 .irq_set_wake = intel_gpio_irq_wake,
875 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
879 pctrl->chip = intel_gpio_chip;
881 pctrl->chip.ngpio = pctrl->soc->npins;
882 pctrl->chip.label = dev_name(pctrl->dev);
883 pctrl->chip.parent = pctrl->dev;
884 pctrl->chip.base = -1;
887 ret = gpiochip_add_data(&pctrl->chip, pctrl);
889 dev_err(pctrl->dev, "failed to register gpiochip\n");
893 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
894 0, 0, pctrl->soc->npins);
896 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
901 * We need to request the interrupt here (instead of providing chip
902 * to the irq directly) because on some platforms several GPIO
903 * controllers share the same interrupt line.
905 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
906 IRQF_SHARED | IRQF_NO_THREAD,
907 dev_name(pctrl->dev), pctrl);
909 dev_err(pctrl->dev, "failed to request interrupt\n");
913 ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
914 handle_bad_irq, IRQ_TYPE_NONE);
916 dev_err(pctrl->dev, "failed to add irqchip\n");
920 gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
925 gpiochip_remove(&pctrl->chip);
930 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
932 #ifdef CONFIG_PM_SLEEP
933 const struct intel_pinctrl_soc_data *soc = pctrl->soc;
934 struct intel_community_context *communities;
935 struct intel_pad_context *pads;
938 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
942 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
943 sizeof(*communities), GFP_KERNEL);
948 for (i = 0; i < pctrl->ncommunities; i++) {
949 struct intel_community *community = &pctrl->communities[i];
952 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
953 sizeof(*intmask), GFP_KERNEL);
957 communities[i].intmask = intmask;
960 pctrl->context.pads = pads;
961 pctrl->context.communities = communities;
967 int intel_pinctrl_probe(struct platform_device *pdev,
968 const struct intel_pinctrl_soc_data *soc_data)
970 struct intel_pinctrl *pctrl;
976 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
980 pctrl->dev = &pdev->dev;
981 pctrl->soc = soc_data;
982 raw_spin_lock_init(&pctrl->lock);
985 * Make a copy of the communities which we can use to hold pointers
988 pctrl->ncommunities = pctrl->soc->ncommunities;
989 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
990 sizeof(*pctrl->communities), GFP_KERNEL);
991 if (!pctrl->communities)
994 for (i = 0; i < pctrl->ncommunities; i++) {
995 struct intel_community *community = &pctrl->communities[i];
996 struct resource *res;
1000 *community = pctrl->soc->communities[i];
1002 res = platform_get_resource(pdev, IORESOURCE_MEM,
1004 regs = devm_ioremap_resource(&pdev->dev, res);
1006 return PTR_ERR(regs);
1008 /* Read offset of the pad configuration registers */
1009 padbar = readl(regs + PADBAR);
1011 community->regs = regs;
1012 community->pad_regs = regs + padbar;
1013 community->ngpps = DIV_ROUND_UP(community->npins,
1014 community->gpp_size);
1017 irq = platform_get_irq(pdev, 0);
1019 dev_err(&pdev->dev, "failed to get interrupt number\n");
1023 ret = intel_pinctrl_pm_init(pctrl);
1027 pctrl->pctldesc = intel_pinctrl_desc;
1028 pctrl->pctldesc.name = dev_name(&pdev->dev);
1029 pctrl->pctldesc.pins = pctrl->soc->pins;
1030 pctrl->pctldesc.npins = pctrl->soc->npins;
1032 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1034 if (IS_ERR(pctrl->pctldev)) {
1035 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1036 return PTR_ERR(pctrl->pctldev);
1039 ret = intel_gpio_probe(pctrl, irq);
1043 platform_set_drvdata(pdev, pctrl);
1047 EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1049 int intel_pinctrl_remove(struct platform_device *pdev)
1051 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1053 gpiochip_remove(&pctrl->chip);
1057 EXPORT_SYMBOL_GPL(intel_pinctrl_remove);
1059 #ifdef CONFIG_PM_SLEEP
1060 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin)
1062 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1064 if (!pd || !intel_pad_usable(pctrl, pin))
1068 * Only restore the pin if it is actually in use by the kernel (or
1069 * by userspace). It is possible that some pins are used by the
1070 * BIOS during resume and those are not always locked down so leave
1073 if (pd->mux_owner || pd->gpio_owner ||
1074 gpiochip_line_is_irq(&pctrl->chip, pin))
1080 int intel_pinctrl_suspend(struct device *dev)
1082 struct platform_device *pdev = to_platform_device(dev);
1083 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1084 struct intel_community_context *communities;
1085 struct intel_pad_context *pads;
1088 pads = pctrl->context.pads;
1089 for (i = 0; i < pctrl->soc->npins; i++) {
1090 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1093 if (!intel_pinctrl_should_save(pctrl, desc->number))
1096 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1097 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1098 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1099 pads[i].padcfg1 = val;
1102 communities = pctrl->context.communities;
1103 for (i = 0; i < pctrl->ncommunities; i++) {
1104 struct intel_community *community = &pctrl->communities[i];
1108 base = community->regs + community->ie_offset;
1109 for (gpp = 0; gpp < community->ngpps; gpp++)
1110 communities[i].intmask[gpp] = readl(base + gpp * 4);
1115 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1117 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1121 for (i = 0; i < pctrl->ncommunities; i++) {
1122 const struct intel_community *community;
1126 community = &pctrl->communities[i];
1127 base = community->regs;
1129 for (gpp = 0; gpp < community->ngpps; gpp++) {
1130 /* Mask and clear all interrupts */
1131 writel(0, base + community->ie_offset + gpp * 4);
1132 writel(0xffff, base + GPI_IS + gpp * 4);
1137 int intel_pinctrl_resume(struct device *dev)
1139 struct platform_device *pdev = to_platform_device(dev);
1140 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1141 const struct intel_community_context *communities;
1142 const struct intel_pad_context *pads;
1145 /* Mask all interrupts */
1146 intel_gpio_irq_init(pctrl);
1148 pads = pctrl->context.pads;
1149 for (i = 0; i < pctrl->soc->npins; i++) {
1150 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1151 void __iomem *padcfg;
1154 if (!intel_pinctrl_should_save(pctrl, desc->number))
1157 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1158 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1159 if (val != pads[i].padcfg0) {
1160 writel(pads[i].padcfg0, padcfg);
1161 dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1162 desc->number, readl(padcfg));
1165 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1166 val = readl(padcfg);
1167 if (val != pads[i].padcfg1) {
1168 writel(pads[i].padcfg1, padcfg);
1169 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1170 desc->number, readl(padcfg));
1174 communities = pctrl->context.communities;
1175 for (i = 0; i < pctrl->ncommunities; i++) {
1176 struct intel_community *community = &pctrl->communities[i];
1180 base = community->regs + community->ie_offset;
1181 for (gpp = 0; gpp < community->ngpps; gpp++) {
1182 writel(communities[i].intmask[gpp], base + gpp * 4);
1183 dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1184 readl(base + gpp * 4));
1190 EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1193 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1194 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1195 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1196 MODULE_LICENSE("GPL v2");