2 * Pinctrl GPIO driver for Intel Baytrail
3 * Copyright (c) 2012-2013, Intel Corporation.
5 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/types.h>
26 #include <linux/bitops.h>
27 #include <linux/interrupt.h>
28 #include <linux/gpio.h>
29 #include <linux/acpi.h>
30 #include <linux/platform_device.h>
31 #include <linux/seq_file.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/pinctrl/pinctrl.h>
36 /* memory mapped register offsets */
37 #define BYT_CONF0_REG 0x000
38 #define BYT_CONF1_REG 0x004
39 #define BYT_VAL_REG 0x008
40 #define BYT_DFT_REG 0x00c
41 #define BYT_INT_STAT_REG 0x800
43 /* BYT_CONF0_REG register bits */
44 #define BYT_IODEN BIT(31)
45 #define BYT_DIRECT_IRQ_EN BIT(27)
46 #define BYT_TRIG_NEG BIT(26)
47 #define BYT_TRIG_POS BIT(25)
48 #define BYT_TRIG_LVL BIT(24)
49 #define BYT_PULL_STR_SHIFT 9
50 #define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT)
51 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
52 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
53 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
54 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
55 #define BYT_PULL_ASSIGN_SHIFT 7
56 #define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT)
57 #define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
58 #define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
59 #define BYT_PIN_MUX 0x07
61 /* BYT_VAL_REG register bits */
62 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
63 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
64 #define BYT_LEVEL BIT(0)
66 #define BYT_DIR_MASK (BIT(1) | BIT(2))
67 #define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24))
69 #define BYT_NGPIO_SCORE 102
70 #define BYT_NGPIO_NCORE 28
71 #define BYT_NGPIO_SUS 44
73 #define BYT_SCORE_ACPI_UID "1"
74 #define BYT_NCORE_ACPI_UID "2"
75 #define BYT_SUS_ACPI_UID "3"
78 * Baytrail gpio controller consist of three separate sub-controllers called
79 * SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID.
81 * GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does
82 * _not_ correspond to the first gpio register at controller's gpio base.
83 * There is no logic or pattern in mapping gpio numbers to registers (pads) so
84 * each sub-controller needs to have its own mapping table
87 /* score_pins[gpio_nr] = pad_nr */
89 static unsigned const score_pins[BYT_NGPIO_SCORE] = {
90 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
91 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
92 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
93 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
94 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
95 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
96 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
97 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
98 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
99 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
103 static unsigned const ncore_pins[BYT_NGPIO_NCORE] = {
104 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
105 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
106 3, 6, 10, 13, 2, 5, 9, 7,
109 static unsigned const sus_pins[BYT_NGPIO_SUS] = {
110 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
111 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
112 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
113 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
117 static struct pinctrl_gpio_range byt_ranges[] = {
119 .name = BYT_SCORE_ACPI_UID, /* match with acpi _UID in probe */
120 .npins = BYT_NGPIO_SCORE,
124 .name = BYT_NCORE_ACPI_UID,
125 .npins = BYT_NGPIO_NCORE,
129 .name = BYT_SUS_ACPI_UID,
130 .npins = BYT_NGPIO_SUS,
138 struct gpio_chip chip;
139 struct platform_device *pdev;
141 void __iomem *reg_base;
142 struct pinctrl_gpio_range *range;
145 #define to_byt_gpio(c) container_of(c, struct byt_gpio, chip)
147 static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset,
150 struct byt_gpio *vg = to_byt_gpio(chip);
153 if (reg == BYT_INT_STAT_REG)
154 reg_offset = (offset / 32) * 4;
156 reg_offset = vg->range->pins[offset] * 16;
158 return vg->reg_base + reg_offset + reg;
161 static bool is_special_pin(struct byt_gpio *vg, unsigned offset)
163 /* SCORE pin 92-93 */
164 if (!strcmp(vg->range->name, BYT_SCORE_ACPI_UID) &&
165 offset >= 92 && offset <= 93)
169 if (!strcmp(vg->range->name, BYT_SUS_ACPI_UID) &&
170 offset >= 11 && offset <= 21)
176 static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
178 struct byt_gpio *vg = to_byt_gpio(chip);
179 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG);
184 * In most cases, func pin mux 000 means GPIO function.
185 * But, some pins may have func pin mux 001 represents
186 * GPIO function. Only allow user to export pin with
187 * func pin mux preset as GPIO function by BIOS/FW.
189 value = readl(reg) & BYT_PIN_MUX;
190 special = is_special_pin(vg, offset);
191 if ((special && value != 1) || (!special && value)) {
192 dev_err(&vg->pdev->dev,
193 "pin %u cannot be used as GPIO.\n", offset);
197 pm_runtime_get(&vg->pdev->dev);
202 static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
204 struct byt_gpio *vg = to_byt_gpio(chip);
205 void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
208 /* clear interrupt triggering */
210 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
213 pm_runtime_put(&vg->pdev->dev);
216 static int byt_irq_type(struct irq_data *d, unsigned type)
218 struct byt_gpio *vg = to_byt_gpio(irq_data_get_irq_chip_data(d));
219 u32 offset = irqd_to_hwirq(d);
222 void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
224 if (offset >= vg->chip.ngpio)
227 spin_lock_irqsave(&vg->lock, flags);
230 WARN(value & BYT_DIRECT_IRQ_EN,
231 "Bad pad config for io mode, force direct_irq_en bit clearing");
233 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
234 * are used to indicate high and low level triggering
236 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
240 case IRQ_TYPE_LEVEL_HIGH:
241 value |= BYT_TRIG_LVL;
242 case IRQ_TYPE_EDGE_RISING:
243 value |= BYT_TRIG_POS;
245 case IRQ_TYPE_LEVEL_LOW:
246 value |= BYT_TRIG_LVL;
247 case IRQ_TYPE_EDGE_FALLING:
248 value |= BYT_TRIG_NEG;
250 case IRQ_TYPE_EDGE_BOTH:
251 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
256 spin_unlock_irqrestore(&vg->lock, flags);
261 static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
263 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
264 return readl(reg) & BYT_LEVEL;
267 static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
269 struct byt_gpio *vg = to_byt_gpio(chip);
270 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
274 spin_lock_irqsave(&vg->lock, flags);
276 old_val = readl(reg);
279 writel(old_val | BYT_LEVEL, reg);
281 writel(old_val & ~BYT_LEVEL, reg);
283 spin_unlock_irqrestore(&vg->lock, flags);
286 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
288 struct byt_gpio *vg = to_byt_gpio(chip);
289 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
293 spin_lock_irqsave(&vg->lock, flags);
295 value = readl(reg) | BYT_DIR_MASK;
296 value &= ~BYT_INPUT_EN; /* active low */
299 spin_unlock_irqrestore(&vg->lock, flags);
304 static int byt_gpio_direction_output(struct gpio_chip *chip,
305 unsigned gpio, int value)
307 struct byt_gpio *vg = to_byt_gpio(chip);
308 void __iomem *conf_reg = byt_gpio_reg(chip, gpio, BYT_CONF0_REG);
309 void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG);
313 spin_lock_irqsave(&vg->lock, flags);
316 * Before making any direction modifications, do a check if gpio
317 * is set for direct IRQ. On baytrail, setting GPIO to output does
318 * not make sense, so let's at least warn the caller before they shoot
319 * themselves in the foot.
321 WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
322 "Potential Error: Setting GPIO with direct_irq_en to output");
324 reg_val = readl(reg) | BYT_DIR_MASK;
325 reg_val &= ~(BYT_OUTPUT_EN | BYT_INPUT_EN);
328 writel(reg_val | BYT_LEVEL, reg);
330 writel(reg_val & ~BYT_LEVEL, reg);
332 spin_unlock_irqrestore(&vg->lock, flags);
337 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
339 struct byt_gpio *vg = to_byt_gpio(chip);
342 u32 conf0, val, offs;
344 spin_lock_irqsave(&vg->lock, flags);
346 for (i = 0; i < vg->chip.ngpio; i++) {
347 const char *pull_str = NULL;
348 const char *pull = NULL;
350 offs = vg->range->pins[i] * 16;
351 conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
352 val = readl(vg->reg_base + offs + BYT_VAL_REG);
354 label = gpiochip_is_requested(chip, i);
356 label = "Unrequested";
358 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
359 case BYT_PULL_ASSIGN_UP:
362 case BYT_PULL_ASSIGN_DOWN:
367 switch (conf0 & BYT_PULL_STR_MASK) {
368 case BYT_PULL_STR_2K:
371 case BYT_PULL_STR_10K:
374 case BYT_PULL_STR_20K:
377 case BYT_PULL_STR_40K:
383 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
386 val & BYT_INPUT_EN ? " " : "in",
387 val & BYT_OUTPUT_EN ? " " : "out",
388 val & BYT_LEVEL ? "hi" : "lo",
389 vg->range->pins[i], offs,
391 conf0 & BYT_TRIG_NEG ? " fall" : " ",
392 conf0 & BYT_TRIG_POS ? " rise" : " ",
393 conf0 & BYT_TRIG_LVL ? " level" : " ");
395 if (pull && pull_str)
396 seq_printf(s, " %-4s %-3s", pull, pull_str);
400 if (conf0 & BYT_IODEN)
401 seq_puts(s, " open-drain");
405 spin_unlock_irqrestore(&vg->lock, flags);
408 static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
410 struct irq_data *data = irq_desc_get_irq_data(desc);
411 struct byt_gpio *vg = to_byt_gpio(irq_desc_get_handler_data(desc));
412 struct irq_chip *chip = irq_data_get_irq_chip(data);
419 /* check from GPIO controller which pin triggered the interrupt */
420 for (base = 0; base < vg->chip.ngpio; base += 32) {
422 reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
424 while ((pending = readl(reg))) {
425 pin = __ffs(pending);
427 /* Clear before handling so we can't lose an edge */
430 virq = irq_find_mapping(vg->chip.irqdomain, base + pin);
431 generic_handle_irq(virq);
433 /* In case bios or user sets triggering incorretly a pin
434 * might remain in "interrupt triggered" state.
436 if (looplimit++ > 32) {
437 dev_err(&vg->pdev->dev,
438 "Gpio %d interrupt flood, disabling\n",
441 reg = byt_gpio_reg(&vg->chip, base + pin,
444 mask &= ~(BYT_TRIG_NEG | BYT_TRIG_POS |
447 mask = readl(reg); /* flush */
455 static void byt_irq_unmask(struct irq_data *d)
459 static void byt_irq_mask(struct irq_data *d)
463 static struct irq_chip byt_irqchip = {
465 .irq_mask = byt_irq_mask,
466 .irq_unmask = byt_irq_unmask,
467 .irq_set_type = byt_irq_type,
468 .flags = IRQCHIP_SKIP_SET_WAKE,
471 static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
476 /* clear interrupt status trigger registers */
477 for (base = 0; base < vg->chip.ngpio; base += 32) {
478 reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
479 writel(0xffffffff, reg);
480 /* make sure trigger bits are cleared, if not then a pin
481 might be misconfigured in bios */
484 dev_err(&vg->pdev->dev,
485 "GPIO interrupt error, pins misconfigured\n");
489 static int byt_gpio_probe(struct platform_device *pdev)
492 struct gpio_chip *gc;
493 struct resource *mem_rc, *irq_rc;
494 struct device *dev = &pdev->dev;
495 struct acpi_device *acpi_dev;
496 struct pinctrl_gpio_range *range;
497 acpi_handle handle = ACPI_HANDLE(dev);
500 if (acpi_bus_get_device(handle, &acpi_dev))
503 vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL);
505 dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n");
509 for (range = byt_ranges; range->name; range++) {
510 if (!strcmp(acpi_dev->pnp.unique_id, range->name)) {
511 vg->chip.ngpio = range->npins;
517 if (!vg->chip.ngpio || !vg->range)
521 platform_set_drvdata(pdev, vg);
523 mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
524 vg->reg_base = devm_ioremap_resource(dev, mem_rc);
525 if (IS_ERR(vg->reg_base))
526 return PTR_ERR(vg->reg_base);
528 spin_lock_init(&vg->lock);
531 gc->label = dev_name(&pdev->dev);
532 gc->owner = THIS_MODULE;
533 gc->request = byt_gpio_request;
534 gc->free = byt_gpio_free;
535 gc->direction_input = byt_gpio_direction_input;
536 gc->direction_output = byt_gpio_direction_output;
537 gc->get = byt_gpio_get;
538 gc->set = byt_gpio_set;
539 gc->dbg_show = byt_gpio_dbg_show;
541 gc->can_sleep = false;
544 ret = gpiochip_add(gc);
546 dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
550 /* set up interrupts */
551 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
552 if (irq_rc && irq_rc->start) {
553 byt_gpio_irq_init_hw(vg);
554 ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
555 handle_simple_irq, IRQ_TYPE_NONE);
557 dev_err(dev, "failed to add irqchip\n");
562 gpiochip_set_chained_irqchip(gc, &byt_irqchip,
563 (unsigned)irq_rc->start,
564 byt_gpio_irq_handler);
567 pm_runtime_enable(dev);
572 static int byt_gpio_runtime_suspend(struct device *dev)
577 static int byt_gpio_runtime_resume(struct device *dev)
582 static const struct dev_pm_ops byt_gpio_pm_ops = {
583 .runtime_suspend = byt_gpio_runtime_suspend,
584 .runtime_resume = byt_gpio_runtime_resume,
587 static const struct acpi_device_id byt_gpio_acpi_match[] = {
592 MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
594 static int byt_gpio_remove(struct platform_device *pdev)
596 struct byt_gpio *vg = platform_get_drvdata(pdev);
598 pm_runtime_disable(&pdev->dev);
599 gpiochip_remove(&vg->chip);
604 static struct platform_driver byt_gpio_driver = {
605 .probe = byt_gpio_probe,
606 .remove = byt_gpio_remove,
609 .owner = THIS_MODULE,
610 .pm = &byt_gpio_pm_ops,
611 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
615 static int __init byt_gpio_init(void)
617 return platform_driver_register(&byt_gpio_driver);
619 subsys_initcall(byt_gpio_init);
621 static void __exit byt_gpio_exit(void)
623 platform_driver_unregister(&byt_gpio_driver);
625 module_exit(byt_gpio_exit);