2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include <linux/err.h>
13 #include <linux/init.h>
16 #include <linux/of_address.h>
17 #include <linux/pinctrl/machine.h>
18 #include <linux/pinctrl/pinconf.h>
19 #include <linux/pinctrl/pinctrl.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
24 #include "pinctrl-mxs.h"
28 struct mxs_pinctrl_data {
30 struct pinctrl_dev *pctl;
32 struct mxs_pinctrl_soc_data *soc;
35 static int mxs_get_groups_count(struct pinctrl_dev *pctldev)
37 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
39 return d->soc->ngroups;
42 static const char *mxs_get_group_name(struct pinctrl_dev *pctldev,
45 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
47 return d->soc->groups[group].name;
50 static int mxs_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
51 const unsigned **pins, unsigned *num_pins)
53 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
55 *pins = d->soc->groups[group].pins;
56 *num_pins = d->soc->groups[group].npins;
61 static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
64 seq_printf(s, " %s", dev_name(pctldev->dev));
67 static int mxs_dt_node_to_map(struct pinctrl_dev *pctldev,
68 struct device_node *np,
69 struct pinctrl_map **map, unsigned *num_maps)
71 struct pinctrl_map *new_map;
74 unsigned long config = 0;
75 unsigned long *pconfig;
76 int length = strlen(np->name) + SUFFIX_LEN;
81 /* Check for pin config node which has no 'reg' property */
82 if (of_property_read_u32(np, "reg", ®))
85 ret = of_property_read_u32(np, "fsl,drive-strength", &val);
87 config = val | MA_PRESENT;
88 ret = of_property_read_u32(np, "fsl,voltage", &val);
90 config |= val << VOL_SHIFT | VOL_PRESENT;
91 ret = of_property_read_u32(np, "fsl,pull-up", &val);
93 config |= val << PULL_SHIFT | PULL_PRESENT;
95 /* Check for group node which has both mux and config settings */
96 if (!purecfg && config)
99 new_map = kzalloc(sizeof(*new_map) * new_num, GFP_KERNEL);
104 new_map[i].type = PIN_MAP_TYPE_MUX_GROUP;
105 new_map[i].data.mux.function = np->name;
107 /* Compose group name */
108 group = kzalloc(length, GFP_KERNEL);
113 snprintf(group, length, "%s.%d", np->name, reg);
114 new_map[i].data.mux.group = group;
119 pconfig = kmemdup(&config, sizeof(config), GFP_KERNEL);
125 new_map[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
126 new_map[i].data.configs.group_or_pin = purecfg ? np->name :
128 new_map[i].data.configs.configs = pconfig;
129 new_map[i].data.configs.num_configs = 1;
145 static void mxs_dt_free_map(struct pinctrl_dev *pctldev,
146 struct pinctrl_map *map, unsigned num_maps)
150 for (i = 0; i < num_maps; i++) {
151 if (map[i].type == PIN_MAP_TYPE_MUX_GROUP)
152 kfree(map[i].data.mux.group);
153 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
154 kfree(map[i].data.configs.configs);
160 static const struct pinctrl_ops mxs_pinctrl_ops = {
161 .get_groups_count = mxs_get_groups_count,
162 .get_group_name = mxs_get_group_name,
163 .get_group_pins = mxs_get_group_pins,
164 .pin_dbg_show = mxs_pin_dbg_show,
165 .dt_node_to_map = mxs_dt_node_to_map,
166 .dt_free_map = mxs_dt_free_map,
169 static int mxs_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
171 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
173 return d->soc->nfunctions;
176 static const char *mxs_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
179 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
181 return d->soc->functions[function].name;
184 static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
186 const char * const **groups,
187 unsigned * const num_groups)
189 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
191 *groups = d->soc->functions[group].groups;
192 *num_groups = d->soc->functions[group].ngroups;
197 static void mxs_pinctrl_rmwl(u32 value, u32 mask, u8 shift, void __iomem *reg)
202 tmp &= ~(mask << shift);
203 tmp |= value << shift;
207 static int mxs_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
210 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
211 struct mxs_group *g = &d->soc->groups[group];
217 for (i = 0; i < g->npins; i++) {
218 bank = PINID_TO_BANK(g->pins[i]);
219 pin = PINID_TO_PIN(g->pins[i]);
220 reg = d->base + d->soc->regs->muxsel;
221 reg += bank * 0x20 + pin / 16 * 0x10;
222 shift = pin % 16 * 2;
224 mxs_pinctrl_rmwl(g->muxsel[i], 0x3, shift, reg);
230 static const struct pinmux_ops mxs_pinmux_ops = {
231 .get_functions_count = mxs_pinctrl_get_funcs_count,
232 .get_function_name = mxs_pinctrl_get_func_name,
233 .get_function_groups = mxs_pinctrl_get_func_groups,
234 .set_mux = mxs_pinctrl_set_mux,
237 static int mxs_pinconf_get(struct pinctrl_dev *pctldev,
238 unsigned pin, unsigned long *config)
243 static int mxs_pinconf_set(struct pinctrl_dev *pctldev,
244 unsigned pin, unsigned long *configs,
245 unsigned num_configs)
250 static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev,
251 unsigned group, unsigned long *config)
253 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
255 *config = d->soc->groups[group].config;
260 static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev,
261 unsigned group, unsigned long *configs,
262 unsigned num_configs)
264 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
265 struct mxs_group *g = &d->soc->groups[group];
267 u8 ma, vol, pull, bank, shift;
271 unsigned long config;
273 for (n = 0; n < num_configs; n++) {
276 ma = CONFIG_TO_MA(config);
277 vol = CONFIG_TO_VOL(config);
278 pull = CONFIG_TO_PULL(config);
280 for (i = 0; i < g->npins; i++) {
281 bank = PINID_TO_BANK(g->pins[i]);
282 pin = PINID_TO_PIN(g->pins[i]);
285 reg = d->base + d->soc->regs->drive;
286 reg += bank * 0x40 + pin / 8 * 0x10;
289 if (config & MA_PRESENT) {
291 mxs_pinctrl_rmwl(ma, 0x3, shift, reg);
295 if (config & VOL_PRESENT) {
296 shift = pin % 8 * 4 + 2;
298 writel(1 << shift, reg + SET);
300 writel(1 << shift, reg + CLR);
304 if (config & PULL_PRESENT) {
305 reg = d->base + d->soc->regs->pull;
309 writel(1 << shift, reg + SET);
311 writel(1 << shift, reg + CLR);
315 /* cache the config value for mxs_pinconf_group_get() */
318 } /* for each config */
323 static void mxs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
324 struct seq_file *s, unsigned pin)
329 static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
330 struct seq_file *s, unsigned group)
332 unsigned long config;
334 if (!mxs_pinconf_group_get(pctldev, group, &config))
335 seq_printf(s, "0x%lx", config);
338 static const struct pinconf_ops mxs_pinconf_ops = {
339 .pin_config_get = mxs_pinconf_get,
340 .pin_config_set = mxs_pinconf_set,
341 .pin_config_group_get = mxs_pinconf_group_get,
342 .pin_config_group_set = mxs_pinconf_group_set,
343 .pin_config_dbg_show = mxs_pinconf_dbg_show,
344 .pin_config_group_dbg_show = mxs_pinconf_group_dbg_show,
347 static struct pinctrl_desc mxs_pinctrl_desc = {
348 .pctlops = &mxs_pinctrl_ops,
349 .pmxops = &mxs_pinmux_ops,
350 .confops = &mxs_pinconf_ops,
351 .owner = THIS_MODULE,
354 static int mxs_pinctrl_parse_group(struct platform_device *pdev,
355 struct device_node *np, int idx,
356 const char **out_name)
358 struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
359 struct mxs_group *g = &d->soc->groups[idx];
360 struct property *prop;
361 const char *propname = "fsl,pinmux-ids";
363 int length = strlen(np->name) + SUFFIX_LEN;
366 group = devm_kzalloc(&pdev->dev, length, GFP_KERNEL);
369 if (of_property_read_u32(np, "reg", &val))
370 snprintf(group, length, "%s", np->name);
372 snprintf(group, length, "%s.%d", np->name, val);
375 prop = of_find_property(np, propname, &length);
378 g->npins = length / sizeof(u32);
380 g->pins = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->pins),
385 g->muxsel = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->muxsel),
390 of_property_read_u32_array(np, propname, g->pins, g->npins);
391 for (i = 0; i < g->npins; i++) {
392 g->muxsel[i] = MUXID_TO_MUXSEL(g->pins[i]);
393 g->pins[i] = MUXID_TO_PINID(g->pins[i]);
402 static int mxs_pinctrl_probe_dt(struct platform_device *pdev,
403 struct mxs_pinctrl_data *d)
405 struct mxs_pinctrl_soc_data *soc = d->soc;
406 struct device_node *np = pdev->dev.of_node;
407 struct device_node *child;
408 struct mxs_function *f;
409 const char *gpio_compat = "fsl,mxs-gpio";
410 const char *fn, *fnull = "";
411 int i = 0, idxf = 0, idxg = 0;
415 child = of_get_next_child(np, NULL);
417 dev_err(&pdev->dev, "no group is defined\n");
421 /* Count total functions and groups */
423 for_each_child_of_node(np, child) {
424 if (of_device_is_compatible(child, gpio_compat))
427 /* Skip pure pinconf node */
428 if (of_property_read_u32(child, "reg", &val))
430 if (strcmp(fn, child->name)) {
436 soc->functions = devm_kzalloc(&pdev->dev, soc->nfunctions *
437 sizeof(*soc->functions), GFP_KERNEL);
441 soc->groups = devm_kzalloc(&pdev->dev, soc->ngroups *
442 sizeof(*soc->groups), GFP_KERNEL);
446 /* Count groups for each function */
448 f = &soc->functions[idxf];
449 for_each_child_of_node(np, child) {
450 if (of_device_is_compatible(child, gpio_compat))
452 if (of_property_read_u32(child, "reg", &val))
454 if (strcmp(fn, child->name)) {
455 struct device_node *child2;
458 * This reference is dropped by
459 * of_get_next_child(np, * child)
464 * The logic parsing the functions from dt currently
465 * doesn't handle if functions with the same name are
466 * not grouped together. Only the first contiguous
467 * cluster is usable for each function name. This is a
468 * bug that is not trivial to fix, but at least warn
471 for (child2 = of_get_next_child(np, child);
473 child2 = of_get_next_child(np, child2)) {
474 if (!strcmp(child2->name, fn))
476 "function nodes must be grouped by name (failed for: %s)",
480 f = &soc->functions[idxf++];
481 f->name = fn = child->name;
486 /* Get groups for each function */
489 for_each_child_of_node(np, child) {
490 if (of_device_is_compatible(child, gpio_compat))
492 if (of_property_read_u32(child, "reg", &val)) {
493 ret = mxs_pinctrl_parse_group(pdev, child,
500 if (strcmp(fn, child->name)) {
501 f = &soc->functions[idxf++];
502 f->groups = devm_kzalloc(&pdev->dev, f->ngroups *
510 ret = mxs_pinctrl_parse_group(pdev, child, idxg++,
519 int mxs_pinctrl_probe(struct platform_device *pdev,
520 struct mxs_pinctrl_soc_data *soc)
522 struct device_node *np = pdev->dev.of_node;
523 struct mxs_pinctrl_data *d;
526 d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL);
533 d->base = of_iomap(np, 0);
535 return -EADDRNOTAVAIL;
537 mxs_pinctrl_desc.pins = d->soc->pins;
538 mxs_pinctrl_desc.npins = d->soc->npins;
539 mxs_pinctrl_desc.name = dev_name(&pdev->dev);
541 platform_set_drvdata(pdev, d);
543 ret = mxs_pinctrl_probe_dt(pdev, d);
545 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
549 d->pctl = pinctrl_register(&mxs_pinctrl_desc, &pdev->dev, d);
550 if (IS_ERR(d->pctl)) {
551 dev_err(&pdev->dev, "Couldn't register MXS pinctrl driver\n");
552 ret = PTR_ERR(d->pctl);
562 EXPORT_SYMBOL_GPL(mxs_pinctrl_probe);