1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2017 Broadcom
7 * This file contains the Broadcom Iproc GPIO driver that supports 3
8 * GPIO controllers on Iproc including the ASIU GPIO controller, the
9 * chipCommonG GPIO controller, and the always-on GPIO controller. Basic
10 * PINCONF such as bias pull up/down, and drive strength are also supported
13 * It provides the functionality where pins from the GPIO can be
14 * individually muxed to GPIO function, if individual pad
15 * configuration is supported, through the interaction with respective
16 * SoCs IOMUX controller.
19 #include <linux/kernel.h>
20 #include <linux/slab.h>
21 #include <linux/interrupt.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/ioport.h>
25 #include <linux/of_device.h>
26 #include <linux/of_irq.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinconf.h>
29 #include <linux/pinctrl/pinconf-generic.h>
31 #include "../pinctrl-utils.h"
33 #define IPROC_GPIO_DATA_IN_OFFSET 0x00
34 #define IPROC_GPIO_DATA_OUT_OFFSET 0x04
35 #define IPROC_GPIO_OUT_EN_OFFSET 0x08
36 #define IPROC_GPIO_INT_TYPE_OFFSET 0x0c
37 #define IPROC_GPIO_INT_DE_OFFSET 0x10
38 #define IPROC_GPIO_INT_EDGE_OFFSET 0x14
39 #define IPROC_GPIO_INT_MSK_OFFSET 0x18
40 #define IPROC_GPIO_INT_STAT_OFFSET 0x1c
41 #define IPROC_GPIO_INT_MSTAT_OFFSET 0x20
42 #define IPROC_GPIO_INT_CLR_OFFSET 0x24
43 #define IPROC_GPIO_PAD_RES_OFFSET 0x34
44 #define IPROC_GPIO_RES_EN_OFFSET 0x38
46 /* drive strength control for ASIU GPIO */
47 #define IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58
49 /* pinconf for CCM GPIO */
50 #define IPROC_GPIO_PULL_DN_OFFSET 0x10
51 #define IPROC_GPIO_PULL_UP_OFFSET 0x14
53 /* pinconf for CRMU(aon) GPIO and CCM GPIO*/
54 #define IPROC_GPIO_DRV_CTRL_OFFSET 0x00
56 #define GPIO_BANK_SIZE 0x200
57 #define NGPIOS_PER_BANK 32
58 #define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK)
60 #define IPROC_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg))
61 #define IPROC_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK)
63 #define GPIO_DRV_STRENGTH_BIT_SHIFT 20
64 #define GPIO_DRV_STRENGTH_BITS 3
65 #define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1)
67 enum iproc_pinconf_param {
68 IPROC_PINCONF_DRIVE_STRENGTH = 0,
69 IPROC_PINCONF_BIAS_DISABLE,
70 IPROC_PINCONF_BIAS_PULL_UP,
71 IPROC_PINCONF_BIAS_PULL_DOWN,
75 enum iproc_pinconf_ctrl_type {
84 * @dev: pointer to device
85 * @base: I/O register base for Iproc GPIO controller
86 * @io_ctrl: I/O register base for certain type of Iproc GPIO controller that
87 * has the PINCONF support implemented outside of the GPIO block
88 * @lock: lock to protect access to I/O registers
90 * @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs
91 * @pinmux_is_supported: flag to indicate this GPIO controller contains pins
92 * that can be individually muxed to GPIO
93 * @pinconf_disable: contains a list of PINCONF parameters that need to be
95 * @nr_pinconf_disable: total number of PINCONF parameters that need to be
97 * @pctl: pointer to pinctrl_dev
98 * @pctldesc: pinctrl descriptor
104 void __iomem *io_ctrl;
105 enum iproc_pinconf_ctrl_type io_ctrl_type;
109 struct irq_chip irqchip;
113 bool pinmux_is_supported;
115 enum pin_config_param *pinconf_disable;
116 unsigned int nr_pinconf_disable;
118 struct pinctrl_dev *pctl;
119 struct pinctrl_desc pctldesc;
123 * Mapping from PINCONF pins to GPIO pins is 1-to-1
125 static inline unsigned iproc_pin_to_gpio(unsigned pin)
131 * iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
132 * Iproc GPIO register
134 * @chip: Iproc GPIO device
135 * @reg: register offset
139 static inline void iproc_set_bit(struct iproc_gpio *chip, unsigned int reg,
140 unsigned gpio, bool set)
142 unsigned int offset = IPROC_GPIO_REG(gpio, reg);
143 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
146 val = readl(chip->base + offset);
151 writel(val, chip->base + offset);
154 static inline bool iproc_get_bit(struct iproc_gpio *chip, unsigned int reg,
157 unsigned int offset = IPROC_GPIO_REG(gpio, reg);
158 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
160 return !!(readl(chip->base + offset) & BIT(shift));
163 static void iproc_gpio_irq_handler(struct irq_desc *desc)
165 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
166 struct iproc_gpio *chip = gpiochip_get_data(gc);
167 struct irq_chip *irq_chip = irq_desc_get_chip(desc);
170 chained_irq_enter(irq_chip, desc);
172 /* go through the entire GPIO banks and handle all interrupts */
173 for (i = 0; i < chip->num_banks; i++) {
174 unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) +
175 IPROC_GPIO_INT_MSTAT_OFFSET);
177 for_each_set_bit(bit, &val, NGPIOS_PER_BANK) {
178 unsigned pin = NGPIOS_PER_BANK * i + bit;
181 * Clear the interrupt before invoking the
182 * handler, so we do not leave any window
184 writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) +
185 IPROC_GPIO_INT_CLR_OFFSET);
187 generic_handle_domain_irq(gc->irq.domain, pin);
191 chained_irq_exit(irq_chip, desc);
195 static void iproc_gpio_irq_ack(struct irq_data *d)
197 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
198 struct iproc_gpio *chip = gpiochip_get_data(gc);
199 unsigned gpio = d->hwirq;
200 unsigned int offset = IPROC_GPIO_REG(gpio,
201 IPROC_GPIO_INT_CLR_OFFSET);
202 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
203 u32 val = BIT(shift);
205 writel(val, chip->base + offset);
209 * iproc_gpio_irq_set_mask - mask/unmask a GPIO interrupt
212 * @unmask: mask/unmask GPIO interrupt
214 static void iproc_gpio_irq_set_mask(struct irq_data *d, bool unmask)
216 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
217 struct iproc_gpio *chip = gpiochip_get_data(gc);
218 unsigned gpio = d->hwirq;
220 iproc_set_bit(chip, IPROC_GPIO_INT_MSK_OFFSET, gpio, unmask);
223 static void iproc_gpio_irq_mask(struct irq_data *d)
225 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
226 struct iproc_gpio *chip = gpiochip_get_data(gc);
229 raw_spin_lock_irqsave(&chip->lock, flags);
230 iproc_gpio_irq_set_mask(d, false);
231 raw_spin_unlock_irqrestore(&chip->lock, flags);
234 static void iproc_gpio_irq_unmask(struct irq_data *d)
236 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
237 struct iproc_gpio *chip = gpiochip_get_data(gc);
240 raw_spin_lock_irqsave(&chip->lock, flags);
241 iproc_gpio_irq_set_mask(d, true);
242 raw_spin_unlock_irqrestore(&chip->lock, flags);
245 static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type)
247 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
248 struct iproc_gpio *chip = gpiochip_get_data(gc);
249 unsigned gpio = d->hwirq;
250 bool level_triggered = false;
251 bool dual_edge = false;
252 bool rising_or_high = false;
255 switch (type & IRQ_TYPE_SENSE_MASK) {
256 case IRQ_TYPE_EDGE_RISING:
257 rising_or_high = true;
260 case IRQ_TYPE_EDGE_FALLING:
263 case IRQ_TYPE_EDGE_BOTH:
267 case IRQ_TYPE_LEVEL_HIGH:
268 level_triggered = true;
269 rising_or_high = true;
272 case IRQ_TYPE_LEVEL_LOW:
273 level_triggered = true;
277 dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
282 raw_spin_lock_irqsave(&chip->lock, flags);
283 iproc_set_bit(chip, IPROC_GPIO_INT_TYPE_OFFSET, gpio,
285 iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge);
286 iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio,
289 if (type & IRQ_TYPE_EDGE_BOTH)
290 irq_set_handler_locked(d, handle_edge_irq);
292 irq_set_handler_locked(d, handle_level_irq);
294 raw_spin_unlock_irqrestore(&chip->lock, flags);
297 "gpio:%u level_triggered:%d dual_edge:%d rising_or_high:%d\n",
298 gpio, level_triggered, dual_edge, rising_or_high);
304 * Request the Iproc IOMUX pinmux controller to mux individual pins to GPIO
306 static int iproc_gpio_request(struct gpio_chip *gc, unsigned offset)
308 struct iproc_gpio *chip = gpiochip_get_data(gc);
309 unsigned gpio = gc->base + offset;
311 /* not all Iproc GPIO pins can be muxed individually */
312 if (!chip->pinmux_is_supported)
315 return pinctrl_gpio_request(gpio);
318 static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset)
320 struct iproc_gpio *chip = gpiochip_get_data(gc);
321 unsigned gpio = gc->base + offset;
323 if (!chip->pinmux_is_supported)
326 pinctrl_gpio_free(gpio);
329 static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
331 struct iproc_gpio *chip = gpiochip_get_data(gc);
334 raw_spin_lock_irqsave(&chip->lock, flags);
335 iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, false);
336 raw_spin_unlock_irqrestore(&chip->lock, flags);
338 dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
343 static int iproc_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
346 struct iproc_gpio *chip = gpiochip_get_data(gc);
349 raw_spin_lock_irqsave(&chip->lock, flags);
350 iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, true);
351 iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
352 raw_spin_unlock_irqrestore(&chip->lock, flags);
354 dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
359 static int iproc_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
361 struct iproc_gpio *chip = gpiochip_get_data(gc);
362 unsigned int offset = IPROC_GPIO_REG(gpio, IPROC_GPIO_OUT_EN_OFFSET);
363 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
365 if (readl(chip->base + offset) & BIT(shift))
366 return GPIO_LINE_DIRECTION_OUT;
368 return GPIO_LINE_DIRECTION_IN;
371 static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
373 struct iproc_gpio *chip = gpiochip_get_data(gc);
376 raw_spin_lock_irqsave(&chip->lock, flags);
377 iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
378 raw_spin_unlock_irqrestore(&chip->lock, flags);
380 dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
383 static int iproc_gpio_get(struct gpio_chip *gc, unsigned gpio)
385 struct iproc_gpio *chip = gpiochip_get_data(gc);
386 unsigned int offset = IPROC_GPIO_REG(gpio,
387 IPROC_GPIO_DATA_IN_OFFSET);
388 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
390 return !!(readl(chip->base + offset) & BIT(shift));
394 * Mapping of the iProc PINCONF parameters to the generic pin configuration
397 static const enum pin_config_param iproc_pinconf_disable_map[] = {
398 [IPROC_PINCONF_DRIVE_STRENGTH] = PIN_CONFIG_DRIVE_STRENGTH,
399 [IPROC_PINCONF_BIAS_DISABLE] = PIN_CONFIG_BIAS_DISABLE,
400 [IPROC_PINCONF_BIAS_PULL_UP] = PIN_CONFIG_BIAS_PULL_UP,
401 [IPROC_PINCONF_BIAS_PULL_DOWN] = PIN_CONFIG_BIAS_PULL_DOWN,
404 static bool iproc_pinconf_param_is_disabled(struct iproc_gpio *chip,
405 enum pin_config_param param)
409 if (!chip->nr_pinconf_disable)
412 for (i = 0; i < chip->nr_pinconf_disable; i++)
413 if (chip->pinconf_disable[i] == param)
419 static int iproc_pinconf_disable_map_create(struct iproc_gpio *chip,
420 unsigned long disable_mask)
422 unsigned int map_size = ARRAY_SIZE(iproc_pinconf_disable_map);
423 unsigned int bit, nbits = 0;
425 /* figure out total number of PINCONF parameters to disable */
426 for_each_set_bit(bit, &disable_mask, map_size)
433 * Allocate an array to store PINCONF parameters that need to be
436 chip->pinconf_disable = devm_kcalloc(chip->dev, nbits,
437 sizeof(*chip->pinconf_disable),
439 if (!chip->pinconf_disable)
442 chip->nr_pinconf_disable = nbits;
444 /* now store these parameters */
446 for_each_set_bit(bit, &disable_mask, map_size)
447 chip->pinconf_disable[nbits++] = iproc_pinconf_disable_map[bit];
452 static int iproc_get_groups_count(struct pinctrl_dev *pctldev)
458 * Only one group: "gpio_grp", since this local pinctrl device only performs
459 * GPIO specific PINCONF configurations
461 static const char *iproc_get_group_name(struct pinctrl_dev *pctldev,
467 static const struct pinctrl_ops iproc_pctrl_ops = {
468 .get_groups_count = iproc_get_groups_count,
469 .get_group_name = iproc_get_group_name,
470 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
471 .dt_free_map = pinctrl_utils_free_map,
474 static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio,
475 bool disable, bool pull_up)
482 raw_spin_lock_irqsave(&chip->lock, flags);
483 if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
484 base = chip->io_ctrl;
485 shift = IPROC_GPIO_SHIFT(gpio);
487 val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET);
488 val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET);
490 /* no pull-up or pull-down */
491 val_1 &= ~BIT(shift);
492 val_2 &= ~BIT(shift);
493 } else if (pull_up) {
495 val_2 &= ~BIT(shift);
497 val_1 &= ~BIT(shift);
500 writel(val_1, base + IPROC_GPIO_PULL_UP_OFFSET);
501 writel(val_2, base + IPROC_GPIO_PULL_DN_OFFSET);
504 iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
507 iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio,
509 iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
514 raw_spin_unlock_irqrestore(&chip->lock, flags);
515 dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up);
520 static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio,
521 bool *disable, bool *pull_up)
528 raw_spin_lock_irqsave(&chip->lock, flags);
529 if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
530 base = chip->io_ctrl;
531 shift = IPROC_GPIO_SHIFT(gpio);
533 val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET) & BIT(shift);
534 val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET) & BIT(shift);
536 *pull_up = val_1 ? true : false;
537 *disable = (val_1 | val_2) ? false : true;
540 *disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio);
541 *pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio);
543 raw_spin_unlock_irqrestore(&chip->lock, flags);
546 #define DRV_STRENGTH_OFFSET(gpio, bit, type) ((type) == IOCTRL_TYPE_AON ? \
547 ((2 - (bit)) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
548 ((type) == IOCTRL_TYPE_CDRU) ? \
549 ((bit) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
550 ((bit) * 4 + IPROC_GPIO_REG(gpio, IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET)))
552 static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio,
556 unsigned int i, offset, shift;
560 /* make sure drive strength is supported */
561 if (strength < 2 || strength > 16 || (strength % 2))
565 base = chip->io_ctrl;
570 shift = IPROC_GPIO_SHIFT(gpio);
572 dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
575 raw_spin_lock_irqsave(&chip->lock, flags);
576 strength = (strength / 2) - 1;
577 for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
578 offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
579 val = readl(base + offset);
581 val |= ((strength >> i) & 0x1) << shift;
582 writel(val, base + offset);
584 raw_spin_unlock_irqrestore(&chip->lock, flags);
589 static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio,
593 unsigned int i, offset, shift;
598 base = chip->io_ctrl;
603 shift = IPROC_GPIO_SHIFT(gpio);
605 raw_spin_lock_irqsave(&chip->lock, flags);
607 for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
608 offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
609 val = readl(base + offset) & BIT(shift);
611 *strength += (val << i);
615 *strength = (*strength + 1) * 2;
616 raw_spin_unlock_irqrestore(&chip->lock, flags);
621 static int iproc_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
622 unsigned long *config)
624 struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
625 enum pin_config_param param = pinconf_to_config_param(*config);
626 unsigned gpio = iproc_pin_to_gpio(pin);
628 bool disable, pull_up;
631 if (iproc_pinconf_param_is_disabled(chip, param))
635 case PIN_CONFIG_BIAS_DISABLE:
636 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
642 case PIN_CONFIG_BIAS_PULL_UP:
643 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
644 if (!disable && pull_up)
649 case PIN_CONFIG_BIAS_PULL_DOWN:
650 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
651 if (!disable && !pull_up)
656 case PIN_CONFIG_DRIVE_STRENGTH:
657 ret = iproc_gpio_get_strength(chip, gpio, &arg);
660 *config = pinconf_to_config_packed(param, arg);
671 static int iproc_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
672 unsigned long *configs, unsigned num_configs)
674 struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
675 enum pin_config_param param;
677 unsigned i, gpio = iproc_pin_to_gpio(pin);
680 for (i = 0; i < num_configs; i++) {
681 param = pinconf_to_config_param(configs[i]);
683 if (iproc_pinconf_param_is_disabled(chip, param))
686 arg = pinconf_to_config_argument(configs[i]);
689 case PIN_CONFIG_BIAS_DISABLE:
690 ret = iproc_gpio_set_pull(chip, gpio, true, false);
695 case PIN_CONFIG_BIAS_PULL_UP:
696 ret = iproc_gpio_set_pull(chip, gpio, false, true);
701 case PIN_CONFIG_BIAS_PULL_DOWN:
702 ret = iproc_gpio_set_pull(chip, gpio, false, false);
707 case PIN_CONFIG_DRIVE_STRENGTH:
708 ret = iproc_gpio_set_strength(chip, gpio, arg);
714 dev_err(chip->dev, "invalid configuration\n");
717 } /* for each config */
723 static const struct pinconf_ops iproc_pconf_ops = {
725 .pin_config_get = iproc_pin_config_get,
726 .pin_config_set = iproc_pin_config_set,
730 * Iproc GPIO controller supports some PINCONF related configurations such as
731 * pull up, pull down, and drive strength, when the pin is configured to GPIO
733 * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
736 static int iproc_gpio_register_pinconf(struct iproc_gpio *chip)
738 struct pinctrl_desc *pctldesc = &chip->pctldesc;
739 struct pinctrl_pin_desc *pins;
740 struct gpio_chip *gc = &chip->gc;
743 pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
747 for (i = 0; i < gc->ngpio; i++) {
749 pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
755 pctldesc->name = dev_name(chip->dev);
756 pctldesc->pctlops = &iproc_pctrl_ops;
757 pctldesc->pins = pins;
758 pctldesc->npins = gc->ngpio;
759 pctldesc->confops = &iproc_pconf_ops;
761 chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip);
762 if (IS_ERR(chip->pctl)) {
763 dev_err(chip->dev, "unable to register pinctrl device\n");
764 return PTR_ERR(chip->pctl);
770 static const struct of_device_id iproc_gpio_of_match[] = {
771 { .compatible = "brcm,iproc-gpio" },
772 { .compatible = "brcm,cygnus-ccm-gpio" },
773 { .compatible = "brcm,cygnus-asiu-gpio" },
774 { .compatible = "brcm,cygnus-crmu-gpio" },
775 { .compatible = "brcm,iproc-nsp-gpio" },
776 { .compatible = "brcm,iproc-stingray-gpio" },
780 static int iproc_gpio_probe(struct platform_device *pdev)
782 struct device *dev = &pdev->dev;
783 struct resource *res;
784 struct iproc_gpio *chip;
785 struct gpio_chip *gc;
786 u32 ngpios, pinconf_disable_mask = 0;
788 bool no_pinconf = false;
789 enum iproc_pinconf_ctrl_type io_ctrl_type = IOCTRL_TYPE_INVALID;
791 /* NSP does not support drive strength config */
792 if (of_device_is_compatible(dev->of_node, "brcm,iproc-nsp-gpio"))
793 pinconf_disable_mask = BIT(IPROC_PINCONF_DRIVE_STRENGTH);
794 /* Stingray does not support pinconf in this controller */
795 else if (of_device_is_compatible(dev->of_node,
796 "brcm,iproc-stingray-gpio"))
799 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
804 platform_set_drvdata(pdev, chip);
806 chip->base = devm_platform_ioremap_resource(pdev, 0);
807 if (IS_ERR(chip->base)) {
808 dev_err(dev, "unable to map I/O memory\n");
809 return PTR_ERR(chip->base);
812 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
814 chip->io_ctrl = devm_ioremap_resource(dev, res);
815 if (IS_ERR(chip->io_ctrl))
816 return PTR_ERR(chip->io_ctrl);
817 if (of_device_is_compatible(dev->of_node,
818 "brcm,cygnus-ccm-gpio"))
819 io_ctrl_type = IOCTRL_TYPE_CDRU;
821 io_ctrl_type = IOCTRL_TYPE_AON;
824 chip->io_ctrl_type = io_ctrl_type;
826 if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) {
827 dev_err(&pdev->dev, "missing ngpios DT property\n");
831 raw_spin_lock_init(&chip->lock);
836 chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK;
837 gc->label = dev_name(dev);
839 gc->request = iproc_gpio_request;
840 gc->free = iproc_gpio_free;
841 gc->direction_input = iproc_gpio_direction_input;
842 gc->direction_output = iproc_gpio_direction_output;
843 gc->get_direction = iproc_gpio_get_direction;
844 gc->set = iproc_gpio_set;
845 gc->get = iproc_gpio_get;
847 chip->pinmux_is_supported = of_property_read_bool(dev->of_node,
850 /* optional GPIO interrupt support */
851 irq = platform_get_irq_optional(pdev, 0);
853 struct irq_chip *irqc;
854 struct gpio_irq_chip *girq;
856 irqc = &chip->irqchip;
857 irqc->name = dev_name(dev);
858 irqc->irq_ack = iproc_gpio_irq_ack;
859 irqc->irq_mask = iproc_gpio_irq_mask;
860 irqc->irq_unmask = iproc_gpio_irq_unmask;
861 irqc->irq_set_type = iproc_gpio_irq_set_type;
862 irqc->irq_enable = iproc_gpio_irq_unmask;
863 irqc->irq_disable = iproc_gpio_irq_mask;
867 girq->parent_handler = iproc_gpio_irq_handler;
868 girq->num_parents = 1;
869 girq->parents = devm_kcalloc(dev, 1,
870 sizeof(*girq->parents),
874 girq->parents[0] = irq;
875 girq->default_type = IRQ_TYPE_NONE;
876 girq->handler = handle_bad_irq;
879 ret = gpiochip_add_data(gc, chip);
881 dev_err(dev, "unable to add GPIO chip\n");
886 ret = iproc_gpio_register_pinconf(chip);
888 dev_err(dev, "unable to register pinconf\n");
889 goto err_rm_gpiochip;
892 if (pinconf_disable_mask) {
893 ret = iproc_pinconf_disable_map_create(chip,
894 pinconf_disable_mask);
897 "unable to create pinconf disable map\n");
898 goto err_rm_gpiochip;
911 static struct platform_driver iproc_gpio_driver = {
913 .name = "iproc-gpio",
914 .of_match_table = iproc_gpio_of_match,
916 .probe = iproc_gpio_probe,
919 static int __init iproc_gpio_init(void)
921 return platform_driver_register(&iproc_gpio_driver);
923 arch_initcall_sync(iproc_gpio_init);