1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
5 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
7 * This driver is inspired by:
8 * pinctrl-nomadik.c, please see original file for copyright information
9 * pinctrl-tegra.c, please see original file for copyright information
12 #include <linux/bitmap.h>
13 #include <linux/bug.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/err.h>
17 #include <linux/gpio/driver.h>
19 #include <linux/irq.h>
20 #include <linux/irqdesc.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/module.h>
24 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/pinctrl/machine.h>
29 #include <linux/pinctrl/pinconf.h>
30 #include <linux/pinctrl/pinctrl.h>
31 #include <linux/pinctrl/pinmux.h>
32 #include <linux/pinctrl/pinconf-generic.h>
33 #include <linux/platform_device.h>
34 #include <linux/seq_file.h>
35 #include <linux/slab.h>
36 #include <linux/spinlock.h>
37 #include <linux/types.h>
38 #include <dt-bindings/pinctrl/bcm2835.h>
40 #define MODULE_NAME "pinctrl-bcm2835"
41 #define BCM2835_NUM_GPIOS 54
42 #define BCM2711_NUM_GPIOS 58
43 #define BCM2835_NUM_BANKS 2
44 #define BCM2835_NUM_IRQS 3
46 /* GPIO register offsets */
47 #define GPFSEL0 0x0 /* Function Select */
48 #define GPSET0 0x1c /* Pin Output Set */
49 #define GPCLR0 0x28 /* Pin Output Clear */
50 #define GPLEV0 0x34 /* Pin Level */
51 #define GPEDS0 0x40 /* Pin Event Detect Status */
52 #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */
53 #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */
54 #define GPHEN0 0x64 /* Pin High Detect Enable */
55 #define GPLEN0 0x70 /* Pin Low Detect Enable */
56 #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */
57 #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
58 #define GPPUD 0x94 /* Pin Pull-up/down Enable */
59 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
60 #define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */
62 #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
63 #define FSEL_SHIFT(p) (((p) % 10) * 3)
64 #define GPIO_REG_OFFSET(p) ((p) / 32)
65 #define GPIO_REG_SHIFT(p) ((p) % 32)
67 #define PUD_2711_MASK 0x3
68 #define PUD_2711_REG_OFFSET(p) ((p) / 16)
69 #define PUD_2711_REG_SHIFT(p) (((p) % 16) * 2)
71 /* argument: bcm2835_pinconf_pull */
72 #define BCM2835_PINCONF_PARAM_PULL (PIN_CONFIG_END + 1)
74 #define BCM2711_PULL_NONE 0x0
75 #define BCM2711_PULL_UP 0x1
76 #define BCM2711_PULL_DOWN 0x2
78 struct bcm2835_pinctrl {
83 /* note: locking assumes each bank will have its own unsigned long */
84 unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
85 unsigned int irq_type[BCM2711_NUM_GPIOS];
87 struct pinctrl_dev *pctl_dev;
88 struct gpio_chip gpio_chip;
89 struct pinctrl_desc pctl_desc;
90 struct pinctrl_gpio_range gpio_range;
92 raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
95 /* pins are just named GPIO0..GPIO53 */
96 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
97 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
108 BCM2835_GPIO_PIN(10),
109 BCM2835_GPIO_PIN(11),
110 BCM2835_GPIO_PIN(12),
111 BCM2835_GPIO_PIN(13),
112 BCM2835_GPIO_PIN(14),
113 BCM2835_GPIO_PIN(15),
114 BCM2835_GPIO_PIN(16),
115 BCM2835_GPIO_PIN(17),
116 BCM2835_GPIO_PIN(18),
117 BCM2835_GPIO_PIN(19),
118 BCM2835_GPIO_PIN(20),
119 BCM2835_GPIO_PIN(21),
120 BCM2835_GPIO_PIN(22),
121 BCM2835_GPIO_PIN(23),
122 BCM2835_GPIO_PIN(24),
123 BCM2835_GPIO_PIN(25),
124 BCM2835_GPIO_PIN(26),
125 BCM2835_GPIO_PIN(27),
126 BCM2835_GPIO_PIN(28),
127 BCM2835_GPIO_PIN(29),
128 BCM2835_GPIO_PIN(30),
129 BCM2835_GPIO_PIN(31),
130 BCM2835_GPIO_PIN(32),
131 BCM2835_GPIO_PIN(33),
132 BCM2835_GPIO_PIN(34),
133 BCM2835_GPIO_PIN(35),
134 BCM2835_GPIO_PIN(36),
135 BCM2835_GPIO_PIN(37),
136 BCM2835_GPIO_PIN(38),
137 BCM2835_GPIO_PIN(39),
138 BCM2835_GPIO_PIN(40),
139 BCM2835_GPIO_PIN(41),
140 BCM2835_GPIO_PIN(42),
141 BCM2835_GPIO_PIN(43),
142 BCM2835_GPIO_PIN(44),
143 BCM2835_GPIO_PIN(45),
144 BCM2835_GPIO_PIN(46),
145 BCM2835_GPIO_PIN(47),
146 BCM2835_GPIO_PIN(48),
147 BCM2835_GPIO_PIN(49),
148 BCM2835_GPIO_PIN(50),
149 BCM2835_GPIO_PIN(51),
150 BCM2835_GPIO_PIN(52),
151 BCM2835_GPIO_PIN(53),
152 BCM2835_GPIO_PIN(54),
153 BCM2835_GPIO_PIN(55),
154 BCM2835_GPIO_PIN(56),
155 BCM2835_GPIO_PIN(57),
158 /* one pin per group */
159 static const char * const bcm2835_gpio_groups[] = {
221 BCM2835_FSEL_COUNT = 8,
222 BCM2835_FSEL_MASK = 0x7,
225 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
226 [BCM2835_FSEL_GPIO_IN] = "gpio_in",
227 [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
228 [BCM2835_FSEL_ALT0] = "alt0",
229 [BCM2835_FSEL_ALT1] = "alt1",
230 [BCM2835_FSEL_ALT2] = "alt2",
231 [BCM2835_FSEL_ALT3] = "alt3",
232 [BCM2835_FSEL_ALT4] = "alt4",
233 [BCM2835_FSEL_ALT5] = "alt5",
236 static const char * const irq_type_names[] = {
237 [IRQ_TYPE_NONE] = "none",
238 [IRQ_TYPE_EDGE_RISING] = "edge-rising",
239 [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
240 [IRQ_TYPE_EDGE_BOTH] = "edge-both",
241 [IRQ_TYPE_LEVEL_HIGH] = "level-high",
242 [IRQ_TYPE_LEVEL_LOW] = "level-low",
245 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
247 return readl(pc->base + reg);
250 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
253 writel(val, pc->base + reg);
256 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
259 reg += GPIO_REG_OFFSET(bit) * 4;
260 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
263 /* note NOT a read/modify/write cycle */
264 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
265 unsigned reg, unsigned bit)
267 reg += GPIO_REG_OFFSET(bit) * 4;
268 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
271 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
272 struct bcm2835_pinctrl *pc, unsigned pin)
274 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
275 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
277 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
278 bcm2835_functions[status]);
283 static inline void bcm2835_pinctrl_fsel_set(
284 struct bcm2835_pinctrl *pc, unsigned pin,
285 enum bcm2835_fsel fsel)
287 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
288 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
290 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
291 bcm2835_functions[cur]);
296 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
297 /* always transition through GPIO_IN */
298 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
299 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
301 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
302 bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
303 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
306 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
307 val |= fsel << FSEL_SHIFT(pin);
309 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
310 bcm2835_functions[fsel]);
311 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
314 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
316 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
318 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
322 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
324 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
326 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
329 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
331 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
332 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
334 /* Alternative function doesn't clearly provide a direction */
335 if (fsel > BCM2835_FSEL_GPIO_OUT)
338 if (fsel == BCM2835_FSEL_GPIO_IN)
339 return GPIO_LINE_DIRECTION_IN;
341 return GPIO_LINE_DIRECTION_OUT;
344 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
346 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
348 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
351 static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
352 unsigned offset, int value)
354 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
356 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
357 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_OUT);
361 static const struct gpio_chip bcm2835_gpio_chip = {
362 .label = MODULE_NAME,
363 .owner = THIS_MODULE,
364 .request = gpiochip_generic_request,
365 .free = gpiochip_generic_free,
366 .direction_input = bcm2835_gpio_direction_input,
367 .direction_output = bcm2835_gpio_direction_output,
368 .get_direction = bcm2835_gpio_get_direction,
369 .get = bcm2835_gpio_get,
370 .set = bcm2835_gpio_set,
371 .set_config = gpiochip_generic_config,
373 .ngpio = BCM2835_NUM_GPIOS,
377 static const struct gpio_chip bcm2711_gpio_chip = {
378 .label = "pinctrl-bcm2711",
379 .owner = THIS_MODULE,
380 .request = gpiochip_generic_request,
381 .free = gpiochip_generic_free,
382 .direction_input = bcm2835_gpio_direction_input,
383 .direction_output = bcm2835_gpio_direction_output,
384 .get_direction = bcm2835_gpio_get_direction,
385 .get = bcm2835_gpio_get,
386 .set = bcm2835_gpio_set,
387 .set_config = gpiochip_generic_config,
389 .ngpio = BCM2711_NUM_GPIOS,
393 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
394 unsigned int bank, u32 mask)
396 unsigned long events;
400 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
402 events &= pc->enabled_irq_map[bank];
403 for_each_set_bit(offset, &events, 32) {
404 gpio = (32 * bank) + offset;
405 generic_handle_domain_irq(pc->gpio_chip.irq.domain,
410 static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
412 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
413 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
414 struct irq_chip *host_chip = irq_desc_get_chip(desc);
415 int irq = irq_desc_get_irq(desc);
419 for (i = 0; i < BCM2835_NUM_IRQS; i++) {
420 if (chip->irq.parents[i] == irq) {
425 /* This should not happen, every IRQ has a bank */
426 BUG_ON(i == BCM2835_NUM_IRQS);
428 chained_irq_enter(host_chip, desc);
431 case 0: /* IRQ0 covers GPIOs 0-27 */
432 bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
434 case 1: /* IRQ1 covers GPIOs 28-45 */
435 bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
436 bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
438 case 2: /* IRQ2 covers GPIOs 46-57 */
439 bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
443 chained_irq_exit(host_chip, desc);
446 static irqreturn_t bcm2835_gpio_wake_irq_handler(int irq, void *dev_id)
451 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
452 unsigned reg, unsigned offset, bool enable)
455 reg += GPIO_REG_OFFSET(offset) * 4;
456 value = bcm2835_gpio_rd(pc, reg);
458 value |= BIT(GPIO_REG_SHIFT(offset));
460 value &= ~(BIT(GPIO_REG_SHIFT(offset)));
461 bcm2835_gpio_wr(pc, reg, value);
464 /* fast path for IRQ handler */
465 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
466 unsigned offset, bool enable)
468 switch (pc->irq_type[offset]) {
469 case IRQ_TYPE_EDGE_RISING:
470 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
473 case IRQ_TYPE_EDGE_FALLING:
474 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
477 case IRQ_TYPE_EDGE_BOTH:
478 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
479 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
482 case IRQ_TYPE_LEVEL_HIGH:
483 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
486 case IRQ_TYPE_LEVEL_LOW:
487 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
492 static void bcm2835_gpio_irq_enable(struct irq_data *data)
494 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
495 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
496 unsigned gpio = irqd_to_hwirq(data);
497 unsigned offset = GPIO_REG_SHIFT(gpio);
498 unsigned bank = GPIO_REG_OFFSET(gpio);
501 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
502 set_bit(offset, &pc->enabled_irq_map[bank]);
503 bcm2835_gpio_irq_config(pc, gpio, true);
504 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
507 static void bcm2835_gpio_irq_disable(struct irq_data *data)
509 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
510 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
511 unsigned gpio = irqd_to_hwirq(data);
512 unsigned offset = GPIO_REG_SHIFT(gpio);
513 unsigned bank = GPIO_REG_OFFSET(gpio);
516 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
517 bcm2835_gpio_irq_config(pc, gpio, false);
518 /* Clear events that were latched prior to clearing event sources */
519 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
520 clear_bit(offset, &pc->enabled_irq_map[bank]);
521 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
524 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
525 unsigned offset, unsigned int type)
529 case IRQ_TYPE_EDGE_RISING:
530 case IRQ_TYPE_EDGE_FALLING:
531 case IRQ_TYPE_EDGE_BOTH:
532 case IRQ_TYPE_LEVEL_HIGH:
533 case IRQ_TYPE_LEVEL_LOW:
534 pc->irq_type[offset] = type;
543 /* slower path for reconfiguring IRQ type */
544 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
545 unsigned offset, unsigned int type)
549 if (pc->irq_type[offset] != type) {
550 bcm2835_gpio_irq_config(pc, offset, false);
551 pc->irq_type[offset] = type;
555 case IRQ_TYPE_EDGE_RISING:
556 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
557 /* RISING already enabled, disable FALLING */
558 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
559 bcm2835_gpio_irq_config(pc, offset, false);
560 pc->irq_type[offset] = type;
561 } else if (pc->irq_type[offset] != type) {
562 bcm2835_gpio_irq_config(pc, offset, false);
563 pc->irq_type[offset] = type;
564 bcm2835_gpio_irq_config(pc, offset, true);
568 case IRQ_TYPE_EDGE_FALLING:
569 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
570 /* FALLING already enabled, disable RISING */
571 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
572 bcm2835_gpio_irq_config(pc, offset, false);
573 pc->irq_type[offset] = type;
574 } else if (pc->irq_type[offset] != type) {
575 bcm2835_gpio_irq_config(pc, offset, false);
576 pc->irq_type[offset] = type;
577 bcm2835_gpio_irq_config(pc, offset, true);
581 case IRQ_TYPE_EDGE_BOTH:
582 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
583 /* RISING already enabled, enable FALLING too */
584 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
585 bcm2835_gpio_irq_config(pc, offset, true);
586 pc->irq_type[offset] = type;
587 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
588 /* FALLING already enabled, enable RISING too */
589 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
590 bcm2835_gpio_irq_config(pc, offset, true);
591 pc->irq_type[offset] = type;
592 } else if (pc->irq_type[offset] != type) {
593 bcm2835_gpio_irq_config(pc, offset, false);
594 pc->irq_type[offset] = type;
595 bcm2835_gpio_irq_config(pc, offset, true);
599 case IRQ_TYPE_LEVEL_HIGH:
600 case IRQ_TYPE_LEVEL_LOW:
601 if (pc->irq_type[offset] != type) {
602 bcm2835_gpio_irq_config(pc, offset, false);
603 pc->irq_type[offset] = type;
604 bcm2835_gpio_irq_config(pc, offset, true);
614 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
616 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
617 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
618 unsigned gpio = irqd_to_hwirq(data);
619 unsigned offset = GPIO_REG_SHIFT(gpio);
620 unsigned bank = GPIO_REG_OFFSET(gpio);
624 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
626 if (test_bit(offset, &pc->enabled_irq_map[bank]))
627 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
629 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
631 if (type & IRQ_TYPE_EDGE_BOTH)
632 irq_set_handler_locked(data, handle_edge_irq);
634 irq_set_handler_locked(data, handle_level_irq);
636 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
641 static void bcm2835_gpio_irq_ack(struct irq_data *data)
643 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
644 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
645 unsigned gpio = irqd_to_hwirq(data);
647 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
650 static int bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
652 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
653 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
654 unsigned gpio = irqd_to_hwirq(data);
655 unsigned int irqgroup;
663 else if (gpio >= 28 && gpio <= 45)
665 else if (gpio >= 46 && gpio <= 57)
671 ret = enable_irq_wake(pc->wake_irq[irqgroup]);
673 ret = disable_irq_wake(pc->wake_irq[irqgroup]);
678 static struct irq_chip bcm2835_gpio_irq_chip = {
680 .irq_enable = bcm2835_gpio_irq_enable,
681 .irq_disable = bcm2835_gpio_irq_disable,
682 .irq_set_type = bcm2835_gpio_irq_set_type,
683 .irq_ack = bcm2835_gpio_irq_ack,
684 .irq_mask = bcm2835_gpio_irq_disable,
685 .irq_unmask = bcm2835_gpio_irq_enable,
686 .irq_set_wake = bcm2835_gpio_irq_set_wake,
687 .flags = IRQCHIP_MASK_ON_SUSPEND,
690 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
692 return BCM2835_NUM_GPIOS;
695 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
698 return bcm2835_gpio_groups[selector];
701 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
703 const unsigned **pins,
706 *pins = &bcm2835_gpio_pins[selector].number;
712 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
716 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
717 struct gpio_chip *chip = &pc->gpio_chip;
718 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
719 const char *fname = bcm2835_functions[fsel];
720 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
721 int irq = irq_find_mapping(chip->irq.domain, offset);
723 seq_printf(s, "function %s in %s; irq %d (%s)",
724 fname, value ? "hi" : "lo",
725 irq, irq_type_names[pc->irq_type[offset]]);
728 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
729 struct pinctrl_map *maps, unsigned num_maps)
733 for (i = 0; i < num_maps; i++)
734 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
735 kfree(maps[i].data.configs.configs);
740 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
741 struct device_node *np, u32 pin, u32 fnum,
742 struct pinctrl_map **maps)
744 struct pinctrl_map *map = *maps;
746 if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
747 dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
751 map->type = PIN_MAP_TYPE_MUX_GROUP;
752 map->data.mux.group = bcm2835_gpio_groups[pin];
753 map->data.mux.function = bcm2835_functions[fnum];
759 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
760 struct device_node *np, u32 pin, u32 pull,
761 struct pinctrl_map **maps)
763 struct pinctrl_map *map = *maps;
764 unsigned long *configs;
767 dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
771 configs = kzalloc(sizeof(*configs), GFP_KERNEL);
774 configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull);
776 map->type = PIN_MAP_TYPE_CONFIGS_PIN;
777 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
778 map->data.configs.configs = configs;
779 map->data.configs.num_configs = 1;
785 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
786 struct device_node *np,
787 struct pinctrl_map **map, unsigned int *num_maps)
789 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
790 struct property *pins, *funcs, *pulls;
791 int num_pins, num_funcs, num_pulls, maps_per_pin;
792 struct pinctrl_map *maps, *cur_map;
796 /* Check for generic binding in this node */
797 err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
798 if (err || *num_maps)
801 /* Generic binding did not find anything continue with legacy parse */
802 pins = of_find_property(np, "brcm,pins", NULL);
804 dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
808 funcs = of_find_property(np, "brcm,function", NULL);
809 pulls = of_find_property(np, "brcm,pull", NULL);
811 if (!funcs && !pulls) {
813 "%pOF: neither brcm,function nor brcm,pull specified\n",
818 num_pins = pins->length / 4;
819 num_funcs = funcs ? (funcs->length / 4) : 0;
820 num_pulls = pulls ? (pulls->length / 4) : 0;
822 if (num_funcs > 1 && num_funcs != num_pins) {
824 "%pOF: brcm,function must have 1 or %d entries\n",
829 if (num_pulls > 1 && num_pulls != num_pins) {
831 "%pOF: brcm,pull must have 1 or %d entries\n",
841 cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps),
846 for (i = 0; i < num_pins; i++) {
847 err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
850 if (pin >= pc->pctl_desc.npins) {
851 dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
858 err = of_property_read_u32_index(np, "brcm,function",
859 (num_funcs > 1) ? i : 0, &func);
862 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
868 err = of_property_read_u32_index(np, "brcm,pull",
869 (num_pulls > 1) ? i : 0, &pull);
872 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
880 *num_maps = num_pins * maps_per_pin;
885 bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
889 static const struct pinctrl_ops bcm2835_pctl_ops = {
890 .get_groups_count = bcm2835_pctl_get_groups_count,
891 .get_group_name = bcm2835_pctl_get_group_name,
892 .get_group_pins = bcm2835_pctl_get_group_pins,
893 .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
894 .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
895 .dt_free_map = bcm2835_pctl_dt_free_map,
898 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
901 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
903 /* disable by setting to GPIO_IN */
904 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
908 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
910 return BCM2835_FSEL_COUNT;
913 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
916 return bcm2835_functions[selector];
919 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
921 const char * const **groups,
922 unsigned * const num_groups)
924 /* every pin can do every function */
925 *groups = bcm2835_gpio_groups;
926 *num_groups = BCM2835_NUM_GPIOS;
931 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
932 unsigned func_selector,
933 unsigned group_selector)
935 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
937 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
942 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
943 struct pinctrl_gpio_range *range,
946 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
948 /* disable by setting to GPIO_IN */
949 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
952 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
953 struct pinctrl_gpio_range *range,
957 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
958 enum bcm2835_fsel fsel = input ?
959 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
961 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
966 static const struct pinmux_ops bcm2835_pmx_ops = {
967 .free = bcm2835_pmx_free,
968 .get_functions_count = bcm2835_pmx_get_functions_count,
969 .get_function_name = bcm2835_pmx_get_function_name,
970 .get_function_groups = bcm2835_pmx_get_function_groups,
971 .set_mux = bcm2835_pmx_set,
972 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
973 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
976 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
977 unsigned pin, unsigned long *config)
979 /* No way to read back config in HW */
983 static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc,
984 unsigned int pin, unsigned int arg)
988 off = GPIO_REG_OFFSET(pin);
989 bit = GPIO_REG_SHIFT(pin);
991 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
993 * BCM2835 datasheet say to wait 150 cycles, but not of what.
994 * But the VideoCore firmware delay for this operation
995 * based nearly on the same amount of VPU cycles and this clock
999 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
1001 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
1004 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
1005 unsigned int pin, unsigned long *configs,
1006 unsigned int num_configs)
1008 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1012 for (i = 0; i < num_configs; i++) {
1013 param = pinconf_to_config_param(configs[i]);
1014 arg = pinconf_to_config_argument(configs[i]);
1017 /* Set legacy brcm,pull */
1018 case BCM2835_PINCONF_PARAM_PULL:
1019 bcm2835_pull_config_set(pc, pin, arg);
1022 /* Set pull generic bindings */
1023 case PIN_CONFIG_BIAS_DISABLE:
1024 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF);
1027 case PIN_CONFIG_BIAS_PULL_DOWN:
1028 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN);
1031 case PIN_CONFIG_BIAS_PULL_UP:
1032 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP);
1035 /* Set output-high or output-low */
1036 case PIN_CONFIG_OUTPUT:
1037 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1043 } /* switch param type */
1044 } /* for each config */
1049 static const struct pinconf_ops bcm2835_pinconf_ops = {
1051 .pin_config_get = bcm2835_pinconf_get,
1052 .pin_config_set = bcm2835_pinconf_set,
1055 static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc,
1056 unsigned int pin, unsigned int arg)
1062 off = PUD_2711_REG_OFFSET(pin);
1063 shifter = PUD_2711_REG_SHIFT(pin);
1065 value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4));
1066 value &= ~(PUD_2711_MASK << shifter);
1067 value |= (arg << shifter);
1068 bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value);
1071 static int bcm2711_pinconf_set(struct pinctrl_dev *pctldev,
1072 unsigned int pin, unsigned long *configs,
1073 unsigned int num_configs)
1075 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1079 for (i = 0; i < num_configs; i++) {
1080 param = pinconf_to_config_param(configs[i]);
1081 arg = pinconf_to_config_argument(configs[i]);
1084 /* convert legacy brcm,pull */
1085 case BCM2835_PINCONF_PARAM_PULL:
1086 if (arg == BCM2835_PUD_UP)
1087 arg = BCM2711_PULL_UP;
1088 else if (arg == BCM2835_PUD_DOWN)
1089 arg = BCM2711_PULL_DOWN;
1091 arg = BCM2711_PULL_NONE;
1093 bcm2711_pull_config_set(pc, pin, arg);
1096 /* Set pull generic bindings */
1097 case PIN_CONFIG_BIAS_DISABLE:
1098 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE);
1100 case PIN_CONFIG_BIAS_PULL_DOWN:
1101 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN);
1103 case PIN_CONFIG_BIAS_PULL_UP:
1104 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP);
1107 /* Set output-high or output-low */
1108 case PIN_CONFIG_OUTPUT:
1109 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1115 } /* for each config */
1120 static const struct pinconf_ops bcm2711_pinconf_ops = {
1122 .pin_config_get = bcm2835_pinconf_get,
1123 .pin_config_set = bcm2711_pinconf_set,
1126 static const struct pinctrl_desc bcm2835_pinctrl_desc = {
1127 .name = MODULE_NAME,
1128 .pins = bcm2835_gpio_pins,
1129 .npins = BCM2835_NUM_GPIOS,
1130 .pctlops = &bcm2835_pctl_ops,
1131 .pmxops = &bcm2835_pmx_ops,
1132 .confops = &bcm2835_pinconf_ops,
1133 .owner = THIS_MODULE,
1136 static const struct pinctrl_desc bcm2711_pinctrl_desc = {
1137 .name = "pinctrl-bcm2711",
1138 .pins = bcm2835_gpio_pins,
1139 .npins = BCM2711_NUM_GPIOS,
1140 .pctlops = &bcm2835_pctl_ops,
1141 .pmxops = &bcm2835_pmx_ops,
1142 .confops = &bcm2711_pinconf_ops,
1143 .owner = THIS_MODULE,
1146 static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
1147 .name = MODULE_NAME,
1148 .npins = BCM2835_NUM_GPIOS,
1151 static const struct pinctrl_gpio_range bcm2711_pinctrl_gpio_range = {
1152 .name = "pinctrl-bcm2711",
1153 .npins = BCM2711_NUM_GPIOS,
1156 struct bcm_plat_data {
1157 const struct gpio_chip *gpio_chip;
1158 const struct pinctrl_desc *pctl_desc;
1159 const struct pinctrl_gpio_range *gpio_range;
1162 static const struct bcm_plat_data bcm2835_plat_data = {
1163 .gpio_chip = &bcm2835_gpio_chip,
1164 .pctl_desc = &bcm2835_pinctrl_desc,
1165 .gpio_range = &bcm2835_pinctrl_gpio_range,
1168 static const struct bcm_plat_data bcm2711_plat_data = {
1169 .gpio_chip = &bcm2711_gpio_chip,
1170 .pctl_desc = &bcm2711_pinctrl_desc,
1171 .gpio_range = &bcm2711_pinctrl_gpio_range,
1174 static const struct of_device_id bcm2835_pinctrl_match[] = {
1176 .compatible = "brcm,bcm2835-gpio",
1177 .data = &bcm2835_plat_data,
1180 .compatible = "brcm,bcm2711-gpio",
1181 .data = &bcm2711_plat_data,
1184 .compatible = "brcm,bcm7211-gpio",
1185 .data = &bcm2711_plat_data,
1190 static int bcm2835_pinctrl_probe(struct platform_device *pdev)
1192 struct device *dev = &pdev->dev;
1193 struct device_node *np = dev->of_node;
1194 const struct bcm_plat_data *pdata;
1195 struct bcm2835_pinctrl *pc;
1196 struct gpio_irq_chip *girq;
1197 struct resource iomem;
1199 const struct of_device_id *match;
1202 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS);
1203 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS);
1205 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1209 platform_set_drvdata(pdev, pc);
1212 err = of_address_to_resource(np, 0, &iomem);
1214 dev_err(dev, "could not get IO memory\n");
1218 pc->base = devm_ioremap_resource(dev, &iomem);
1219 if (IS_ERR(pc->base))
1220 return PTR_ERR(pc->base);
1222 match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node);
1226 pdata = match->data;
1227 is_7211 = of_device_is_compatible(np, "brcm,bcm7211-gpio");
1229 pc->gpio_chip = *pdata->gpio_chip;
1230 pc->gpio_chip.parent = dev;
1232 for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1233 unsigned long events;
1236 /* clear event detection flags */
1237 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1238 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1239 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1240 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1241 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1242 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1244 /* clear all the events */
1245 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1246 for_each_set_bit(offset, &events, 32)
1247 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1249 raw_spin_lock_init(&pc->irq_lock[i]);
1252 pc->pctl_desc = *pdata->pctl_desc;
1253 pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
1254 if (IS_ERR(pc->pctl_dev)) {
1255 gpiochip_remove(&pc->gpio_chip);
1256 return PTR_ERR(pc->pctl_dev);
1259 pc->gpio_range = *pdata->gpio_range;
1260 pc->gpio_range.base = pc->gpio_chip.base;
1261 pc->gpio_range.gc = &pc->gpio_chip;
1262 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1264 girq = &pc->gpio_chip.irq;
1265 girq->chip = &bcm2835_gpio_irq_chip;
1266 girq->parent_handler = bcm2835_gpio_irq_handler;
1267 girq->num_parents = BCM2835_NUM_IRQS;
1268 girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1269 sizeof(*girq->parents),
1271 if (!girq->parents) {
1277 pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1278 sizeof(*pc->wake_irq),
1280 if (!pc->wake_irq) {
1287 * Use the same handler for all groups: this is necessary
1288 * since we use one gpiochip to cover all lines - the
1289 * irq handler then needs to figure out which group and
1290 * bank that was firing the IRQ and look up the per-group
1293 for (i = 0; i < BCM2835_NUM_IRQS; i++) {
1297 girq->parents[i] = irq_of_parse_and_map(np, i);
1299 if (!girq->parents[i]) {
1300 girq->num_parents = i;
1305 /* Skip over the all banks interrupts */
1306 pc->wake_irq[i] = irq_of_parse_and_map(np, i +
1307 BCM2835_NUM_IRQS + 1);
1309 len = strlen(dev_name(pc->dev)) + 16;
1310 name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
1316 snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
1318 /* These are optional interrupts */
1319 err = devm_request_irq(dev, pc->wake_irq[i],
1320 bcm2835_gpio_wake_irq_handler,
1321 IRQF_SHARED, name, pc);
1323 dev_warn(dev, "unable to request wake IRQ %d\n",
1327 girq->default_type = IRQ_TYPE_NONE;
1328 girq->handler = handle_level_irq;
1330 err = gpiochip_add_data(&pc->gpio_chip, pc);
1332 dev_err(dev, "could not add GPIO chip\n");
1339 pinctrl_remove_gpio_range(pc->pctl_dev, &pc->gpio_range);
1343 static struct platform_driver bcm2835_pinctrl_driver = {
1344 .probe = bcm2835_pinctrl_probe,
1346 .name = MODULE_NAME,
1347 .of_match_table = bcm2835_pinctrl_match,
1348 .suppress_bind_attrs = true,
1351 module_platform_driver(bcm2835_pinctrl_driver);
1353 MODULE_AUTHOR("Chris Boot");
1354 MODULE_AUTHOR("Simon Arlott");
1355 MODULE_AUTHOR("Stephen Warren");
1356 MODULE_DESCRIPTION("Broadcom BCM2835/2711 pinctrl and GPIO driver");
1357 MODULE_LICENSE("GPL");