Merge tag 'usb-5.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb

[linux-block.git] / drivers / phy / qualcomm / phy-qcom-qmp.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
 */

#ifndef QCOM_PHY_QMP_H_
#define QCOM_PHY_QMP_H_

/* Only for QMP V2 PHY - QSERDES COM registers */
#define QSERDES_COM_BG_TIMER                            0x00c
#define QSERDES_COM_SSC_EN_CENTER                       0x010
#define QSERDES_COM_SSC_ADJ_PER1                        0x014
#define QSERDES_COM_SSC_ADJ_PER2                        0x018
#define QSERDES_COM_SSC_PER1                            0x01c
#define QSERDES_COM_SSC_PER2                            0x020
#define QSERDES_COM_SSC_STEP_SIZE1                      0x024
#define QSERDES_COM_SSC_STEP_SIZE2                      0x028
#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN                 0x034
#define QSERDES_COM_CLK_ENABLE1                         0x038
#define QSERDES_COM_SYS_CLK_CTRL                        0x03c
#define QSERDES_COM_SYSCLK_BUF_ENABLE                   0x040
#define QSERDES_COM_PLL_IVCO                            0x048
#define QSERDES_COM_LOCK_CMP1_MODE0                     0x04c
#define QSERDES_COM_LOCK_CMP2_MODE0                     0x050
#define QSERDES_COM_LOCK_CMP3_MODE0                     0x054
#define QSERDES_COM_LOCK_CMP1_MODE1                     0x058
#define QSERDES_COM_LOCK_CMP2_MODE1                     0x05c
#define QSERDES_COM_LOCK_CMP3_MODE1                     0x060
#define QSERDES_COM_BG_TRIM                             0x070
#define QSERDES_COM_CLK_EP_DIV                          0x074
#define QSERDES_COM_CP_CTRL_MODE0                       0x078
#define QSERDES_COM_CP_CTRL_MODE1                       0x07c
#define QSERDES_COM_PLL_RCTRL_MODE0                     0x084
#define QSERDES_COM_PLL_RCTRL_MODE1                     0x088
#define QSERDES_COM_PLL_CCTRL_MODE0                     0x090
#define QSERDES_COM_PLL_CCTRL_MODE1                     0x094
#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM                 0x0a8
#define QSERDES_COM_SYSCLK_EN_SEL                       0x0ac
#define QSERDES_COM_RESETSM_CNTRL                       0x0b4
#define QSERDES_COM_RESTRIM_CTRL                        0x0bc
#define QSERDES_COM_RESCODE_DIV_NUM                     0x0c4
#define QSERDES_COM_LOCK_CMP_EN                         0x0c8
#define QSERDES_COM_LOCK_CMP_CFG                        0x0cc
#define QSERDES_COM_DEC_START_MODE0                     0x0d0
#define QSERDES_COM_DEC_START_MODE1                     0x0d4
#define QSERDES_COM_DIV_FRAC_START1_MODE0               0x0dc
#define QSERDES_COM_DIV_FRAC_START2_MODE0               0x0e0
#define QSERDES_COM_DIV_FRAC_START3_MODE0               0x0e4
#define QSERDES_COM_DIV_FRAC_START1_MODE1               0x0e8
#define QSERDES_COM_DIV_FRAC_START2_MODE1               0x0ec
#define QSERDES_COM_DIV_FRAC_START3_MODE1               0x0f0
#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0               0x108
#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0               0x10c
#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1               0x110
#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1               0x114
#define QSERDES_COM_VCO_TUNE_CTRL                       0x124
#define QSERDES_COM_VCO_TUNE_MAP                        0x128
#define QSERDES_COM_VCO_TUNE1_MODE0                     0x12c
#define QSERDES_COM_VCO_TUNE2_MODE0                     0x130
#define QSERDES_COM_VCO_TUNE1_MODE1                     0x134
#define QSERDES_COM_VCO_TUNE2_MODE1                     0x138
#define QSERDES_COM_VCO_TUNE_TIMER1                     0x144
#define QSERDES_COM_VCO_TUNE_TIMER2                     0x148
#define QSERDES_COM_BG_CTRL                             0x170
#define QSERDES_COM_CLK_SELECT                          0x174
#define QSERDES_COM_HSCLK_SEL                           0x178
#define QSERDES_COM_CORECLK_DIV                         0x184
#define QSERDES_COM_CORE_CLK_EN                         0x18c
#define QSERDES_COM_C_READY_STATUS                      0x190
#define QSERDES_COM_CMN_CONFIG                          0x194
#define QSERDES_COM_SVS_MODE_CLK_SEL                    0x19c
#define QSERDES_COM_DEBUG_BUS0                          0x1a0
#define QSERDES_COM_DEBUG_BUS1                          0x1a4
#define QSERDES_COM_DEBUG_BUS2                          0x1a8
#define QSERDES_COM_DEBUG_BUS3                          0x1ac
#define QSERDES_COM_DEBUG_BUS_SEL                       0x1b0
#define QSERDES_COM_CORECLK_DIV_MODE1                   0x1bc

/* Only for QMP V2 PHY - TX registers */
#define QSERDES_TX_RES_CODE_LANE_OFFSET                 0x054
#define QSERDES_TX_DEBUG_BUS_SEL                        0x064
#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN     0x068
#define QSERDES_TX_LANE_MODE                            0x094
#define QSERDES_TX_RCV_DETECT_LVL_2                     0x0ac

/* Only for QMP V2 PHY - RX registers */
#define QSERDES_RX_UCDR_SO_GAIN_HALF                    0x010
#define QSERDES_RX_UCDR_SO_GAIN                         0x01c
#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN                0x040
#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE        0x048
#define QSERDES_RX_RX_TERM_BW                           0x090
#define QSERDES_RX_RX_EQ_GAIN1_LSB                      0x0c4
#define QSERDES_RX_RX_EQ_GAIN1_MSB                      0x0c8
#define QSERDES_RX_RX_EQ_GAIN2_LSB                      0x0cc
#define QSERDES_RX_RX_EQ_GAIN2_MSB                      0x0d0
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2                0x0d8
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3                0x0dc
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4                0x0e0
#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1          0x108
#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2             0x10c
#define QSERDES_RX_SIGDET_ENABLES                       0x110
#define QSERDES_RX_SIGDET_CNTRL                         0x114
#define QSERDES_RX_SIGDET_LVL                           0x118
#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL                0x11c
#define QSERDES_RX_RX_BAND                              0x120
#define QSERDES_RX_RX_INTERFACE_MODE                    0x12c

/* Only for QMP V2 PHY - PCS registers */
#define QPHY_POWER_DOWN_CONTROL                         0x04
#define QPHY_TXDEEMPH_M6DB_V0                           0x24
#define QPHY_TXDEEMPH_M3P5DB_V0                         0x28
#define QPHY_ENDPOINT_REFCLK_DRIVE                      0x54
#define QPHY_RX_IDLE_DTCT_CNTRL                         0x58
#define QPHY_POWER_STATE_CONFIG1                        0x60
#define QPHY_POWER_STATE_CONFIG2                        0x64
#define QPHY_POWER_STATE_CONFIG4                        0x6c
#define QPHY_LOCK_DETECT_CONFIG1                        0x80
#define QPHY_LOCK_DETECT_CONFIG2                        0x84
#define QPHY_LOCK_DETECT_CONFIG3                        0x88
#define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK                0xa0
#define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK                  0xa4
#define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB           0x1A8
#define QPHY_OSC_DTCT_ACTIONS                           0x1AC
#define QPHY_RX_SIGDET_LVL                              0x1D8
#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB            0x1DC
#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB            0x1E0

/* Only for QMP V3 PHY - DP COM registers */
#define QPHY_V3_DP_COM_PHY_MODE_CTRL                    0x00
#define QPHY_V3_DP_COM_SW_RESET                         0x04
#define QPHY_V3_DP_COM_POWER_DOWN_CTRL                  0x08
#define QPHY_V3_DP_COM_SWI_CTRL                         0x0c
#define QPHY_V3_DP_COM_TYPEC_CTRL                       0x10
#define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL                 0x14
#define QPHY_V3_DP_COM_RESET_OVRD_CTRL                  0x1c

/* Only for QMP V3 PHY - QSERDES COM registers */
#define QSERDES_V3_COM_BG_TIMER                         0x00c
#define QSERDES_V3_COM_SSC_EN_CENTER                    0x010
#define QSERDES_V3_COM_SSC_ADJ_PER1                     0x014
#define QSERDES_V3_COM_SSC_ADJ_PER2                     0x018
#define QSERDES_V3_COM_SSC_PER1                         0x01c
#define QSERDES_V3_COM_SSC_PER2                         0x020
#define QSERDES_V3_COM_SSC_STEP_SIZE1                   0x024
#define QSERDES_V3_COM_SSC_STEP_SIZE2                   0x028
#define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN              0x034
#define QSERDES_V3_COM_CLK_ENABLE1                      0x038
#define QSERDES_V3_COM_SYS_CLK_CTRL                     0x03c
#define QSERDES_V3_COM_SYSCLK_BUF_ENABLE                0x040
#define QSERDES_V3_COM_PLL_IVCO                         0x048
#define QSERDES_V3_COM_LOCK_CMP1_MODE0                  0x098
#define QSERDES_V3_COM_LOCK_CMP2_MODE0                  0x09c
#define QSERDES_V3_COM_LOCK_CMP3_MODE0                  0x0a0
#define QSERDES_V3_COM_LOCK_CMP1_MODE1                  0x0a4
#define QSERDES_V3_COM_LOCK_CMP2_MODE1                  0x0a8
#define QSERDES_V3_COM_LOCK_CMP3_MODE1                  0x0ac
#define QSERDES_V3_COM_CLK_EP_DIV                       0x05c
#define QSERDES_V3_COM_CP_CTRL_MODE0                    0x060
#define QSERDES_V3_COM_CP_CTRL_MODE1                    0x064
#define QSERDES_V3_COM_PLL_RCTRL_MODE0                  0x068
#define QSERDES_V3_COM_PLL_RCTRL_MODE1                  0x06c
#define QSERDES_V3_COM_PLL_CCTRL_MODE0                  0x070
#define QSERDES_V3_COM_PLL_CCTRL_MODE1                  0x074
#define QSERDES_V3_COM_SYSCLK_EN_SEL                    0x080
#define QSERDES_V3_COM_RESETSM_CNTRL                    0x088
#define QSERDES_V3_COM_RESETSM_CNTRL2                   0x08c
#define QSERDES_V3_COM_LOCK_CMP_EN                      0x090
#define QSERDES_V3_COM_LOCK_CMP_CFG                     0x094
#define QSERDES_V3_COM_DEC_START_MODE0                  0x0b0
#define QSERDES_V3_COM_DEC_START_MODE1                  0x0b4
#define QSERDES_V3_COM_DIV_FRAC_START1_MODE0            0x0b8
#define QSERDES_V3_COM_DIV_FRAC_START2_MODE0            0x0bc
#define QSERDES_V3_COM_DIV_FRAC_START3_MODE0            0x0c0
#define QSERDES_V3_COM_DIV_FRAC_START1_MODE1            0x0c4
#define QSERDES_V3_COM_DIV_FRAC_START2_MODE1            0x0c8
#define QSERDES_V3_COM_DIV_FRAC_START3_MODE1            0x0cc
#define QSERDES_V3_COM_INTEGLOOP_INITVAL                0x0d0
#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0            0x0d8
#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0            0x0dc
#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1            0x0e0
#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1            0x0e4
#define QSERDES_V3_COM_VCO_TUNE_CTRL                    0x0ec
#define QSERDES_V3_COM_VCO_TUNE_MAP                     0x0f0
#define QSERDES_V3_COM_VCO_TUNE1_MODE0                  0x0f4
#define QSERDES_V3_COM_VCO_TUNE2_MODE0                  0x0f8
#define QSERDES_V3_COM_VCO_TUNE1_MODE1                  0x0fc
#define QSERDES_V3_COM_VCO_TUNE2_MODE1                  0x100
#define QSERDES_V3_COM_VCO_TUNE_INITVAL1                0x104
#define QSERDES_V3_COM_VCO_TUNE_INITVAL2                0x108
#define QSERDES_V3_COM_VCO_TUNE_TIMER1                  0x11c
#define QSERDES_V3_COM_VCO_TUNE_TIMER2                  0x120
#define QSERDES_V3_COM_CLK_SELECT                       0x138
#define QSERDES_V3_COM_HSCLK_SEL                        0x13c
#define QSERDES_V3_COM_CORECLK_DIV_MODE0                0x148
#define QSERDES_V3_COM_CORECLK_DIV_MODE1                0x14c
#define QSERDES_V3_COM_CORE_CLK_EN                      0x154
#define QSERDES_V3_COM_C_READY_STATUS                   0x158
#define QSERDES_V3_COM_CMN_CONFIG                       0x15c
#define QSERDES_V3_COM_SVS_MODE_CLK_SEL                 0x164
#define QSERDES_V3_COM_DEBUG_BUS0                       0x168
#define QSERDES_V3_COM_DEBUG_BUS1                       0x16c
#define QSERDES_V3_COM_DEBUG_BUS2                       0x170
#define QSERDES_V3_COM_DEBUG_BUS3                       0x174
#define QSERDES_V3_COM_DEBUG_BUS_SEL                    0x178
#define QSERDES_V3_COM_CMN_MODE                         0x184

/* Only for QMP V3 PHY - TX registers */
#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX           0x044
#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX           0x048
#define QSERDES_V3_TX_DEBUG_BUS_SEL                     0x058
#define QSERDES_V3_TX_HIGHZ_DRVR_EN                     0x060
#define QSERDES_V3_TX_LANE_MODE_1                       0x08c
#define QSERDES_V3_TX_RCV_DETECT_LVL_2                  0x0a4

/* Only for QMP V3 PHY - RX registers */
#define QSERDES_V3_RX_UCDR_FO_GAIN                      0x008
#define QSERDES_V3_RX_UCDR_SO_GAIN_HALF                 0x00c
#define QSERDES_V3_RX_UCDR_SO_GAIN                      0x014
#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF             0x024
#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER          0x028
#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN                  0x02c
#define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN             0x030
#define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE     0x034
#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW           0x03c
#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH          0x040
#define QSERDES_V3_RX_UCDR_PI_CONTROLS                  0x044
#define QSERDES_V3_RX_RX_TERM_BW                        0x07c
#define QSERDES_V3_RX_VGA_CAL_CNTRL1                    0x0bc
#define QSERDES_V3_RX_VGA_CAL_CNTRL2                    0x0c0
#define QSERDES_V3_RX_RX_EQ_GAIN2_LSB                   0x0c8
#define QSERDES_V3_RX_RX_EQ_GAIN2_MSB                   0x0cc
#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2             0x0d4
#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3             0x0d8
#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4             0x0dc
#define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1       0x0f8
#define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2          0x0fc
#define QSERDES_V3_RX_SIGDET_ENABLES                    0x100
#define QSERDES_V3_RX_SIGDET_CNTRL                      0x104
#define QSERDES_V3_RX_SIGDET_LVL                        0x108
#define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL             0x10c
#define QSERDES_V3_RX_RX_BAND                           0x110
#define QSERDES_V3_RX_RX_INTERFACE_MODE                 0x11c
#define QSERDES_V3_RX_RX_MODE_00                        0x164
#define QSERDES_V3_RX_RX_MODE_01                        0x168

/* Only for QMP V3 PHY - PCS registers */
#define QPHY_V3_PCS_POWER_DOWN_CONTROL                  0x004
#define QPHY_V3_PCS_TXMGN_V0                            0x00c
#define QPHY_V3_PCS_TXMGN_V1                            0x010
#define QPHY_V3_PCS_TXMGN_V2                            0x014
#define QPHY_V3_PCS_TXMGN_V3                            0x018
#define QPHY_V3_PCS_TXMGN_V4                            0x01c
#define QPHY_V3_PCS_TXMGN_LS                            0x020
#define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL                0x02c
#define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL                0x034
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V0                    0x024
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0                  0x028
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V1                    0x02c
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1                  0x030
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V2                    0x034
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2                  0x038
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V3                    0x03c
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3                  0x040
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V4                    0x044
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4                  0x048
#define QPHY_V3_PCS_TXDEEMPH_M6DB_LS                    0x04c
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS                  0x050
#define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE               0x054
#define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL                  0x058
#define QPHY_V3_PCS_RATE_SLEW_CNTRL                     0x05c
#define QPHY_V3_PCS_POWER_STATE_CONFIG1                 0x060
#define QPHY_V3_PCS_POWER_STATE_CONFIG2                 0x064
#define QPHY_V3_PCS_POWER_STATE_CONFIG4                 0x06c
#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L                0x070
#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H                0x074
#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L                  0x078
#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H                  0x07c
#define QPHY_V3_PCS_LOCK_DETECT_CONFIG1                 0x080
#define QPHY_V3_PCS_LOCK_DETECT_CONFIG2                 0x084
#define QPHY_V3_PCS_LOCK_DETECT_CONFIG3                 0x088
#define QPHY_V3_PCS_TSYNC_RSYNC_TIME                    0x08c
#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK         0x0a0
#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK           0x0a4
#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME               0x0a8
#define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK             0x0b0
#define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME              0x0b8
#define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME               0x0bc
#define QPHY_V3_PCS_FLL_CNTRL1                          0x0c4
#define QPHY_V3_PCS_FLL_CNTRL2                          0x0c8
#define QPHY_V3_PCS_FLL_CNT_VAL_L                       0x0cc
#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL                   0x0d0
#define QPHY_V3_PCS_FLL_MAN_CODE                        0x0d4
#define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL                  0x134
#define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME                 0x138
#define QPHY_V3_PCS_RX_SIGDET_CTRL1                     0x13c
#define QPHY_V3_PCS_RX_SIGDET_CTRL2                     0x140
#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB       0x1a8
#define QPHY_V3_PCS_OSC_DTCT_ACTIONS                    0x1ac
#define QPHY_V3_PCS_SIGDET_CNTRL                        0x1b0
#define QPHY_V3_PCS_TX_MID_TERM_CTRL1                   0x1bc
#define QPHY_V3_PCS_MULTI_LANE_CTRL1                    0x1c4
#define QPHY_V3_PCS_RX_SIGDET_LVL                       0x1d8
#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB     0x1dc
#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB     0x1e0
#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1                  0x20c
#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2                  0x210

/* Only for QMP V3 PHY - PCS_MISC registers */
#define QPHY_V3_PCS_MISC_CLAMP_ENABLE                   0x0c
#define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2               0x2c
#define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1       0x44
#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2         0x54
#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4         0x5c
#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5         0x60

/* Only for QMP V4 PHY - QSERDES COM registers */
#define QSERDES_V4_COM_PLL_IVCO                         0x058
#define QSERDES_V4_COM_CMN_IPTRIM                       0x060
#define QSERDES_V4_COM_CP_CTRL_MODE0                    0x074
#define QSERDES_V4_COM_CP_CTRL_MODE1                    0x078
#define QSERDES_V4_COM_PLL_RCTRL_MODE0                  0x07c
#define QSERDES_V4_COM_PLL_RCTRL_MODE1                  0x080
#define QSERDES_V4_COM_PLL_CCTRL_MODE0                  0x084
#define QSERDES_V4_COM_PLL_CCTRL_MODE1                  0x088
#define QSERDES_V4_COM_SYSCLK_EN_SEL                    0x094
#define QSERDES_V4_COM_LOCK_CMP_EN                      0x0a4
#define QSERDES_V4_COM_LOCK_CMP1_MODE0                  0x0ac
#define QSERDES_V4_COM_LOCK_CMP2_MODE0                  0x0b0
#define QSERDES_V4_COM_LOCK_CMP1_MODE1                  0x0b4
#define QSERDES_V4_COM_DEC_START_MODE0                  0x0bc
#define QSERDES_V4_COM_LOCK_CMP2_MODE1                  0x0b8
#define QSERDES_V4_COM_DEC_START_MODE1                  0x0c4
#define QSERDES_V4_COM_VCO_TUNE_MAP                     0x10c
#define QSERDES_V4_COM_VCO_TUNE_INITVAL2                0x124
#define QSERDES_V4_COM_HSCLK_SEL                        0x158
#define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL              0x15c
#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0       0x1ac
#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0       0x1b0
#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1       0x1b4
#define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL             0x1bc
#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1       0x1b8

/* Only for QMP V4 PHY - TX registers */
#define QSERDES_V4_TX_LANE_MODE_1                       0x84
#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1        0xd8
#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1        0xdC
#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1        0xe0
#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1        0xe4
#define QSERDES_V4_TX_TRAN_DRVR_EMP_EN                  0xb8

/* Only for QMP V4 PHY - RX registers */
#define QSERDES_V4_RX_UCDR_FO_GAIN                      0x008
#define QSERDES_V4_RX_UCDR_SO_GAIN                      0x014
#define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN             0x030
#define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE     0x034
#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW           0x03c
#define QSERDES_V4_RX_UCDR_PI_CONTROLS                  0x044
#define QSERDES_V4_RX_UCDR_PI_CTRL2                     0x048
#define QSERDES_V4_RX_AC_JTAG_ENABLE                    0x068
#define QSERDES_V4_RX_AC_JTAG_MODE                      0x078
#define QSERDES_V4_RX_RX_TERM_BW                        0x080
#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2             0x0ec
#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3             0x0f0
#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4             0x0f4
#define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW               0x0f8
#define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH              0x0fc
#define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME              0x100
#define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2          0x114
#define QSERDES_V4_RX_SIGDET_CNTRL                      0x11c
#define QSERDES_V4_RX_SIGDET_LVL                        0x120
#define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL             0x124
#define QSERDES_V4_RX_RX_BAND                           0x128
#define QSERDES_V4_RX_RX_MODE_00_LOW                    0x170
#define QSERDES_V4_RX_RX_MODE_00_HIGH                   0x174
#define QSERDES_V4_RX_RX_MODE_00_HIGH2                  0x178
#define QSERDES_V4_RX_RX_MODE_00_HIGH3                  0x17c
#define QSERDES_V4_RX_RX_MODE_00_HIGH4                  0x180
#define QSERDES_V4_RX_RX_MODE_01_LOW                    0x184
#define QSERDES_V4_RX_RX_MODE_01_HIGH                   0x188
#define QSERDES_V4_RX_RX_MODE_01_HIGH2                  0x18c
#define QSERDES_V4_RX_RX_MODE_01_HIGH3                  0x190
#define QSERDES_V4_RX_RX_MODE_01_HIGH4                  0x194
#define QSERDES_V4_RX_RX_MODE_10_LOW                    0x198
#define QSERDES_V4_RX_RX_MODE_10_HIGH                   0x19c
#define QSERDES_V4_RX_RX_MODE_10_HIGH2                  0x1a0
#define QSERDES_V4_RX_RX_MODE_10_HIGH3                  0x1a4
#define QSERDES_V4_RX_RX_MODE_10_HIGH4                  0x1a8
#define QSERDES_V4_RX_DCC_CTRL1                         0x1bc

/* Only for QMP V4 PHY - PCS registers */
#define QPHY_V4_PHY_START                               0x000
#define QPHY_V4_POWER_DOWN_CONTROL                      0x004
#define QPHY_V4_SW_RESET                                0x008
#define QPHY_V4_TIMER_20US_CORECLK_STEPS_MSB            0x00c
#define QPHY_V4_TIMER_20US_CORECLK_STEPS_LSB            0x010
#define QPHY_V4_PLL_CNTL                                0x02c
#define QPHY_V4_TX_LARGE_AMP_DRV_LVL                    0x030
#define QPHY_V4_TX_SMALL_AMP_DRV_LVL                    0x038
#define QPHY_V4_BIST_FIXED_PAT_CTRL                     0x060
#define QPHY_V4_TX_HSGEAR_CAPABILITY                    0x074
#define QPHY_V4_RX_HSGEAR_CAPABILITY                    0x0b4
#define QPHY_V4_DEBUG_BUS_CLKSEL                        0x124
#define QPHY_V4_LINECFG_DISABLE                         0x148
#define QPHY_V4_RX_MIN_HIBERN8_TIME                     0x150
#define QPHY_V4_RX_SIGDET_CTRL2                         0x158
#define QPHY_V4_TX_PWM_GEAR_BAND                        0x160
#define QPHY_V4_TX_HS_GEAR_BAND                         0x168
#define QPHY_V4_PCS_READY_STATUS                        0x180
#define QPHY_V4_TX_MID_TERM_CTRL1                       0x1d8
#define QPHY_V4_MULTI_LANE_CTRL1                        0x1e0

/* PCIE GEN3 COM registers */
#define PCIE_GEN3_QHP_COM_SSC_EN_CENTER                 0x14
#define PCIE_GEN3_QHP_COM_SSC_PER1                      0x20
#define PCIE_GEN3_QHP_COM_SSC_PER2                      0x24
#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1                0x28
#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2                0x2c
#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1          0x34
#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1          0x38
#define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN            0x54
#define PCIE_GEN3_QHP_COM_CLK_ENABLE1                   0x58
#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0               0x6c
#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0               0x70
#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1               0x78
#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1               0x7c
#define PCIE_GEN3_QHP_COM_BGV_TRIM                      0x98
#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0                 0xb4
#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1                 0xb8
#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0               0xc0
#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1               0xc4
#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0               0xcc
#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1               0xd0
#define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL                 0xdc
#define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2                 0xf0
#define PCIE_GEN3_QHP_COM_LOCK_CMP_EN                   0xf8
#define PCIE_GEN3_QHP_COM_DEC_START_MODE0               0x100
#define PCIE_GEN3_QHP_COM_DEC_START_MODE1               0x108
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0         0x11c
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0         0x120
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0         0x124
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1         0x128
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1         0x12c
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1         0x130
#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0         0x150
#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1         0x158
#define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP                  0x178
#define PCIE_GEN3_QHP_COM_BG_CTRL                       0x1c8
#define PCIE_GEN3_QHP_COM_CLK_SELECT                    0x1cc
#define PCIE_GEN3_QHP_COM_HSCLK_SEL1                    0x1d0
#define PCIE_GEN3_QHP_COM_CORECLK_DIV                   0x1e0
#define PCIE_GEN3_QHP_COM_CORE_CLK_EN                   0x1e8
#define PCIE_GEN3_QHP_COM_CMN_CONFIG                    0x1f0
#define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL              0x1fc
#define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1             0x21c
#define PCIE_GEN3_QHP_COM_CMN_MODE                      0x224
#define PCIE_GEN3_QHP_COM_VREGCLK_DIV1                  0x228
#define PCIE_GEN3_QHP_COM_VREGCLK_DIV2                  0x22c

/* PCIE GEN3 QHP Lane registers */
#define PCIE_GEN3_QHP_L0_DRVR_CTRL0                     0xc
#define PCIE_GEN3_QHP_L0_DRVR_CTRL1                     0x10
#define PCIE_GEN3_QHP_L0_DRVR_CTRL2                     0x14
#define PCIE_GEN3_QHP_L0_DRVR_TAP_EN                    0x18
#define PCIE_GEN3_QHP_L0_TX_BAND_MODE                   0x60
#define PCIE_GEN3_QHP_L0_LANE_MODE                      0x64
#define PCIE_GEN3_QHP_L0_PARALLEL_RATE                  0x7c
#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0                 0xc0
#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1                 0xc4
#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2                 0xc8
#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1              0xd0
#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2              0xd4
#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0               0xd8
#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1               0xdc
#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2               0xe0
#define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE                0xfc
#define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE                 0x100
#define PCIE_GEN3_QHP_L0_RXENGINE_EN0                   0x108
#define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME                0x114
#define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME            0x118
#define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME               0x11c
#define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME                0x120
#define PCIE_GEN3_QHP_L0_VGA_GAIN                       0x124
#define PCIE_GEN3_QHP_L0_DFE_GAIN                       0x128
#define PCIE_GEN3_QHP_L0_EQ_GAIN                        0x130
#define PCIE_GEN3_QHP_L0_OFFSET_GAIN                    0x134
#define PCIE_GEN3_QHP_L0_PRE_GAIN                       0x138
#define PCIE_GEN3_QHP_L0_VGA_INITVAL                    0x13c
#define PCIE_GEN3_QHP_L0_EQ_INTVAL                      0x154
#define PCIE_GEN3_QHP_L0_EDAC_INITVAL                   0x160
#define PCIE_GEN3_QHP_L0_RXEQ_INITB0                    0x168
#define PCIE_GEN3_QHP_L0_RXEQ_INITB1                    0x16c
#define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1               0x178
#define PCIE_GEN3_QHP_L0_RXEQ_CTRL                      0x180
#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0             0x184
#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1             0x188
#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2             0x18c
#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0             0x190
#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1             0x194
#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2             0x198
#define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG                 0x19c
#define PCIE_GEN3_QHP_L0_RX_BAND                        0x1a4
#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0            0x1c0
#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1            0x1c4
#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2            0x1c8
#define PCIE_GEN3_QHP_L0_SIGDET_ENABLES                 0x230
#define PCIE_GEN3_QHP_L0_SIGDET_CNTRL                   0x234
#define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL          0x238
#define PCIE_GEN3_QHP_L0_DCC_GAIN                       0x2a4
#define PCIE_GEN3_QHP_L0_RSM_START                      0x2a8
#define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL                   0x2ac
#define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL                  0x2b0
#define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0                 0x2b8
#define PCIE_GEN3_QHP_L0_TS0_TIMER                      0x2c0
#define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE               0x2c4
#define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET            0x2cc

/* PCIE GEN3 PCS registers */
#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB          0x2c
#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB          0x40
#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB            0x54
#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB            0x68
#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG            0x15c
#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5           0x16c
#define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG              0x174

#endif