drivers/phy/qualcomm/phy-qcom-qmp.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_address.h>
  17 #include <linux/phy/phy.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/reset.h>
  21 #include <linux/slab.h>
  22
  23 #include <dt-bindings/phy/phy.h>
  24
  25 #include "phy-qcom-qmp.h"
  26
  27 /* QPHY_SW_RESET bit */
  28 #define SW_RESET                                BIT(0)
  29 /* QPHY_POWER_DOWN_CONTROL */
  30 #define SW_PWRDN                                BIT(0)
  31 #define REFCLK_DRV_DSBL                         BIT(1)
  32 /* QPHY_START_CONTROL bits */
  33 #define SERDES_START                            BIT(0)
  34 #define PCS_START                               BIT(1)
  35 #define PLL_READY_GATE_EN                       BIT(3)
  36 /* QPHY_PCS_STATUS bit */
  37 #define PHYSTATUS                               BIT(6)
  38 /* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
  39 #define PCS_READY                               BIT(0)
  40
  41 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
  42 /* DP PHY soft reset */
  43 #define SW_DPPHY_RESET                          BIT(0)
  44 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
  45 #define SW_DPPHY_RESET_MUX                      BIT(1)
  46 /* USB3 PHY soft reset */
  47 #define SW_USB3PHY_RESET                        BIT(2)
  48 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
  49 #define SW_USB3PHY_RESET_MUX                    BIT(3)
  50
  51 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
  52 #define USB3_MODE                               BIT(0) /* enables USB3 mode */
  53 #define DP_MODE                                 BIT(1) /* enables DP mode */
  54
  55 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
  56 #define ARCVR_DTCT_EN                           BIT(0)
  57 #define ALFPS_DTCT_EN                           BIT(1)
  58 #define ARCVR_DTCT_EVENT_SEL                    BIT(4)
  59
  60 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
  61 #define IRQ_CLEAR                               BIT(0)
  62
  63 /* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
  64 #define RCVR_DETECT                             BIT(0)
  65
  66 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
  67 #define CLAMP_EN                                BIT(0) /* enables i/o clamp_n */
  68
  69 #define PHY_INIT_COMPLETE_TIMEOUT               10000
  70 #define POWER_DOWN_DELAY_US_MIN                 10
  71 #define POWER_DOWN_DELAY_US_MAX                 11
  72
  73 #define MAX_PROP_NAME                           32
  74
  75 /* Define the assumed distance between lanes for underspecified device trees. */
  76 #define QMP_PHY_LEGACY_LANE_STRIDE              0x400
  77
  78 struct qmp_phy_init_tbl {
  79         unsigned int offset;
  80         unsigned int val;
  81         /*
  82          * register part of layout ?
  83          * if yes, then offset gives index in the reg-layout
  84          */
  85         int in_layout;
  86 };
  87
  88 #define QMP_PHY_INIT_CFG(o, v)          \
  89         {                               \
  90                 .offset = o,            \
  91                 .val = v,               \
  92         }
  93
  94 #define QMP_PHY_INIT_CFG_L(o, v)        \
  95         {                               \
  96                 .offset = o,            \
  97                 .val = v,               \
  98                 .in_layout = 1,         \
  99         }
 100
 101 /* set of registers with offsets different per-PHY */
 102 enum qphy_reg_layout {
 103         /* Common block control registers */
 104         QPHY_COM_SW_RESET,
 105         QPHY_COM_POWER_DOWN_CONTROL,
 106         QPHY_COM_START_CONTROL,
 107         QPHY_COM_PCS_READY_STATUS,
 108         /* PCS registers */
 109         QPHY_PLL_LOCK_CHK_DLY_TIME,
 110         QPHY_FLL_CNTRL1,
 111         QPHY_FLL_CNTRL2,
 112         QPHY_FLL_CNT_VAL_L,
 113         QPHY_FLL_CNT_VAL_H_TOL,
 114         QPHY_FLL_MAN_CODE,
 115         QPHY_SW_RESET,
 116         QPHY_START_CTRL,
 117         QPHY_PCS_READY_STATUS,
 118         QPHY_PCS_STATUS,
 119         QPHY_PCS_AUTONOMOUS_MODE_CTRL,
 120         QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
 121         QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
 122 };
 123
 124 static const unsigned int msm8996_ufsphy_regs_layout[] = {
 125         [QPHY_START_CTRL]               = 0x00,
 126         [QPHY_PCS_READY_STATUS]         = 0x168,
 127 };
 128
 129 static const unsigned int pciephy_regs_layout[] = {
 130         [QPHY_COM_SW_RESET]             = 0x400,
 131         [QPHY_COM_POWER_DOWN_CONTROL]   = 0x404,
 132         [QPHY_COM_START_CONTROL]        = 0x408,
 133         [QPHY_COM_PCS_READY_STATUS]     = 0x448,
 134         [QPHY_PLL_LOCK_CHK_DLY_TIME]    = 0xa8,
 135         [QPHY_FLL_CNTRL1]               = 0xc4,
 136         [QPHY_FLL_CNTRL2]               = 0xc8,
 137         [QPHY_FLL_CNT_VAL_L]            = 0xcc,
 138         [QPHY_FLL_CNT_VAL_H_TOL]        = 0xd0,
 139         [QPHY_FLL_MAN_CODE]             = 0xd4,
 140         [QPHY_SW_RESET]                 = 0x00,
 141         [QPHY_START_CTRL]               = 0x08,
 142         [QPHY_PCS_STATUS]               = 0x174,
 143 };
 144
 145 static const unsigned int usb3phy_regs_layout[] = {
 146         [QPHY_FLL_CNTRL1]               = 0xc0,
 147         [QPHY_FLL_CNTRL2]               = 0xc4,
 148         [QPHY_FLL_CNT_VAL_L]            = 0xc8,
 149         [QPHY_FLL_CNT_VAL_H_TOL]        = 0xcc,
 150         [QPHY_FLL_MAN_CODE]             = 0xd0,
 151         [QPHY_SW_RESET]                 = 0x00,
 152         [QPHY_START_CTRL]               = 0x08,
 153         [QPHY_PCS_STATUS]               = 0x17c,
 154         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
 155         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0d8,
 156         [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
 157 };
 158
 159 static const unsigned int qmp_v3_usb3phy_regs_layout[] = {
 160         [QPHY_SW_RESET]                 = 0x00,
 161         [QPHY_START_CTRL]               = 0x08,
 162         [QPHY_PCS_STATUS]               = 0x174,
 163         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
 164         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0dc,
 165         [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
 166 };
 167
 168 static const unsigned int sdm845_qmp_pciephy_regs_layout[] = {
 169         [QPHY_SW_RESET]                 = 0x00,
 170         [QPHY_START_CTRL]               = 0x08,
 171         [QPHY_PCS_STATUS]               = 0x174,
 172 };
 173
 174 static const unsigned int sdm845_qhp_pciephy_regs_layout[] = {
 175         [QPHY_SW_RESET]                 = 0x00,
 176         [QPHY_START_CTRL]               = 0x08,
 177         [QPHY_PCS_STATUS]               = 0x2ac,
 178 };
 179
 180 static const unsigned int sdm845_ufsphy_regs_layout[] = {
 181         [QPHY_START_CTRL]               = 0x00,
 182         [QPHY_PCS_READY_STATUS]         = 0x160,
 183 };
 184
 185 static const unsigned int sm8150_ufsphy_regs_layout[] = {
 186         [QPHY_START_CTRL]               = QPHY_V4_PHY_START,
 187         [QPHY_PCS_READY_STATUS]         = QPHY_V4_PCS_READY_STATUS,
 188         [QPHY_SW_RESET]                 = QPHY_V4_SW_RESET,
 189 };
 190
 191 static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
 192         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
 193         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 194         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 195         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 196         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
 197         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 198         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 199         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
 200         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
 201         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 202         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 203         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
 204         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
 205         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 206         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 207         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 208         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 209         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 210         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
 211         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
 212         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 213         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
 214         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
 215         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
 216         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 217         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 218         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 219         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 220         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 221         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 222         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 223         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 224         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
 225         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 226         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
 227         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
 228         QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
 229         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 230         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 231         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
 232         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 233         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 234         QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
 235 };
 236
 237 static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
 238         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 239         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 240 };
 241
 242 static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
 243         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
 244         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
 245         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
 246         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
 247         QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
 248         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 249         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
 250         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 251         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 252         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
 253 };
 254
 255 static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
 256         QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
 257         QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
 258         QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 259
 260         QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
 261
 262         QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
 263         QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
 264         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
 265         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
 266         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
 267 };
 268
 269 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
 270         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
 271         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 272         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
 273         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 274         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
 275         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
 276         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 277         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 278         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 279         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
 280         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
 281         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 282         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 283         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 284         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
 285         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
 286         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 287         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
 288         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
 289         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
 290         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 291         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
 292         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
 293         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 294         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
 295         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 296         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
 297         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 298         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
 299         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 300         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
 301         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
 302         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 303         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 304         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
 305         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 306         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
 307         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 308         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
 309         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 310         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
 311         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
 312 };
 313
 314 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
 315         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
 316         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 317         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 318         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
 319 };
 320
 321 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
 322         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 323         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
 324         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 325         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
 326         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 327         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
 328         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 329         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
 330         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
 331         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
 332         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 333         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 334         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
 335         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
 336 };
 337
 338 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
 339         QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
 340         QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
 341         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
 342         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 343         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
 344         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 345         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 346         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
 347         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
 348         QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
 349 };
 350
 351 static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
 352         QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
 353         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
 354         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
 355         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 356         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
 357         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 358         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 359         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
 360         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
 361         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
 362         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
 363         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
 364         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
 365         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 366         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 367         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 368         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
 369         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
 370         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
 371         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 372         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
 373         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
 374         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
 375         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 376         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 377         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 378         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 379         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 380         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
 381         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
 382         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
 383         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
 384         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 385         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
 386         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
 387         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
 388         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
 389         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
 390         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
 391         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
 392         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
 393         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
 394         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
 395         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
 396         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
 397         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
 398         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
 399 };
 400
 401 static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
 402         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 403         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
 404 };
 405
 406 static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
 407         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
 408         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
 409         QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
 410         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
 411         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
 412         QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
 413         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
 414         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
 415         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
 416         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
 417         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
 418 };
 419
 420 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
 421         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
 422         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 423         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 424         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 425         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 426         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 427         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 428         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 429         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
 430         /* PLL and Loop filter settings */
 431         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 432         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 433         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 434         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 435         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 436         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 437         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 438         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 439         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
 440         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 441         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 442         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 443         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 444         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 445         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 446         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 447         /* SSC settings */
 448         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 449         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 450         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 451         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 452         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 453         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 454         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 455 };
 456
 457 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
 458         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 459         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 460         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 461 };
 462
 463 static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
 464         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 465         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 466         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 467         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 468         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
 469         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 470         QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 471         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 472         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
 473         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 474 };
 475
 476 static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
 477         /* FLL settings */
 478         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
 479         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
 480         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
 481         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
 482         QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
 483
 484         /* Lock Det settings */
 485         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
 486         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
 487         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
 488         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
 489 };
 490
 491 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
 492         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
 493         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 494         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
 495         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
 496         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
 497         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0x1f),
 498         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
 499         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
 500         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
 501         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
 502         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
 503         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
 504         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
 505         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
 506         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
 507         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
 508         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 509         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
 510         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 511         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 512         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
 513         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
 514         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
 515         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 516         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
 517         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
 518         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
 519         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 520         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 521         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
 522         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 523         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
 524         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0xa),
 525         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
 526         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 527         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
 528         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
 529         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
 530         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
 531         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
 532         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
 533         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x7),
 534 };
 535
 536 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
 537         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 538         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
 539         QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
 540         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 541 };
 542
 543 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
 544         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
 545         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 546         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
 547         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
 548         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
 549         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 550         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
 551         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4),
 552 };
 553
 554 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
 555         QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
 556         QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
 557         QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
 558         QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
 559         QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
 560         QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
 561         QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
 562         QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
 563         QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
 564         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
 565         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
 566         QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
 567         QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
 568 };
 569
 570 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
 571         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
 572         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 573         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
 574         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 575         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
 576         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
 577         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 578         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 579         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 580         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
 581         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
 582         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 583         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 584         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 585         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
 586         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
 587         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 588         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 589         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 590         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 591         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 592         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
 593         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
 594         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 595         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 596         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 597         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 598         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
 599         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
 600         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 601         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
 602         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
 603         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 604         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 605         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
 606         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 607         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
 608         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 609         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
 610         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 611         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
 612         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
 613 };
 614
 615 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
 616         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
 617         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 618         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 619         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
 620 };
 621
 622 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
 623         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 624         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
 625         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 626         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
 627         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 628         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
 629         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 630         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
 631         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
 632         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
 633         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
 634         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
 635         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 636         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 637         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
 638         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
 639 };
 640
 641 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
 642         QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
 643
 644         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 645         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 646         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 647         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 648         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 649
 650         QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
 651         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
 652         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 653         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
 654         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 655         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 656         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
 657
 658         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
 659         QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
 660         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
 661
 662         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
 663 };
 664
 665 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
 666         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
 667         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
 668         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
 669         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
 670         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
 671 };
 672
 673 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
 674         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
 675         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
 676         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
 677         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
 678         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
 679         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
 680         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
 681         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
 682         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
 683         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
 684         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
 685         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
 686         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
 687         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
 688         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
 689         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
 690         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
 691         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
 692         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
 693         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
 694         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
 695         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
 696         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
 697         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
 698         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
 699         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
 700         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
 701         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
 702         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
 703         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
 704         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 705         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
 706         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
 707         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
 708         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
 709         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
 710         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
 711         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
 712         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
 713         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
 714         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
 715         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
 716         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
 717         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
 718         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
 719 };
 720
 721 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
 722         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
 723         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
 724         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
 725         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
 726         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
 727         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
 728         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
 729         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
 730         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
 731         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
 732         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
 733         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
 734         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
 735         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
 736         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
 737         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
 738         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
 739         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
 740         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
 741         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
 742         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
 743         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
 744         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
 745         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
 746         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
 747         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
 748         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
 749         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
 750         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
 751         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
 752         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
 753         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
 754         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
 755         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
 756         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
 757         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
 758         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
 759         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
 760         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
 761         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
 762         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
 763         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
 764         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
 765         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
 766         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
 767         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
 768         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
 769         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
 770         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
 771         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
 772         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
 773         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
 774         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
 775         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
 776         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
 777         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
 778 };
 779
 780 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
 781 };
 782
 783 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
 784         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
 785         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
 786         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
 787         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
 788         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
 789         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
 790         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
 791 };
 792
 793 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
 794         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 795         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 796         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 797         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 798         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 799         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 800         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
 801         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 802         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 803         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 804         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 805         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 806         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 807         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 808         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 809         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 810         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 811         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 812         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 813         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 814         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 815         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 816         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 817         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 818         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 819         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 820         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 821         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 822         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
 823         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 824         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 825         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 826         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 827         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 828         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 829         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 830 };
 831
 832 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
 833         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 834         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 835         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
 836         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
 837         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
 838 };
 839
 840 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
 841         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 842         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 843         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 844         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 845         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 846         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 847         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 848         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 849         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 850 };
 851
 852 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
 853         /* FLL settings */
 854         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 855         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 856         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 857         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 858         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 859
 860         /* Lock Det settings */
 861         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 862         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 863         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 864         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 865
 866         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
 867         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 868         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 869         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
 870         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
 871         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
 872         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
 873         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 874         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 875         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 876         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 877         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 878         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 879         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 880         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
 881         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 882         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 883         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 884         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 885
 886         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 887         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 888         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 889         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 890         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 891         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 892         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 893         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 894         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 895         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 896         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 897 };
 898
 899 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
 900         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 901         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 902         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
 903         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 904         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 905         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 906         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 907         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 908         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 909         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 910         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 911         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 912         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 913         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 914         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 915         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 916         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 917         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 918         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 919         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 920         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 921         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 922         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 923         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 924         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 925         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 926         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 927         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 928         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
 929         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 930         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 931         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 932         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 933         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 934         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 935         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 936 };
 937
 938 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
 939         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 940         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 941         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
 942         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
 943         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
 944 };
 945
 946 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
 947         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
 948         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
 949         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 950         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
 951         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 952         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 953         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 954         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 955         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 956         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
 957         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 958 };
 959
 960 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
 961         /* FLL settings */
 962         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 963         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 964         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 965         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 966         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 967
 968         /* Lock Det settings */
 969         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 970         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 971         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 972         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 973
 974         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
 975         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 976         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 977         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
 978         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
 979         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
 980         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
 981         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 982         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 983         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 984         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 985         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 986         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 987         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 988         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
 989         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 990         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 991         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 992         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 993
 994         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 995         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 996         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 997         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 998         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 999         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1000         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1001         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1002         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1003         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1004         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1005
1006         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
1007         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
1008 };
1009
1010 static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
1011         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1012         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1013         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1014         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1015         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1016         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
1017         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
1018         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1019         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
1020         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
1021         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
1022         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1023         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
1024         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
1025         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
1026         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
1027         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1028         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1029         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1030         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1031         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1032         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1033         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
1034         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1035         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
1036         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
1037         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
1038         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
1039         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
1040         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
1041         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
1042         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
1043         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
1044         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
1045         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
1046         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
1047
1048         /* Rate B */
1049         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
1050 };
1051
1052 static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
1053         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
1054         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
1055         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
1056 };
1057
1058 static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
1059         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
1060         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
1061         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1062         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
1063         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1064         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
1065         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
1066         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
1067         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
1068         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
1069         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
1070         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
1071         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
1072         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
1073         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
1074         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
1075 };
1076
1077 static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
1078         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
1079         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
1080         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
1081         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
1082         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
1083         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
1084         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
1085         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
1086 };
1087
1088 static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
1089         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1090         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1091         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1092         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
1093         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1094         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1095         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1096         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1097         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1098         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1099         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1100         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1101         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1102         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1103         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1104         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1105         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1106         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1107         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1108         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1109         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1110         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1111         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1112         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1113         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1114         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1115         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1116         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1117         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1118         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
1119         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
1120         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1121         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1122         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1123         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1124         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1125         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1126         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1127 };
1128
1129 static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
1130         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1131         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1132         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
1133         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
1134 };
1135
1136 static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
1137         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1138         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1139         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1140         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1141         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
1142         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1143         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
1144         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
1145         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1146         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
1147         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
1148         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
1149         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
1150         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
1151         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
1152         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
1153         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
1154 };
1155
1156 static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
1157         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1158         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1159         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1160         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1161         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1162         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1163         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1164         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1165         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1166         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1167         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1168         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
1169         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
1170         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
1171         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
1172         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1173         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1174         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
1175         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1176         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1177         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1178         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1179         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
1180         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1181         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1182         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1183         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1184         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1185         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1186         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1187         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1188         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1189         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1190         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1191         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
1192         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1193         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1194         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1195 };
1196
1197 static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
1198         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
1199         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
1200         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1201         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
1202         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1203         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1204         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
1205         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1206         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1207         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1208         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1209         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1210         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
1211         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
1212         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
1213         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1214         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
1215         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1216         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1217         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1218         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
1219         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
1220         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
1221         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
1222
1223         /* Rate B */
1224         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
1225 };
1226
1227 static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
1228         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
1229         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
1230         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
1231         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
1232         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
1233         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
1234 };
1235
1236 static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
1237         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
1238         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
1239         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1240         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
1241         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
1242         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
1243         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
1244         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
1245         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
1246         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
1247         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
1248         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
1249         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
1250         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
1251         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
1252         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
1253         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
1254         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1255         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1256         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
1257         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
1258         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
1259         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
1260         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
1261         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
1262         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
1263         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
1264         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
1265         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
1266         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
1267         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
1268         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
1269         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
1270         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
1271
1272 };
1273
1274 static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
1275         QMP_PHY_INIT_CFG(QPHY_V4_RX_SIGDET_CTRL2, 0x6d),
1276         QMP_PHY_INIT_CFG(QPHY_V4_TX_LARGE_AMP_DRV_LVL, 0x0a),
1277         QMP_PHY_INIT_CFG(QPHY_V4_TX_SMALL_AMP_DRV_LVL, 0x02),
1278         QMP_PHY_INIT_CFG(QPHY_V4_TX_MID_TERM_CTRL1, 0x43),
1279         QMP_PHY_INIT_CFG(QPHY_V4_DEBUG_BUS_CLKSEL, 0x1f),
1280         QMP_PHY_INIT_CFG(QPHY_V4_RX_MIN_HIBERN8_TIME, 0xff),
1281         QMP_PHY_INIT_CFG(QPHY_V4_MULTI_LANE_CTRL1, 0x02),
1282 };
1283
1284 /* struct qmp_phy_cfg - per-PHY initialization config */
1285 struct qmp_phy_cfg {
1286         /* phy-type - PCIE/UFS/USB */
1287         unsigned int type;
1288         /* number of lanes provided by phy */
1289         int nlanes;
1290
1291         /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1292         const struct qmp_phy_init_tbl *serdes_tbl;
1293         int serdes_tbl_num;
1294         const struct qmp_phy_init_tbl *tx_tbl;
1295         int tx_tbl_num;
1296         const struct qmp_phy_init_tbl *rx_tbl;
1297         int rx_tbl_num;
1298         const struct qmp_phy_init_tbl *pcs_tbl;
1299         int pcs_tbl_num;
1300         const struct qmp_phy_init_tbl *pcs_misc_tbl;
1301         int pcs_misc_tbl_num;
1302
1303         /* clock ids to be requested */
1304         const char * const *clk_list;
1305         int num_clks;
1306         /* resets to be requested */
1307         const char * const *reset_list;
1308         int num_resets;
1309         /* regulators to be requested */
1310         const char * const *vreg_list;
1311         int num_vregs;
1312
1313         /* array of registers with different offsets */
1314         const unsigned int *regs;
1315
1316         unsigned int start_ctrl;
1317         unsigned int pwrdn_ctrl;
1318         unsigned int mask_com_pcs_ready;
1319
1320         /* true, if PHY has a separate PHY_COM control block */
1321         bool has_phy_com_ctrl;
1322         /* true, if PHY has a reset for individual lanes */
1323         bool has_lane_rst;
1324         /* true, if PHY needs delay after POWER_DOWN */
1325         bool has_pwrdn_delay;
1326         /* power_down delay in usec */
1327         int pwrdn_delay_min;
1328         int pwrdn_delay_max;
1329
1330         /* true, if PHY has a separate DP_COM control block */
1331         bool has_phy_dp_com_ctrl;
1332         /* true, if PHY has secondary tx/rx lanes to be configured */
1333         bool is_dual_lane_phy;
1334
1335         /* true, if PCS block has no separate SW_RESET register */
1336         bool no_pcs_sw_reset;
1337 };
1338
1339 /**
1340  * struct qmp_phy - per-lane phy descriptor
1341  *
1342  * @phy: generic phy
1343  * @tx: iomapped memory space for lane's tx
1344  * @rx: iomapped memory space for lane's rx
1345  * @pcs: iomapped memory space for lane's pcs
1346  * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
1347  * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
1348  * @pcs_misc: iomapped memory space for lane's pcs_misc
1349  * @pipe_clk: pipe lock
1350  * @index: lane index
1351  * @qmp: QMP phy to which this lane belongs
1352  * @lane_rst: lane's reset controller
1353  */
1354 struct qmp_phy {
1355         struct phy *phy;
1356         void __iomem *tx;
1357         void __iomem *rx;
1358         void __iomem *pcs;
1359         void __iomem *tx2;
1360         void __iomem *rx2;
1361         void __iomem *pcs_misc;
1362         struct clk *pipe_clk;
1363         unsigned int index;
1364         struct qcom_qmp *qmp;
1365         struct reset_control *lane_rst;
1366 };
1367
1368 /**
1369  * struct qcom_qmp - structure holding QMP phy block attributes
1370  *
1371  * @dev: device
1372  * @serdes: iomapped memory space for phy's serdes
1373  * @dp_com: iomapped memory space for phy's dp_com control block
1374  *
1375  * @clks: array of clocks required by phy
1376  * @resets: array of resets required by phy
1377  * @vregs: regulator supplies bulk data
1378  *
1379  * @cfg: phy specific configuration
1380  * @phys: array of per-lane phy descriptors
1381  * @phy_mutex: mutex lock for PHY common block initialization
1382  * @init_count: phy common block initialization count
1383  * @phy_initialized: indicate if PHY has been initialized
1384  * @mode: current PHY mode
1385  * @ufs_reset: optional UFS PHY reset handle
1386  */
1387 struct qcom_qmp {
1388         struct device *dev;
1389         void __iomem *serdes;
1390         void __iomem *dp_com;
1391
1392         struct clk_bulk_data *clks;
1393         struct reset_control **resets;
1394         struct regulator_bulk_data *vregs;
1395
1396         const struct qmp_phy_cfg *cfg;
1397         struct qmp_phy **phys;
1398
1399         struct mutex phy_mutex;
1400         int init_count;
1401         bool phy_initialized;
1402         enum phy_mode mode;
1403
1404         struct reset_control *ufs_reset;
1405 };
1406
1407 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1408 {
1409         u32 reg;
1410
1411         reg = readl(base + offset);
1412         reg |= val;
1413         writel(reg, base + offset);
1414
1415         /* ensure that above write is through */
1416         readl(base + offset);
1417 }
1418
1419 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1420 {
1421         u32 reg;
1422
1423         reg = readl(base + offset);
1424         reg &= ~val;
1425         writel(reg, base + offset);
1426
1427         /* ensure that above write is through */
1428         readl(base + offset);
1429 }
1430
1431 /* list of clocks required by phy */
1432 static const char * const msm8996_phy_clk_l[] = {
1433         "aux", "cfg_ahb", "ref",
1434 };
1435
1436 static const char * const msm8996_ufs_phy_clk_l[] = {
1437         "ref",
1438 };
1439
1440 static const char * const qmp_v3_phy_clk_l[] = {
1441         "aux", "cfg_ahb", "ref", "com_aux",
1442 };
1443
1444 static const char * const sdm845_pciephy_clk_l[] = {
1445         "aux", "cfg_ahb", "ref", "refgen",
1446 };
1447
1448 static const char * const sdm845_ufs_phy_clk_l[] = {
1449         "ref", "ref_aux",
1450 };
1451
1452 /* list of resets */
1453 static const char * const msm8996_pciephy_reset_l[] = {
1454         "phy", "common", "cfg",
1455 };
1456
1457 static const char * const msm8996_usb3phy_reset_l[] = {
1458         "phy", "common",
1459 };
1460
1461 static const char * const sdm845_pciephy_reset_l[] = {
1462         "phy",
1463 };
1464
1465 /* list of regulators */
1466 static const char * const qmp_phy_vreg_l[] = {
1467         "vdda-phy", "vdda-pll",
1468 };
1469
1470 static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
1471         .type                   = PHY_TYPE_PCIE,
1472         .nlanes                 = 3,
1473
1474         .serdes_tbl             = msm8996_pcie_serdes_tbl,
1475         .serdes_tbl_num         = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
1476         .tx_tbl                 = msm8996_pcie_tx_tbl,
1477         .tx_tbl_num             = ARRAY_SIZE(msm8996_pcie_tx_tbl),
1478         .rx_tbl                 = msm8996_pcie_rx_tbl,
1479         .rx_tbl_num             = ARRAY_SIZE(msm8996_pcie_rx_tbl),
1480         .pcs_tbl                = msm8996_pcie_pcs_tbl,
1481         .pcs_tbl_num            = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
1482         .clk_list               = msm8996_phy_clk_l,
1483         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
1484         .reset_list             = msm8996_pciephy_reset_l,
1485         .num_resets             = ARRAY_SIZE(msm8996_pciephy_reset_l),
1486         .vreg_list              = qmp_phy_vreg_l,
1487         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1488         .regs                   = pciephy_regs_layout,
1489
1490         .start_ctrl             = PCS_START | PLL_READY_GATE_EN,
1491         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
1492         .mask_com_pcs_ready     = PCS_READY,
1493
1494         .has_phy_com_ctrl       = true,
1495         .has_lane_rst           = true,
1496         .has_pwrdn_delay        = true,
1497         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
1498         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
1499 };
1500
1501 static const struct qmp_phy_cfg msm8996_ufs_cfg = {
1502         .type                   = PHY_TYPE_UFS,
1503         .nlanes                 = 1,
1504
1505         .serdes_tbl             = msm8996_ufs_serdes_tbl,
1506         .serdes_tbl_num         = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
1507         .tx_tbl                 = msm8996_ufs_tx_tbl,
1508         .tx_tbl_num             = ARRAY_SIZE(msm8996_ufs_tx_tbl),
1509         .rx_tbl                 = msm8996_ufs_rx_tbl,
1510         .rx_tbl_num             = ARRAY_SIZE(msm8996_ufs_rx_tbl),
1511
1512         .clk_list               = msm8996_ufs_phy_clk_l,
1513         .num_clks               = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
1514
1515         .vreg_list              = qmp_phy_vreg_l,
1516         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1517
1518         .regs                   = msm8996_ufsphy_regs_layout,
1519
1520         .start_ctrl             = SERDES_START,
1521         .pwrdn_ctrl             = SW_PWRDN,
1522
1523         .no_pcs_sw_reset        = true,
1524 };
1525
1526 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
1527         .type                   = PHY_TYPE_USB3,
1528         .nlanes                 = 1,
1529
1530         .serdes_tbl             = msm8996_usb3_serdes_tbl,
1531         .serdes_tbl_num         = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
1532         .tx_tbl                 = msm8996_usb3_tx_tbl,
1533         .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1534         .rx_tbl                 = msm8996_usb3_rx_tbl,
1535         .rx_tbl_num             = ARRAY_SIZE(msm8996_usb3_rx_tbl),
1536         .pcs_tbl                = msm8996_usb3_pcs_tbl,
1537         .pcs_tbl_num            = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
1538         .clk_list               = msm8996_phy_clk_l,
1539         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
1540         .reset_list             = msm8996_usb3phy_reset_l,
1541         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1542         .vreg_list              = qmp_phy_vreg_l,
1543         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1544         .regs                   = usb3phy_regs_layout,
1545
1546         .start_ctrl             = SERDES_START | PCS_START,
1547         .pwrdn_ctrl             = SW_PWRDN,
1548 };
1549
1550 /* list of resets */
1551 static const char * const ipq8074_pciephy_reset_l[] = {
1552         "phy", "common",
1553 };
1554
1555 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
1556         .type                   = PHY_TYPE_PCIE,
1557         .nlanes                 = 1,
1558
1559         .serdes_tbl             = ipq8074_pcie_serdes_tbl,
1560         .serdes_tbl_num         = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
1561         .tx_tbl                 = ipq8074_pcie_tx_tbl,
1562         .tx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
1563         .rx_tbl                 = ipq8074_pcie_rx_tbl,
1564         .rx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
1565         .pcs_tbl                = ipq8074_pcie_pcs_tbl,
1566         .pcs_tbl_num            = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
1567         .clk_list               = NULL,
1568         .num_clks               = 0,
1569         .reset_list             = ipq8074_pciephy_reset_l,
1570         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1571         .vreg_list              = NULL,
1572         .num_vregs              = 0,
1573         .regs                   = pciephy_regs_layout,
1574
1575         .start_ctrl             = SERDES_START | PCS_START,
1576         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
1577
1578         .has_phy_com_ctrl       = false,
1579         .has_lane_rst           = false,
1580         .has_pwrdn_delay        = true,
1581         .pwrdn_delay_min        = 995,          /* us */
1582         .pwrdn_delay_max        = 1005,         /* us */
1583 };
1584
1585 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
1586         .type = PHY_TYPE_PCIE,
1587         .nlanes = 1,
1588
1589         .serdes_tbl             = sdm845_qmp_pcie_serdes_tbl,
1590         .serdes_tbl_num         = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
1591         .tx_tbl                 = sdm845_qmp_pcie_tx_tbl,
1592         .tx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
1593         .rx_tbl                 = sdm845_qmp_pcie_rx_tbl,
1594         .rx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
1595         .pcs_tbl                = sdm845_qmp_pcie_pcs_tbl,
1596         .pcs_tbl_num            = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
1597         .pcs_misc_tbl           = sdm845_qmp_pcie_pcs_misc_tbl,
1598         .pcs_misc_tbl_num       = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
1599         .clk_list               = sdm845_pciephy_clk_l,
1600         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
1601         .reset_list             = sdm845_pciephy_reset_l,
1602         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
1603         .vreg_list              = qmp_phy_vreg_l,
1604         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1605         .regs                   = sdm845_qmp_pciephy_regs_layout,
1606
1607         .start_ctrl             = PCS_START | SERDES_START,
1608         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
1609
1610         .has_pwrdn_delay        = true,
1611         .pwrdn_delay_min        = 995,          /* us */
1612         .pwrdn_delay_max        = 1005,         /* us */
1613 };
1614
1615 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
1616         .type = PHY_TYPE_PCIE,
1617         .nlanes = 1,
1618
1619         .serdes_tbl             = sdm845_qhp_pcie_serdes_tbl,
1620         .serdes_tbl_num         = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
1621         .tx_tbl                 = sdm845_qhp_pcie_tx_tbl,
1622         .tx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
1623         .rx_tbl                 = sdm845_qhp_pcie_rx_tbl,
1624         .rx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
1625         .pcs_tbl                = sdm845_qhp_pcie_pcs_tbl,
1626         .pcs_tbl_num            = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
1627         .clk_list               = sdm845_pciephy_clk_l,
1628         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
1629         .reset_list             = sdm845_pciephy_reset_l,
1630         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
1631         .vreg_list              = qmp_phy_vreg_l,
1632         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1633         .regs                   = sdm845_qhp_pciephy_regs_layout,
1634
1635         .start_ctrl             = PCS_START | SERDES_START,
1636         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
1637
1638         .has_pwrdn_delay        = true,
1639         .pwrdn_delay_min        = 995,          /* us */
1640         .pwrdn_delay_max        = 1005,         /* us */
1641 };
1642
1643 static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
1644         .type                   = PHY_TYPE_USB3,
1645         .nlanes                 = 1,
1646
1647         .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
1648         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1649         .tx_tbl                 = qmp_v3_usb3_tx_tbl,
1650         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1651         .rx_tbl                 = qmp_v3_usb3_rx_tbl,
1652         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1653         .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
1654         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1655         .clk_list               = qmp_v3_phy_clk_l,
1656         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
1657         .reset_list             = msm8996_usb3phy_reset_l,
1658         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1659         .vreg_list              = qmp_phy_vreg_l,
1660         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1661         .regs                   = qmp_v3_usb3phy_regs_layout,
1662
1663         .start_ctrl             = SERDES_START | PCS_START,
1664         .pwrdn_ctrl             = SW_PWRDN,
1665
1666         .has_pwrdn_delay        = true,
1667         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
1668         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
1669
1670         .has_phy_dp_com_ctrl    = true,
1671         .is_dual_lane_phy       = true,
1672 };
1673
1674 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
1675         .type                   = PHY_TYPE_USB3,
1676         .nlanes                 = 1,
1677
1678         .serdes_tbl             = qmp_v3_usb3_uniphy_serdes_tbl,
1679         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
1680         .tx_tbl                 = qmp_v3_usb3_uniphy_tx_tbl,
1681         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
1682         .rx_tbl                 = qmp_v3_usb3_uniphy_rx_tbl,
1683         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
1684         .pcs_tbl                = qmp_v3_usb3_uniphy_pcs_tbl,
1685         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
1686         .clk_list               = qmp_v3_phy_clk_l,
1687         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
1688         .reset_list             = msm8996_usb3phy_reset_l,
1689         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1690         .vreg_list              = qmp_phy_vreg_l,
1691         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1692         .regs                   = qmp_v3_usb3phy_regs_layout,
1693
1694         .start_ctrl             = SERDES_START | PCS_START,
1695         .pwrdn_ctrl             = SW_PWRDN,
1696
1697         .has_pwrdn_delay        = true,
1698         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
1699         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
1700 };
1701
1702 static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
1703         .type                   = PHY_TYPE_UFS,
1704         .nlanes                 = 2,
1705
1706         .serdes_tbl             = sdm845_ufsphy_serdes_tbl,
1707         .serdes_tbl_num         = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
1708         .tx_tbl                 = sdm845_ufsphy_tx_tbl,
1709         .tx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
1710         .rx_tbl                 = sdm845_ufsphy_rx_tbl,
1711         .rx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
1712         .pcs_tbl                = sdm845_ufsphy_pcs_tbl,
1713         .pcs_tbl_num            = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
1714         .clk_list               = sdm845_ufs_phy_clk_l,
1715         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1716         .vreg_list              = qmp_phy_vreg_l,
1717         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1718         .regs                   = sdm845_ufsphy_regs_layout,
1719
1720         .start_ctrl             = SERDES_START,
1721         .pwrdn_ctrl             = SW_PWRDN,
1722
1723         .is_dual_lane_phy       = true,
1724         .no_pcs_sw_reset        = true,
1725 };
1726
1727 static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
1728         .type                   = PHY_TYPE_PCIE,
1729         .nlanes                 = 1,
1730
1731         .serdes_tbl             = msm8998_pcie_serdes_tbl,
1732         .serdes_tbl_num         = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
1733         .tx_tbl                 = msm8998_pcie_tx_tbl,
1734         .tx_tbl_num             = ARRAY_SIZE(msm8998_pcie_tx_tbl),
1735         .rx_tbl                 = msm8998_pcie_rx_tbl,
1736         .rx_tbl_num             = ARRAY_SIZE(msm8998_pcie_rx_tbl),
1737         .pcs_tbl                = msm8998_pcie_pcs_tbl,
1738         .pcs_tbl_num            = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
1739         .clk_list               = msm8996_phy_clk_l,
1740         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
1741         .reset_list             = ipq8074_pciephy_reset_l,
1742         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1743         .vreg_list              = qmp_phy_vreg_l,
1744         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1745         .regs                   = pciephy_regs_layout,
1746
1747         .start_ctrl             = SERDES_START | PCS_START,
1748         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
1749 };
1750
1751 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
1752         .type                   = PHY_TYPE_USB3,
1753         .nlanes                 = 1,
1754
1755         .serdes_tbl             = msm8998_usb3_serdes_tbl,
1756         .serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
1757         .tx_tbl                 = msm8998_usb3_tx_tbl,
1758         .tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),
1759         .rx_tbl                 = msm8998_usb3_rx_tbl,
1760         .rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),
1761         .pcs_tbl                = msm8998_usb3_pcs_tbl,
1762         .pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
1763         .clk_list               = msm8996_phy_clk_l,
1764         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
1765         .reset_list             = msm8996_usb3phy_reset_l,
1766         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1767         .vreg_list              = qmp_phy_vreg_l,
1768         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1769         .regs                   = qmp_v3_usb3phy_regs_layout,
1770
1771         .start_ctrl             = SERDES_START | PCS_START,
1772         .pwrdn_ctrl             = SW_PWRDN,
1773
1774         .is_dual_lane_phy       = true,
1775 };
1776
1777 static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
1778         .type                   = PHY_TYPE_UFS,
1779         .nlanes                 = 2,
1780
1781         .serdes_tbl             = sm8150_ufsphy_serdes_tbl,
1782         .serdes_tbl_num         = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
1783         .tx_tbl                 = sm8150_ufsphy_tx_tbl,
1784         .tx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
1785         .rx_tbl                 = sm8150_ufsphy_rx_tbl,
1786         .rx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
1787         .pcs_tbl                = sm8150_ufsphy_pcs_tbl,
1788         .pcs_tbl_num            = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
1789         .clk_list               = sdm845_ufs_phy_clk_l,
1790         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1791         .vreg_list              = qmp_phy_vreg_l,
1792         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1793         .regs                   = sm8150_ufsphy_regs_layout,
1794
1795         .start_ctrl             = SERDES_START,
1796         .pwrdn_ctrl             = SW_PWRDN,
1797
1798         .is_dual_lane_phy       = true,
1799 };
1800
1801 static void qcom_qmp_phy_configure(void __iomem *base,
1802                                    const unsigned int *regs,
1803                                    const struct qmp_phy_init_tbl tbl[],
1804                                    int num)
1805 {
1806         int i;
1807         const struct qmp_phy_init_tbl *t = tbl;
1808
1809         if (!t)
1810                 return;
1811
1812         for (i = 0; i < num; i++, t++) {
1813                 if (t->in_layout)
1814                         writel(t->val, base + regs[t->offset]);
1815                 else
1816                         writel(t->val, base + t->offset);
1817         }
1818 }
1819
1820 static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
1821 {
1822         struct qcom_qmp *qmp = qphy->qmp;
1823         const struct qmp_phy_cfg *cfg = qmp->cfg;
1824         void __iomem *serdes = qmp->serdes;
1825         void __iomem *pcs = qphy->pcs;
1826         void __iomem *dp_com = qmp->dp_com;
1827         int ret, i;
1828
1829         mutex_lock(&qmp->phy_mutex);
1830         if (qmp->init_count++) {
1831                 mutex_unlock(&qmp->phy_mutex);
1832                 return 0;
1833         }
1834
1835         /* turn on regulator supplies */
1836         ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
1837         if (ret) {
1838                 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
1839                 goto err_reg_enable;
1840         }
1841
1842         for (i = 0; i < cfg->num_resets; i++) {
1843                 ret = reset_control_assert(qmp->resets[i]);
1844                 if (ret) {
1845                         dev_err(qmp->dev, "%s reset assert failed\n",
1846                                 cfg->reset_list[i]);
1847                         goto err_rst_assert;
1848                 }
1849         }
1850
1851         for (i = cfg->num_resets - 1; i >= 0; i--) {
1852                 ret = reset_control_deassert(qmp->resets[i]);
1853                 if (ret) {
1854                         dev_err(qmp->dev, "%s reset deassert failed\n",
1855                                 qmp->cfg->reset_list[i]);
1856                         goto err_rst;
1857                 }
1858         }
1859
1860         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
1861         if (ret) {
1862                 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
1863                 goto err_rst;
1864         }
1865
1866         if (cfg->has_phy_dp_com_ctrl) {
1867                 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
1868                              SW_PWRDN);
1869                 /* override hardware control for reset of qmp phy */
1870                 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
1871                              SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
1872                              SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
1873
1874                 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
1875                              USB3_MODE | DP_MODE);
1876
1877                 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
1878                 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
1879                              SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
1880                              SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
1881         }
1882
1883         if (cfg->has_phy_com_ctrl)
1884                 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
1885                              SW_PWRDN);
1886         else
1887                 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
1888
1889         /* Serdes configuration */
1890         qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl,
1891                                cfg->serdes_tbl_num);
1892
1893         if (cfg->has_phy_com_ctrl) {
1894                 void __iomem *status;
1895                 unsigned int mask, val;
1896
1897                 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
1898                 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
1899                              SERDES_START | PCS_START);
1900
1901                 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
1902                 mask = cfg->mask_com_pcs_ready;
1903
1904                 ret = readl_poll_timeout(status, val, (val & mask), 10,
1905                                          PHY_INIT_COMPLETE_TIMEOUT);
1906                 if (ret) {
1907                         dev_err(qmp->dev,
1908                                 "phy common block init timed-out\n");
1909                         goto err_com_init;
1910                 }
1911         }
1912
1913         mutex_unlock(&qmp->phy_mutex);
1914
1915         return 0;
1916
1917 err_com_init:
1918         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1919 err_rst:
1920         while (++i < cfg->num_resets)
1921                 reset_control_assert(qmp->resets[i]);
1922 err_rst_assert:
1923         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1924 err_reg_enable:
1925         mutex_unlock(&qmp->phy_mutex);
1926
1927         return ret;
1928 }
1929
1930 static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp)
1931 {
1932         const struct qmp_phy_cfg *cfg = qmp->cfg;
1933         void __iomem *serdes = qmp->serdes;
1934         int i = cfg->num_resets;
1935
1936         mutex_lock(&qmp->phy_mutex);
1937         if (--qmp->init_count) {
1938                 mutex_unlock(&qmp->phy_mutex);
1939                 return 0;
1940         }
1941
1942         reset_control_assert(qmp->ufs_reset);
1943         if (cfg->has_phy_com_ctrl) {
1944                 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
1945                              SERDES_START | PCS_START);
1946                 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
1947                              SW_RESET);
1948                 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
1949                              SW_PWRDN);
1950         }
1951
1952         while (--i >= 0)
1953                 reset_control_assert(qmp->resets[i]);
1954
1955         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1956
1957         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1958
1959         mutex_unlock(&qmp->phy_mutex);
1960
1961         return 0;
1962 }
1963
1964 static int qcom_qmp_phy_enable(struct phy *phy)
1965 {
1966         struct qmp_phy *qphy = phy_get_drvdata(phy);
1967         struct qcom_qmp *qmp = qphy->qmp;
1968         const struct qmp_phy_cfg *cfg = qmp->cfg;
1969         void __iomem *tx = qphy->tx;
1970         void __iomem *rx = qphy->rx;
1971         void __iomem *pcs = qphy->pcs;
1972         void __iomem *pcs_misc = qphy->pcs_misc;
1973         void __iomem *dp_com = qmp->dp_com;
1974         void __iomem *status;
1975         unsigned int mask, val, ready;
1976         int ret;
1977
1978         dev_vdbg(qmp->dev, "Initializing QMP phy\n");
1979
1980         if (cfg->no_pcs_sw_reset) {
1981                 /*
1982                  * Get UFS reset, which is delayed until now to avoid a
1983                  * circular dependency where UFS needs its PHY, but the PHY
1984                  * needs this UFS reset.
1985                  */
1986                 if (!qmp->ufs_reset) {
1987                         qmp->ufs_reset =
1988                                 devm_reset_control_get_exclusive(qmp->dev,
1989                                                                  "ufsphy");
1990
1991                         if (IS_ERR(qmp->ufs_reset)) {
1992                                 ret = PTR_ERR(qmp->ufs_reset);
1993                                 dev_err(qmp->dev,
1994                                         "failed to get UFS reset: %d\n",
1995                                         ret);
1996
1997                                 qmp->ufs_reset = NULL;
1998                                 return ret;
1999                         }
2000                 }
2001
2002                 ret = reset_control_assert(qmp->ufs_reset);
2003                 if (ret)
2004                         goto err_lane_rst;
2005         }
2006
2007         ret = qcom_qmp_phy_com_init(qphy);
2008         if (ret)
2009                 return ret;
2010
2011         if (cfg->has_lane_rst) {
2012                 ret = reset_control_deassert(qphy->lane_rst);
2013                 if (ret) {
2014                         dev_err(qmp->dev, "lane%d reset deassert failed\n",
2015                                 qphy->index);
2016                         goto err_lane_rst;
2017                 }
2018         }
2019
2020         ret = clk_prepare_enable(qphy->pipe_clk);
2021         if (ret) {
2022                 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
2023                 goto err_clk_enable;
2024         }
2025
2026         /* Tx, Rx, and PCS configurations */
2027         qcom_qmp_phy_configure(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num);
2028         /* Configuration for other LANE for USB-DP combo PHY */
2029         if (cfg->is_dual_lane_phy)
2030                 qcom_qmp_phy_configure(qphy->tx2, cfg->regs,
2031                                        cfg->tx_tbl, cfg->tx_tbl_num);
2032
2033         qcom_qmp_phy_configure(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num);
2034         if (cfg->is_dual_lane_phy)
2035                 qcom_qmp_phy_configure(qphy->rx2, cfg->regs,
2036                                        cfg->rx_tbl, cfg->rx_tbl_num);
2037
2038         qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
2039         ret = reset_control_deassert(qmp->ufs_reset);
2040         if (ret)
2041                 goto err_lane_rst;
2042
2043         qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
2044                                cfg->pcs_misc_tbl_num);
2045
2046         /*
2047          * Pull out PHY from POWER DOWN state.
2048          * This is active low enable signal to power-down PHY.
2049          */
2050         if(cfg->type == PHY_TYPE_PCIE)
2051                 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
2052
2053         if (cfg->has_pwrdn_delay)
2054                 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
2055
2056         /* Pull PHY out of reset state */
2057         if (!cfg->no_pcs_sw_reset)
2058                 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2059
2060         if (cfg->has_phy_dp_com_ctrl)
2061                 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
2062
2063         /* start SerDes and Phy-Coding-Sublayer */
2064         qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
2065
2066         if (cfg->type == PHY_TYPE_UFS) {
2067                 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
2068                 mask = PCS_READY;
2069                 ready = PCS_READY;
2070         } else {
2071                 status = pcs + cfg->regs[QPHY_PCS_STATUS];
2072                 mask = PHYSTATUS;
2073                 ready = 0;
2074         }
2075
2076         ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
2077                                  PHY_INIT_COMPLETE_TIMEOUT);
2078         if (ret) {
2079                 dev_err(qmp->dev, "phy initialization timed-out\n");
2080                 goto err_pcs_ready;
2081         }
2082         qmp->phy_initialized = true;
2083         return 0;
2084
2085 err_pcs_ready:
2086         reset_control_assert(qmp->ufs_reset);
2087         clk_disable_unprepare(qphy->pipe_clk);
2088 err_clk_enable:
2089         if (cfg->has_lane_rst)
2090                 reset_control_assert(qphy->lane_rst);
2091 err_lane_rst:
2092         qcom_qmp_phy_com_exit(qmp);
2093
2094         return ret;
2095 }
2096
2097 static int qcom_qmp_phy_disable(struct phy *phy)
2098 {
2099         struct qmp_phy *qphy = phy_get_drvdata(phy);
2100         struct qcom_qmp *qmp = qphy->qmp;
2101         const struct qmp_phy_cfg *cfg = qmp->cfg;
2102
2103         clk_disable_unprepare(qphy->pipe_clk);
2104
2105         /* PHY reset */
2106         if (!cfg->no_pcs_sw_reset)
2107                 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2108
2109         /* stop SerDes and Phy-Coding-Sublayer */
2110         qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
2111
2112         /* Put PHY into POWER DOWN state: active low */
2113         qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
2114
2115         if (cfg->has_lane_rst)
2116                 reset_control_assert(qphy->lane_rst);
2117
2118         qcom_qmp_phy_com_exit(qmp);
2119
2120         qmp->phy_initialized = false;
2121
2122         return 0;
2123 }
2124
2125 static int qcom_qmp_phy_set_mode(struct phy *phy,
2126                                  enum phy_mode mode, int submode)
2127 {
2128         struct qmp_phy *qphy = phy_get_drvdata(phy);
2129         struct qcom_qmp *qmp = qphy->qmp;
2130
2131         qmp->mode = mode;
2132
2133         return 0;
2134 }
2135
2136 static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
2137 {
2138         struct qcom_qmp *qmp = qphy->qmp;
2139         const struct qmp_phy_cfg *cfg = qmp->cfg;
2140         void __iomem *pcs = qphy->pcs;
2141         void __iomem *pcs_misc = qphy->pcs_misc;
2142         u32 intr_mask;
2143
2144         if (qmp->mode == PHY_MODE_USB_HOST_SS ||
2145             qmp->mode == PHY_MODE_USB_DEVICE_SS)
2146                 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
2147         else
2148                 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
2149
2150         /* Clear any pending interrupts status */
2151         qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2152         /* Writing 1 followed by 0 clears the interrupt */
2153         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2154
2155         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
2156                      ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
2157
2158         /* Enable required PHY autonomous mode interrupts */
2159         qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
2160
2161         /* Enable i/o clamp_n for autonomous mode */
2162         if (pcs_misc)
2163                 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
2164 }
2165
2166 static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
2167 {
2168         struct qcom_qmp *qmp = qphy->qmp;
2169         const struct qmp_phy_cfg *cfg = qmp->cfg;
2170         void __iomem *pcs = qphy->pcs;
2171         void __iomem *pcs_misc = qphy->pcs_misc;
2172
2173         /* Disable i/o clamp_n on resume for normal mode */
2174         if (pcs_misc)
2175                 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
2176
2177         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
2178                      ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
2179
2180         qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2181         /* Writing 1 followed by 0 clears the interrupt */
2182         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2183 }
2184
2185 static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
2186 {
2187         struct qcom_qmp *qmp = dev_get_drvdata(dev);
2188         struct qmp_phy *qphy = qmp->phys[0];
2189         const struct qmp_phy_cfg *cfg = qmp->cfg;
2190
2191         dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
2192
2193         /* Supported only for USB3 PHY */
2194         if (cfg->type != PHY_TYPE_USB3)
2195                 return 0;
2196
2197         if (!qmp->phy_initialized) {
2198                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2199                 return 0;
2200         }
2201
2202         qcom_qmp_phy_enable_autonomous_mode(qphy);
2203
2204         clk_disable_unprepare(qphy->pipe_clk);
2205         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2206
2207         return 0;
2208 }
2209
2210 static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
2211 {
2212         struct qcom_qmp *qmp = dev_get_drvdata(dev);
2213         struct qmp_phy *qphy = qmp->phys[0];
2214         const struct qmp_phy_cfg *cfg = qmp->cfg;
2215         int ret = 0;
2216
2217         dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
2218
2219         /* Supported only for USB3 PHY */
2220         if (cfg->type != PHY_TYPE_USB3)
2221                 return 0;
2222
2223         if (!qmp->phy_initialized) {
2224                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2225                 return 0;
2226         }
2227
2228         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
2229         if (ret) {
2230                 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
2231                 return ret;
2232         }
2233
2234         ret = clk_prepare_enable(qphy->pipe_clk);
2235         if (ret) {
2236                 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
2237                 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2238                 return ret;
2239         }
2240
2241         qcom_qmp_phy_disable_autonomous_mode(qphy);
2242
2243         return 0;
2244 }
2245
2246 static int qcom_qmp_phy_vreg_init(struct device *dev)
2247 {
2248         struct qcom_qmp *qmp = dev_get_drvdata(dev);
2249         int num = qmp->cfg->num_vregs;
2250         int i;
2251
2252         qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
2253         if (!qmp->vregs)
2254                 return -ENOMEM;
2255
2256         for (i = 0; i < num; i++)
2257                 qmp->vregs[i].supply = qmp->cfg->vreg_list[i];
2258
2259         return devm_regulator_bulk_get(dev, num, qmp->vregs);
2260 }
2261
2262 static int qcom_qmp_phy_reset_init(struct device *dev)
2263 {
2264         struct qcom_qmp *qmp = dev_get_drvdata(dev);
2265         int i;
2266
2267         qmp->resets = devm_kcalloc(dev, qmp->cfg->num_resets,
2268                                    sizeof(*qmp->resets), GFP_KERNEL);
2269         if (!qmp->resets)
2270                 return -ENOMEM;
2271
2272         for (i = 0; i < qmp->cfg->num_resets; i++) {
2273                 struct reset_control *rst;
2274                 const char *name = qmp->cfg->reset_list[i];
2275
2276                 rst = devm_reset_control_get(dev, name);
2277                 if (IS_ERR(rst)) {
2278                         dev_err(dev, "failed to get %s reset\n", name);
2279                         return PTR_ERR(rst);
2280                 }
2281                 qmp->resets[i] = rst;
2282         }
2283
2284         return 0;
2285 }
2286
2287 static int qcom_qmp_phy_clk_init(struct device *dev)
2288 {
2289         struct qcom_qmp *qmp = dev_get_drvdata(dev);
2290         int num = qmp->cfg->num_clks;
2291         int i;
2292
2293         qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
2294         if (!qmp->clks)
2295                 return -ENOMEM;
2296
2297         for (i = 0; i < num; i++)
2298                 qmp->clks[i].id = qmp->cfg->clk_list[i];
2299
2300         return devm_clk_bulk_get(dev, num, qmp->clks);
2301 }
2302
2303 static void phy_pipe_clk_release_provider(void *res)
2304 {
2305         of_clk_del_provider(res);
2306 }
2307
2308 /*
2309  * Register a fixed rate pipe clock.
2310  *
2311  * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
2312  * controls it. The <s>_pipe_clk coming out of the GCC is requested
2313  * by the PHY driver for its operations.
2314  * We register the <s>_pipe_clksrc here. The gcc driver takes care
2315  * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
2316  * Below picture shows this relationship.
2317  *
2318  *         +---------------+
2319  *         |   PHY block   |<<---------------------------------------+
2320  *         |               |                                         |
2321  *         |   +-------+   |                   +-----+               |
2322  *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
2323  *    clk  |   +-------+   |                   +-----+
2324  *         +---------------+
2325  */
2326 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
2327 {
2328         struct clk_fixed_rate *fixed;
2329         struct clk_init_data init = { };
2330         int ret;
2331
2332         if ((qmp->cfg->type != PHY_TYPE_USB3) &&
2333             (qmp->cfg->type != PHY_TYPE_PCIE)) {
2334                 /* not all phys register pipe clocks, so return success */
2335                 return 0;
2336         }
2337
2338         ret = of_property_read_string(np, "clock-output-names", &init.name);
2339         if (ret) {
2340                 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
2341                 return ret;
2342         }
2343
2344         fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
2345         if (!fixed)
2346                 return -ENOMEM;
2347
2348         init.ops = &clk_fixed_rate_ops;
2349
2350         /* controllers using QMP phys use 125MHz pipe clock interface */
2351         fixed->fixed_rate = 125000000;
2352         fixed->hw.init = &init;
2353
2354         ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
2355         if (ret)
2356                 return ret;
2357
2358         ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
2359         if (ret)
2360                 return ret;
2361
2362         /*
2363          * Roll a devm action because the clock provider is the child node, but
2364          * the child node is not actually a device.
2365          */
2366         ret = devm_add_action(qmp->dev, phy_pipe_clk_release_provider, np);
2367         if (ret)
2368                 phy_pipe_clk_release_provider(np);
2369
2370         return ret;
2371 }
2372
2373 static const struct phy_ops qcom_qmp_phy_gen_ops = {
2374         .init           = qcom_qmp_phy_enable,
2375         .exit           = qcom_qmp_phy_disable,
2376         .set_mode       = qcom_qmp_phy_set_mode,
2377         .owner          = THIS_MODULE,
2378 };
2379
2380 static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
2381         .power_on       = qcom_qmp_phy_enable,
2382         .power_off      = qcom_qmp_phy_disable,
2383         .set_mode       = qcom_qmp_phy_set_mode,
2384         .owner          = THIS_MODULE,
2385 };
2386
2387 static
2388 int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
2389 {
2390         struct qcom_qmp *qmp = dev_get_drvdata(dev);
2391         struct phy *generic_phy;
2392         struct qmp_phy *qphy;
2393         const struct phy_ops *ops = &qcom_qmp_phy_gen_ops;
2394         char prop_name[MAX_PROP_NAME];
2395         int ret;
2396
2397         qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
2398         if (!qphy)
2399                 return -ENOMEM;
2400
2401         /*
2402          * Get memory resources for each phy lane:
2403          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
2404          * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
2405          * For single lane PHYs: pcs_misc (optional) -> 3.
2406          */
2407         qphy->tx = of_iomap(np, 0);
2408         if (!qphy->tx)
2409                 return -ENOMEM;
2410
2411         qphy->rx = of_iomap(np, 1);
2412         if (!qphy->rx)
2413                 return -ENOMEM;
2414
2415         qphy->pcs = of_iomap(np, 2);
2416         if (!qphy->pcs)
2417                 return -ENOMEM;
2418
2419         /*
2420          * If this is a dual-lane PHY, then there should be registers for the
2421          * second lane. Some old device trees did not specify this, so fall
2422          * back to old legacy behavior of assuming they can be reached at an
2423          * offset from the first lane.
2424          */
2425         if (qmp->cfg->is_dual_lane_phy) {
2426                 qphy->tx2 = of_iomap(np, 3);
2427                 qphy->rx2 = of_iomap(np, 4);
2428                 if (!qphy->tx2 || !qphy->rx2) {
2429                         dev_warn(dev,
2430                                  "Underspecified device tree, falling back to legacy register regions\n");
2431
2432                         /* In the old version, pcs_misc is at index 3. */
2433                         qphy->pcs_misc = qphy->tx2;
2434                         qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
2435                         qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
2436
2437                 } else {
2438                         qphy->pcs_misc = of_iomap(np, 5);
2439                 }
2440
2441         } else {
2442                 qphy->pcs_misc = of_iomap(np, 3);
2443         }
2444
2445         if (!qphy->pcs_misc)
2446                 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
2447
2448         /*
2449          * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
2450          * based phys, so they essentially have pipe clock. So,
2451          * we return error in case phy is USB3 or PIPE type.
2452          * Otherwise, we initialize pipe clock to NULL for
2453          * all phys that don't need this.
2454          */
2455         snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
2456         qphy->pipe_clk = of_clk_get_by_name(np, prop_name);
2457         if (IS_ERR(qphy->pipe_clk)) {
2458                 if (qmp->cfg->type == PHY_TYPE_PCIE ||
2459                     qmp->cfg->type == PHY_TYPE_USB3) {
2460                         ret = PTR_ERR(qphy->pipe_clk);
2461                         if (ret != -EPROBE_DEFER)
2462                                 dev_err(dev,
2463                                         "failed to get lane%d pipe_clk, %d\n",
2464                                         id, ret);
2465                         return ret;
2466                 }
2467                 qphy->pipe_clk = NULL;
2468         }
2469
2470         /* Get lane reset, if any */
2471         if (qmp->cfg->has_lane_rst) {
2472                 snprintf(prop_name, sizeof(prop_name), "lane%d", id);
2473                 qphy->lane_rst = of_reset_control_get(np, prop_name);
2474                 if (IS_ERR(qphy->lane_rst)) {
2475                         dev_err(dev, "failed to get lane%d reset\n", id);
2476                         return PTR_ERR(qphy->lane_rst);
2477                 }
2478         }
2479
2480         if (qmp->cfg->type == PHY_TYPE_UFS || qmp->cfg->type == PHY_TYPE_PCIE)
2481                 ops = &qcom_qmp_pcie_ufs_ops;
2482
2483         generic_phy = devm_phy_create(dev, np, ops);
2484         if (IS_ERR(generic_phy)) {
2485                 ret = PTR_ERR(generic_phy);
2486                 dev_err(dev, "failed to create qphy %d\n", ret);
2487                 return ret;
2488         }
2489
2490         qphy->phy = generic_phy;
2491         qphy->index = id;
2492         qphy->qmp = qmp;
2493         qmp->phys[id] = qphy;
2494         phy_set_drvdata(generic_phy, qphy);
2495
2496         return 0;
2497 }
2498
2499 static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
2500         {
2501                 .compatible = "qcom,msm8996-qmp-pcie-phy",
2502                 .data = &msm8996_pciephy_cfg,
2503         }, {
2504                 .compatible = "qcom,msm8996-qmp-ufs-phy",
2505                 .data = &msm8996_ufs_cfg,
2506         }, {
2507                 .compatible = "qcom,msm8996-qmp-usb3-phy",
2508                 .data = &msm8996_usb3phy_cfg,
2509         }, {
2510                 .compatible = "qcom,msm8998-qmp-pcie-phy",
2511                 .data = &msm8998_pciephy_cfg,
2512         }, {
2513                 .compatible = "qcom,msm8998-qmp-ufs-phy",
2514                 .data = &sdm845_ufsphy_cfg,
2515         }, {
2516                 .compatible = "qcom,ipq8074-qmp-pcie-phy",
2517                 .data = &ipq8074_pciephy_cfg,
2518         }, {
2519                 .compatible = "qcom,sdm845-qhp-pcie-phy",
2520                 .data = &sdm845_qhp_pciephy_cfg,
2521         }, {
2522                 .compatible = "qcom,sdm845-qmp-pcie-phy",
2523                 .data = &sdm845_qmp_pciephy_cfg,
2524         }, {
2525                 .compatible = "qcom,sdm845-qmp-usb3-phy",
2526                 .data = &qmp_v3_usb3phy_cfg,
2527         }, {
2528                 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
2529                 .data = &qmp_v3_usb3_uniphy_cfg,
2530         }, {
2531                 .compatible = "qcom,sdm845-qmp-ufs-phy",
2532                 .data = &sdm845_ufsphy_cfg,
2533         }, {
2534                 .compatible = "qcom,msm8998-qmp-usb3-phy",
2535                 .data = &msm8998_usb3phy_cfg,
2536         }, {
2537                 .compatible = "qcom,sm8150-qmp-ufs-phy",
2538                 .data = &sm8150_ufsphy_cfg,
2539         },
2540         { },
2541 };
2542 MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
2543
2544 static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
2545         SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
2546                            qcom_qmp_phy_runtime_resume, NULL)
2547 };
2548
2549 static int qcom_qmp_phy_probe(struct platform_device *pdev)
2550 {
2551         struct qcom_qmp *qmp;
2552         struct device *dev = &pdev->dev;
2553         struct resource *res;
2554         struct device_node *child;
2555         struct phy_provider *phy_provider;
2556         void __iomem *base;
2557         int num, id;
2558         int ret;
2559
2560         qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
2561         if (!qmp)
2562                 return -ENOMEM;
2563
2564         qmp->dev = dev;
2565         dev_set_drvdata(dev, qmp);
2566
2567         /* Get the specific init parameters of QMP phy */
2568         qmp->cfg = of_device_get_match_data(dev);
2569         if (!qmp->cfg)
2570                 return -EINVAL;
2571
2572         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2573         base = devm_ioremap_resource(dev, res);
2574         if (IS_ERR(base))
2575                 return PTR_ERR(base);
2576
2577         /* per PHY serdes; usually located at base address */
2578         qmp->serdes = base;
2579
2580         /* per PHY dp_com; if PHY has dp_com control block */
2581         if (qmp->cfg->has_phy_dp_com_ctrl) {
2582                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2583                                                    "dp_com");
2584                 base = devm_ioremap_resource(dev, res);
2585                 if (IS_ERR(base))
2586                         return PTR_ERR(base);
2587
2588                 qmp->dp_com = base;
2589         }
2590
2591         mutex_init(&qmp->phy_mutex);
2592
2593         ret = qcom_qmp_phy_clk_init(dev);
2594         if (ret)
2595                 return ret;
2596
2597         ret = qcom_qmp_phy_reset_init(dev);
2598         if (ret)
2599                 return ret;
2600
2601         ret = qcom_qmp_phy_vreg_init(dev);
2602         if (ret) {
2603                 if (ret != -EPROBE_DEFER)
2604                         dev_err(dev, "failed to get regulator supplies: %d\n",
2605                                 ret);
2606                 return ret;
2607         }
2608
2609         num = of_get_available_child_count(dev->of_node);
2610         /* do we have a rogue child node ? */
2611         if (num > qmp->cfg->nlanes)
2612                 return -EINVAL;
2613
2614         qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
2615         if (!qmp->phys)
2616                 return -ENOMEM;
2617
2618         id = 0;
2619         pm_runtime_set_active(dev);
2620         pm_runtime_enable(dev);
2621         /*
2622          * Prevent runtime pm from being ON by default. Users can enable
2623          * it using power/control in sysfs.
2624          */
2625         pm_runtime_forbid(dev);
2626
2627         for_each_available_child_of_node(dev->of_node, child) {
2628                 /* Create per-lane phy */
2629                 ret = qcom_qmp_phy_create(dev, child, id);
2630                 if (ret) {
2631                         dev_err(dev, "failed to create lane%d phy, %d\n",
2632                                 id, ret);
2633                         goto err_node_put;
2634                 }
2635
2636                 /*
2637                  * Register the pipe clock provided by phy.
2638                  * See function description to see details of this pipe clock.
2639                  */
2640                 ret = phy_pipe_clk_register(qmp, child);
2641                 if (ret) {
2642                         dev_err(qmp->dev,
2643                                 "failed to register pipe clock source\n");
2644                         goto err_node_put;
2645                 }
2646                 id++;
2647         }
2648
2649         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2650         if (!IS_ERR(phy_provider))
2651                 dev_info(dev, "Registered Qcom-QMP phy\n");
2652         else
2653                 pm_runtime_disable(dev);
2654
2655         return PTR_ERR_OR_ZERO(phy_provider);
2656
2657 err_node_put:
2658         pm_runtime_disable(dev);
2659         of_node_put(child);
2660         return ret;
2661 }
2662
2663 static struct platform_driver qcom_qmp_phy_driver = {
2664         .probe          = qcom_qmp_phy_probe,
2665         .driver = {
2666                 .name   = "qcom-qmp-phy",
2667                 .pm     = &qcom_qmp_phy_pm_ops,
2668                 .of_match_table = qcom_qmp_phy_of_match_table,
2669         },
2670 };
2671
2672 module_platform_driver(qcom_qmp_phy_driver);
2673
2674 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
2675 MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
2676 MODULE_LICENSE("GPL v2");