1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: jitao.shi <jitao.shi@mediatek.com>
7 #include "phy-mtk-mipi-dsi.h"
9 #define MIPITX_LANE_CON 0x000c
10 #define RG_DSI_CPHY_T1DRV_EN BIT(0)
11 #define RG_DSI_ANA_CK_SEL BIT(1)
12 #define RG_DSI_PHY_CK_SEL BIT(2)
13 #define RG_DSI_CPHY_EN BIT(3)
14 #define RG_DSI_PHYCK_INV_EN BIT(4)
15 #define RG_DSI_PWR04_EN BIT(5)
16 #define RG_DSI_BG_LPF_EN BIT(6)
17 #define RG_DSI_BG_CORE_EN BIT(7)
18 #define RG_DSI_PAD_TIEL_SEL BIT(8)
20 #define MIPITX_VOLTAGE_SEL 0x0010
21 #define RG_DSI_HSTX_LDO_REF_SEL (0xf << 6)
23 #define MIPITX_PLL_PWR 0x0028
24 #define MIPITX_PLL_CON0 0x002c
25 #define MIPITX_PLL_CON1 0x0030
26 #define MIPITX_PLL_CON2 0x0034
27 #define MIPITX_PLL_CON3 0x0038
28 #define MIPITX_PLL_CON4 0x003c
29 #define RG_DSI_PLL_IBIAS (3 << 10)
31 #define MIPITX_D2P_RTCODE 0x0100
32 #define MIPITX_D2_SW_CTL_EN 0x0144
33 #define MIPITX_D0_SW_CTL_EN 0x0244
34 #define MIPITX_CK_CKMODE_EN 0x0328
35 #define DSI_CK_CKMODE_EN BIT(0)
36 #define MIPITX_CK_SW_CTL_EN 0x0344
37 #define MIPITX_D1_SW_CTL_EN 0x0444
38 #define MIPITX_D3_SW_CTL_EN 0x0544
39 #define DSI_SW_CTL_EN BIT(0)
40 #define AD_DSI_PLL_SDM_PWR_ON BIT(0)
41 #define AD_DSI_PLL_SDM_ISO_EN BIT(1)
43 #define RG_DSI_PLL_EN BIT(4)
44 #define RG_DSI_PLL_POSDIV (0x7 << 8)
46 static int mtk_mipi_tx_pll_enable(struct clk_hw *hw)
48 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
49 unsigned int txdiv, txdiv0;
52 dev_dbg(mipi_tx->dev, "enable: %u bps\n", mipi_tx->data_rate);
54 if (mipi_tx->data_rate >= 2000000000) {
57 } else if (mipi_tx->data_rate >= 1000000000) {
60 } else if (mipi_tx->data_rate >= 500000000) {
63 } else if (mipi_tx->data_rate > 250000000) {
66 } else if (mipi_tx->data_rate >= 125000000) {
73 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS);
75 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
76 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN);
78 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
79 pcw = div_u64(((u64)mipi_tx->data_rate * txdiv) << 24, 26000000);
80 writel(pcw, mipi_tx->regs + MIPITX_PLL_CON0);
81 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV,
83 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN);
88 static void mtk_mipi_tx_pll_disable(struct clk_hw *hw)
90 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
92 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN);
94 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
95 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
98 static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
101 return clamp_val(rate, 50000000, 1600000000);
104 static const struct clk_ops mtk_mipi_tx_pll_ops = {
105 .enable = mtk_mipi_tx_pll_enable,
106 .disable = mtk_mipi_tx_pll_disable,
107 .round_rate = mtk_mipi_tx_pll_round_rate,
108 .set_rate = mtk_mipi_tx_pll_set_rate,
109 .recalc_rate = mtk_mipi_tx_pll_recalc_rate,
112 static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx)
116 for (i = 0; i < 5; i++) {
117 if ((mipi_tx->rt_code[i] & 0x1f) == 0)
118 mipi_tx->rt_code[i] |= 0x10;
120 if ((mipi_tx->rt_code[i] >> 5 & 0x1f) == 0)
121 mipi_tx->rt_code[i] |= 0x10 << 5;
123 for (j = 0; j < 10; j++)
124 mtk_mipi_tx_update_bits(mipi_tx,
125 MIPITX_D2P_RTCODE * (i + 1) + j * 4,
126 1, mipi_tx->rt_code[i] >> j & 1);
130 static void mtk_mipi_tx_power_on_signal(struct phy *phy)
132 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
134 /* BG_LPF_EN / BG_CORE_EN */
135 writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN,
136 mipi_tx->regs + MIPITX_LANE_CON);
137 usleep_range(30, 100);
138 writel(RG_DSI_BG_CORE_EN | RG_DSI_BG_LPF_EN,
139 mipi_tx->regs + MIPITX_LANE_CON);
141 /* Switch OFF each Lane */
142 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
143 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
144 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
145 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
146 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
148 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_VOLTAGE_SEL,
149 RG_DSI_HSTX_LDO_REF_SEL,
150 (mipi_tx->mipitx_drive - 3000) / 200 << 6);
152 mtk_mipi_tx_config_calibration_data(mipi_tx);
154 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
157 static void mtk_mipi_tx_power_off_signal(struct phy *phy)
159 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
161 /* Switch ON each Lane */
162 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
163 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
164 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
165 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
166 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
168 writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN,
169 mipi_tx->regs + MIPITX_LANE_CON);
170 writel(RG_DSI_PAD_TIEL_SEL, mipi_tx->regs + MIPITX_LANE_CON);
173 const struct mtk_mipitx_data mt8183_mipitx_data = {
174 .mipi_tx_clk_ops = &mtk_mipi_tx_pll_ops,
175 .mipi_tx_enable_signal = mtk_mipi_tx_power_on_signal,
176 .mipi_tx_disable_signal = mtk_mipi_tx_power_off_signal,