1 // SPDX-License-Identifier: GPL-2.0-only
3 * This driver adds support for HNS3 PMU iEP device. Related perf events are
4 * bandwidth, latency, packet rate, interrupt rate etc.
6 * Copyright (C) 2022 HiSilicon Limited
8 #include <linux/bitfield.h>
9 #include <linux/bitmap.h>
10 #include <linux/bug.h>
11 #include <linux/cpuhotplug.h>
12 #include <linux/cpumask.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/err.h>
16 #include <linux/interrupt.h>
17 #include <linux/iopoll.h>
18 #include <linux/io-64-nonatomic-hi-lo.h>
19 #include <linux/irq.h>
20 #include <linux/kernel.h>
21 #include <linux/list.h>
22 #include <linux/module.h>
23 #include <linux/pci.h>
24 #include <linux/pci-epf.h>
25 #include <linux/perf_event.h>
26 #include <linux/smp.h>
28 /* registers offset address */
29 #define HNS3_PMU_REG_GLOBAL_CTRL 0x0000
30 #define HNS3_PMU_REG_CLOCK_FREQ 0x0020
31 #define HNS3_PMU_REG_BDF 0x0fe0
32 #define HNS3_PMU_REG_VERSION 0x0fe4
33 #define HNS3_PMU_REG_DEVICE_ID 0x0fe8
35 #define HNS3_PMU_REG_EVENT_OFFSET 0x1000
36 #define HNS3_PMU_REG_EVENT_SIZE 0x1000
37 #define HNS3_PMU_REG_EVENT_CTRL_LOW 0x00
38 #define HNS3_PMU_REG_EVENT_CTRL_HIGH 0x04
39 #define HNS3_PMU_REG_EVENT_INTR_STATUS 0x08
40 #define HNS3_PMU_REG_EVENT_INTR_MASK 0x0c
41 #define HNS3_PMU_REG_EVENT_COUNTER 0x10
42 #define HNS3_PMU_REG_EVENT_EXT_COUNTER 0x18
43 #define HNS3_PMU_REG_EVENT_QID_CTRL 0x28
44 #define HNS3_PMU_REG_EVENT_QID_PARA 0x2c
46 #define HNS3_PMU_FILTER_SUPPORT_GLOBAL BIT(0)
47 #define HNS3_PMU_FILTER_SUPPORT_PORT BIT(1)
48 #define HNS3_PMU_FILTER_SUPPORT_PORT_TC BIT(2)
49 #define HNS3_PMU_FILTER_SUPPORT_FUNC BIT(3)
50 #define HNS3_PMU_FILTER_SUPPORT_FUNC_QUEUE BIT(4)
51 #define HNS3_PMU_FILTER_SUPPORT_FUNC_INTR BIT(5)
53 #define HNS3_PMU_FILTER_ALL_TC 0xf
54 #define HNS3_PMU_FILTER_ALL_QUEUE 0xffff
56 #define HNS3_PMU_CTRL_SUBEVENT_S 4
57 #define HNS3_PMU_CTRL_FILTER_MODE_S 24
59 #define HNS3_PMU_GLOBAL_START BIT(0)
61 #define HNS3_PMU_EVENT_STATUS_RESET BIT(11)
62 #define HNS3_PMU_EVENT_EN BIT(12)
63 #define HNS3_PMU_EVENT_OVERFLOW_RESTART BIT(15)
65 #define HNS3_PMU_QID_PARA_FUNC_S 0
66 #define HNS3_PMU_QID_PARA_QUEUE_S 16
68 #define HNS3_PMU_QID_CTRL_REQ_ENABLE BIT(0)
69 #define HNS3_PMU_QID_CTRL_DONE BIT(1)
70 #define HNS3_PMU_QID_CTRL_MISS BIT(2)
72 #define HNS3_PMU_INTR_MASK_OVERFLOW BIT(1)
74 #define HNS3_PMU_MAX_HW_EVENTS 8
77 * Each hardware event contains two registers (counter and ext_counter) for
78 * bandwidth, packet rate, latency and interrupt rate. These two registers will
79 * be triggered to run at the same when a hardware event is enabled. The meaning
80 * of counter and ext_counter of different event type are different, their
81 * meaning show as follow:
83 * +----------------+------------------+---------------+
84 * | event type | counter | ext_counter |
85 * +----------------+------------------+---------------+
86 * | bandwidth | byte number | cycle number |
87 * +----------------+------------------+---------------+
88 * | packet rate | packet number | cycle number |
89 * +----------------+------------------+---------------+
90 * | latency | cycle number | packet number |
91 * +----------------+------------------+---------------+
92 * | interrupt rate | interrupt number | cycle number |
93 * +----------------+------------------+---------------+
95 * The cycle number indicates increment of counter of hardware timer, the
96 * frequency of hardware timer can be read from hw_clk_freq file.
98 * Performance of each hardware event is calculated by: counter / ext_counter.
100 * Since processing of data is preferred to be done in userspace, we expose
101 * ext_counter as a separate event for userspace and use bit 16 to indicate it.
102 * For example, event 0x00001 and 0x10001 are actually one event for hardware
103 * because bit 0-15 are same. If the bit 16 of one event is 0 means to read
104 * counter register, otherwise means to read ext_counter register.
106 /* bandwidth events */
107 #define HNS3_PMU_EVT_BW_SSU_EGU_BYTE_NUM 0x00001
108 #define HNS3_PMU_EVT_BW_SSU_EGU_TIME 0x10001
109 #define HNS3_PMU_EVT_BW_SSU_RPU_BYTE_NUM 0x00002
110 #define HNS3_PMU_EVT_BW_SSU_RPU_TIME 0x10002
111 #define HNS3_PMU_EVT_BW_SSU_ROCE_BYTE_NUM 0x00003
112 #define HNS3_PMU_EVT_BW_SSU_ROCE_TIME 0x10003
113 #define HNS3_PMU_EVT_BW_ROCE_SSU_BYTE_NUM 0x00004
114 #define HNS3_PMU_EVT_BW_ROCE_SSU_TIME 0x10004
115 #define HNS3_PMU_EVT_BW_TPU_SSU_BYTE_NUM 0x00005
116 #define HNS3_PMU_EVT_BW_TPU_SSU_TIME 0x10005
117 #define HNS3_PMU_EVT_BW_RPU_RCBRX_BYTE_NUM 0x00006
118 #define HNS3_PMU_EVT_BW_RPU_RCBRX_TIME 0x10006
119 #define HNS3_PMU_EVT_BW_RCBTX_TXSCH_BYTE_NUM 0x00008
120 #define HNS3_PMU_EVT_BW_RCBTX_TXSCH_TIME 0x10008
121 #define HNS3_PMU_EVT_BW_WR_FBD_BYTE_NUM 0x00009
122 #define HNS3_PMU_EVT_BW_WR_FBD_TIME 0x10009
123 #define HNS3_PMU_EVT_BW_WR_EBD_BYTE_NUM 0x0000a
124 #define HNS3_PMU_EVT_BW_WR_EBD_TIME 0x1000a
125 #define HNS3_PMU_EVT_BW_RD_FBD_BYTE_NUM 0x0000b
126 #define HNS3_PMU_EVT_BW_RD_FBD_TIME 0x1000b
127 #define HNS3_PMU_EVT_BW_RD_EBD_BYTE_NUM 0x0000c
128 #define HNS3_PMU_EVT_BW_RD_EBD_TIME 0x1000c
129 #define HNS3_PMU_EVT_BW_RD_PAY_M0_BYTE_NUM 0x0000d
130 #define HNS3_PMU_EVT_BW_RD_PAY_M0_TIME 0x1000d
131 #define HNS3_PMU_EVT_BW_RD_PAY_M1_BYTE_NUM 0x0000e
132 #define HNS3_PMU_EVT_BW_RD_PAY_M1_TIME 0x1000e
133 #define HNS3_PMU_EVT_BW_WR_PAY_M0_BYTE_NUM 0x0000f
134 #define HNS3_PMU_EVT_BW_WR_PAY_M0_TIME 0x1000f
135 #define HNS3_PMU_EVT_BW_WR_PAY_M1_BYTE_NUM 0x00010
136 #define HNS3_PMU_EVT_BW_WR_PAY_M1_TIME 0x10010
138 /* packet rate events */
139 #define HNS3_PMU_EVT_PPS_IGU_SSU_PACKET_NUM 0x00100
140 #define HNS3_PMU_EVT_PPS_IGU_SSU_TIME 0x10100
141 #define HNS3_PMU_EVT_PPS_SSU_EGU_PACKET_NUM 0x00101
142 #define HNS3_PMU_EVT_PPS_SSU_EGU_TIME 0x10101
143 #define HNS3_PMU_EVT_PPS_SSU_RPU_PACKET_NUM 0x00102
144 #define HNS3_PMU_EVT_PPS_SSU_RPU_TIME 0x10102
145 #define HNS3_PMU_EVT_PPS_SSU_ROCE_PACKET_NUM 0x00103
146 #define HNS3_PMU_EVT_PPS_SSU_ROCE_TIME 0x10103
147 #define HNS3_PMU_EVT_PPS_ROCE_SSU_PACKET_NUM 0x00104
148 #define HNS3_PMU_EVT_PPS_ROCE_SSU_TIME 0x10104
149 #define HNS3_PMU_EVT_PPS_TPU_SSU_PACKET_NUM 0x00105
150 #define HNS3_PMU_EVT_PPS_TPU_SSU_TIME 0x10105
151 #define HNS3_PMU_EVT_PPS_RPU_RCBRX_PACKET_NUM 0x00106
152 #define HNS3_PMU_EVT_PPS_RPU_RCBRX_TIME 0x10106
153 #define HNS3_PMU_EVT_PPS_RCBTX_TPU_PACKET_NUM 0x00107
154 #define HNS3_PMU_EVT_PPS_RCBTX_TPU_TIME 0x10107
155 #define HNS3_PMU_EVT_PPS_RCBTX_TXSCH_PACKET_NUM 0x00108
156 #define HNS3_PMU_EVT_PPS_RCBTX_TXSCH_TIME 0x10108
157 #define HNS3_PMU_EVT_PPS_WR_FBD_PACKET_NUM 0x00109
158 #define HNS3_PMU_EVT_PPS_WR_FBD_TIME 0x10109
159 #define HNS3_PMU_EVT_PPS_WR_EBD_PACKET_NUM 0x0010a
160 #define HNS3_PMU_EVT_PPS_WR_EBD_TIME 0x1010a
161 #define HNS3_PMU_EVT_PPS_RD_FBD_PACKET_NUM 0x0010b
162 #define HNS3_PMU_EVT_PPS_RD_FBD_TIME 0x1010b
163 #define HNS3_PMU_EVT_PPS_RD_EBD_PACKET_NUM 0x0010c
164 #define HNS3_PMU_EVT_PPS_RD_EBD_TIME 0x1010c
165 #define HNS3_PMU_EVT_PPS_RD_PAY_M0_PACKET_NUM 0x0010d
166 #define HNS3_PMU_EVT_PPS_RD_PAY_M0_TIME 0x1010d
167 #define HNS3_PMU_EVT_PPS_RD_PAY_M1_PACKET_NUM 0x0010e
168 #define HNS3_PMU_EVT_PPS_RD_PAY_M1_TIME 0x1010e
169 #define HNS3_PMU_EVT_PPS_WR_PAY_M0_PACKET_NUM 0x0010f
170 #define HNS3_PMU_EVT_PPS_WR_PAY_M0_TIME 0x1010f
171 #define HNS3_PMU_EVT_PPS_WR_PAY_M1_PACKET_NUM 0x00110
172 #define HNS3_PMU_EVT_PPS_WR_PAY_M1_TIME 0x10110
173 #define HNS3_PMU_EVT_PPS_NICROH_TX_PRE_PACKET_NUM 0x00111
174 #define HNS3_PMU_EVT_PPS_NICROH_TX_PRE_TIME 0x10111
175 #define HNS3_PMU_EVT_PPS_NICROH_RX_PRE_PACKET_NUM 0x00112
176 #define HNS3_PMU_EVT_PPS_NICROH_RX_PRE_TIME 0x10112
179 #define HNS3_PMU_EVT_DLY_TX_PUSH_TIME 0x00202
180 #define HNS3_PMU_EVT_DLY_TX_PUSH_PACKET_NUM 0x10202
181 #define HNS3_PMU_EVT_DLY_TX_TIME 0x00204
182 #define HNS3_PMU_EVT_DLY_TX_PACKET_NUM 0x10204
183 #define HNS3_PMU_EVT_DLY_SSU_TX_NIC_TIME 0x00206
184 #define HNS3_PMU_EVT_DLY_SSU_TX_NIC_PACKET_NUM 0x10206
185 #define HNS3_PMU_EVT_DLY_SSU_TX_ROCE_TIME 0x00207
186 #define HNS3_PMU_EVT_DLY_SSU_TX_ROCE_PACKET_NUM 0x10207
187 #define HNS3_PMU_EVT_DLY_SSU_RX_NIC_TIME 0x00208
188 #define HNS3_PMU_EVT_DLY_SSU_RX_NIC_PACKET_NUM 0x10208
189 #define HNS3_PMU_EVT_DLY_SSU_RX_ROCE_TIME 0x00209
190 #define HNS3_PMU_EVT_DLY_SSU_RX_ROCE_PACKET_NUM 0x10209
191 #define HNS3_PMU_EVT_DLY_RPU_TIME 0x0020e
192 #define HNS3_PMU_EVT_DLY_RPU_PACKET_NUM 0x1020e
193 #define HNS3_PMU_EVT_DLY_TPU_TIME 0x0020f
194 #define HNS3_PMU_EVT_DLY_TPU_PACKET_NUM 0x1020f
195 #define HNS3_PMU_EVT_DLY_RPE_TIME 0x00210
196 #define HNS3_PMU_EVT_DLY_RPE_PACKET_NUM 0x10210
197 #define HNS3_PMU_EVT_DLY_TPE_TIME 0x00211
198 #define HNS3_PMU_EVT_DLY_TPE_PACKET_NUM 0x10211
199 #define HNS3_PMU_EVT_DLY_TPE_PUSH_TIME 0x00212
200 #define HNS3_PMU_EVT_DLY_TPE_PUSH_PACKET_NUM 0x10212
201 #define HNS3_PMU_EVT_DLY_WR_FBD_TIME 0x00213
202 #define HNS3_PMU_EVT_DLY_WR_FBD_PACKET_NUM 0x10213
203 #define HNS3_PMU_EVT_DLY_WR_EBD_TIME 0x00214
204 #define HNS3_PMU_EVT_DLY_WR_EBD_PACKET_NUM 0x10214
205 #define HNS3_PMU_EVT_DLY_RD_FBD_TIME 0x00215
206 #define HNS3_PMU_EVT_DLY_RD_FBD_PACKET_NUM 0x10215
207 #define HNS3_PMU_EVT_DLY_RD_EBD_TIME 0x00216
208 #define HNS3_PMU_EVT_DLY_RD_EBD_PACKET_NUM 0x10216
209 #define HNS3_PMU_EVT_DLY_RD_PAY_M0_TIME 0x00217
210 #define HNS3_PMU_EVT_DLY_RD_PAY_M0_PACKET_NUM 0x10217
211 #define HNS3_PMU_EVT_DLY_RD_PAY_M1_TIME 0x00218
212 #define HNS3_PMU_EVT_DLY_RD_PAY_M1_PACKET_NUM 0x10218
213 #define HNS3_PMU_EVT_DLY_WR_PAY_M0_TIME 0x00219
214 #define HNS3_PMU_EVT_DLY_WR_PAY_M0_PACKET_NUM 0x10219
215 #define HNS3_PMU_EVT_DLY_WR_PAY_M1_TIME 0x0021a
216 #define HNS3_PMU_EVT_DLY_WR_PAY_M1_PACKET_NUM 0x1021a
217 #define HNS3_PMU_EVT_DLY_MSIX_WRITE_TIME 0x0021c
218 #define HNS3_PMU_EVT_DLY_MSIX_WRITE_PACKET_NUM 0x1021c
220 /* interrupt rate events */
221 #define HNS3_PMU_EVT_PPS_MSIX_NIC_INTR_NUM 0x00300
222 #define HNS3_PMU_EVT_PPS_MSIX_NIC_TIME 0x10300
224 /* filter mode supported by each bandwidth event */
225 #define HNS3_PMU_FILTER_BW_SSU_EGU 0x07
226 #define HNS3_PMU_FILTER_BW_SSU_RPU 0x1f
227 #define HNS3_PMU_FILTER_BW_SSU_ROCE 0x0f
228 #define HNS3_PMU_FILTER_BW_ROCE_SSU 0x0f
229 #define HNS3_PMU_FILTER_BW_TPU_SSU 0x1f
230 #define HNS3_PMU_FILTER_BW_RPU_RCBRX 0x11
231 #define HNS3_PMU_FILTER_BW_RCBTX_TXSCH 0x11
232 #define HNS3_PMU_FILTER_BW_WR_FBD 0x1b
233 #define HNS3_PMU_FILTER_BW_WR_EBD 0x11
234 #define HNS3_PMU_FILTER_BW_RD_FBD 0x01
235 #define HNS3_PMU_FILTER_BW_RD_EBD 0x1b
236 #define HNS3_PMU_FILTER_BW_RD_PAY_M0 0x01
237 #define HNS3_PMU_FILTER_BW_RD_PAY_M1 0x01
238 #define HNS3_PMU_FILTER_BW_WR_PAY_M0 0x01
239 #define HNS3_PMU_FILTER_BW_WR_PAY_M1 0x01
241 /* filter mode supported by each packet rate event */
242 #define HNS3_PMU_FILTER_PPS_IGU_SSU 0x07
243 #define HNS3_PMU_FILTER_PPS_SSU_EGU 0x07
244 #define HNS3_PMU_FILTER_PPS_SSU_RPU 0x1f
245 #define HNS3_PMU_FILTER_PPS_SSU_ROCE 0x0f
246 #define HNS3_PMU_FILTER_PPS_ROCE_SSU 0x0f
247 #define HNS3_PMU_FILTER_PPS_TPU_SSU 0x1f
248 #define HNS3_PMU_FILTER_PPS_RPU_RCBRX 0x11
249 #define HNS3_PMU_FILTER_PPS_RCBTX_TPU 0x1f
250 #define HNS3_PMU_FILTER_PPS_RCBTX_TXSCH 0x11
251 #define HNS3_PMU_FILTER_PPS_WR_FBD 0x1b
252 #define HNS3_PMU_FILTER_PPS_WR_EBD 0x11
253 #define HNS3_PMU_FILTER_PPS_RD_FBD 0x01
254 #define HNS3_PMU_FILTER_PPS_RD_EBD 0x1b
255 #define HNS3_PMU_FILTER_PPS_RD_PAY_M0 0x01
256 #define HNS3_PMU_FILTER_PPS_RD_PAY_M1 0x01
257 #define HNS3_PMU_FILTER_PPS_WR_PAY_M0 0x01
258 #define HNS3_PMU_FILTER_PPS_WR_PAY_M1 0x01
259 #define HNS3_PMU_FILTER_PPS_NICROH_TX_PRE 0x01
260 #define HNS3_PMU_FILTER_PPS_NICROH_RX_PRE 0x01
262 /* filter mode supported by each latency event */
263 #define HNS3_PMU_FILTER_DLY_TX_PUSH 0x01
264 #define HNS3_PMU_FILTER_DLY_TX 0x01
265 #define HNS3_PMU_FILTER_DLY_SSU_TX_NIC 0x07
266 #define HNS3_PMU_FILTER_DLY_SSU_TX_ROCE 0x07
267 #define HNS3_PMU_FILTER_DLY_SSU_RX_NIC 0x07
268 #define HNS3_PMU_FILTER_DLY_SSU_RX_ROCE 0x07
269 #define HNS3_PMU_FILTER_DLY_RPU 0x11
270 #define HNS3_PMU_FILTER_DLY_TPU 0x1f
271 #define HNS3_PMU_FILTER_DLY_RPE 0x01
272 #define HNS3_PMU_FILTER_DLY_TPE 0x0b
273 #define HNS3_PMU_FILTER_DLY_TPE_PUSH 0x1b
274 #define HNS3_PMU_FILTER_DLY_WR_FBD 0x1b
275 #define HNS3_PMU_FILTER_DLY_WR_EBD 0x11
276 #define HNS3_PMU_FILTER_DLY_RD_FBD 0x01
277 #define HNS3_PMU_FILTER_DLY_RD_EBD 0x1b
278 #define HNS3_PMU_FILTER_DLY_RD_PAY_M0 0x01
279 #define HNS3_PMU_FILTER_DLY_RD_PAY_M1 0x01
280 #define HNS3_PMU_FILTER_DLY_WR_PAY_M0 0x01
281 #define HNS3_PMU_FILTER_DLY_WR_PAY_M1 0x01
282 #define HNS3_PMU_FILTER_DLY_MSIX_WRITE 0x01
284 /* filter mode supported by each interrupt rate event */
285 #define HNS3_PMU_FILTER_INTR_MSIX_NIC 0x01
287 enum hns3_pmu_hw_filter_mode {
288 HNS3_PMU_HW_FILTER_GLOBAL,
289 HNS3_PMU_HW_FILTER_PORT,
290 HNS3_PMU_HW_FILTER_PORT_TC,
291 HNS3_PMU_HW_FILTER_FUNC,
292 HNS3_PMU_HW_FILTER_FUNC_QUEUE,
293 HNS3_PMU_HW_FILTER_FUNC_INTR,
296 struct hns3_pmu_event_attr {
302 struct perf_event *hw_events[HNS3_PMU_MAX_HW_EVENTS];
303 struct hlist_node node;
304 struct pci_dev *pdev;
310 u32 hw_clk_freq; /* hardware clock frequency of PMU */
311 /* maximum and minimum bdf allowed by PMU */
316 #define to_hns3_pmu(p) (container_of((p), struct hns3_pmu, pmu))
318 #define GET_PCI_DEVFN(bdf) ((bdf) & 0xff)
320 #define FILTER_CONDITION_PORT(port) ((1 << (port)) & 0xff)
321 #define FILTER_CONDITION_PORT_TC(port, tc) (((port) << 3) | ((tc) & 0x07))
322 #define FILTER_CONDITION_FUNC_INTR(func, intr) (((intr) << 8) | (func))
324 #define HNS3_PMU_FILTER_ATTR(_name, _config, _start, _end) \
325 static inline u64 hns3_pmu_get_##_name(struct perf_event *event) \
327 return FIELD_GET(GENMASK_ULL(_end, _start), \
328 event->attr._config); \
331 HNS3_PMU_FILTER_ATTR(subevent, config, 0, 7);
332 HNS3_PMU_FILTER_ATTR(event_type, config, 8, 15);
333 HNS3_PMU_FILTER_ATTR(ext_counter_used, config, 16, 16);
334 HNS3_PMU_FILTER_ATTR(port, config1, 0, 3);
335 HNS3_PMU_FILTER_ATTR(tc, config1, 4, 7);
336 HNS3_PMU_FILTER_ATTR(bdf, config1, 8, 23);
337 HNS3_PMU_FILTER_ATTR(queue, config1, 24, 39);
338 HNS3_PMU_FILTER_ATTR(intr, config1, 40, 51);
339 HNS3_PMU_FILTER_ATTR(global, config1, 52, 52);
341 #define HNS3_BW_EVT_BYTE_NUM(_name) (&(struct hns3_pmu_event_attr) {\
342 HNS3_PMU_EVT_BW_##_name##_BYTE_NUM, \
343 HNS3_PMU_FILTER_BW_##_name})
344 #define HNS3_BW_EVT_TIME(_name) (&(struct hns3_pmu_event_attr) {\
345 HNS3_PMU_EVT_BW_##_name##_TIME, \
346 HNS3_PMU_FILTER_BW_##_name})
347 #define HNS3_PPS_EVT_PACKET_NUM(_name) (&(struct hns3_pmu_event_attr) {\
348 HNS3_PMU_EVT_PPS_##_name##_PACKET_NUM, \
349 HNS3_PMU_FILTER_PPS_##_name})
350 #define HNS3_PPS_EVT_TIME(_name) (&(struct hns3_pmu_event_attr) {\
351 HNS3_PMU_EVT_PPS_##_name##_TIME, \
352 HNS3_PMU_FILTER_PPS_##_name})
353 #define HNS3_DLY_EVT_TIME(_name) (&(struct hns3_pmu_event_attr) {\
354 HNS3_PMU_EVT_DLY_##_name##_TIME, \
355 HNS3_PMU_FILTER_DLY_##_name})
356 #define HNS3_DLY_EVT_PACKET_NUM(_name) (&(struct hns3_pmu_event_attr) {\
357 HNS3_PMU_EVT_DLY_##_name##_PACKET_NUM, \
358 HNS3_PMU_FILTER_DLY_##_name})
359 #define HNS3_INTR_EVT_INTR_NUM(_name) (&(struct hns3_pmu_event_attr) {\
360 HNS3_PMU_EVT_PPS_##_name##_INTR_NUM, \
361 HNS3_PMU_FILTER_INTR_##_name})
362 #define HNS3_INTR_EVT_TIME(_name) (&(struct hns3_pmu_event_attr) {\
363 HNS3_PMU_EVT_PPS_##_name##_TIME, \
364 HNS3_PMU_FILTER_INTR_##_name})
366 static ssize_t hns3_pmu_format_show(struct device *dev,
367 struct device_attribute *attr, char *buf)
369 struct dev_ext_attribute *eattr;
371 eattr = container_of(attr, struct dev_ext_attribute, attr);
373 return sysfs_emit(buf, "%s\n", (char *)eattr->var);
376 static ssize_t hns3_pmu_event_show(struct device *dev,
377 struct device_attribute *attr, char *buf)
379 struct hns3_pmu_event_attr *event;
380 struct dev_ext_attribute *eattr;
382 eattr = container_of(attr, struct dev_ext_attribute, attr);
385 return sysfs_emit(buf, "config=0x%x\n", event->event);
388 static ssize_t hns3_pmu_filter_mode_show(struct device *dev,
389 struct device_attribute *attr,
392 struct hns3_pmu_event_attr *event;
393 struct dev_ext_attribute *eattr;
396 eattr = container_of(attr, struct dev_ext_attribute, attr);
399 len = sysfs_emit_at(buf, 0, "filter mode supported: ");
400 if (event->filter_support & HNS3_PMU_FILTER_SUPPORT_GLOBAL)
401 len += sysfs_emit_at(buf, len, "global ");
402 if (event->filter_support & HNS3_PMU_FILTER_SUPPORT_PORT)
403 len += sysfs_emit_at(buf, len, "port ");
404 if (event->filter_support & HNS3_PMU_FILTER_SUPPORT_PORT_TC)
405 len += sysfs_emit_at(buf, len, "port-tc ");
406 if (event->filter_support & HNS3_PMU_FILTER_SUPPORT_FUNC)
407 len += sysfs_emit_at(buf, len, "func ");
408 if (event->filter_support & HNS3_PMU_FILTER_SUPPORT_FUNC_QUEUE)
409 len += sysfs_emit_at(buf, len, "func-queue ");
410 if (event->filter_support & HNS3_PMU_FILTER_SUPPORT_FUNC_INTR)
411 len += sysfs_emit_at(buf, len, "func-intr ");
413 len += sysfs_emit_at(buf, len, "\n");
418 #define HNS3_PMU_ATTR(_name, _func, _config) \
419 (&((struct dev_ext_attribute[]) { \
420 { __ATTR(_name, 0444, _func, NULL), (void *)_config } \
423 #define HNS3_PMU_FORMAT_ATTR(_name, _format) \
424 HNS3_PMU_ATTR(_name, hns3_pmu_format_show, (void *)_format)
425 #define HNS3_PMU_EVENT_ATTR(_name, _event) \
426 HNS3_PMU_ATTR(_name, hns3_pmu_event_show, (void *)_event)
427 #define HNS3_PMU_FLT_MODE_ATTR(_name, _event) \
428 HNS3_PMU_ATTR(_name, hns3_pmu_filter_mode_show, (void *)_event)
430 #define HNS3_PMU_BW_EVT_PAIR(_name, _macro) \
431 HNS3_PMU_EVENT_ATTR(_name##_byte_num, HNS3_BW_EVT_BYTE_NUM(_macro)), \
432 HNS3_PMU_EVENT_ATTR(_name##_time, HNS3_BW_EVT_TIME(_macro))
433 #define HNS3_PMU_PPS_EVT_PAIR(_name, _macro) \
434 HNS3_PMU_EVENT_ATTR(_name##_packet_num, HNS3_PPS_EVT_PACKET_NUM(_macro)), \
435 HNS3_PMU_EVENT_ATTR(_name##_time, HNS3_PPS_EVT_TIME(_macro))
436 #define HNS3_PMU_DLY_EVT_PAIR(_name, _macro) \
437 HNS3_PMU_EVENT_ATTR(_name##_time, HNS3_DLY_EVT_TIME(_macro)), \
438 HNS3_PMU_EVENT_ATTR(_name##_packet_num, HNS3_DLY_EVT_PACKET_NUM(_macro))
439 #define HNS3_PMU_INTR_EVT_PAIR(_name, _macro) \
440 HNS3_PMU_EVENT_ATTR(_name##_intr_num, HNS3_INTR_EVT_INTR_NUM(_macro)), \
441 HNS3_PMU_EVENT_ATTR(_name##_time, HNS3_INTR_EVT_TIME(_macro))
443 #define HNS3_PMU_BW_FLT_MODE_PAIR(_name, _macro) \
444 HNS3_PMU_FLT_MODE_ATTR(_name##_byte_num, HNS3_BW_EVT_BYTE_NUM(_macro)), \
445 HNS3_PMU_FLT_MODE_ATTR(_name##_time, HNS3_BW_EVT_TIME(_macro))
446 #define HNS3_PMU_PPS_FLT_MODE_PAIR(_name, _macro) \
447 HNS3_PMU_FLT_MODE_ATTR(_name##_packet_num, HNS3_PPS_EVT_PACKET_NUM(_macro)), \
448 HNS3_PMU_FLT_MODE_ATTR(_name##_time, HNS3_PPS_EVT_TIME(_macro))
449 #define HNS3_PMU_DLY_FLT_MODE_PAIR(_name, _macro) \
450 HNS3_PMU_FLT_MODE_ATTR(_name##_time, HNS3_DLY_EVT_TIME(_macro)), \
451 HNS3_PMU_FLT_MODE_ATTR(_name##_packet_num, HNS3_DLY_EVT_PACKET_NUM(_macro))
452 #define HNS3_PMU_INTR_FLT_MODE_PAIR(_name, _macro) \
453 HNS3_PMU_FLT_MODE_ATTR(_name##_intr_num, HNS3_INTR_EVT_INTR_NUM(_macro)), \
454 HNS3_PMU_FLT_MODE_ATTR(_name##_time, HNS3_INTR_EVT_TIME(_macro))
456 static u8 hns3_pmu_hw_filter_modes[] = {
457 HNS3_PMU_HW_FILTER_GLOBAL,
458 HNS3_PMU_HW_FILTER_PORT,
459 HNS3_PMU_HW_FILTER_PORT_TC,
460 HNS3_PMU_HW_FILTER_FUNC,
461 HNS3_PMU_HW_FILTER_FUNC_QUEUE,
462 HNS3_PMU_HW_FILTER_FUNC_INTR,
465 #define HNS3_PMU_SET_HW_FILTER(_hwc, _mode) \
466 ((_hwc)->addr_filters = (void *)&hns3_pmu_hw_filter_modes[(_mode)])
468 static ssize_t identifier_show(struct device *dev,
469 struct device_attribute *attr, char *buf)
471 struct hns3_pmu *hns3_pmu = to_hns3_pmu(dev_get_drvdata(dev));
473 return sysfs_emit(buf, "0x%x\n", hns3_pmu->identifier);
475 static DEVICE_ATTR_RO(identifier);
477 static ssize_t cpumask_show(struct device *dev, struct device_attribute *attr,
480 struct hns3_pmu *hns3_pmu = to_hns3_pmu(dev_get_drvdata(dev));
482 return sysfs_emit(buf, "%d\n", hns3_pmu->on_cpu);
484 static DEVICE_ATTR_RO(cpumask);
486 static ssize_t bdf_min_show(struct device *dev, struct device_attribute *attr,
489 struct hns3_pmu *hns3_pmu = to_hns3_pmu(dev_get_drvdata(dev));
490 u16 bdf = hns3_pmu->bdf_min;
492 return sysfs_emit(buf, "%02x:%02x.%x\n", PCI_BUS_NUM(bdf),
493 PCI_SLOT(bdf), PCI_FUNC(bdf));
495 static DEVICE_ATTR_RO(bdf_min);
497 static ssize_t bdf_max_show(struct device *dev, struct device_attribute *attr,
500 struct hns3_pmu *hns3_pmu = to_hns3_pmu(dev_get_drvdata(dev));
501 u16 bdf = hns3_pmu->bdf_max;
503 return sysfs_emit(buf, "%02x:%02x.%x\n", PCI_BUS_NUM(bdf),
504 PCI_SLOT(bdf), PCI_FUNC(bdf));
506 static DEVICE_ATTR_RO(bdf_max);
508 static ssize_t hw_clk_freq_show(struct device *dev,
509 struct device_attribute *attr, char *buf)
511 struct hns3_pmu *hns3_pmu = to_hns3_pmu(dev_get_drvdata(dev));
513 return sysfs_emit(buf, "%u\n", hns3_pmu->hw_clk_freq);
515 static DEVICE_ATTR_RO(hw_clk_freq);
517 static struct attribute *hns3_pmu_events_attr[] = {
518 /* bandwidth events */
519 HNS3_PMU_BW_EVT_PAIR(bw_ssu_egu, SSU_EGU),
520 HNS3_PMU_BW_EVT_PAIR(bw_ssu_rpu, SSU_RPU),
521 HNS3_PMU_BW_EVT_PAIR(bw_ssu_roce, SSU_ROCE),
522 HNS3_PMU_BW_EVT_PAIR(bw_roce_ssu, ROCE_SSU),
523 HNS3_PMU_BW_EVT_PAIR(bw_tpu_ssu, TPU_SSU),
524 HNS3_PMU_BW_EVT_PAIR(bw_rpu_rcbrx, RPU_RCBRX),
525 HNS3_PMU_BW_EVT_PAIR(bw_rcbtx_txsch, RCBTX_TXSCH),
526 HNS3_PMU_BW_EVT_PAIR(bw_wr_fbd, WR_FBD),
527 HNS3_PMU_BW_EVT_PAIR(bw_wr_ebd, WR_EBD),
528 HNS3_PMU_BW_EVT_PAIR(bw_rd_fbd, RD_FBD),
529 HNS3_PMU_BW_EVT_PAIR(bw_rd_ebd, RD_EBD),
530 HNS3_PMU_BW_EVT_PAIR(bw_rd_pay_m0, RD_PAY_M0),
531 HNS3_PMU_BW_EVT_PAIR(bw_rd_pay_m1, RD_PAY_M1),
532 HNS3_PMU_BW_EVT_PAIR(bw_wr_pay_m0, WR_PAY_M0),
533 HNS3_PMU_BW_EVT_PAIR(bw_wr_pay_m1, WR_PAY_M1),
535 /* packet rate events */
536 HNS3_PMU_PPS_EVT_PAIR(pps_igu_ssu, IGU_SSU),
537 HNS3_PMU_PPS_EVT_PAIR(pps_ssu_egu, SSU_EGU),
538 HNS3_PMU_PPS_EVT_PAIR(pps_ssu_rpu, SSU_RPU),
539 HNS3_PMU_PPS_EVT_PAIR(pps_ssu_roce, SSU_ROCE),
540 HNS3_PMU_PPS_EVT_PAIR(pps_roce_ssu, ROCE_SSU),
541 HNS3_PMU_PPS_EVT_PAIR(pps_tpu_ssu, TPU_SSU),
542 HNS3_PMU_PPS_EVT_PAIR(pps_rpu_rcbrx, RPU_RCBRX),
543 HNS3_PMU_PPS_EVT_PAIR(pps_rcbtx_tpu, RCBTX_TPU),
544 HNS3_PMU_PPS_EVT_PAIR(pps_rcbtx_txsch, RCBTX_TXSCH),
545 HNS3_PMU_PPS_EVT_PAIR(pps_wr_fbd, WR_FBD),
546 HNS3_PMU_PPS_EVT_PAIR(pps_wr_ebd, WR_EBD),
547 HNS3_PMU_PPS_EVT_PAIR(pps_rd_fbd, RD_FBD),
548 HNS3_PMU_PPS_EVT_PAIR(pps_rd_ebd, RD_EBD),
549 HNS3_PMU_PPS_EVT_PAIR(pps_rd_pay_m0, RD_PAY_M0),
550 HNS3_PMU_PPS_EVT_PAIR(pps_rd_pay_m1, RD_PAY_M1),
551 HNS3_PMU_PPS_EVT_PAIR(pps_wr_pay_m0, WR_PAY_M0),
552 HNS3_PMU_PPS_EVT_PAIR(pps_wr_pay_m1, WR_PAY_M1),
553 HNS3_PMU_PPS_EVT_PAIR(pps_intr_nicroh_tx_pre, NICROH_TX_PRE),
554 HNS3_PMU_PPS_EVT_PAIR(pps_intr_nicroh_rx_pre, NICROH_RX_PRE),
557 HNS3_PMU_DLY_EVT_PAIR(dly_tx_push_to_mac, TX_PUSH),
558 HNS3_PMU_DLY_EVT_PAIR(dly_tx_normal_to_mac, TX),
559 HNS3_PMU_DLY_EVT_PAIR(dly_ssu_tx_th_nic, SSU_TX_NIC),
560 HNS3_PMU_DLY_EVT_PAIR(dly_ssu_tx_th_roce, SSU_TX_ROCE),
561 HNS3_PMU_DLY_EVT_PAIR(dly_ssu_rx_th_nic, SSU_RX_NIC),
562 HNS3_PMU_DLY_EVT_PAIR(dly_ssu_rx_th_roce, SSU_RX_ROCE),
563 HNS3_PMU_DLY_EVT_PAIR(dly_rpu, RPU),
564 HNS3_PMU_DLY_EVT_PAIR(dly_tpu, TPU),
565 HNS3_PMU_DLY_EVT_PAIR(dly_rpe, RPE),
566 HNS3_PMU_DLY_EVT_PAIR(dly_tpe_normal, TPE),
567 HNS3_PMU_DLY_EVT_PAIR(dly_tpe_push, TPE_PUSH),
568 HNS3_PMU_DLY_EVT_PAIR(dly_wr_fbd, WR_FBD),
569 HNS3_PMU_DLY_EVT_PAIR(dly_wr_ebd, WR_EBD),
570 HNS3_PMU_DLY_EVT_PAIR(dly_rd_fbd, RD_FBD),
571 HNS3_PMU_DLY_EVT_PAIR(dly_rd_ebd, RD_EBD),
572 HNS3_PMU_DLY_EVT_PAIR(dly_rd_pay_m0, RD_PAY_M0),
573 HNS3_PMU_DLY_EVT_PAIR(dly_rd_pay_m1, RD_PAY_M1),
574 HNS3_PMU_DLY_EVT_PAIR(dly_wr_pay_m0, WR_PAY_M0),
575 HNS3_PMU_DLY_EVT_PAIR(dly_wr_pay_m1, WR_PAY_M1),
576 HNS3_PMU_DLY_EVT_PAIR(dly_msix_write, MSIX_WRITE),
578 /* interrupt rate events */
579 HNS3_PMU_INTR_EVT_PAIR(pps_intr_msix_nic, MSIX_NIC),
584 static struct attribute *hns3_pmu_filter_mode_attr[] = {
585 /* bandwidth events */
586 HNS3_PMU_BW_FLT_MODE_PAIR(bw_ssu_egu, SSU_EGU),
587 HNS3_PMU_BW_FLT_MODE_PAIR(bw_ssu_rpu, SSU_RPU),
588 HNS3_PMU_BW_FLT_MODE_PAIR(bw_ssu_roce, SSU_ROCE),
589 HNS3_PMU_BW_FLT_MODE_PAIR(bw_roce_ssu, ROCE_SSU),
590 HNS3_PMU_BW_FLT_MODE_PAIR(bw_tpu_ssu, TPU_SSU),
591 HNS3_PMU_BW_FLT_MODE_PAIR(bw_rpu_rcbrx, RPU_RCBRX),
592 HNS3_PMU_BW_FLT_MODE_PAIR(bw_rcbtx_txsch, RCBTX_TXSCH),
593 HNS3_PMU_BW_FLT_MODE_PAIR(bw_wr_fbd, WR_FBD),
594 HNS3_PMU_BW_FLT_MODE_PAIR(bw_wr_ebd, WR_EBD),
595 HNS3_PMU_BW_FLT_MODE_PAIR(bw_rd_fbd, RD_FBD),
596 HNS3_PMU_BW_FLT_MODE_PAIR(bw_rd_ebd, RD_EBD),
597 HNS3_PMU_BW_FLT_MODE_PAIR(bw_rd_pay_m0, RD_PAY_M0),
598 HNS3_PMU_BW_FLT_MODE_PAIR(bw_rd_pay_m1, RD_PAY_M1),
599 HNS3_PMU_BW_FLT_MODE_PAIR(bw_wr_pay_m0, WR_PAY_M0),
600 HNS3_PMU_BW_FLT_MODE_PAIR(bw_wr_pay_m1, WR_PAY_M1),
602 /* packet rate events */
603 HNS3_PMU_PPS_FLT_MODE_PAIR(pps_igu_ssu, IGU_SSU),
604 HNS3_PMU_PPS_FLT_MODE_PAIR(pps_ssu_egu, SSU_EGU),
605 HNS3_PMU_PPS_FLT_MODE_PAIR(pps_ssu_rpu, SSU_RPU),
606 HNS3_PMU_PPS_FLT_MODE_PAIR(pps_ssu_roce, SSU_ROCE),
607 HNS3_PMU_PPS_FLT_MODE_PAIR(pps_roce_ssu, ROCE_SSU),
608 HNS3_PMU_PPS_FLT_MODE_PAIR(pps_tpu_ssu, TPU_SSU),
609 HNS3_PMU_PPS_FLT_MODE_PAIR(pps_rpu_rcbrx, RPU_RCBRX),
610 HNS3_PMU_PPS_FLT_MODE_PAIR(pps_rcbtx_tpu, RCBTX_TPU),
611 HNS3_PMU_PPS_FLT_MODE_PAIR(pps_rcbtx_txsch, RCBTX_TXSCH),
612 HNS3_PMU_PPS_FLT_MODE_PAIR(pps_wr_fbd, WR_FBD),
613 HNS3_PMU_PPS_FLT_MODE_PAIR(pps_wr_ebd, WR_EBD),
614 HNS3_PMU_PPS_FLT_MODE_PAIR(pps_rd_fbd, RD_FBD),
615 HNS3_PMU_PPS_FLT_MODE_PAIR(pps_rd_ebd, RD_EBD),
616 HNS3_PMU_PPS_FLT_MODE_PAIR(pps_rd_pay_m0, RD_PAY_M0),
617 HNS3_PMU_PPS_FLT_MODE_PAIR(pps_rd_pay_m1, RD_PAY_M1),
618 HNS3_PMU_PPS_FLT_MODE_PAIR(pps_wr_pay_m0, WR_PAY_M0),
619 HNS3_PMU_PPS_FLT_MODE_PAIR(pps_wr_pay_m1, WR_PAY_M1),
620 HNS3_PMU_PPS_FLT_MODE_PAIR(pps_intr_nicroh_tx_pre, NICROH_TX_PRE),
621 HNS3_PMU_PPS_FLT_MODE_PAIR(pps_intr_nicroh_rx_pre, NICROH_RX_PRE),
624 HNS3_PMU_DLY_FLT_MODE_PAIR(dly_tx_push_to_mac, TX_PUSH),
625 HNS3_PMU_DLY_FLT_MODE_PAIR(dly_tx_normal_to_mac, TX),
626 HNS3_PMU_DLY_FLT_MODE_PAIR(dly_ssu_tx_th_nic, SSU_TX_NIC),
627 HNS3_PMU_DLY_FLT_MODE_PAIR(dly_ssu_tx_th_roce, SSU_TX_ROCE),
628 HNS3_PMU_DLY_FLT_MODE_PAIR(dly_ssu_rx_th_nic, SSU_RX_NIC),
629 HNS3_PMU_DLY_FLT_MODE_PAIR(dly_ssu_rx_th_roce, SSU_RX_ROCE),
630 HNS3_PMU_DLY_FLT_MODE_PAIR(dly_rpu, RPU),
631 HNS3_PMU_DLY_FLT_MODE_PAIR(dly_tpu, TPU),
632 HNS3_PMU_DLY_FLT_MODE_PAIR(dly_rpe, RPE),
633 HNS3_PMU_DLY_FLT_MODE_PAIR(dly_tpe_normal, TPE),
634 HNS3_PMU_DLY_FLT_MODE_PAIR(dly_tpe_push, TPE_PUSH),
635 HNS3_PMU_DLY_FLT_MODE_PAIR(dly_wr_fbd, WR_FBD),
636 HNS3_PMU_DLY_FLT_MODE_PAIR(dly_wr_ebd, WR_EBD),
637 HNS3_PMU_DLY_FLT_MODE_PAIR(dly_rd_fbd, RD_FBD),
638 HNS3_PMU_DLY_FLT_MODE_PAIR(dly_rd_ebd, RD_EBD),
639 HNS3_PMU_DLY_FLT_MODE_PAIR(dly_rd_pay_m0, RD_PAY_M0),
640 HNS3_PMU_DLY_FLT_MODE_PAIR(dly_rd_pay_m1, RD_PAY_M1),
641 HNS3_PMU_DLY_FLT_MODE_PAIR(dly_wr_pay_m0, WR_PAY_M0),
642 HNS3_PMU_DLY_FLT_MODE_PAIR(dly_wr_pay_m1, WR_PAY_M1),
643 HNS3_PMU_DLY_FLT_MODE_PAIR(dly_msix_write, MSIX_WRITE),
645 /* interrupt rate events */
646 HNS3_PMU_INTR_FLT_MODE_PAIR(pps_intr_msix_nic, MSIX_NIC),
651 static struct attribute_group hns3_pmu_events_group = {
653 .attrs = hns3_pmu_events_attr,
656 static struct attribute_group hns3_pmu_filter_mode_group = {
657 .name = "filtermode",
658 .attrs = hns3_pmu_filter_mode_attr,
661 static struct attribute *hns3_pmu_format_attr[] = {
662 HNS3_PMU_FORMAT_ATTR(subevent, "config:0-7"),
663 HNS3_PMU_FORMAT_ATTR(event_type, "config:8-15"),
664 HNS3_PMU_FORMAT_ATTR(ext_counter_used, "config:16"),
665 HNS3_PMU_FORMAT_ATTR(port, "config1:0-3"),
666 HNS3_PMU_FORMAT_ATTR(tc, "config1:4-7"),
667 HNS3_PMU_FORMAT_ATTR(bdf, "config1:8-23"),
668 HNS3_PMU_FORMAT_ATTR(queue, "config1:24-39"),
669 HNS3_PMU_FORMAT_ATTR(intr, "config1:40-51"),
670 HNS3_PMU_FORMAT_ATTR(global, "config1:52"),
674 static struct attribute_group hns3_pmu_format_group = {
676 .attrs = hns3_pmu_format_attr,
679 static struct attribute *hns3_pmu_cpumask_attrs[] = {
680 &dev_attr_cpumask.attr,
684 static struct attribute_group hns3_pmu_cpumask_attr_group = {
685 .attrs = hns3_pmu_cpumask_attrs,
688 static struct attribute *hns3_pmu_identifier_attrs[] = {
689 &dev_attr_identifier.attr,
693 static struct attribute_group hns3_pmu_identifier_attr_group = {
694 .attrs = hns3_pmu_identifier_attrs,
697 static struct attribute *hns3_pmu_bdf_range_attrs[] = {
698 &dev_attr_bdf_min.attr,
699 &dev_attr_bdf_max.attr,
703 static struct attribute_group hns3_pmu_bdf_range_attr_group = {
704 .attrs = hns3_pmu_bdf_range_attrs,
707 static struct attribute *hns3_pmu_hw_clk_freq_attrs[] = {
708 &dev_attr_hw_clk_freq.attr,
712 static struct attribute_group hns3_pmu_hw_clk_freq_attr_group = {
713 .attrs = hns3_pmu_hw_clk_freq_attrs,
716 static const struct attribute_group *hns3_pmu_attr_groups[] = {
717 &hns3_pmu_events_group,
718 &hns3_pmu_filter_mode_group,
719 &hns3_pmu_format_group,
720 &hns3_pmu_cpumask_attr_group,
721 &hns3_pmu_identifier_attr_group,
722 &hns3_pmu_bdf_range_attr_group,
723 &hns3_pmu_hw_clk_freq_attr_group,
727 static u32 hns3_pmu_get_event(struct perf_event *event)
729 return hns3_pmu_get_ext_counter_used(event) << 16 |
730 hns3_pmu_get_event_type(event) << 8 |
731 hns3_pmu_get_subevent(event);
734 static u32 hns3_pmu_get_real_event(struct perf_event *event)
736 return hns3_pmu_get_event_type(event) << 8 |
737 hns3_pmu_get_subevent(event);
740 static u32 hns3_pmu_get_offset(u32 offset, u32 idx)
742 return offset + HNS3_PMU_REG_EVENT_OFFSET +
743 HNS3_PMU_REG_EVENT_SIZE * idx;
746 static u32 hns3_pmu_readl(struct hns3_pmu *hns3_pmu, u32 reg_offset, u32 idx)
748 u32 offset = hns3_pmu_get_offset(reg_offset, idx);
750 return readl(hns3_pmu->base + offset);
753 static void hns3_pmu_writel(struct hns3_pmu *hns3_pmu, u32 reg_offset, u32 idx,
756 u32 offset = hns3_pmu_get_offset(reg_offset, idx);
758 writel(val, hns3_pmu->base + offset);
761 static u64 hns3_pmu_readq(struct hns3_pmu *hns3_pmu, u32 reg_offset, u32 idx)
763 u32 offset = hns3_pmu_get_offset(reg_offset, idx);
765 return readq(hns3_pmu->base + offset);
768 static void hns3_pmu_writeq(struct hns3_pmu *hns3_pmu, u32 reg_offset, u32 idx,
771 u32 offset = hns3_pmu_get_offset(reg_offset, idx);
773 writeq(val, hns3_pmu->base + offset);
776 static bool hns3_pmu_cmp_event(struct perf_event *target,
777 struct perf_event *event)
779 return hns3_pmu_get_real_event(target) == hns3_pmu_get_real_event(event);
782 static int hns3_pmu_find_related_event_idx(struct hns3_pmu *hns3_pmu,
783 struct perf_event *event)
785 struct perf_event *sibling;
786 int hw_event_used = 0;
789 for (idx = 0; idx < HNS3_PMU_MAX_HW_EVENTS; idx++) {
790 sibling = hns3_pmu->hw_events[idx];
796 if (!hns3_pmu_cmp_event(sibling, event))
799 /* Related events is used in group */
800 if (sibling->group_leader == event->group_leader)
804 /* No related event and all hardware events are used up */
805 if (hw_event_used >= HNS3_PMU_MAX_HW_EVENTS)
808 /* No related event and there is extra hardware events can be use */
812 static int hns3_pmu_get_event_idx(struct hns3_pmu *hns3_pmu)
816 for (idx = 0; idx < HNS3_PMU_MAX_HW_EVENTS; idx++) {
817 if (!hns3_pmu->hw_events[idx])
824 static bool hns3_pmu_valid_bdf(struct hns3_pmu *hns3_pmu, u16 bdf)
826 struct pci_dev *pdev;
828 if (bdf < hns3_pmu->bdf_min || bdf > hns3_pmu->bdf_max) {
829 pci_err(hns3_pmu->pdev, "Invalid EP device: %#x!\n", bdf);
833 pdev = pci_get_domain_bus_and_slot(pci_domain_nr(hns3_pmu->pdev->bus),
837 pci_err(hns3_pmu->pdev, "Nonexistent EP device: %#x!\n", bdf);
845 static void hns3_pmu_set_qid_para(struct hns3_pmu *hns3_pmu, u32 idx, u16 bdf,
850 val = GET_PCI_DEVFN(bdf);
851 val |= (u32)queue << HNS3_PMU_QID_PARA_QUEUE_S;
852 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_QID_PARA, idx, val);
855 static bool hns3_pmu_qid_req_start(struct hns3_pmu *hns3_pmu, u32 idx)
857 bool queue_id_valid = false;
858 u32 reg_qid_ctrl, val;
861 /* enable queue id request */
862 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_QID_CTRL, idx,
863 HNS3_PMU_QID_CTRL_REQ_ENABLE);
865 reg_qid_ctrl = hns3_pmu_get_offset(HNS3_PMU_REG_EVENT_QID_CTRL, idx);
866 err = readl_poll_timeout(hns3_pmu->base + reg_qid_ctrl, val,
867 val & HNS3_PMU_QID_CTRL_DONE, 1, 1000);
868 if (err == -ETIMEDOUT) {
869 pci_err(hns3_pmu->pdev, "QID request timeout!\n");
873 queue_id_valid = !(val & HNS3_PMU_QID_CTRL_MISS);
876 /* disable qid request and clear status */
877 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_QID_CTRL, idx, 0);
879 return queue_id_valid;
882 static bool hns3_pmu_valid_queue(struct hns3_pmu *hns3_pmu, u32 idx, u16 bdf,
885 hns3_pmu_set_qid_para(hns3_pmu, idx, bdf, queue);
887 return hns3_pmu_qid_req_start(hns3_pmu, idx);
890 static struct hns3_pmu_event_attr *hns3_pmu_get_pmu_event(u32 event)
892 struct hns3_pmu_event_attr *pmu_event;
893 struct dev_ext_attribute *eattr;
894 struct device_attribute *dattr;
895 struct attribute *attr;
898 for (i = 0; i < ARRAY_SIZE(hns3_pmu_events_attr) - 1; i++) {
899 attr = hns3_pmu_events_attr[i];
900 dattr = container_of(attr, struct device_attribute, attr);
901 eattr = container_of(dattr, struct dev_ext_attribute, attr);
902 pmu_event = eattr->var;
904 if (event == pmu_event->event)
911 static int hns3_pmu_set_func_mode(struct perf_event *event,
912 struct hns3_pmu *hns3_pmu)
914 struct hw_perf_event *hwc = &event->hw;
915 u16 bdf = hns3_pmu_get_bdf(event);
917 if (!hns3_pmu_valid_bdf(hns3_pmu, bdf))
920 HNS3_PMU_SET_HW_FILTER(hwc, HNS3_PMU_HW_FILTER_FUNC);
925 static int hns3_pmu_set_func_queue_mode(struct perf_event *event,
926 struct hns3_pmu *hns3_pmu)
928 u16 queue_id = hns3_pmu_get_queue(event);
929 struct hw_perf_event *hwc = &event->hw;
930 u16 bdf = hns3_pmu_get_bdf(event);
932 if (!hns3_pmu_valid_bdf(hns3_pmu, bdf))
935 if (!hns3_pmu_valid_queue(hns3_pmu, hwc->idx, bdf, queue_id)) {
936 pci_err(hns3_pmu->pdev, "Invalid queue: %u\n", queue_id);
940 HNS3_PMU_SET_HW_FILTER(hwc, HNS3_PMU_HW_FILTER_FUNC_QUEUE);
946 hns3_pmu_is_enabled_global_mode(struct perf_event *event,
947 struct hns3_pmu_event_attr *pmu_event)
949 u8 global = hns3_pmu_get_global(event);
951 if (!(pmu_event->filter_support & HNS3_PMU_FILTER_SUPPORT_GLOBAL))
957 static bool hns3_pmu_is_enabled_func_mode(struct perf_event *event,
958 struct hns3_pmu_event_attr *pmu_event)
960 u16 queue_id = hns3_pmu_get_queue(event);
961 u16 bdf = hns3_pmu_get_bdf(event);
963 if (!(pmu_event->filter_support & HNS3_PMU_FILTER_SUPPORT_FUNC))
965 else if (queue_id != HNS3_PMU_FILTER_ALL_QUEUE)
972 hns3_pmu_is_enabled_func_queue_mode(struct perf_event *event,
973 struct hns3_pmu_event_attr *pmu_event)
975 u16 queue_id = hns3_pmu_get_queue(event);
976 u16 bdf = hns3_pmu_get_bdf(event);
978 if (!(pmu_event->filter_support & HNS3_PMU_FILTER_SUPPORT_FUNC_QUEUE))
980 else if (queue_id == HNS3_PMU_FILTER_ALL_QUEUE)
986 static bool hns3_pmu_is_enabled_port_mode(struct perf_event *event,
987 struct hns3_pmu_event_attr *pmu_event)
989 u8 tc_id = hns3_pmu_get_tc(event);
991 if (!(pmu_event->filter_support & HNS3_PMU_FILTER_SUPPORT_PORT))
994 return tc_id == HNS3_PMU_FILTER_ALL_TC;
998 hns3_pmu_is_enabled_port_tc_mode(struct perf_event *event,
999 struct hns3_pmu_event_attr *pmu_event)
1001 u8 tc_id = hns3_pmu_get_tc(event);
1003 if (!(pmu_event->filter_support & HNS3_PMU_FILTER_SUPPORT_PORT_TC))
1006 return tc_id != HNS3_PMU_FILTER_ALL_TC;
1010 hns3_pmu_is_enabled_func_intr_mode(struct perf_event *event,
1011 struct hns3_pmu *hns3_pmu,
1012 struct hns3_pmu_event_attr *pmu_event)
1014 u16 bdf = hns3_pmu_get_bdf(event);
1016 if (!(pmu_event->filter_support & HNS3_PMU_FILTER_SUPPORT_FUNC_INTR))
1019 return hns3_pmu_valid_bdf(hns3_pmu, bdf);
1022 static int hns3_pmu_select_filter_mode(struct perf_event *event,
1023 struct hns3_pmu *hns3_pmu)
1025 u32 event_id = hns3_pmu_get_event(event);
1026 struct hw_perf_event *hwc = &event->hw;
1027 struct hns3_pmu_event_attr *pmu_event;
1029 pmu_event = hns3_pmu_get_pmu_event(event_id);
1031 pci_err(hns3_pmu->pdev, "Invalid pmu event\n");
1035 if (hns3_pmu_is_enabled_global_mode(event, pmu_event)) {
1036 HNS3_PMU_SET_HW_FILTER(hwc, HNS3_PMU_HW_FILTER_GLOBAL);
1040 if (hns3_pmu_is_enabled_func_mode(event, pmu_event))
1041 return hns3_pmu_set_func_mode(event, hns3_pmu);
1043 if (hns3_pmu_is_enabled_func_queue_mode(event, pmu_event))
1044 return hns3_pmu_set_func_queue_mode(event, hns3_pmu);
1046 if (hns3_pmu_is_enabled_port_mode(event, pmu_event)) {
1047 HNS3_PMU_SET_HW_FILTER(hwc, HNS3_PMU_HW_FILTER_PORT);
1051 if (hns3_pmu_is_enabled_port_tc_mode(event, pmu_event)) {
1052 HNS3_PMU_SET_HW_FILTER(hwc, HNS3_PMU_HW_FILTER_PORT_TC);
1056 if (hns3_pmu_is_enabled_func_intr_mode(event, hns3_pmu, pmu_event)) {
1057 HNS3_PMU_SET_HW_FILTER(hwc, HNS3_PMU_HW_FILTER_FUNC_INTR);
1064 static bool hns3_pmu_validate_event_group(struct perf_event *event)
1066 struct perf_event *sibling, *leader = event->group_leader;
1067 struct perf_event *event_group[HNS3_PMU_MAX_HW_EVENTS];
1071 event_group[0] = leader;
1072 if (!is_software_event(leader)) {
1073 if (leader->pmu != event->pmu)
1076 if (leader != event && !hns3_pmu_cmp_event(leader, event))
1077 event_group[counters++] = event;
1080 for_each_sibling_event(sibling, event->group_leader) {
1081 if (is_software_event(sibling))
1084 if (sibling->pmu != event->pmu)
1087 for (num = 0; num < counters; num++) {
1088 if (hns3_pmu_cmp_event(event_group[num], sibling))
1092 if (num == counters)
1093 event_group[counters++] = sibling;
1096 return counters <= HNS3_PMU_MAX_HW_EVENTS;
1099 static u32 hns3_pmu_get_filter_condition(struct perf_event *event)
1101 struct hw_perf_event *hwc = &event->hw;
1102 u16 intr_id = hns3_pmu_get_intr(event);
1103 u8 port_id = hns3_pmu_get_port(event);
1104 u16 bdf = hns3_pmu_get_bdf(event);
1105 u8 tc_id = hns3_pmu_get_tc(event);
1108 filter_mode = *(u8 *)hwc->addr_filters;
1109 switch (filter_mode) {
1110 case HNS3_PMU_HW_FILTER_PORT:
1111 return FILTER_CONDITION_PORT(port_id);
1112 case HNS3_PMU_HW_FILTER_PORT_TC:
1113 return FILTER_CONDITION_PORT_TC(port_id, tc_id);
1114 case HNS3_PMU_HW_FILTER_FUNC:
1115 case HNS3_PMU_HW_FILTER_FUNC_QUEUE:
1116 return GET_PCI_DEVFN(bdf);
1117 case HNS3_PMU_HW_FILTER_FUNC_INTR:
1118 return FILTER_CONDITION_FUNC_INTR(GET_PCI_DEVFN(bdf), intr_id);
1126 static void hns3_pmu_config_filter(struct perf_event *event)
1128 struct hns3_pmu *hns3_pmu = to_hns3_pmu(event->pmu);
1129 u8 event_type = hns3_pmu_get_event_type(event);
1130 u8 subevent_id = hns3_pmu_get_subevent(event);
1131 u16 queue_id = hns3_pmu_get_queue(event);
1132 struct hw_perf_event *hwc = &event->hw;
1133 u8 filter_mode = *(u8 *)hwc->addr_filters;
1134 u16 bdf = hns3_pmu_get_bdf(event);
1139 val |= subevent_id << HNS3_PMU_CTRL_SUBEVENT_S;
1140 val |= filter_mode << HNS3_PMU_CTRL_FILTER_MODE_S;
1141 val |= HNS3_PMU_EVENT_OVERFLOW_RESTART;
1142 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx, val);
1144 val = hns3_pmu_get_filter_condition(event);
1145 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_HIGH, idx, val);
1147 if (filter_mode == HNS3_PMU_HW_FILTER_FUNC_QUEUE)
1148 hns3_pmu_set_qid_para(hns3_pmu, idx, bdf, queue_id);
1151 static void hns3_pmu_enable_counter(struct hns3_pmu *hns3_pmu,
1152 struct hw_perf_event *hwc)
1157 val = hns3_pmu_readl(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx);
1158 val |= HNS3_PMU_EVENT_EN;
1159 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx, val);
1162 static void hns3_pmu_disable_counter(struct hns3_pmu *hns3_pmu,
1163 struct hw_perf_event *hwc)
1168 val = hns3_pmu_readl(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx);
1169 val &= ~HNS3_PMU_EVENT_EN;
1170 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx, val);
1173 static void hns3_pmu_enable_intr(struct hns3_pmu *hns3_pmu,
1174 struct hw_perf_event *hwc)
1179 val = hns3_pmu_readl(hns3_pmu, HNS3_PMU_REG_EVENT_INTR_MASK, idx);
1180 val &= ~HNS3_PMU_INTR_MASK_OVERFLOW;
1181 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_INTR_MASK, idx, val);
1184 static void hns3_pmu_disable_intr(struct hns3_pmu *hns3_pmu,
1185 struct hw_perf_event *hwc)
1190 val = hns3_pmu_readl(hns3_pmu, HNS3_PMU_REG_EVENT_INTR_MASK, idx);
1191 val |= HNS3_PMU_INTR_MASK_OVERFLOW;
1192 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_INTR_MASK, idx, val);
1195 static void hns3_pmu_clear_intr_status(struct hns3_pmu *hns3_pmu, u32 idx)
1199 val = hns3_pmu_readl(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx);
1200 val |= HNS3_PMU_EVENT_STATUS_RESET;
1201 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx, val);
1203 val = hns3_pmu_readl(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx);
1204 val &= ~HNS3_PMU_EVENT_STATUS_RESET;
1205 hns3_pmu_writel(hns3_pmu, HNS3_PMU_REG_EVENT_CTRL_LOW, idx, val);
1208 static u64 hns3_pmu_read_counter(struct perf_event *event)
1210 struct hns3_pmu *hns3_pmu = to_hns3_pmu(event->pmu);
1212 return hns3_pmu_readq(hns3_pmu, event->hw.event_base, event->hw.idx);
1215 static void hns3_pmu_write_counter(struct perf_event *event, u64 value)
1217 struct hns3_pmu *hns3_pmu = to_hns3_pmu(event->pmu);
1218 u32 idx = event->hw.idx;
1220 hns3_pmu_writeq(hns3_pmu, HNS3_PMU_REG_EVENT_COUNTER, idx, value);
1221 hns3_pmu_writeq(hns3_pmu, HNS3_PMU_REG_EVENT_EXT_COUNTER, idx, value);
1224 static void hns3_pmu_init_counter(struct perf_event *event)
1226 struct hw_perf_event *hwc = &event->hw;
1228 local64_set(&hwc->prev_count, 0);
1229 hns3_pmu_write_counter(event, 0);
1232 static int hns3_pmu_event_init(struct perf_event *event)
1234 struct hns3_pmu *hns3_pmu = to_hns3_pmu(event->pmu);
1235 struct hw_perf_event *hwc = &event->hw;
1239 if (event->attr.type != event->pmu->type)
1242 /* Sampling is not supported */
1243 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
1246 event->cpu = hns3_pmu->on_cpu;
1248 idx = hns3_pmu_get_event_idx(hns3_pmu);
1250 pci_err(hns3_pmu->pdev, "Up to %u events are supported!\n",
1251 HNS3_PMU_MAX_HW_EVENTS);
1257 ret = hns3_pmu_select_filter_mode(event, hns3_pmu);
1259 pci_err(hns3_pmu->pdev, "Invalid filter, ret = %d.\n", ret);
1263 if (!hns3_pmu_validate_event_group(event)) {
1264 pci_err(hns3_pmu->pdev, "Invalid event group.\n");
1268 if (hns3_pmu_get_ext_counter_used(event))
1269 hwc->event_base = HNS3_PMU_REG_EVENT_EXT_COUNTER;
1271 hwc->event_base = HNS3_PMU_REG_EVENT_COUNTER;
1276 static void hns3_pmu_read(struct perf_event *event)
1278 struct hw_perf_event *hwc = &event->hw;
1279 u64 new_cnt, prev_cnt, delta;
1282 prev_cnt = local64_read(&hwc->prev_count);
1283 new_cnt = hns3_pmu_read_counter(event);
1284 } while (local64_cmpxchg(&hwc->prev_count, prev_cnt, new_cnt) !=
1287 delta = new_cnt - prev_cnt;
1288 local64_add(delta, &event->count);
1291 static void hns3_pmu_start(struct perf_event *event, int flags)
1293 struct hns3_pmu *hns3_pmu = to_hns3_pmu(event->pmu);
1294 struct hw_perf_event *hwc = &event->hw;
1296 if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
1299 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
1302 hns3_pmu_config_filter(event);
1303 hns3_pmu_init_counter(event);
1304 hns3_pmu_enable_intr(hns3_pmu, hwc);
1305 hns3_pmu_enable_counter(hns3_pmu, hwc);
1307 perf_event_update_userpage(event);
1310 static void hns3_pmu_stop(struct perf_event *event, int flags)
1312 struct hns3_pmu *hns3_pmu = to_hns3_pmu(event->pmu);
1313 struct hw_perf_event *hwc = &event->hw;
1315 hns3_pmu_disable_counter(hns3_pmu, hwc);
1316 hns3_pmu_disable_intr(hns3_pmu, hwc);
1318 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1319 hwc->state |= PERF_HES_STOPPED;
1321 if (hwc->state & PERF_HES_UPTODATE)
1324 /* Read hardware counter and update the perf counter statistics */
1325 hns3_pmu_read(event);
1326 hwc->state |= PERF_HES_UPTODATE;
1329 static int hns3_pmu_add(struct perf_event *event, int flags)
1331 struct hns3_pmu *hns3_pmu = to_hns3_pmu(event->pmu);
1332 struct hw_perf_event *hwc = &event->hw;
1335 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
1337 /* Check all working events to find a related event. */
1338 idx = hns3_pmu_find_related_event_idx(hns3_pmu, event);
1339 if (idx < 0 && idx != -ENOENT)
1342 /* Current event shares an enabled hardware event with related event */
1343 if (idx >= 0 && idx < HNS3_PMU_MAX_HW_EVENTS) {
1348 idx = hns3_pmu_get_event_idx(hns3_pmu);
1353 hns3_pmu->hw_events[idx] = event;
1356 if (flags & PERF_EF_START)
1357 hns3_pmu_start(event, PERF_EF_RELOAD);
1362 static void hns3_pmu_del(struct perf_event *event, int flags)
1364 struct hns3_pmu *hns3_pmu = to_hns3_pmu(event->pmu);
1365 struct hw_perf_event *hwc = &event->hw;
1367 hns3_pmu_stop(event, PERF_EF_UPDATE);
1368 hns3_pmu->hw_events[hwc->idx] = NULL;
1369 perf_event_update_userpage(event);
1372 static void hns3_pmu_enable(struct pmu *pmu)
1374 struct hns3_pmu *hns3_pmu = to_hns3_pmu(pmu);
1377 val = readl(hns3_pmu->base + HNS3_PMU_REG_GLOBAL_CTRL);
1378 val |= HNS3_PMU_GLOBAL_START;
1379 writel(val, hns3_pmu->base + HNS3_PMU_REG_GLOBAL_CTRL);
1382 static void hns3_pmu_disable(struct pmu *pmu)
1384 struct hns3_pmu *hns3_pmu = to_hns3_pmu(pmu);
1387 val = readl(hns3_pmu->base + HNS3_PMU_REG_GLOBAL_CTRL);
1388 val &= ~HNS3_PMU_GLOBAL_START;
1389 writel(val, hns3_pmu->base + HNS3_PMU_REG_GLOBAL_CTRL);
1392 static int hns3_pmu_alloc_pmu(struct pci_dev *pdev, struct hns3_pmu *hns3_pmu)
1398 hns3_pmu->base = pcim_iomap_table(pdev)[BAR_2];
1399 if (!hns3_pmu->base) {
1400 pci_err(pdev, "ioremap failed\n");
1404 hns3_pmu->hw_clk_freq = readl(hns3_pmu->base + HNS3_PMU_REG_CLOCK_FREQ);
1406 val = readl(hns3_pmu->base + HNS3_PMU_REG_BDF);
1407 hns3_pmu->bdf_min = val & 0xffff;
1408 hns3_pmu->bdf_max = val >> 16;
1410 val = readl(hns3_pmu->base + HNS3_PMU_REG_DEVICE_ID);
1411 device_id = val & 0xffff;
1412 name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "hns3_pmu_sicl_%u", device_id);
1416 hns3_pmu->pdev = pdev;
1417 hns3_pmu->on_cpu = -1;
1418 hns3_pmu->identifier = readl(hns3_pmu->base + HNS3_PMU_REG_VERSION);
1419 hns3_pmu->pmu = (struct pmu) {
1421 .module = THIS_MODULE,
1422 .event_init = hns3_pmu_event_init,
1423 .pmu_enable = hns3_pmu_enable,
1424 .pmu_disable = hns3_pmu_disable,
1425 .add = hns3_pmu_add,
1426 .del = hns3_pmu_del,
1427 .start = hns3_pmu_start,
1428 .stop = hns3_pmu_stop,
1429 .read = hns3_pmu_read,
1430 .task_ctx_nr = perf_invalid_context,
1431 .attr_groups = hns3_pmu_attr_groups,
1432 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
1438 static irqreturn_t hns3_pmu_irq(int irq, void *data)
1440 struct hns3_pmu *hns3_pmu = data;
1441 u32 intr_status, idx;
1443 for (idx = 0; idx < HNS3_PMU_MAX_HW_EVENTS; idx++) {
1444 intr_status = hns3_pmu_readl(hns3_pmu,
1445 HNS3_PMU_REG_EVENT_INTR_STATUS,
1449 * As each counter will restart from 0 when it is overflowed,
1450 * extra processing is no need, just clear interrupt status.
1453 hns3_pmu_clear_intr_status(hns3_pmu, idx);
1459 static int hns3_pmu_online_cpu(unsigned int cpu, struct hlist_node *node)
1461 struct hns3_pmu *hns3_pmu;
1463 hns3_pmu = hlist_entry_safe(node, struct hns3_pmu, node);
1467 if (hns3_pmu->on_cpu == -1) {
1468 hns3_pmu->on_cpu = cpu;
1469 irq_set_affinity(hns3_pmu->irq, cpumask_of(cpu));
1475 static int hns3_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
1477 struct hns3_pmu *hns3_pmu;
1478 unsigned int target;
1480 hns3_pmu = hlist_entry_safe(node, struct hns3_pmu, node);
1484 /* Nothing to do if this CPU doesn't own the PMU */
1485 if (hns3_pmu->on_cpu != cpu)
1488 /* Choose a new CPU from all online cpus */
1489 target = cpumask_any_but(cpu_online_mask, cpu);
1490 if (target >= nr_cpu_ids)
1493 perf_pmu_migrate_context(&hns3_pmu->pmu, cpu, target);
1494 hns3_pmu->on_cpu = target;
1495 irq_set_affinity(hns3_pmu->irq, cpumask_of(target));
1500 static void hns3_pmu_free_irq(void *data)
1502 struct pci_dev *pdev = data;
1504 pci_free_irq_vectors(pdev);
1507 static int hns3_pmu_irq_register(struct pci_dev *pdev,
1508 struct hns3_pmu *hns3_pmu)
1512 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1514 pci_err(pdev, "failed to enable MSI vectors, ret = %d.\n", ret);
1518 ret = devm_add_action(&pdev->dev, hns3_pmu_free_irq, pdev);
1520 pci_err(pdev, "failed to add free irq action, ret = %d.\n", ret);
1524 irq = pci_irq_vector(pdev, 0);
1525 ret = devm_request_irq(&pdev->dev, irq, hns3_pmu_irq, 0,
1526 hns3_pmu->pmu.name, hns3_pmu);
1528 pci_err(pdev, "failed to register irq, ret = %d.\n", ret);
1532 hns3_pmu->irq = irq;
1537 static int hns3_pmu_init_pmu(struct pci_dev *pdev, struct hns3_pmu *hns3_pmu)
1541 ret = hns3_pmu_alloc_pmu(pdev, hns3_pmu);
1545 ret = hns3_pmu_irq_register(pdev, hns3_pmu);
1549 ret = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_HNS3_PMU_ONLINE,
1552 pci_err(pdev, "failed to register hotplug, ret = %d.\n", ret);
1556 ret = perf_pmu_register(&hns3_pmu->pmu, hns3_pmu->pmu.name, -1);
1558 pci_err(pdev, "failed to register perf PMU, ret = %d.\n", ret);
1559 cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_HNS3_PMU_ONLINE,
1566 static void hns3_pmu_uninit_pmu(struct pci_dev *pdev)
1568 struct hns3_pmu *hns3_pmu = pci_get_drvdata(pdev);
1570 perf_pmu_unregister(&hns3_pmu->pmu);
1571 cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_HNS3_PMU_ONLINE,
1575 static int hns3_pmu_init_dev(struct pci_dev *pdev)
1579 ret = pcim_enable_device(pdev);
1581 pci_err(pdev, "failed to enable pci device, ret = %d.\n", ret);
1585 ret = pcim_iomap_regions(pdev, BIT(BAR_2), "hns3_pmu");
1587 pci_err(pdev, "failed to request pci region, ret = %d.\n", ret);
1591 pci_set_master(pdev);
1596 static int hns3_pmu_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1598 struct hns3_pmu *hns3_pmu;
1601 hns3_pmu = devm_kzalloc(&pdev->dev, sizeof(*hns3_pmu), GFP_KERNEL);
1605 ret = hns3_pmu_init_dev(pdev);
1609 ret = hns3_pmu_init_pmu(pdev, hns3_pmu);
1611 pci_clear_master(pdev);
1615 pci_set_drvdata(pdev, hns3_pmu);
1620 static void hns3_pmu_remove(struct pci_dev *pdev)
1622 hns3_pmu_uninit_pmu(pdev);
1623 pci_clear_master(pdev);
1624 pci_set_drvdata(pdev, NULL);
1627 static const struct pci_device_id hns3_pmu_ids[] = {
1628 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, 0xa22b) },
1631 MODULE_DEVICE_TABLE(pci, hns3_pmu_ids);
1633 static struct pci_driver hns3_pmu_driver = {
1635 .id_table = hns3_pmu_ids,
1636 .probe = hns3_pmu_probe,
1637 .remove = hns3_pmu_remove,
1640 static int __init hns3_pmu_module_init(void)
1644 ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_HNS3_PMU_ONLINE,
1645 "AP_PERF_ARM_HNS3_PMU_ONLINE",
1646 hns3_pmu_online_cpu,
1647 hns3_pmu_offline_cpu);
1649 pr_err("failed to setup HNS3 PMU hotplug, ret = %d.\n", ret);
1653 ret = pci_register_driver(&hns3_pmu_driver);
1655 pr_err("failed to register pci driver, ret = %d.\n", ret);
1656 cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HNS3_PMU_ONLINE);
1661 module_init(hns3_pmu_module_init);
1663 static void __exit hns3_pmu_module_exit(void)
1665 pci_unregister_driver(&hns3_pmu_driver);
1666 cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HNS3_PMU_ONLINE);
1668 module_exit(hns3_pmu_module_exit);
1670 MODULE_DESCRIPTION("HNS3 PMU driver");
1671 MODULE_LICENSE("GPL v2");