1 # SPDX-License-Identifier: GPL-2.0-only
3 # Performance Monitor Drivers
6 menu "Performance monitor support"
10 tristate "ARM CCI PMU driver"
11 depends on (ARM && CPU_V7) || ARM64
14 Support for PMU events monitoring on the ARM CCI (Cache Coherent
15 Interconnect) family of products.
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
22 depends on ARM_CCI_PMU
23 select ARM_CCI400_COMMON
25 CCI-400 provides 4 independent event counters counting events related
26 to the connected slave/master interfaces, plus a cycle counter.
29 bool "support CCI-500/CCI-550"
31 depends on ARM_CCI_PMU
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
34 count events pertaining to the slave/master interfaces as well as the
35 internal events to the CCI.
38 tristate "ARM CCN driver support"
39 depends on ARM || ARM64 || COMPILE_TEST
41 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
45 tristate "Arm CMN-600 PMU support"
46 depends on ARM64 || COMPILE_TEST
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
52 depends on ARM || ARM64
53 bool "ARM PMU framework"
56 Say y if you want to use CPU performance monitors on ARM-based
61 bool "RISC-V PMU framework"
64 Say y if you want to use CPU performance monitors on RISCV-based
65 systems. This provides the core PMU framework that abstracts common
66 PMU functionalities in a core library so that different PMU drivers
69 config RISCV_PMU_LEGACY
71 bool "RISC-V legacy PMU implementation"
74 Say y if you want to use the legacy CPU performance monitor
75 implementation on RISC-V based systems. This only allows counting
76 of cycle/instruction counter and doesn't support counter overflow,
77 or programmable counters. It will be removed in future.
80 depends on RISCV_PMU && RISCV_SBI
81 bool "RISC-V PMU based on SBI PMU extension"
84 Say y if you want to use the CPU performance monitor
85 using SBI PMU extension on RISC-V based systems. This option provides
86 full perf feature support i.e. counter overflow, privilege mode
87 filtering, counter configuration.
89 config ANDES_CUSTOM_PMU
90 bool "Andes custom PMU support"
91 depends on ARCH_RENESAS && RISCV_ALTERNATIVE && RISCV_PMU_SBI
94 The Andes cores implement the PMU overflow extension very
95 similar to the standard Sscofpmf and Smcntrpmf extension.
97 This will patch the overflow and pending CSRs and handle the
98 non-standard behaviour via the regular SBI PMU driver and
101 If you don't know what to do here, say "Y".
104 depends on ARM_PMU && ACPI
107 config ARM_SMMU_V3_PMU
108 tristate "ARM SMMUv3 Performance Monitors Extension"
109 depends on ARM64 || (COMPILE_TEST && 64BIT)
110 depends on GENERIC_MSI_IRQ
112 Provides support for the ARM SMMUv3 Performance Monitor Counter
113 Groups (PMCG), which provide monitoring of transactions passing
114 through the SMMU and allow the resulting information to be filtered
115 based on the Stream ID of the corresponding master.
118 depends on HW_PERF_EVENTS && ((ARM && CPU_V7) || ARM64)
119 bool "ARM PMUv3 support" if !ARM64
122 Say y if you want to use the ARM performance monitor unit (PMU)
123 version 3. The PMUv3 is the CPU performance monitors on ARMv8
124 (aarch32 and aarch64) systems that implement the PMUv3
128 tristate "ARM DynamIQ Shared Unit (DSU) PMU"
131 Provides support for performance monitor unit in ARM DynamIQ Shared
132 Unit (DSU). The DSU integrates one or more cores with an L3 memory
133 system, control logic. The PMU allows counting various events related
136 config FSL_IMX8_DDR_PMU
137 tristate "Freescale i.MX8 DDR perf monitor"
138 depends on ARCH_MXC || COMPILE_TEST
140 Provides support for the DDR performance monitor in i.MX8, which
141 can give information about memory throughput and other related
144 config FSL_IMX9_DDR_PMU
145 tristate "Freescale i.MX9 DDR perf monitor"
148 Provides support for the DDR performance monitor in i.MX9, which
149 can give information about memory throughput and other related
153 bool "Qualcomm Technologies L2-cache PMU"
154 depends on ARCH_QCOM && ARM64 && ACPI
155 select QCOM_KRYO_L2_ACCESSORS
157 Provides support for the L2 cache performance monitor unit (PMU)
158 in Qualcomm Technologies processors.
159 Adds the L2 cache PMU into the perf events subsystem for
160 monitoring L2 cache events.
163 bool "Qualcomm Technologies L3-cache PMU"
164 depends on ARCH_QCOM && ARM64 && ACPI
165 select QCOM_IRQ_COMBINER
167 Provides support for the L3 cache performance monitor unit (PMU)
168 in Qualcomm Technologies processors.
169 Adds the L3 cache PMU into the perf events subsystem for
170 monitoring L3 cache events.
173 tristate "Cavium ThunderX2 SoC PMU UNCORE"
174 depends on ARCH_THUNDER2 || COMPILE_TEST
175 depends on NUMA && ACPI
178 Provides support for ThunderX2 UNCORE events.
179 The SoC has PMU support in its L3 cache controller (L3C) and
180 in the DDR4 Memory Controller (DMC).
183 depends on ARCH_XGENE || (COMPILE_TEST && 64BIT)
184 bool "APM X-Gene SoC PMU"
187 Say y if you want to use APM X-Gene SoC performance monitors.
190 tristate "Enable support for the ARMv8.2 Statistical Profiling Extension"
193 Enable perf support for the ARMv8.2 Statistical Profiling
194 Extension, which provides periodic sampling of operations in
195 the CPU pipeline and reports this via the perf AUX interface.
197 config ARM_DMC620_PMU
198 tristate "Enable PMU support for the ARM DMC-620 memory controller"
199 depends on (ARM64 && ACPI) || COMPILE_TEST
201 Support for PMU events monitoring on the ARM DMC-620 memory
204 config MARVELL_CN10K_TAD_PMU
205 tristate "Marvell CN10K LLC-TAD PMU"
206 depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT)
208 Provides support for Last-Level cache Tag-and-data Units (LLC-TAD)
209 performance monitors on CN10K family silicons.
211 config APPLE_M1_CPU_PMU
212 bool "Apple M1 CPU PMU support"
213 depends on ARM_PMU && ARCH_APPLE
215 Provides support for the non-architectural CPU PMUs present on
216 the Apple M1 SoCs and derivatives.
218 config ALIBABA_UNCORE_DRW_PMU
219 tristate "Alibaba T-Head Yitian 710 DDR Sub-system Driveway PMU driver"
220 depends on (ARM64 && ACPI) || COMPILE_TEST
222 Support for Driveway PMU events monitoring on Yitian 710 DDR
225 source "drivers/perf/hisilicon/Kconfig"
227 config MARVELL_CN10K_DDR_PMU
228 tristate "Enable MARVELL CN10K DRAM Subsystem(DSS) PMU Support"
229 depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT)
231 Enable perf support for Marvell DDR Performance monitoring
232 event on CN10K platform.
235 tristate "Synopsys DesignWare PCIe PMU"
238 Enable perf support for Synopsys DesignWare PCIe PMU Performance
239 monitoring event on platform including the Alibaba Yitian 710.
241 source "drivers/perf/arm_cspmu/Kconfig"
243 source "drivers/perf/amlogic/Kconfig"
246 tristate "CXL Performance Monitoring Unit"
249 Support performance monitoring as defined in CXL rev 3.0
250 section 13.2: Performance Monitoring. CXL components may have
251 one or more CXL Performance Monitoring Units (CPMUs).
253 Say 'y/m' to enable a driver that will attach to performance
254 monitoring units and provide standard perf based interfaces.