2 # Performance Monitor Drivers
5 menu "Performance monitor support"
9 tristate "ARM CCI PMU driver"
10 depends on (ARM && CPU_V7) || ARM64
13 Support for PMU events monitoring on the ARM CCI (Cache Coherent
14 Interconnect) family of products.
16 If compiled as a module, it will be called arm-cci.
19 bool "support CCI-400"
21 depends on ARM_CCI_PMU
22 select ARM_CCI400_COMMON
24 CCI-400 provides 4 independent event counters counting events related
25 to the connected slave/master interfaces, plus a cycle counter.
28 bool "support CCI-500/CCI-550"
30 depends on ARM_CCI_PMU
32 CCI-500/CCI-550 both provide 8 independent event counters, which can
33 count events pertaining to the slave/master interfaces as well as the
34 internal events to the CCI.
37 tristate "ARM CCN driver support"
38 depends on ARM || ARM64
40 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
44 depends on ARM || ARM64
45 bool "ARM PMU framework"
48 Say y if you want to use CPU performance monitors on ARM-based
52 depends on ARM_PMU && ACPI
55 config ARM_SMMU_V3_PMU
56 tristate "ARM SMMUv3 Performance Monitors Extension"
57 depends on ARM64 && ACPI && ARM_SMMU_V3
59 Provides support for the ARM SMMUv3 Performance Monitor Counter
60 Groups (PMCG), which provide monitoring of transactions passing
61 through the SMMU and allow the resulting information to be filtered
62 based on the Stream ID of the corresponding master.
65 tristate "ARM DynamIQ Shared Unit (DSU) PMU"
68 Provides support for performance monitor unit in ARM DynamIQ Shared
69 Unit (DSU). The DSU integrates one or more cores with an L3 memory
70 system, control logic. The PMU allows counting various events related
74 bool "HiSilicon SoC PMU"
75 depends on ARM64 && ACPI
77 Support for HiSilicon SoC uncore performance monitoring
78 unit (PMU), such as: L3C, HHA and DDRC.
81 bool "Qualcomm Technologies L2-cache PMU"
82 depends on ARCH_QCOM && ARM64 && ACPI
84 Provides support for the L2 cache performance monitor unit (PMU)
85 in Qualcomm Technologies processors.
86 Adds the L2 cache PMU into the perf events subsystem for
87 monitoring L2 cache events.
90 bool "Qualcomm Technologies L3-cache PMU"
91 depends on ARCH_QCOM && ARM64 && ACPI
92 select QCOM_IRQ_COMBINER
94 Provides support for the L3 cache performance monitor unit (PMU)
95 in Qualcomm Technologies processors.
96 Adds the L3 cache PMU into the perf events subsystem for
97 monitoring L3 cache events.
100 tristate "Cavium ThunderX2 SoC PMU UNCORE"
101 depends on ARCH_THUNDER2 && ARM64 && ACPI && NUMA
104 Provides support for ThunderX2 UNCORE events.
105 The SoC has PMU support in its L3 cache controller (L3C) and
106 in the DDR4 Memory Controller (DMC).
109 depends on ARCH_XGENE
110 bool "APM X-Gene SoC PMU"
113 Say y if you want to use APM X-Gene SoC performance monitors.
116 tristate "Enable support for the ARMv8.2 Statistical Profiling Extension"
119 Enable perf support for the ARMv8.2 Statistical Profiling
120 Extension, which provides periodic sampling of operations in
121 the CPU pipeline and reports this via the perf AUX interface.