1 # SPDX-License-Identifier: GPL-2.0-only
3 # Performance Monitor Drivers
6 menu "Performance monitor support"
10 tristate "ARM CCI PMU driver"
11 depends on (ARM && CPU_V7) || ARM64
14 Support for PMU events monitoring on the ARM CCI (Cache Coherent
15 Interconnect) family of products.
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
22 depends on ARM_CCI_PMU
23 select ARM_CCI400_COMMON
25 CCI-400 provides 4 independent event counters counting events related
26 to the connected slave/master interfaces, plus a cycle counter.
29 bool "support CCI-500/CCI-550"
31 depends on ARM_CCI_PMU
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
34 count events pertaining to the slave/master interfaces as well as the
35 internal events to the CCI.
38 tristate "ARM CCN driver support"
39 depends on ARM || ARM64 || COMPILE_TEST
41 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
45 tristate "Arm CMN-600 PMU support"
46 depends on ARM64 || COMPILE_TEST
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
52 depends on ARM || ARM64
53 bool "ARM PMU framework"
56 Say y if you want to use CPU performance monitors on ARM-based
61 bool "RISC-V PMU framework"
64 Say y if you want to use CPU performance monitors on RISCV-based
65 systems. This provides the core PMU framework that abstracts common
66 PMU functionalities in a core library so that different PMU drivers
69 config RISCV_PMU_LEGACY
71 bool "RISC-V legacy PMU implementation"
74 Say y if you want to use the legacy CPU performance monitor
75 implementation on RISC-V based systems. This only allows counting
76 of cycle/instruction counter and doesn't support counter overflow,
77 or programmable counters. It will be removed in future.
80 depends on RISCV_PMU && RISCV_SBI
81 bool "RISC-V PMU based on SBI PMU extension"
84 Say y if you want to use the CPU performance monitor
85 using SBI PMU extension on RISC-V based systems. This option provides
86 full perf feature support i.e. counter overflow, privilege mode
87 filtering, counter configuration.
89 config STARFIVE_STARLINK_PMU
90 depends on ARCH_STARFIVE || COMPILE_TEST
92 bool "StarFive StarLink PMU"
94 Provide support for StarLink Performance Monitor Unit.
95 StarLink Performance Monitor Unit integrates one or more cores with
96 an L3 memory system. The L3 cache events are added into perf event
97 subsystem, allowing monitoring of various L3 cache perf events.
99 config ANDES_CUSTOM_PMU
100 bool "Andes custom PMU support"
101 depends on ARCH_RENESAS && RISCV_ALTERNATIVE && RISCV_PMU_SBI
104 The Andes cores implement the PMU overflow extension very
105 similar to the standard Sscofpmf and Smcntrpmf extension.
107 This will patch the overflow and pending CSRs and handle the
108 non-standard behaviour via the regular SBI PMU driver and
111 If you don't know what to do here, say "Y".
114 depends on ARM_PMU && ACPI
117 config ARM_SMMU_V3_PMU
118 tristate "ARM SMMUv3 Performance Monitors Extension"
119 depends on ARM64 || (COMPILE_TEST && 64BIT)
120 depends on GENERIC_MSI_IRQ
122 Provides support for the ARM SMMUv3 Performance Monitor Counter
123 Groups (PMCG), which provide monitoring of transactions passing
124 through the SMMU and allow the resulting information to be filtered
125 based on the Stream ID of the corresponding master.
128 depends on HW_PERF_EVENTS && ((ARM && CPU_V7) || ARM64)
129 bool "ARM PMUv3 support" if !ARM64
132 Say y if you want to use the ARM performance monitor unit (PMU)
133 version 3. The PMUv3 is the CPU performance monitors on ARMv8
134 (aarch32 and aarch64) systems that implement the PMUv3
138 tristate "ARM DynamIQ Shared Unit (DSU) PMU"
141 Provides support for performance monitor unit in ARM DynamIQ Shared
142 Unit (DSU). The DSU integrates one or more cores with an L3 memory
143 system, control logic. The PMU allows counting various events related
146 config FSL_IMX8_DDR_PMU
147 tristate "Freescale i.MX8 DDR perf monitor"
148 depends on ARCH_MXC || COMPILE_TEST
150 Provides support for the DDR performance monitor in i.MX8, which
151 can give information about memory throughput and other related
154 config FSL_IMX9_DDR_PMU
155 tristate "Freescale i.MX9 DDR perf monitor"
158 Provides support for the DDR performance monitor in i.MX9, which
159 can give information about memory throughput and other related
163 bool "Qualcomm Technologies L2-cache PMU"
164 depends on ARCH_QCOM && ARM64 && ACPI
165 select QCOM_KRYO_L2_ACCESSORS
167 Provides support for the L2 cache performance monitor unit (PMU)
168 in Qualcomm Technologies processors.
169 Adds the L2 cache PMU into the perf events subsystem for
170 monitoring L2 cache events.
173 bool "Qualcomm Technologies L3-cache PMU"
174 depends on ARCH_QCOM && ARM64 && ACPI
175 select QCOM_IRQ_COMBINER
177 Provides support for the L3 cache performance monitor unit (PMU)
178 in Qualcomm Technologies processors.
179 Adds the L3 cache PMU into the perf events subsystem for
180 monitoring L3 cache events.
183 tristate "Cavium ThunderX2 SoC PMU UNCORE"
184 depends on ARCH_THUNDER2 || COMPILE_TEST
185 depends on NUMA && ACPI
188 Provides support for ThunderX2 UNCORE events.
189 The SoC has PMU support in its L3 cache controller (L3C) and
190 in the DDR4 Memory Controller (DMC).
193 depends on ARCH_XGENE || (COMPILE_TEST && 64BIT)
194 bool "APM X-Gene SoC PMU"
197 Say y if you want to use APM X-Gene SoC performance monitors.
200 tristate "Enable support for the ARMv8.2 Statistical Profiling Extension"
203 Enable perf support for the ARMv8.2 Statistical Profiling
204 Extension, which provides periodic sampling of operations in
205 the CPU pipeline and reports this via the perf AUX interface.
207 config ARM_DMC620_PMU
208 tristate "Enable PMU support for the ARM DMC-620 memory controller"
209 depends on (ARM64 && ACPI) || COMPILE_TEST
211 Support for PMU events monitoring on the ARM DMC-620 memory
214 config MARVELL_CN10K_TAD_PMU
215 tristate "Marvell CN10K LLC-TAD PMU"
216 depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT)
218 Provides support for Last-Level cache Tag-and-data Units (LLC-TAD)
219 performance monitors on CN10K family silicons.
221 config APPLE_M1_CPU_PMU
222 bool "Apple M1 CPU PMU support"
223 depends on ARM_PMU && ARCH_APPLE
225 Provides support for the non-architectural CPU PMUs present on
226 the Apple M1 SoCs and derivatives.
228 config ALIBABA_UNCORE_DRW_PMU
229 tristate "Alibaba T-Head Yitian 710 DDR Sub-system Driveway PMU driver"
230 depends on (ARM64 && ACPI) || COMPILE_TEST
232 Support for Driveway PMU events monitoring on Yitian 710 DDR
235 source "drivers/perf/hisilicon/Kconfig"
237 config MARVELL_CN10K_DDR_PMU
238 tristate "Enable MARVELL CN10K DRAM Subsystem(DSS) PMU Support"
239 depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT)
241 Enable perf support for Marvell DDR Performance monitoring
242 event on CN10K platform.
245 tristate "Synopsys DesignWare PCIe PMU"
248 Enable perf support for Synopsys DesignWare PCIe PMU Performance
249 monitoring event on platform including the Alibaba Yitian 710.
251 source "drivers/perf/arm_cspmu/Kconfig"
253 source "drivers/perf/amlogic/Kconfig"
256 tristate "CXL Performance Monitoring Unit"
259 Support performance monitoring as defined in CXL rev 3.0
260 section 13.2: Performance Monitoring. CXL components may have
261 one or more CXL Performance Monitoring Units (CPMUs).
263 Say 'y/m' to enable a driver that will attach to performance
264 monitoring units and provide standard perf based interfaces.