2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/of_device.h>
10 #include <linux/of_pci.h>
11 #include <linux/pci_hotplug.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/cpumask.h>
15 #include <linux/pci-aspm.h>
16 #include <linux/aer.h>
17 #include <linux/acpi.h>
20 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
21 #define CARDBUS_RESERVE_BUSNR 3
23 static struct resource busn_resource = {
27 .flags = IORESOURCE_BUS,
30 /* Ugh. Need to stop exporting this to modules. */
31 LIST_HEAD(pci_root_buses);
32 EXPORT_SYMBOL(pci_root_buses);
34 static LIST_HEAD(pci_domain_busn_res_list);
36 struct pci_domain_busn_res {
37 struct list_head list;
42 static struct resource *get_pci_domain_busn_res(int domain_nr)
44 struct pci_domain_busn_res *r;
46 list_for_each_entry(r, &pci_domain_busn_res_list, list)
47 if (r->domain_nr == domain_nr)
50 r = kzalloc(sizeof(*r), GFP_KERNEL);
54 r->domain_nr = domain_nr;
57 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
59 list_add_tail(&r->list, &pci_domain_busn_res_list);
64 static int find_anything(struct device *dev, void *data)
70 * Some device drivers need know if pci is initiated.
71 * Basically, we think pci is not initiated when there
72 * is no device to be found on the pci_bus_type.
74 int no_pci_devices(void)
79 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
80 no_devices = (dev == NULL);
84 EXPORT_SYMBOL(no_pci_devices);
89 static void release_pcibus_dev(struct device *dev)
91 struct pci_bus *pci_bus = to_pci_bus(dev);
93 put_device(pci_bus->bridge);
94 pci_bus_remove_resources(pci_bus);
95 pci_release_bus_of_node(pci_bus);
99 static struct class pcibus_class = {
101 .dev_release = &release_pcibus_dev,
102 .dev_groups = pcibus_groups,
105 static int __init pcibus_class_init(void)
107 return class_register(&pcibus_class);
109 postcore_initcall(pcibus_class_init);
111 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
113 u64 size = mask & maxbase; /* Find the significant bits */
117 /* Get the lowest of them to find the decode size, and
118 from that the extent. */
119 size = (size & ~(size-1)) - 1;
121 /* base == maxbase can be valid only if the BAR has
122 already been programmed with all 1s. */
123 if (base == maxbase && ((base | size) & mask) != mask)
129 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
134 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
135 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
136 flags |= IORESOURCE_IO;
140 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
141 flags |= IORESOURCE_MEM;
142 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
143 flags |= IORESOURCE_PREFETCH;
145 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
147 case PCI_BASE_ADDRESS_MEM_TYPE_32:
149 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
150 /* 1M mem BAR treated as 32-bit BAR */
152 case PCI_BASE_ADDRESS_MEM_TYPE_64:
153 flags |= IORESOURCE_MEM_64;
156 /* mem unknown type treated as 32-bit BAR */
162 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
165 * pci_read_base - read a PCI BAR
166 * @dev: the PCI device
167 * @type: type of the BAR
168 * @res: resource buffer to be filled in
169 * @pos: BAR position in the config space
171 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
173 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
174 struct resource *res, unsigned int pos)
177 u64 l64, sz64, mask64;
179 struct pci_bus_region region, inverted_region;
181 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
183 /* No printks while decoding is disabled! */
184 if (!dev->mmio_always_on) {
185 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
186 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
187 pci_write_config_word(dev, PCI_COMMAND,
188 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
192 res->name = pci_name(dev);
194 pci_read_config_dword(dev, pos, &l);
195 pci_write_config_dword(dev, pos, l | mask);
196 pci_read_config_dword(dev, pos, &sz);
197 pci_write_config_dword(dev, pos, l);
200 * All bits set in sz means the device isn't working properly.
201 * If the BAR isn't implemented, all bits must be 0. If it's a
202 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
205 if (sz == 0xffffffff)
209 * I don't know how l can have all bits set. Copied from old code.
210 * Maybe it fixes a bug on some ancient platform.
215 if (type == pci_bar_unknown) {
216 res->flags = decode_bar(dev, l);
217 res->flags |= IORESOURCE_SIZEALIGN;
218 if (res->flags & IORESOURCE_IO) {
219 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
220 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
221 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
223 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
224 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
225 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
228 res->flags |= (l & IORESOURCE_ROM_ENABLE);
229 l64 = l & PCI_ROM_ADDRESS_MASK;
230 sz64 = sz & PCI_ROM_ADDRESS_MASK;
231 mask64 = (u32)PCI_ROM_ADDRESS_MASK;
234 if (res->flags & IORESOURCE_MEM_64) {
235 pci_read_config_dword(dev, pos + 4, &l);
236 pci_write_config_dword(dev, pos + 4, ~0);
237 pci_read_config_dword(dev, pos + 4, &sz);
238 pci_write_config_dword(dev, pos + 4, l);
240 l64 |= ((u64)l << 32);
241 sz64 |= ((u64)sz << 32);
242 mask64 |= ((u64)~0 << 32);
245 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
246 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
251 sz64 = pci_size(l64, sz64, mask64);
253 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
258 if (res->flags & IORESOURCE_MEM_64) {
259 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
260 && sz64 > 0x100000000ULL) {
261 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
264 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
265 pos, (unsigned long long)sz64);
269 if ((sizeof(pci_bus_addr_t) < 8) && l) {
270 /* Above 32-bit boundary; try to reallocate */
271 res->flags |= IORESOURCE_UNSET;
274 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
275 pos, (unsigned long long)l64);
281 region.end = l64 + sz64;
283 pcibios_bus_to_resource(dev->bus, res, ®ion);
284 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
287 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
288 * the corresponding resource address (the physical address used by
289 * the CPU. Converting that resource address back to a bus address
290 * should yield the original BAR value:
292 * resource_to_bus(bus_to_resource(A)) == A
294 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
295 * be claimed by the device.
297 if (inverted_region.start != region.start) {
298 res->flags |= IORESOURCE_UNSET;
300 res->end = region.end - region.start;
301 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
302 pos, (unsigned long long)region.start);
312 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
314 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
317 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
319 unsigned int pos, reg;
321 for (pos = 0; pos < howmany; pos++) {
322 struct resource *res = &dev->resource[pos];
323 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
324 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
328 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
329 dev->rom_base_reg = rom;
330 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
331 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
332 __pci_read_base(dev, pci_bar_mem32, res, rom);
336 static void pci_read_bridge_io(struct pci_bus *child)
338 struct pci_dev *dev = child->self;
339 u8 io_base_lo, io_limit_lo;
340 unsigned long io_mask, io_granularity, base, limit;
341 struct pci_bus_region region;
342 struct resource *res;
344 io_mask = PCI_IO_RANGE_MASK;
345 io_granularity = 0x1000;
346 if (dev->io_window_1k) {
347 /* Support 1K I/O space granularity */
348 io_mask = PCI_IO_1K_RANGE_MASK;
349 io_granularity = 0x400;
352 res = child->resource[0];
353 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
354 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
355 base = (io_base_lo & io_mask) << 8;
356 limit = (io_limit_lo & io_mask) << 8;
358 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
359 u16 io_base_hi, io_limit_hi;
361 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
362 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
363 base |= ((unsigned long) io_base_hi << 16);
364 limit |= ((unsigned long) io_limit_hi << 16);
368 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
370 region.end = limit + io_granularity - 1;
371 pcibios_bus_to_resource(dev->bus, res, ®ion);
372 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
376 static void pci_read_bridge_mmio(struct pci_bus *child)
378 struct pci_dev *dev = child->self;
379 u16 mem_base_lo, mem_limit_lo;
380 unsigned long base, limit;
381 struct pci_bus_region region;
382 struct resource *res;
384 res = child->resource[1];
385 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
386 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
387 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
388 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
390 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
392 region.end = limit + 0xfffff;
393 pcibios_bus_to_resource(dev->bus, res, ®ion);
394 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
398 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
400 struct pci_dev *dev = child->self;
401 u16 mem_base_lo, mem_limit_lo;
403 pci_bus_addr_t base, limit;
404 struct pci_bus_region region;
405 struct resource *res;
407 res = child->resource[2];
408 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
409 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
410 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
411 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
413 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
414 u32 mem_base_hi, mem_limit_hi;
416 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
417 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
420 * Some bridges set the base > limit by default, and some
421 * (broken) BIOSes do not initialize them. If we find
422 * this, just assume they are not being used.
424 if (mem_base_hi <= mem_limit_hi) {
425 base64 |= (u64) mem_base_hi << 32;
426 limit64 |= (u64) mem_limit_hi << 32;
430 base = (pci_bus_addr_t) base64;
431 limit = (pci_bus_addr_t) limit64;
433 if (base != base64) {
434 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
435 (unsigned long long) base64);
440 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
441 IORESOURCE_MEM | IORESOURCE_PREFETCH;
442 if (res->flags & PCI_PREF_RANGE_TYPE_64)
443 res->flags |= IORESOURCE_MEM_64;
445 region.end = limit + 0xfffff;
446 pcibios_bus_to_resource(dev->bus, res, ®ion);
447 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
451 void pci_read_bridge_bases(struct pci_bus *child)
453 struct pci_dev *dev = child->self;
454 struct resource *res;
457 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
460 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
462 dev->transparent ? " (subtractive decode)" : "");
464 pci_bus_remove_resources(child);
465 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
466 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
468 pci_read_bridge_io(child);
469 pci_read_bridge_mmio(child);
470 pci_read_bridge_mmio_pref(child);
472 if (dev->transparent) {
473 pci_bus_for_each_resource(child->parent, res, i) {
474 if (res && res->flags) {
475 pci_bus_add_resource(child, res,
476 PCI_SUBTRACTIVE_DECODE);
477 dev_printk(KERN_DEBUG, &dev->dev,
478 " bridge window %pR (subtractive decode)\n",
485 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
489 b = kzalloc(sizeof(*b), GFP_KERNEL);
493 INIT_LIST_HEAD(&b->node);
494 INIT_LIST_HEAD(&b->children);
495 INIT_LIST_HEAD(&b->devices);
496 INIT_LIST_HEAD(&b->slots);
497 INIT_LIST_HEAD(&b->resources);
498 b->max_bus_speed = PCI_SPEED_UNKNOWN;
499 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
500 #ifdef CONFIG_PCI_DOMAINS_GENERIC
502 b->domain_nr = parent->domain_nr;
507 static void pci_release_host_bridge_dev(struct device *dev)
509 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
511 if (bridge->release_fn)
512 bridge->release_fn(bridge);
514 pci_free_resource_list(&bridge->windows);
519 static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
521 struct pci_host_bridge *bridge;
523 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
527 INIT_LIST_HEAD(&bridge->windows);
532 static const unsigned char pcix_bus_speed[] = {
533 PCI_SPEED_UNKNOWN, /* 0 */
534 PCI_SPEED_66MHz_PCIX, /* 1 */
535 PCI_SPEED_100MHz_PCIX, /* 2 */
536 PCI_SPEED_133MHz_PCIX, /* 3 */
537 PCI_SPEED_UNKNOWN, /* 4 */
538 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
539 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
540 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
541 PCI_SPEED_UNKNOWN, /* 8 */
542 PCI_SPEED_66MHz_PCIX_266, /* 9 */
543 PCI_SPEED_100MHz_PCIX_266, /* A */
544 PCI_SPEED_133MHz_PCIX_266, /* B */
545 PCI_SPEED_UNKNOWN, /* C */
546 PCI_SPEED_66MHz_PCIX_533, /* D */
547 PCI_SPEED_100MHz_PCIX_533, /* E */
548 PCI_SPEED_133MHz_PCIX_533 /* F */
551 const unsigned char pcie_link_speed[] = {
552 PCI_SPEED_UNKNOWN, /* 0 */
553 PCIE_SPEED_2_5GT, /* 1 */
554 PCIE_SPEED_5_0GT, /* 2 */
555 PCIE_SPEED_8_0GT, /* 3 */
556 PCI_SPEED_UNKNOWN, /* 4 */
557 PCI_SPEED_UNKNOWN, /* 5 */
558 PCI_SPEED_UNKNOWN, /* 6 */
559 PCI_SPEED_UNKNOWN, /* 7 */
560 PCI_SPEED_UNKNOWN, /* 8 */
561 PCI_SPEED_UNKNOWN, /* 9 */
562 PCI_SPEED_UNKNOWN, /* A */
563 PCI_SPEED_UNKNOWN, /* B */
564 PCI_SPEED_UNKNOWN, /* C */
565 PCI_SPEED_UNKNOWN, /* D */
566 PCI_SPEED_UNKNOWN, /* E */
567 PCI_SPEED_UNKNOWN /* F */
570 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
572 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
574 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
576 static unsigned char agp_speeds[] = {
584 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
590 else if (agpstat & 2)
592 else if (agpstat & 1)
604 return agp_speeds[index];
607 static void pci_set_bus_speed(struct pci_bus *bus)
609 struct pci_dev *bridge = bus->self;
612 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
614 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
618 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
619 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
621 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
622 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
625 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
628 enum pci_bus_speed max;
630 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
633 if (status & PCI_X_SSTATUS_533MHZ) {
634 max = PCI_SPEED_133MHz_PCIX_533;
635 } else if (status & PCI_X_SSTATUS_266MHZ) {
636 max = PCI_SPEED_133MHz_PCIX_266;
637 } else if (status & PCI_X_SSTATUS_133MHZ) {
638 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
639 max = PCI_SPEED_133MHz_PCIX_ECC;
641 max = PCI_SPEED_133MHz_PCIX;
643 max = PCI_SPEED_66MHz_PCIX;
646 bus->max_bus_speed = max;
647 bus->cur_bus_speed = pcix_bus_speed[
648 (status & PCI_X_SSTATUS_FREQ) >> 6];
653 if (pci_is_pcie(bridge)) {
657 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
658 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
660 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
661 pcie_update_link_speed(bus, linksta);
665 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
667 struct irq_domain *d;
670 * Any firmware interface that can resolve the msi_domain
671 * should be called from here.
673 d = pci_host_bridge_of_msi_domain(bus);
675 d = pci_host_bridge_acpi_msi_domain(bus);
680 static void pci_set_bus_msi_domain(struct pci_bus *bus)
682 struct irq_domain *d;
686 * The bus can be a root bus, a subordinate bus, or a virtual bus
687 * created by an SR-IOV device. Walk up to the first bridge device
688 * found or derive the domain from the host bridge.
690 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
692 d = dev_get_msi_domain(&b->self->dev);
696 d = pci_host_bridge_msi_domain(b);
698 dev_set_msi_domain(&bus->dev, d);
701 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
702 struct pci_dev *bridge, int busnr)
704 struct pci_bus *child;
709 * Allocate a new bus, and inherit stuff from the parent..
711 child = pci_alloc_bus(parent);
715 child->parent = parent;
716 child->ops = parent->ops;
717 child->msi = parent->msi;
718 child->sysdata = parent->sysdata;
719 child->bus_flags = parent->bus_flags;
721 /* initialize some portions of the bus device, but don't register it
722 * now as the parent is not properly set up yet.
724 child->dev.class = &pcibus_class;
725 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
728 * Set up the primary, secondary and subordinate
731 child->number = child->busn_res.start = busnr;
732 child->primary = parent->busn_res.start;
733 child->busn_res.end = 0xff;
736 child->dev.parent = parent->bridge;
740 child->self = bridge;
741 child->bridge = get_device(&bridge->dev);
742 child->dev.parent = child->bridge;
743 pci_set_bus_of_node(child);
744 pci_set_bus_speed(child);
746 /* Set up default resource pointers and names.. */
747 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
748 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
749 child->resource[i]->name = child->name;
751 bridge->subordinate = child;
754 pci_set_bus_msi_domain(child);
755 ret = device_register(&child->dev);
758 pcibios_add_bus(child);
760 if (child->ops->add_bus) {
761 ret = child->ops->add_bus(child);
762 if (WARN_ON(ret < 0))
763 dev_err(&child->dev, "failed to add bus: %d\n", ret);
766 /* Create legacy_io and legacy_mem files for this bus */
767 pci_create_legacy_files(child);
772 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
775 struct pci_bus *child;
777 child = pci_alloc_child_bus(parent, dev, busnr);
779 down_write(&pci_bus_sem);
780 list_add_tail(&child->node, &parent->children);
781 up_write(&pci_bus_sem);
785 EXPORT_SYMBOL(pci_add_new_bus);
787 static void pci_enable_crs(struct pci_dev *pdev)
791 /* Enable CRS Software Visibility if supported */
792 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
793 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
794 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
795 PCI_EXP_RTCTL_CRSSVE);
799 * If it's a bridge, configure it and scan the bus behind it.
800 * For CardBus bridges, we don't scan behind as the devices will
801 * be handled by the bridge driver itself.
803 * We need to process bridges in two passes -- first we scan those
804 * already configured by the BIOS and after we are done with all of
805 * them, we proceed to assigning numbers to the remaining buses in
806 * order to avoid overlaps between old and new bus numbers.
808 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
810 struct pci_bus *child;
811 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
814 u8 primary, secondary, subordinate;
817 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
818 primary = buses & 0xFF;
819 secondary = (buses >> 8) & 0xFF;
820 subordinate = (buses >> 16) & 0xFF;
822 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
823 secondary, subordinate, pass);
825 if (!primary && (primary != bus->number) && secondary && subordinate) {
826 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
827 primary = bus->number;
830 /* Check if setup is sensible at all */
832 (primary != bus->number || secondary <= bus->number ||
833 secondary > subordinate)) {
834 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
835 secondary, subordinate);
839 /* Disable MasterAbortMode during probing to avoid reporting
840 of bus errors (in some architectures) */
841 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
842 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
843 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
847 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
848 !is_cardbus && !broken) {
851 * Bus already configured by firmware, process it in the first
852 * pass and just note the configuration.
858 * The bus might already exist for two reasons: Either we are
859 * rescanning the bus or the bus is reachable through more than
860 * one bridge. The second case can happen with the i450NX
863 child = pci_find_bus(pci_domain_nr(bus), secondary);
865 child = pci_add_new_bus(bus, dev, secondary);
868 child->primary = primary;
869 pci_bus_insert_busn_res(child, secondary, subordinate);
870 child->bridge_ctl = bctl;
873 cmax = pci_scan_child_bus(child);
874 if (cmax > subordinate)
875 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
877 /* subordinate should equal child->busn_res.end */
878 if (subordinate > max)
882 * We need to assign a number to this bus which we always
883 * do in the second pass.
886 if (pcibios_assign_all_busses() || broken || is_cardbus)
887 /* Temporarily disable forwarding of the
888 configuration cycles on all bridges in
889 this bus segment to avoid possible
890 conflicts in the second pass between two
891 bridges programmed with overlapping
893 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
899 pci_write_config_word(dev, PCI_STATUS, 0xffff);
901 /* Prevent assigning a bus number that already exists.
902 * This can happen when a bridge is hot-plugged, so in
903 * this case we only re-scan this bus. */
904 child = pci_find_bus(pci_domain_nr(bus), max+1);
906 child = pci_add_new_bus(bus, dev, max+1);
909 pci_bus_insert_busn_res(child, max+1, 0xff);
912 buses = (buses & 0xff000000)
913 | ((unsigned int)(child->primary) << 0)
914 | ((unsigned int)(child->busn_res.start) << 8)
915 | ((unsigned int)(child->busn_res.end) << 16);
918 * yenta.c forces a secondary latency timer of 176.
919 * Copy that behaviour here.
922 buses &= ~0xff000000;
923 buses |= CARDBUS_LATENCY_TIMER << 24;
927 * We need to blast all three values with a single write.
929 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
932 child->bridge_ctl = bctl;
933 max = pci_scan_child_bus(child);
936 * For CardBus bridges, we leave 4 bus numbers
937 * as cards with a PCI-to-PCI bridge can be
940 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
941 struct pci_bus *parent = bus;
942 if (pci_find_bus(pci_domain_nr(bus),
945 while (parent->parent) {
946 if ((!pcibios_assign_all_busses()) &&
947 (parent->busn_res.end > max) &&
948 (parent->busn_res.end <= max+i)) {
951 parent = parent->parent;
955 * Often, there are two cardbus bridges
956 * -- try to leave one valid bus number
966 * Set the subordinate bus number to its real value.
968 pci_bus_update_busn_res_end(child, max);
969 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
973 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
974 pci_domain_nr(bus), child->number);
976 /* Has only triggered on CardBus, fixup is in yenta_socket */
977 while (bus->parent) {
978 if ((child->busn_res.end > bus->busn_res.end) ||
979 (child->number > bus->busn_res.end) ||
980 (child->number < bus->number) ||
981 (child->busn_res.end < bus->number)) {
982 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
984 (bus->number > child->busn_res.end &&
985 bus->busn_res.end < child->number) ?
986 "wholly" : "partially",
987 bus->self->transparent ? " transparent" : "",
995 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
999 EXPORT_SYMBOL(pci_scan_bridge);
1002 * Read interrupt line and base address registers.
1003 * The architecture-dependent code can tweak these, of course.
1005 static void pci_read_irq(struct pci_dev *dev)
1009 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1012 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1016 void set_pcie_port_type(struct pci_dev *pdev)
1021 struct pci_dev *parent;
1023 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1026 pdev->pcie_cap = pos;
1027 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1028 pdev->pcie_flags_reg = reg16;
1029 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
1030 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1033 * A Root Port is always the upstream end of a Link. No PCIe
1034 * component has two Links. Two Links are connected by a Switch
1035 * that has a Port on each Link and internal logic to connect the
1038 type = pci_pcie_type(pdev);
1039 if (type == PCI_EXP_TYPE_ROOT_PORT)
1040 pdev->has_secondary_link = 1;
1041 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1042 type == PCI_EXP_TYPE_DOWNSTREAM) {
1043 parent = pci_upstream_bridge(pdev);
1046 * Usually there's an upstream device (Root Port or Switch
1047 * Downstream Port), but we can't assume one exists.
1049 if (parent && !parent->has_secondary_link)
1050 pdev->has_secondary_link = 1;
1054 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1058 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1059 if (reg32 & PCI_EXP_SLTCAP_HPC)
1060 pdev->is_hotplug_bridge = 1;
1064 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1067 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1068 * when forwarding a type1 configuration request the bridge must check that
1069 * the extended register address field is zero. The bridge is not permitted
1070 * to forward the transactions and must handle it as an Unsupported Request.
1071 * Some bridges do not follow this rule and simply drop the extended register
1072 * bits, resulting in the standard config space being aliased, every 256
1073 * bytes across the entire configuration space. Test for this condition by
1074 * comparing the first dword of each potential alias to the vendor/device ID.
1076 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1077 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1079 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1081 #ifdef CONFIG_PCI_QUIRKS
1085 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1087 for (pos = PCI_CFG_SPACE_SIZE;
1088 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1089 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1101 * pci_cfg_space_size - get the configuration space size of the PCI device.
1104 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1105 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1106 * access it. Maybe we don't have a way to generate extended config space
1107 * accesses, or the device is behind a reverse Express bridge. So we try
1108 * reading the dword at 0x100 which must either be 0 or a valid extended
1109 * capability header.
1111 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1114 int pos = PCI_CFG_SPACE_SIZE;
1116 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1117 return PCI_CFG_SPACE_SIZE;
1118 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1119 return PCI_CFG_SPACE_SIZE;
1121 return PCI_CFG_SPACE_EXP_SIZE;
1124 int pci_cfg_space_size(struct pci_dev *dev)
1130 class = dev->class >> 8;
1131 if (class == PCI_CLASS_BRIDGE_HOST)
1132 return pci_cfg_space_size_ext(dev);
1134 if (pci_is_pcie(dev))
1135 return pci_cfg_space_size_ext(dev);
1137 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1139 return PCI_CFG_SPACE_SIZE;
1141 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1142 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1143 return pci_cfg_space_size_ext(dev);
1145 return PCI_CFG_SPACE_SIZE;
1148 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1150 static void pci_msi_setup_pci_dev(struct pci_dev *dev)
1153 * Disable the MSI hardware to avoid screaming interrupts
1154 * during boot. This is the power on reset default so
1155 * usually this should be a noop.
1157 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1159 pci_msi_set_enable(dev, 0);
1161 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1163 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1167 * pci_setup_device - fill in class and map information of a device
1168 * @dev: the device structure to fill
1170 * Initialize the device structure with information about the device's
1171 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1172 * Called at initialisation of the PCI subsystem and by CardBus services.
1173 * Returns 0 on success and negative if unknown type of device (not normal,
1174 * bridge or CardBus).
1176 int pci_setup_device(struct pci_dev *dev)
1181 struct pci_bus_region region;
1182 struct resource *res;
1184 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1187 dev->sysdata = dev->bus->sysdata;
1188 dev->dev.parent = dev->bus->bridge;
1189 dev->dev.bus = &pci_bus_type;
1190 dev->hdr_type = hdr_type & 0x7f;
1191 dev->multifunction = !!(hdr_type & 0x80);
1192 dev->error_state = pci_channel_io_normal;
1193 set_pcie_port_type(dev);
1195 pci_dev_assign_slot(dev);
1196 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1197 set this higher, assuming the system even supports it. */
1198 dev->dma_mask = 0xffffffff;
1200 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1201 dev->bus->number, PCI_SLOT(dev->devfn),
1202 PCI_FUNC(dev->devfn));
1204 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1205 dev->revision = class & 0xff;
1206 dev->class = class >> 8; /* upper 3 bytes */
1208 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1209 dev->vendor, dev->device, dev->hdr_type, dev->class);
1211 /* need to have dev->class ready */
1212 dev->cfg_size = pci_cfg_space_size(dev);
1214 /* "Unknown power state" */
1215 dev->current_state = PCI_UNKNOWN;
1217 /* Early fixups, before probing the BARs */
1218 pci_fixup_device(pci_fixup_early, dev);
1219 /* device class may be changed after fixup */
1220 class = dev->class >> 8;
1222 switch (dev->hdr_type) { /* header type */
1223 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1224 if (class == PCI_CLASS_BRIDGE_PCI)
1227 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1228 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1229 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1232 * Do the ugly legacy mode stuff here rather than broken chip
1233 * quirk code. Legacy mode ATA controllers have fixed
1234 * addresses. These are not always echoed in BAR0-3, and
1235 * BAR0-3 in a few cases contain junk!
1237 if (class == PCI_CLASS_STORAGE_IDE) {
1239 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1240 if ((progif & 1) == 0) {
1241 region.start = 0x1F0;
1243 res = &dev->resource[0];
1244 res->flags = LEGACY_IO_RESOURCE;
1245 pcibios_bus_to_resource(dev->bus, res, ®ion);
1246 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1248 region.start = 0x3F6;
1250 res = &dev->resource[1];
1251 res->flags = LEGACY_IO_RESOURCE;
1252 pcibios_bus_to_resource(dev->bus, res, ®ion);
1253 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1256 if ((progif & 4) == 0) {
1257 region.start = 0x170;
1259 res = &dev->resource[2];
1260 res->flags = LEGACY_IO_RESOURCE;
1261 pcibios_bus_to_resource(dev->bus, res, ®ion);
1262 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1264 region.start = 0x376;
1266 res = &dev->resource[3];
1267 res->flags = LEGACY_IO_RESOURCE;
1268 pcibios_bus_to_resource(dev->bus, res, ®ion);
1269 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1275 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1276 if (class != PCI_CLASS_BRIDGE_PCI)
1278 /* The PCI-to-PCI bridge spec requires that subtractive
1279 decoding (i.e. transparent) bridge must have programming
1280 interface code of 0x01. */
1282 dev->transparent = ((dev->class & 0xff) == 1);
1283 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1284 set_pcie_hotplug_bridge(dev);
1285 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1287 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1288 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1292 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1293 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1296 pci_read_bases(dev, 1, 0);
1297 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1298 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1301 default: /* unknown header */
1302 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1307 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1308 dev->class, dev->hdr_type);
1309 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1312 /* We found a fine healthy device, go go go... */
1316 static void pci_configure_mps(struct pci_dev *dev)
1318 struct pci_dev *bridge = pci_upstream_bridge(dev);
1321 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1324 mps = pcie_get_mps(dev);
1325 p_mps = pcie_get_mps(bridge);
1330 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1331 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1332 mps, pci_name(bridge), p_mps);
1337 * Fancier MPS configuration is done later by
1338 * pcie_bus_configure_settings()
1340 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1343 rc = pcie_set_mps(dev, p_mps);
1345 dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1350 dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
1351 p_mps, mps, 128 << dev->pcie_mpss);
1354 static struct hpp_type0 pci_default_type0 = {
1356 .cache_line_size = 8,
1357 .latency_timer = 0x40,
1362 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1364 u16 pci_cmd, pci_bctl;
1367 hpp = &pci_default_type0;
1369 if (hpp->revision > 1) {
1371 "PCI settings rev %d not supported; using defaults\n",
1373 hpp = &pci_default_type0;
1376 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1377 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1378 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1379 if (hpp->enable_serr)
1380 pci_cmd |= PCI_COMMAND_SERR;
1381 if (hpp->enable_perr)
1382 pci_cmd |= PCI_COMMAND_PARITY;
1383 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1385 /* Program bridge control value */
1386 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1387 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1388 hpp->latency_timer);
1389 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1390 if (hpp->enable_serr)
1391 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1392 if (hpp->enable_perr)
1393 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1394 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1398 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1401 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1404 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1412 if (hpp->revision > 1) {
1413 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1419 * Don't allow _HPX to change MPS or MRRS settings. We manage
1420 * those to make sure they're consistent with the rest of the
1423 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1424 PCI_EXP_DEVCTL_READRQ;
1425 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1426 PCI_EXP_DEVCTL_READRQ);
1428 /* Initialize Device Control Register */
1429 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1430 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1432 /* Initialize Link Control Register */
1433 if (pcie_cap_has_lnkctl(dev))
1434 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1435 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1437 /* Find Advanced Error Reporting Enhanced Capability */
1438 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1442 /* Initialize Uncorrectable Error Mask Register */
1443 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
1444 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1445 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1447 /* Initialize Uncorrectable Error Severity Register */
1448 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
1449 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1450 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1452 /* Initialize Correctable Error Mask Register */
1453 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
1454 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1455 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1457 /* Initialize Advanced Error Capabilities and Control Register */
1458 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
1459 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1460 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1463 * FIXME: The following two registers are not supported yet.
1465 * o Secondary Uncorrectable Error Severity Register
1466 * o Secondary Uncorrectable Error Mask Register
1470 static void pci_configure_device(struct pci_dev *dev)
1472 struct hotplug_params hpp;
1475 pci_configure_mps(dev);
1477 memset(&hpp, 0, sizeof(hpp));
1478 ret = pci_get_hp_params(dev, &hpp);
1482 program_hpp_type2(dev, hpp.t2);
1483 program_hpp_type1(dev, hpp.t1);
1484 program_hpp_type0(dev, hpp.t0);
1487 static void pci_release_capabilities(struct pci_dev *dev)
1489 pci_vpd_release(dev);
1490 pci_iov_release(dev);
1491 pci_free_cap_save_buffers(dev);
1495 * pci_release_dev - free a pci device structure when all users of it are finished.
1496 * @dev: device that's been disconnected
1498 * Will be called only by the device core when all users of this pci device are
1501 static void pci_release_dev(struct device *dev)
1503 struct pci_dev *pci_dev;
1505 pci_dev = to_pci_dev(dev);
1506 pci_release_capabilities(pci_dev);
1507 pci_release_of_node(pci_dev);
1508 pcibios_release_device(pci_dev);
1509 pci_bus_put(pci_dev->bus);
1510 kfree(pci_dev->driver_override);
1514 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1516 struct pci_dev *dev;
1518 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1522 INIT_LIST_HEAD(&dev->bus_list);
1523 dev->dev.type = &pci_dev_type;
1524 dev->bus = pci_bus_get(bus);
1528 EXPORT_SYMBOL(pci_alloc_dev);
1530 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1535 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1538 /* some broken boards return 0 or ~0 if a slot is empty: */
1539 if (*l == 0xffffffff || *l == 0x00000000 ||
1540 *l == 0x0000ffff || *l == 0xffff0000)
1544 * Configuration Request Retry Status. Some root ports return the
1545 * actual device ID instead of the synthetic ID (0xFFFF) required
1546 * by the PCIe spec. Ignore the device ID and only check for
1549 while ((*l & 0xffff) == 0x0001) {
1555 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1557 /* Card hasn't responded in 60 seconds? Must be stuck. */
1558 if (delay > crs_timeout) {
1559 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1560 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1568 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1571 * Read the config data for a PCI device, sanity-check it
1572 * and fill in the dev structure...
1574 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1576 struct pci_dev *dev;
1579 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1582 dev = pci_alloc_dev(bus);
1587 dev->vendor = l & 0xffff;
1588 dev->device = (l >> 16) & 0xffff;
1590 pci_set_of_node(dev);
1592 if (pci_setup_device(dev)) {
1593 pci_bus_put(dev->bus);
1601 static void pci_init_capabilities(struct pci_dev *dev)
1603 /* Enhanced Allocation */
1606 /* Setup MSI caps & disable MSI/MSI-X interrupts */
1607 pci_msi_setup_pci_dev(dev);
1609 /* Buffers for saving PCIe and PCI-X capabilities */
1610 pci_allocate_cap_save_buffers(dev);
1612 /* Power Management */
1615 /* Vital Product Data */
1618 /* Alternative Routing-ID Forwarding */
1619 pci_configure_ari(dev);
1621 /* Single Root I/O Virtualization */
1624 /* Address Translation Services */
1627 /* Enable ACS P2P upstream forwarding */
1628 pci_enable_acs(dev);
1630 pci_cleanup_aer_error_status_regs(dev);
1634 * This is the equivalent of pci_host_bridge_msi_domain that acts on
1635 * devices. Firmware interfaces that can select the MSI domain on a
1636 * per-device basis should be called from here.
1638 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
1640 struct irq_domain *d;
1643 * If a domain has been set through the pcibios_add_device
1644 * callback, then this is the one (platform code knows best).
1646 d = dev_get_msi_domain(&dev->dev);
1651 * Let's see if we have a firmware interface able to provide
1654 d = pci_msi_get_device_domain(dev);
1661 static void pci_set_msi_domain(struct pci_dev *dev)
1663 struct irq_domain *d;
1666 * If the platform or firmware interfaces cannot supply a
1667 * device-specific MSI domain, then inherit the default domain
1668 * from the host bridge itself.
1670 d = pci_dev_msi_domain(dev);
1672 d = dev_get_msi_domain(&dev->bus->dev);
1674 dev_set_msi_domain(&dev->dev, d);
1678 * pci_dma_configure - Setup DMA configuration
1679 * @dev: ptr to pci_dev struct of the PCI device
1681 * Function to update PCI devices's DMA configuration using the same
1682 * info from the OF node or ACPI node of host bridge's parent (if any).
1684 static void pci_dma_configure(struct pci_dev *dev)
1686 struct device *bridge = pci_get_host_bridge_device(dev);
1688 if (IS_ENABLED(CONFIG_OF) &&
1689 bridge->parent && bridge->parent->of_node) {
1690 of_dma_configure(&dev->dev, bridge->parent->of_node);
1691 } else if (has_acpi_companion(bridge)) {
1692 struct acpi_device *adev = to_acpi_device_node(bridge->fwnode);
1693 enum dev_dma_attr attr = acpi_get_dma_attr(adev);
1695 if (attr == DEV_DMA_NOT_SUPPORTED)
1696 dev_warn(&dev->dev, "DMA not supported.\n");
1698 arch_setup_dma_ops(&dev->dev, 0, 0, NULL,
1699 attr == DEV_DMA_COHERENT);
1702 pci_put_host_bridge_device(bridge);
1705 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1709 pci_configure_device(dev);
1711 device_initialize(&dev->dev);
1712 dev->dev.release = pci_release_dev;
1714 set_dev_node(&dev->dev, pcibus_to_node(bus));
1715 dev->dev.dma_mask = &dev->dma_mask;
1716 dev->dev.dma_parms = &dev->dma_parms;
1717 dev->dev.coherent_dma_mask = 0xffffffffull;
1718 pci_dma_configure(dev);
1720 pci_set_dma_max_seg_size(dev, 65536);
1721 pci_set_dma_seg_boundary(dev, 0xffffffff);
1723 /* Fix up broken headers */
1724 pci_fixup_device(pci_fixup_header, dev);
1726 /* moved out from quirk header fixup code */
1727 pci_reassigndev_resource_alignment(dev);
1729 /* Clear the state_saved flag. */
1730 dev->state_saved = false;
1732 /* Initialize various capabilities */
1733 pci_init_capabilities(dev);
1736 * Add the device to our list of discovered devices
1737 * and the bus list for fixup functions, etc.
1739 down_write(&pci_bus_sem);
1740 list_add_tail(&dev->bus_list, &bus->devices);
1741 up_write(&pci_bus_sem);
1743 ret = pcibios_add_device(dev);
1746 /* Setup MSI irq domain */
1747 pci_set_msi_domain(dev);
1749 /* Notifier could use PCI capabilities */
1750 dev->match_driver = false;
1751 ret = device_add(&dev->dev);
1755 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
1757 struct pci_dev *dev;
1759 dev = pci_get_slot(bus, devfn);
1765 dev = pci_scan_device(bus, devfn);
1769 pci_device_add(dev, bus);
1773 EXPORT_SYMBOL(pci_scan_single_device);
1775 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
1781 if (pci_ari_enabled(bus)) {
1784 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1788 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1789 next_fn = PCI_ARI_CAP_NFN(cap);
1791 return 0; /* protect against malformed list */
1796 /* dev may be NULL for non-contiguous multifunction devices */
1797 if (!dev || dev->multifunction)
1798 return (fn + 1) % 8;
1803 static int only_one_child(struct pci_bus *bus)
1805 struct pci_dev *parent = bus->self;
1807 if (!parent || !pci_is_pcie(parent))
1809 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1813 * PCIe downstream ports are bridges that normally lead to only a
1814 * device 0, but if PCI_SCAN_ALL_PCIE_DEVS is set, scan all
1815 * possible devices, not just device 0. See PCIe spec r3.0,
1818 if (parent->has_secondary_link &&
1819 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1825 * pci_scan_slot - scan a PCI slot on a bus for devices.
1826 * @bus: PCI bus to scan
1827 * @devfn: slot number to scan (must have zero function.)
1829 * Scan a PCI slot on the specified PCI bus for devices, adding
1830 * discovered devices to the @bus->devices list. New devices
1831 * will not have is_added set.
1833 * Returns the number of new devices found.
1835 int pci_scan_slot(struct pci_bus *bus, int devfn)
1837 unsigned fn, nr = 0;
1838 struct pci_dev *dev;
1840 if (only_one_child(bus) && (devfn > 0))
1841 return 0; /* Already scanned the entire slot */
1843 dev = pci_scan_single_device(bus, devfn);
1849 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
1850 dev = pci_scan_single_device(bus, devfn + fn);
1854 dev->multifunction = 1;
1858 /* only one slot has pcie device */
1859 if (bus->self && nr)
1860 pcie_aspm_init_link_state(bus->self);
1864 EXPORT_SYMBOL(pci_scan_slot);
1866 static int pcie_find_smpss(struct pci_dev *dev, void *data)
1870 if (!pci_is_pcie(dev))
1874 * We don't have a way to change MPS settings on devices that have
1875 * drivers attached. A hot-added device might support only the minimum
1876 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1877 * where devices may be hot-added, we limit the fabric MPS to 128 so
1878 * hot-added devices will work correctly.
1880 * However, if we hot-add a device to a slot directly below a Root
1881 * Port, it's impossible for there to be other existing devices below
1882 * the port. We don't limit the MPS in this case because we can
1883 * reconfigure MPS on both the Root Port and the hot-added device,
1884 * and there are no other devices involved.
1886 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1888 if (dev->is_hotplug_bridge &&
1889 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
1892 if (*smpss > dev->pcie_mpss)
1893 *smpss = dev->pcie_mpss;
1898 static void pcie_write_mps(struct pci_dev *dev, int mps)
1902 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1903 mps = 128 << dev->pcie_mpss;
1905 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1907 /* For "Performance", the assumption is made that
1908 * downstream communication will never be larger than
1909 * the MRRS. So, the MPS only needs to be configured
1910 * for the upstream communication. This being the case,
1911 * walk from the top down and set the MPS of the child
1912 * to that of the parent bus.
1914 * Configure the device MPS with the smaller of the
1915 * device MPSS or the bridge MPS (which is assumed to be
1916 * properly configured at this point to the largest
1917 * allowable MPS based on its parent bus).
1919 mps = min(mps, pcie_get_mps(dev->bus->self));
1922 rc = pcie_set_mps(dev, mps);
1924 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1927 static void pcie_write_mrrs(struct pci_dev *dev)
1931 /* In the "safe" case, do not configure the MRRS. There appear to be
1932 * issues with setting MRRS to 0 on a number of devices.
1934 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1937 /* For Max performance, the MRRS must be set to the largest supported
1938 * value. However, it cannot be configured larger than the MPS the
1939 * device or the bus can support. This should already be properly
1940 * configured by a prior call to pcie_write_mps.
1942 mrrs = pcie_get_mps(dev);
1944 /* MRRS is a R/W register. Invalid values can be written, but a
1945 * subsequent read will verify if the value is acceptable or not.
1946 * If the MRRS value provided is not acceptable (e.g., too large),
1947 * shrink the value until it is acceptable to the HW.
1949 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1950 rc = pcie_set_readrq(dev, mrrs);
1954 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
1959 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
1962 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1966 if (!pci_is_pcie(dev))
1969 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
1970 pcie_bus_config == PCIE_BUS_DEFAULT)
1973 mps = 128 << *(u8 *)data;
1974 orig_mps = pcie_get_mps(dev);
1976 pcie_write_mps(dev, mps);
1977 pcie_write_mrrs(dev);
1979 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
1980 pcie_get_mps(dev), 128 << dev->pcie_mpss,
1981 orig_mps, pcie_get_readrq(dev));
1986 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
1987 * parents then children fashion. If this changes, then this code will not
1990 void pcie_bus_configure_settings(struct pci_bus *bus)
1997 if (!pci_is_pcie(bus->self))
2000 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
2001 * to be aware of the MPS of the destination. To work around this,
2002 * simply force the MPS of the entire system to the smallest possible.
2004 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2007 if (pcie_bus_config == PCIE_BUS_SAFE) {
2008 smpss = bus->self->pcie_mpss;
2010 pcie_find_smpss(bus->self, &smpss);
2011 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2014 pcie_bus_configure_set(bus->self, &smpss);
2015 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2017 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2019 unsigned int pci_scan_child_bus(struct pci_bus *bus)
2021 unsigned int devfn, pass, max = bus->busn_res.start;
2022 struct pci_dev *dev;
2024 dev_dbg(&bus->dev, "scanning bus\n");
2026 /* Go find them, Rover! */
2027 for (devfn = 0; devfn < 0x100; devfn += 8)
2028 pci_scan_slot(bus, devfn);
2030 /* Reserve buses for SR-IOV capability. */
2031 max += pci_iov_bus_range(bus);
2034 * After performing arch-dependent fixup of the bus, look behind
2035 * all PCI-to-PCI bridges on this bus.
2037 if (!bus->is_added) {
2038 dev_dbg(&bus->dev, "fixups for bus\n");
2039 pcibios_fixup_bus(bus);
2043 for (pass = 0; pass < 2; pass++)
2044 list_for_each_entry(dev, &bus->devices, bus_list) {
2045 if (pci_is_bridge(dev))
2046 max = pci_scan_bridge(bus, dev, max, pass);
2050 * We've scanned the bus and so we know all about what's on
2051 * the other side of any bridges that may be on this bus plus
2054 * Return how far we've got finding sub-buses.
2056 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2059 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2062 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
2063 * @bridge: Host bridge to set up.
2065 * Default empty implementation. Replace with an architecture-specific setup
2066 * routine, if necessary.
2068 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2073 void __weak pcibios_add_bus(struct pci_bus *bus)
2077 void __weak pcibios_remove_bus(struct pci_bus *bus)
2081 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2082 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2085 struct pci_host_bridge *bridge;
2086 struct pci_bus *b, *b2;
2087 struct resource_entry *window, *n;
2088 struct resource *res;
2089 resource_size_t offset;
2093 b = pci_alloc_bus(NULL);
2097 b->sysdata = sysdata;
2099 b->number = b->busn_res.start = bus;
2100 pci_bus_assign_domain_nr(b, parent);
2101 b2 = pci_find_bus(pci_domain_nr(b), bus);
2103 /* If we already got to this bus through a different bridge, ignore it */
2104 dev_dbg(&b2->dev, "bus already known\n");
2108 bridge = pci_alloc_host_bridge(b);
2112 bridge->dev.parent = parent;
2113 bridge->dev.release = pci_release_host_bridge_dev;
2114 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
2115 error = pcibios_root_bridge_prepare(bridge);
2121 error = device_register(&bridge->dev);
2123 put_device(&bridge->dev);
2126 b->bridge = get_device(&bridge->dev);
2127 device_enable_async_suspend(b->bridge);
2128 pci_set_bus_of_node(b);
2129 pci_set_bus_msi_domain(b);
2132 set_dev_node(b->bridge, pcibus_to_node(b));
2134 b->dev.class = &pcibus_class;
2135 b->dev.parent = b->bridge;
2136 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
2137 error = device_register(&b->dev);
2139 goto class_dev_reg_err;
2143 /* Create legacy_io and legacy_mem files for this bus */
2144 pci_create_legacy_files(b);
2147 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
2149 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
2151 /* Add initial resources to the bus */
2152 resource_list_for_each_entry_safe(window, n, resources) {
2153 list_move_tail(&window->node, &bridge->windows);
2155 offset = window->offset;
2156 if (res->flags & IORESOURCE_BUS)
2157 pci_bus_insert_busn_res(b, bus, res->end);
2159 pci_bus_add_resource(b, res, 0);
2161 if (resource_type(res) == IORESOURCE_IO)
2162 fmt = " (bus address [%#06llx-%#06llx])";
2164 fmt = " (bus address [%#010llx-%#010llx])";
2165 snprintf(bus_addr, sizeof(bus_addr), fmt,
2166 (unsigned long long) (res->start - offset),
2167 (unsigned long long) (res->end - offset));
2170 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
2173 down_write(&pci_bus_sem);
2174 list_add_tail(&b->node, &pci_root_buses);
2175 up_write(&pci_bus_sem);
2180 put_device(&bridge->dev);
2181 device_unregister(&bridge->dev);
2186 EXPORT_SYMBOL_GPL(pci_create_root_bus);
2188 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2190 struct resource *res = &b->busn_res;
2191 struct resource *parent_res, *conflict;
2195 res->flags = IORESOURCE_BUS;
2197 if (!pci_is_root_bus(b))
2198 parent_res = &b->parent->busn_res;
2200 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2201 res->flags |= IORESOURCE_PCI_FIXED;
2204 conflict = request_resource_conflict(parent_res, res);
2207 dev_printk(KERN_DEBUG, &b->dev,
2208 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2209 res, pci_is_root_bus(b) ? "domain " : "",
2210 parent_res, conflict->name, conflict);
2212 return conflict == NULL;
2215 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2217 struct resource *res = &b->busn_res;
2218 struct resource old_res = *res;
2219 resource_size_t size;
2222 if (res->start > bus_max)
2225 size = bus_max - res->start + 1;
2226 ret = adjust_resource(res, res->start, size);
2227 dev_printk(KERN_DEBUG, &b->dev,
2228 "busn_res: %pR end %s updated to %02x\n",
2229 &old_res, ret ? "can not be" : "is", bus_max);
2231 if (!ret && !res->parent)
2232 pci_bus_insert_busn_res(b, res->start, res->end);
2237 void pci_bus_release_busn_res(struct pci_bus *b)
2239 struct resource *res = &b->busn_res;
2242 if (!res->flags || !res->parent)
2245 ret = release_resource(res);
2246 dev_printk(KERN_DEBUG, &b->dev,
2247 "busn_res: %pR %s released\n",
2248 res, ret ? "can not be" : "is");
2251 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
2252 struct pci_ops *ops, void *sysdata,
2253 struct list_head *resources, struct msi_controller *msi)
2255 struct resource_entry *window;
2260 resource_list_for_each_entry(window, resources)
2261 if (window->res->flags & IORESOURCE_BUS) {
2266 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2274 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2276 pci_bus_insert_busn_res(b, bus, 255);
2279 max = pci_scan_child_bus(b);
2282 pci_bus_update_busn_res_end(b, max);
2287 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2288 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2290 return pci_scan_root_bus_msi(parent, bus, ops, sysdata, resources,
2293 EXPORT_SYMBOL(pci_scan_root_bus);
2295 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2298 LIST_HEAD(resources);
2301 pci_add_resource(&resources, &ioport_resource);
2302 pci_add_resource(&resources, &iomem_resource);
2303 pci_add_resource(&resources, &busn_resource);
2304 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2306 pci_scan_child_bus(b);
2308 pci_free_resource_list(&resources);
2312 EXPORT_SYMBOL(pci_scan_bus);
2315 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2316 * @bridge: PCI bridge for the bus to scan
2318 * Scan a PCI bus and child buses for new devices, add them,
2319 * and enable them, resizing bridge mmio/io resource if necessary
2320 * and possible. The caller must ensure the child devices are already
2321 * removed for resizing to occur.
2323 * Returns the max number of subordinate bus discovered.
2325 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2328 struct pci_bus *bus = bridge->subordinate;
2330 max = pci_scan_child_bus(bus);
2332 pci_assign_unassigned_bridge_resources(bridge);
2334 pci_bus_add_devices(bus);
2340 * pci_rescan_bus - scan a PCI bus for devices.
2341 * @bus: PCI bus to scan
2343 * Scan a PCI bus and child buses for new devices, adds them,
2346 * Returns the max number of subordinate bus discovered.
2348 unsigned int pci_rescan_bus(struct pci_bus *bus)
2352 max = pci_scan_child_bus(bus);
2353 pci_assign_unassigned_bus_resources(bus);
2354 pci_bus_add_devices(bus);
2358 EXPORT_SYMBOL_GPL(pci_rescan_bus);
2361 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2362 * routines should always be executed under this mutex.
2364 static DEFINE_MUTEX(pci_rescan_remove_lock);
2366 void pci_lock_rescan_remove(void)
2368 mutex_lock(&pci_rescan_remove_lock);
2370 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2372 void pci_unlock_rescan_remove(void)
2374 mutex_unlock(&pci_rescan_remove_lock);
2376 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2378 static int __init pci_sort_bf_cmp(const struct device *d_a,
2379 const struct device *d_b)
2381 const struct pci_dev *a = to_pci_dev(d_a);
2382 const struct pci_dev *b = to_pci_dev(d_b);
2384 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2385 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2387 if (a->bus->number < b->bus->number) return -1;
2388 else if (a->bus->number > b->bus->number) return 1;
2390 if (a->devfn < b->devfn) return -1;
2391 else if (a->devfn > b->devfn) return 1;
2396 void __init pci_sort_breadthfirst(void)
2398 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);