1 /* SPDX-License-Identifier: GPL-2.0 */
7 /* Number of possible devfns: 0.0 to 1f.7 inclusive */
8 #define MAX_NR_DEVFNS 256
10 #define PCI_FIND_CAP_TTL 48
12 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
14 extern const unsigned char pcie_link_speed[];
15 extern bool pci_early_dump;
17 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
18 bool pcie_cap_has_lnkctl2(const struct pci_dev *dev);
19 bool pcie_cap_has_rtctl(const struct pci_dev *dev);
21 /* Functions internal to the PCI core code */
23 int pci_create_sysfs_dev_files(struct pci_dev *pdev);
24 void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
25 void pci_cleanup_rom(struct pci_dev *dev);
27 extern const struct attribute_group pci_dev_smbios_attr_group;
31 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
32 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
34 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
35 enum pci_mmap_api mmap_api);
37 bool pci_reset_supported(struct pci_dev *dev);
38 void pci_init_reset_methods(struct pci_dev *dev);
39 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
40 int pci_bus_error_reset(struct pci_dev *dev);
42 struct pci_cap_saved_data {
49 struct pci_cap_saved_state {
50 struct hlist_node next;
51 struct pci_cap_saved_data cap;
54 void pci_allocate_cap_save_buffers(struct pci_dev *dev);
55 void pci_free_cap_save_buffers(struct pci_dev *dev);
56 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
57 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
58 u16 cap, unsigned int size);
59 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
60 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
63 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
64 #define PCI_PM_D3HOT_WAIT 10 /* msec */
65 #define PCI_PM_D3COLD_WAIT 100 /* msec */
68 * Following exit from Conventional Reset, devices must be ready within 1 sec
69 * (PCIe r6.0 sec 6.6.1). A D3cold to D0 transition implies a Conventional
70 * Reset (PCIe r6.0 sec 5.8).
72 #define PCI_RESET_WAIT 1000 /* msec */
74 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
75 void pci_refresh_power_state(struct pci_dev *dev);
76 int pci_power_up(struct pci_dev *dev);
77 void pci_disable_enabled_device(struct pci_dev *dev);
78 int pci_finish_runtime_suspend(struct pci_dev *dev);
79 void pcie_clear_device_status(struct pci_dev *dev);
80 void pcie_clear_root_pme_status(struct pci_dev *dev);
81 bool pci_check_pme_status(struct pci_dev *dev);
82 void pci_pme_wakeup_bus(struct pci_bus *bus);
83 int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
84 void pci_pme_restore(struct pci_dev *dev);
85 bool pci_dev_need_resume(struct pci_dev *dev);
86 void pci_dev_adjust_pme(struct pci_dev *dev);
87 void pci_dev_complete_resume(struct pci_dev *pci_dev);
88 void pci_config_pm_runtime_get(struct pci_dev *dev);
89 void pci_config_pm_runtime_put(struct pci_dev *dev);
90 void pci_pm_init(struct pci_dev *dev);
91 void pci_ea_init(struct pci_dev *dev);
92 void pci_msi_init(struct pci_dev *dev);
93 void pci_msix_init(struct pci_dev *dev);
94 bool pci_bridge_d3_possible(struct pci_dev *dev);
95 void pci_bridge_d3_update(struct pci_dev *dev);
96 void pci_bridge_reconfigure_ltr(struct pci_dev *dev);
97 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type);
99 static inline void pci_wakeup_event(struct pci_dev *dev)
101 /* Wait 100 ms before the system can be put into a sleep state. */
102 pm_wakeup_event(&dev->dev, 100);
105 static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
107 return !!(pci_dev->subordinate);
110 static inline bool pci_power_manageable(struct pci_dev *pci_dev)
113 * Currently we allow normal PCI devices and PCI bridges transition
114 * into D3 if their bridge_d3 is set.
116 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
119 static inline bool pcie_downstream_port(const struct pci_dev *dev)
121 int type = pci_pcie_type(dev);
123 return type == PCI_EXP_TYPE_ROOT_PORT ||
124 type == PCI_EXP_TYPE_DOWNSTREAM ||
125 type == PCI_EXP_TYPE_PCIE_BRIDGE;
128 void pci_vpd_init(struct pci_dev *dev);
129 void pci_vpd_release(struct pci_dev *dev);
130 extern const struct attribute_group pci_dev_vpd_attr_group;
132 /* PCI Virtual Channel */
133 int pci_save_vc_state(struct pci_dev *dev);
134 void pci_restore_vc_state(struct pci_dev *dev);
135 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
137 /* PCI /proc functions */
138 #ifdef CONFIG_PROC_FS
139 int pci_proc_attach_device(struct pci_dev *dev);
140 int pci_proc_detach_device(struct pci_dev *dev);
141 int pci_proc_detach_bus(struct pci_bus *bus);
143 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
144 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
145 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
148 /* Functions for PCI Hotplug drivers to use */
149 int pci_hp_add_bridge(struct pci_dev *dev);
151 #ifdef HAVE_PCI_LEGACY
152 void pci_create_legacy_files(struct pci_bus *bus);
153 void pci_remove_legacy_files(struct pci_bus *bus);
155 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
156 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
159 /* Lock for read/write access to pci device and bus lists */
160 extern struct rw_semaphore pci_bus_sem;
161 extern struct mutex pci_slot_mutex;
163 extern raw_spinlock_t pci_lock;
165 extern unsigned int pci_pm_d3hot_delay;
167 #ifdef CONFIG_PCI_MSI
168 void pci_no_msi(void);
170 static inline void pci_no_msi(void) { }
173 void pci_realloc_get_opt(char *);
175 static inline int pci_no_d1d2(struct pci_dev *dev)
177 unsigned int parent_dstates = 0;
180 parent_dstates = dev->bus->self->no_d1d2;
181 return (dev->no_d1d2 || parent_dstates);
184 extern const struct attribute_group *pci_dev_groups[];
185 extern const struct attribute_group *pcibus_groups[];
186 extern const struct device_type pci_dev_type;
187 extern const struct attribute_group *pci_bus_groups[];
189 extern unsigned long pci_hotplug_io_size;
190 extern unsigned long pci_hotplug_mmio_size;
191 extern unsigned long pci_hotplug_mmio_pref_size;
192 extern unsigned long pci_hotplug_bus_size;
195 * pci_match_one_device - Tell if a PCI device structure has a matching
196 * PCI device id structure
197 * @id: single PCI device id structure to match
198 * @dev: the PCI device structure to match against
200 * Returns the matching pci_device_id structure or %NULL if there is no match.
202 static inline const struct pci_device_id *
203 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
205 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
206 (id->device == PCI_ANY_ID || id->device == dev->device) &&
207 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
208 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
209 !((id->class ^ dev->class) & id->class_mask))
214 /* PCI slot sysfs helper code */
215 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
217 extern struct kset *pci_slots_kset;
219 struct pci_slot_attribute {
220 struct attribute attr;
221 ssize_t (*show)(struct pci_slot *, char *);
222 ssize_t (*store)(struct pci_slot *, const char *, size_t);
224 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
227 pci_bar_unknown, /* Standard PCI BAR probe */
228 pci_bar_io, /* An I/O port BAR */
229 pci_bar_mem32, /* A 32-bit memory BAR */
230 pci_bar_mem64, /* A 64-bit memory BAR */
233 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
234 void pci_put_host_bridge_device(struct device *dev);
236 int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
237 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
239 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
241 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
243 int pci_setup_device(struct pci_dev *dev);
244 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
245 struct resource *res, unsigned int reg);
246 void pci_configure_ari(struct pci_dev *dev);
247 void __pci_bus_size_bridges(struct pci_bus *bus,
248 struct list_head *realloc_head);
249 void __pci_bus_assign_resources(const struct pci_bus *bus,
250 struct list_head *realloc_head,
251 struct list_head *fail_head);
252 bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
254 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
255 void pci_disable_bridge_window(struct pci_dev *dev);
256 struct pci_bus *pci_bus_get(struct pci_bus *bus);
257 void pci_bus_put(struct pci_bus *bus);
259 /* PCIe link information from Link Capabilities 2 */
260 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
261 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
262 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
263 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
264 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
265 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
266 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
269 /* PCIe speed to Mb/s reduced by encoding overhead */
270 #define PCIE_SPEED2MBS_ENC(speed) \
271 ((speed) == PCIE_SPEED_64_0GT ? 64000*128/130 : \
272 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
273 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
274 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
275 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
276 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
279 const char *pci_speed_string(enum pci_bus_speed speed);
280 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
281 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
282 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
283 enum pcie_link_width *width);
284 void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
285 void pcie_report_downtraining(struct pci_dev *dev);
286 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
288 /* Single Root I/O Virtualization */
290 int pos; /* Capability position */
291 int nres; /* Number of resources */
292 u32 cap; /* SR-IOV Capabilities */
293 u16 ctrl; /* SR-IOV Control */
294 u16 total_VFs; /* Total VFs associated with the PF */
295 u16 initial_VFs; /* Initial VFs associated with the PF */
296 u16 num_VFs; /* Number of VFs available */
297 u16 offset; /* First VF Routing ID offset */
298 u16 stride; /* Following VF stride */
299 u16 vf_device; /* VF device ID */
300 u32 pgsz; /* Page size for BAR alignment */
301 u8 link; /* Function Dependency Link */
302 u8 max_VF_buses; /* Max buses consumed by VFs */
303 u16 driver_max_VFs; /* Max num VFs driver supports */
304 struct pci_dev *dev; /* Lowest numbered PF */
305 struct pci_dev *self; /* This PF */
306 u32 class; /* VF device */
307 u8 hdr_type; /* VF header type */
308 u16 subsystem_vendor; /* VF subsystem vendor */
309 u16 subsystem_device; /* VF subsystem device */
310 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
311 bool drivers_autoprobe; /* Auto probing of VFs by driver */
315 * pci_dev_set_io_state - Set the new error state if possible.
317 * @dev: PCI device to set new error_state
318 * @new: the state we want dev to be in
320 * If the device is experiencing perm_failure, it has to remain in that state.
321 * Any other transition is allowed.
323 * Returns true if state has been changed to the requested state.
325 static inline bool pci_dev_set_io_state(struct pci_dev *dev,
326 pci_channel_state_t new)
328 pci_channel_state_t old;
331 case pci_channel_io_perm_failure:
332 xchg(&dev->error_state, pci_channel_io_perm_failure);
334 case pci_channel_io_frozen:
335 old = cmpxchg(&dev->error_state, pci_channel_io_normal,
336 pci_channel_io_frozen);
337 return old != pci_channel_io_perm_failure;
338 case pci_channel_io_normal:
339 old = cmpxchg(&dev->error_state, pci_channel_io_frozen,
340 pci_channel_io_normal);
341 return old != pci_channel_io_perm_failure;
347 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
349 pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
354 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
356 return dev->error_state == pci_channel_io_perm_failure;
359 /* pci_dev priv_flags */
360 #define PCI_DEV_ADDED 0
361 #define PCI_DPC_RECOVERED 1
362 #define PCI_DPC_RECOVERING 2
364 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
366 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
369 static inline bool pci_dev_is_added(const struct pci_dev *dev)
371 return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
374 #ifdef CONFIG_PCIEAER
375 #include <linux/aer.h>
377 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
379 struct aer_err_info {
380 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
385 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
386 unsigned int __pad1:5;
387 unsigned int multi_error_valid:1;
389 unsigned int first_error:5;
390 unsigned int __pad2:2;
391 unsigned int tlp_header_valid:1;
393 unsigned int status; /* COR/UNCOR Error Status */
394 unsigned int mask; /* COR/UNCOR Error Mask */
395 struct aer_header_log_regs tlp; /* TLP Header */
398 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
399 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
400 #endif /* CONFIG_PCIEAER */
402 #ifdef CONFIG_PCIEPORTBUS
403 /* Cached RCEC Endpoint Association */
411 #ifdef CONFIG_PCIE_DPC
412 void pci_save_dpc_state(struct pci_dev *dev);
413 void pci_restore_dpc_state(struct pci_dev *dev);
414 void pci_dpc_init(struct pci_dev *pdev);
415 void dpc_process_error(struct pci_dev *pdev);
416 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
417 bool pci_dpc_recovered(struct pci_dev *pdev);
419 static inline void pci_save_dpc_state(struct pci_dev *dev) {}
420 static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
421 static inline void pci_dpc_init(struct pci_dev *pdev) {}
422 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
425 #ifdef CONFIG_PCIEPORTBUS
426 void pci_rcec_init(struct pci_dev *dev);
427 void pci_rcec_exit(struct pci_dev *dev);
428 void pcie_link_rcec(struct pci_dev *rcec);
429 void pcie_walk_rcec(struct pci_dev *rcec,
430 int (*cb)(struct pci_dev *, void *),
433 static inline void pci_rcec_init(struct pci_dev *dev) {}
434 static inline void pci_rcec_exit(struct pci_dev *dev) {}
435 static inline void pcie_link_rcec(struct pci_dev *rcec) {}
436 static inline void pcie_walk_rcec(struct pci_dev *rcec,
437 int (*cb)(struct pci_dev *, void *),
441 #ifdef CONFIG_PCI_ATS
442 /* Address Translation Service */
443 void pci_ats_init(struct pci_dev *dev);
444 void pci_restore_ats_state(struct pci_dev *dev);
446 static inline void pci_ats_init(struct pci_dev *d) { }
447 static inline void pci_restore_ats_state(struct pci_dev *dev) { }
448 #endif /* CONFIG_PCI_ATS */
450 #ifdef CONFIG_PCI_PRI
451 void pci_pri_init(struct pci_dev *dev);
452 void pci_restore_pri_state(struct pci_dev *pdev);
454 static inline void pci_pri_init(struct pci_dev *dev) { }
455 static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
458 #ifdef CONFIG_PCI_PASID
459 void pci_pasid_init(struct pci_dev *dev);
460 void pci_restore_pasid_state(struct pci_dev *pdev);
462 static inline void pci_pasid_init(struct pci_dev *dev) { }
463 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
466 #ifdef CONFIG_PCI_IOV
467 int pci_iov_init(struct pci_dev *dev);
468 void pci_iov_release(struct pci_dev *dev);
469 void pci_iov_remove(struct pci_dev *dev);
470 void pci_iov_update_resource(struct pci_dev *dev, int resno);
471 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
472 void pci_restore_iov_state(struct pci_dev *dev);
473 int pci_iov_bus_range(struct pci_bus *bus);
474 extern const struct attribute_group sriov_pf_dev_attr_group;
475 extern const struct attribute_group sriov_vf_dev_attr_group;
477 static inline int pci_iov_init(struct pci_dev *dev)
481 static inline void pci_iov_release(struct pci_dev *dev)
485 static inline void pci_iov_remove(struct pci_dev *dev)
488 static inline void pci_restore_iov_state(struct pci_dev *dev)
491 static inline int pci_iov_bus_range(struct pci_bus *bus)
496 #endif /* CONFIG_PCI_IOV */
498 #ifdef CONFIG_PCIE_PTM
499 void pci_ptm_init(struct pci_dev *dev);
500 void pci_save_ptm_state(struct pci_dev *dev);
501 void pci_restore_ptm_state(struct pci_dev *dev);
502 void pci_suspend_ptm(struct pci_dev *dev);
503 void pci_resume_ptm(struct pci_dev *dev);
505 static inline void pci_ptm_init(struct pci_dev *dev) { }
506 static inline void pci_save_ptm_state(struct pci_dev *dev) { }
507 static inline void pci_restore_ptm_state(struct pci_dev *dev) { }
508 static inline void pci_suspend_ptm(struct pci_dev *dev) { }
509 static inline void pci_resume_ptm(struct pci_dev *dev) { }
512 unsigned long pci_cardbus_resource_alignment(struct resource *);
514 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
515 struct resource *res)
517 #ifdef CONFIG_PCI_IOV
518 int resno = res - dev->resource;
520 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
521 return pci_sriov_resource_alignment(dev, resno);
523 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
524 return pci_cardbus_resource_alignment(res);
525 return resource_alignment(res);
528 void pci_acs_init(struct pci_dev *dev);
529 #ifdef CONFIG_PCI_QUIRKS
530 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
531 int pci_dev_specific_enable_acs(struct pci_dev *dev);
532 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
534 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
539 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
543 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
549 /* PCI error reporting and recovery */
550 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
551 pci_channel_state_t state,
552 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));
554 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
555 #ifdef CONFIG_PCIEASPM
556 void pcie_aspm_init_link_state(struct pci_dev *pdev);
557 void pcie_aspm_exit_link_state(struct pci_dev *pdev);
558 void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
560 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
561 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
562 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
565 #ifdef CONFIG_PCIE_ECRC
566 void pcie_set_ecrc_checking(struct pci_dev *dev);
567 void pcie_ecrc_get_policy(char *str);
569 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
570 static inline void pcie_ecrc_get_policy(char *str) { }
573 struct pci_dev_reset_methods {
576 int (*reset)(struct pci_dev *dev, bool probe);
579 struct pci_reset_fn_method {
580 int (*reset_fn)(struct pci_dev *pdev, bool probe);
584 #ifdef CONFIG_PCI_QUIRKS
585 int pci_dev_specific_reset(struct pci_dev *dev, bool probe);
587 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
593 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
594 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
595 struct resource *res);
597 static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
598 u16 segment, struct resource *res)
604 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
605 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
606 static inline u64 pci_rebar_size_to_bytes(int size)
608 return 1ULL << (size + 20);
614 int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
615 int of_get_pci_domain_nr(struct device_node *node);
616 int of_pci_get_max_link_speed(struct device_node *node);
617 u32 of_pci_get_slot_power_limit(struct device_node *node,
618 u8 *slot_power_limit_value,
619 u8 *slot_power_limit_scale);
620 int pci_set_of_node(struct pci_dev *dev);
621 void pci_release_of_node(struct pci_dev *dev);
622 void pci_set_bus_of_node(struct pci_bus *bus);
623 void pci_release_bus_of_node(struct pci_bus *bus);
625 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
629 of_pci_parse_bus_range(struct device_node *node, struct resource *res)
635 of_get_pci_domain_nr(struct device_node *node)
641 of_pci_get_max_link_speed(struct device_node *node)
647 of_pci_get_slot_power_limit(struct device_node *node,
648 u8 *slot_power_limit_value,
649 u8 *slot_power_limit_scale)
651 if (slot_power_limit_value)
652 *slot_power_limit_value = 0;
653 if (slot_power_limit_scale)
654 *slot_power_limit_scale = 0;
658 static inline int pci_set_of_node(struct pci_dev *dev) { return 0; }
659 static inline void pci_release_of_node(struct pci_dev *dev) { }
660 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
661 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
663 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
668 #endif /* CONFIG_OF */
670 #ifdef CONFIG_PCIEAER
671 void pci_no_aer(void);
672 void pci_aer_init(struct pci_dev *dev);
673 void pci_aer_exit(struct pci_dev *dev);
674 extern const struct attribute_group aer_stats_attr_group;
675 void pci_aer_clear_fatal_status(struct pci_dev *dev);
676 int pci_aer_clear_status(struct pci_dev *dev);
677 int pci_aer_raw_clear_status(struct pci_dev *dev);
679 static inline void pci_no_aer(void) { }
680 static inline void pci_aer_init(struct pci_dev *d) { }
681 static inline void pci_aer_exit(struct pci_dev *d) { }
682 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
683 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
684 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
688 int pci_acpi_program_hp_params(struct pci_dev *dev);
689 extern const struct attribute_group pci_dev_acpi_attr_group;
690 void pci_set_acpi_fwnode(struct pci_dev *dev);
691 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe);
692 bool acpi_pci_power_manageable(struct pci_dev *dev);
693 bool acpi_pci_bridge_d3(struct pci_dev *dev);
694 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state);
695 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev);
696 void acpi_pci_refresh_power_state(struct pci_dev *dev);
697 int acpi_pci_wakeup(struct pci_dev *dev, bool enable);
698 bool acpi_pci_need_resume(struct pci_dev *dev);
699 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev);
701 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe)
705 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) {}
706 static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
710 static inline bool acpi_pci_power_manageable(struct pci_dev *dev)
714 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev)
718 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
722 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)
726 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) {}
727 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable)
731 static inline bool acpi_pci_need_resume(struct pci_dev *dev)
735 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
737 return PCI_POWER_ERROR;
741 #ifdef CONFIG_PCIEASPM
742 extern const struct attribute_group aspm_ctrl_attr_group;
745 extern const struct attribute_group pci_dev_reset_method_attr_group;
747 #ifdef CONFIG_X86_INTEL_MID
748 bool pci_use_mid_pm(void);
749 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
750 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev);
752 static inline bool pci_use_mid_pm(void)
756 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
760 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev)
767 * Config Address for PCI Configuration Mechanism #1
769 * See PCI Local Bus Specification, Revision 3.0,
770 * Section 3.2.2.3.2, Figure 3-2, p. 50.
773 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */
774 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */
775 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */
777 #define PCI_CONF1_BUS_MASK 0xff
778 #define PCI_CONF1_DEV_MASK 0x1f
779 #define PCI_CONF1_FUNC_MASK 0x7
780 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */
782 #define PCI_CONF1_ENABLE BIT(31)
783 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT)
784 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT)
785 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT)
786 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK)
788 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \
789 (PCI_CONF1_ENABLE | \
790 PCI_CONF1_BUS(bus) | \
791 PCI_CONF1_DEV(dev) | \
792 PCI_CONF1_FUNC(func) | \
796 * Extension of PCI Config Address for accessing extended PCIe registers
798 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs
799 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address
800 * are used for specifying additional 4 high bits of PCI Express register.
803 #define PCI_CONF1_EXT_REG_SHIFT 16
804 #define PCI_CONF1_EXT_REG_MASK 0xf00
805 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT)
807 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \
808 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \
809 PCI_CONF1_EXT_REG(reg))
811 #endif /* DRIVERS_PCI_H */