4 #define PCI_FIND_CAP_TTL 48
6 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
8 extern const unsigned char pcie_link_speed[];
10 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
12 /* Functions internal to the PCI core code */
14 int pci_create_sysfs_dev_files(struct pci_dev *pdev);
15 void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
16 #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
17 static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
19 static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
22 void pci_create_firmware_label_files(struct pci_dev *pdev);
23 void pci_remove_firmware_label_files(struct pci_dev *pdev);
25 void pci_cleanup_rom(struct pci_dev *dev);
28 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
29 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
31 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
32 enum pci_mmap_api mmap_api);
34 int pci_probe_reset_function(struct pci_dev *dev);
37 * struct pci_platform_pm_ops - Firmware PM callbacks
39 * @is_manageable: returns 'true' if given device is power manageable by the
42 * @set_state: invokes the platform firmware to set the device's power state
44 * @get_state: queries the platform firmware for a device's current power state
46 * @choose_state: returns PCI power state of given device preferred by the
47 * platform; to be used during system-wide transitions from a
48 * sleeping state to the working state and vice versa
50 * @sleep_wake: enables/disables the system wake up capability of given device
52 * @run_wake: enables/disables the platform to generate run-time wake-up events
53 * for given device (the device's wake-up capability has to be
54 * enabled by @sleep_wake for this feature to work)
56 * @need_resume: returns 'true' if the given device (which is currently
57 * suspended) needs to be resumed to be configured for system
60 * If given platform is generally capable of power managing PCI devices, all of
61 * these callbacks are mandatory.
63 struct pci_platform_pm_ops {
64 bool (*is_manageable)(struct pci_dev *dev);
65 int (*set_state)(struct pci_dev *dev, pci_power_t state);
66 pci_power_t (*get_state)(struct pci_dev *dev);
67 pci_power_t (*choose_state)(struct pci_dev *dev);
68 int (*sleep_wake)(struct pci_dev *dev, bool enable);
69 int (*run_wake)(struct pci_dev *dev, bool enable);
70 bool (*need_resume)(struct pci_dev *dev);
73 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
74 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
75 void pci_power_up(struct pci_dev *dev);
76 void pci_disable_enabled_device(struct pci_dev *dev);
77 int pci_finish_runtime_suspend(struct pci_dev *dev);
78 int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
79 bool pci_dev_keep_suspended(struct pci_dev *dev);
80 void pci_dev_complete_resume(struct pci_dev *pci_dev);
81 void pci_config_pm_runtime_get(struct pci_dev *dev);
82 void pci_config_pm_runtime_put(struct pci_dev *dev);
83 void pci_pm_init(struct pci_dev *dev);
84 void pci_ea_init(struct pci_dev *dev);
85 void pci_allocate_cap_save_buffers(struct pci_dev *dev);
86 void pci_free_cap_save_buffers(struct pci_dev *dev);
87 bool pci_bridge_d3_possible(struct pci_dev *dev);
88 void pci_bridge_d3_update(struct pci_dev *dev);
90 static inline void pci_wakeup_event(struct pci_dev *dev)
92 /* Wait 100 ms before the system can be put into a sleep state. */
93 pm_wakeup_event(&dev->dev, 100);
96 static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
98 return !!(pci_dev->subordinate);
101 static inline bool pci_power_manageable(struct pci_dev *pci_dev)
104 * Currently we allow normal PCI devices and PCI bridges transition
105 * into D3 if their bridge_d3 is set.
107 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
111 ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
112 ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
113 int (*set_size)(struct pci_dev *dev, size_t len);
117 const struct pci_vpd_ops *ops;
118 struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
127 int pci_vpd_init(struct pci_dev *dev);
128 void pci_vpd_release(struct pci_dev *dev);
130 /* PCI /proc functions */
131 #ifdef CONFIG_PROC_FS
132 int pci_proc_attach_device(struct pci_dev *dev);
133 int pci_proc_detach_device(struct pci_dev *dev);
134 int pci_proc_detach_bus(struct pci_bus *bus);
136 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
137 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
138 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
141 /* Functions for PCI Hotplug drivers to use */
142 int pci_hp_add_bridge(struct pci_dev *dev);
144 #ifdef HAVE_PCI_LEGACY
145 void pci_create_legacy_files(struct pci_bus *bus);
146 void pci_remove_legacy_files(struct pci_bus *bus);
148 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
149 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
152 /* Lock for read/write access to pci device and bus lists */
153 extern struct rw_semaphore pci_bus_sem;
155 extern raw_spinlock_t pci_lock;
157 extern unsigned int pci_pm_d3_delay;
159 #ifdef CONFIG_PCI_MSI
160 void pci_no_msi(void);
162 static inline void pci_no_msi(void) { }
165 static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
169 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
170 control &= ~PCI_MSI_FLAGS_ENABLE;
172 control |= PCI_MSI_FLAGS_ENABLE;
173 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
176 static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
180 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
183 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
186 void pci_realloc_get_opt(char *);
188 static inline int pci_no_d1d2(struct pci_dev *dev)
190 unsigned int parent_dstates = 0;
193 parent_dstates = dev->bus->self->no_d1d2;
194 return (dev->no_d1d2 || parent_dstates);
197 extern const struct attribute_group *pci_dev_groups[];
198 extern const struct attribute_group *pcibus_groups[];
199 extern struct device_type pci_dev_type;
200 extern const struct attribute_group *pci_bus_groups[];
204 * pci_match_one_device - Tell if a PCI device structure has a matching
205 * PCI device id structure
206 * @id: single PCI device id structure to match
207 * @dev: the PCI device structure to match against
209 * Returns the matching pci_device_id structure or %NULL if there is no match.
211 static inline const struct pci_device_id *
212 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
214 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
215 (id->device == PCI_ANY_ID || id->device == dev->device) &&
216 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
217 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
218 !((id->class ^ dev->class) & id->class_mask))
223 /* PCI slot sysfs helper code */
224 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
226 extern struct kset *pci_slots_kset;
228 struct pci_slot_attribute {
229 struct attribute attr;
230 ssize_t (*show)(struct pci_slot *, char *);
231 ssize_t (*store)(struct pci_slot *, const char *, size_t);
233 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
236 pci_bar_unknown, /* Standard PCI BAR probe */
237 pci_bar_io, /* An io port BAR */
238 pci_bar_mem32, /* A 32-bit memory BAR */
239 pci_bar_mem64, /* A 64-bit memory BAR */
242 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
244 int pci_setup_device(struct pci_dev *dev);
245 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
246 struct resource *res, unsigned int reg);
247 void pci_configure_ari(struct pci_dev *dev);
248 void __pci_bus_size_bridges(struct pci_bus *bus,
249 struct list_head *realloc_head);
250 void __pci_bus_assign_resources(const struct pci_bus *bus,
251 struct list_head *realloc_head,
252 struct list_head *fail_head);
253 bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
255 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
256 void pci_disable_bridge_window(struct pci_dev *dev);
258 /* Single Root I/O Virtualization */
260 int pos; /* capability position */
261 int nres; /* number of resources */
262 u32 cap; /* SR-IOV Capabilities */
263 u16 ctrl; /* SR-IOV Control */
264 u16 total_VFs; /* total VFs associated with the PF */
265 u16 initial_VFs; /* initial VFs associated with the PF */
266 u16 num_VFs; /* number of VFs available */
267 u16 offset; /* first VF Routing ID offset */
268 u16 stride; /* following VF stride */
269 u32 pgsz; /* page size for BAR alignment */
270 u8 link; /* Function Dependency Link */
271 u8 max_VF_buses; /* max buses consumed by VFs */
272 u16 driver_max_VFs; /* max num VFs driver supports */
273 struct pci_dev *dev; /* lowest numbered PF */
274 struct pci_dev *self; /* this PF */
275 struct mutex lock; /* lock for setting sriov_numvfs in sysfs */
276 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
279 #ifdef CONFIG_PCI_ATS
280 void pci_restore_ats_state(struct pci_dev *dev);
282 static inline void pci_restore_ats_state(struct pci_dev *dev)
285 #endif /* CONFIG_PCI_ATS */
287 #ifdef CONFIG_PCI_IOV
288 int pci_iov_init(struct pci_dev *dev);
289 void pci_iov_release(struct pci_dev *dev);
290 void pci_iov_update_resource(struct pci_dev *dev, int resno);
291 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
292 void pci_restore_iov_state(struct pci_dev *dev);
293 int pci_iov_bus_range(struct pci_bus *bus);
296 static inline int pci_iov_init(struct pci_dev *dev)
300 static inline void pci_iov_release(struct pci_dev *dev)
304 static inline void pci_restore_iov_state(struct pci_dev *dev)
307 static inline int pci_iov_bus_range(struct pci_bus *bus)
312 #endif /* CONFIG_PCI_IOV */
314 unsigned long pci_cardbus_resource_alignment(struct resource *);
316 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
317 struct resource *res)
319 #ifdef CONFIG_PCI_IOV
320 int resno = res - dev->resource;
322 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
323 return pci_sriov_resource_alignment(dev, resno);
325 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
326 return pci_cardbus_resource_alignment(res);
327 return resource_alignment(res);
330 void pci_enable_acs(struct pci_dev *dev);
332 #ifdef CONFIG_PCIE_PTM
333 void pci_ptm_init(struct pci_dev *dev);
335 static inline void pci_ptm_init(struct pci_dev *dev) { }
338 struct pci_dev_reset_methods {
341 int (*reset)(struct pci_dev *dev, int probe);
344 #ifdef CONFIG_PCI_QUIRKS
345 int pci_dev_specific_reset(struct pci_dev *dev, int probe);
347 static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
353 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
354 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
355 struct resource *res);
358 #endif /* DRIVERS_PCI_H */