1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
16 #include <linux/msi.h>
18 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/logic_pio.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pci_hotplug.h>
31 #include <linux/vmalloc.h>
33 #include <linux/aer.h>
34 #include <linux/bitfield.h>
37 DEFINE_MUTEX(pci_slot_mutex);
39 const char *pci_power_names[] = {
40 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
42 EXPORT_SYMBOL_GPL(pci_power_names);
45 int isa_dma_bridge_buggy;
46 EXPORT_SYMBOL(isa_dma_bridge_buggy);
50 EXPORT_SYMBOL(pci_pci_problems);
52 unsigned int pci_pm_d3hot_delay;
54 static void pci_pme_list_scan(struct work_struct *work);
56 static LIST_HEAD(pci_pme_list);
57 static DEFINE_MUTEX(pci_pme_list_mutex);
58 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
60 struct pci_pme_device {
61 struct list_head list;
65 #define PME_TIMEOUT 1000 /* How long between PME checks */
68 * Following exit from Conventional Reset, devices must be ready within 1 sec
69 * (PCIe r6.0 sec 6.6.1). A D3cold to D0 transition implies a Conventional
70 * Reset (PCIe r6.0 sec 5.8).
72 #define PCI_RESET_WAIT 1000 /* msec */
75 * Devices may extend the 1 sec period through Request Retry Status
76 * completions (PCIe r6.0 sec 2.3.1). The spec does not provide an upper
77 * limit, but 60 sec ought to be enough for any device to become
80 #define PCIE_RESET_READY_POLL_MS 60000 /* msec */
82 static void pci_dev_d3_sleep(struct pci_dev *dev)
84 unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay);
88 /* Use a 20% upper bound, 1ms minimum */
89 upper = max(DIV_ROUND_CLOSEST(delay_ms, 5), 1U);
90 usleep_range(delay_ms * USEC_PER_MSEC,
91 (delay_ms + upper) * USEC_PER_MSEC);
95 bool pci_reset_supported(struct pci_dev *dev)
97 return dev->reset_methods[0] != 0;
100 #ifdef CONFIG_PCI_DOMAINS
101 int pci_domains_supported = 1;
104 #define DEFAULT_CARDBUS_IO_SIZE (256)
105 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
106 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
107 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
108 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
110 #define DEFAULT_HOTPLUG_IO_SIZE (256)
111 #define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024)
112 #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024)
113 /* hpiosize=nn can override this */
114 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
116 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
117 * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size;
118 * pci=hpmemsize=nnM overrides both
120 unsigned long pci_hotplug_mmio_size = DEFAULT_HOTPLUG_MMIO_SIZE;
121 unsigned long pci_hotplug_mmio_pref_size = DEFAULT_HOTPLUG_MMIO_PREF_SIZE;
123 #define DEFAULT_HOTPLUG_BUS_SIZE 1
124 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
127 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
128 #ifdef CONFIG_PCIE_BUS_TUNE_OFF
129 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
130 #elif defined CONFIG_PCIE_BUS_SAFE
131 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_SAFE;
132 #elif defined CONFIG_PCIE_BUS_PERFORMANCE
133 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE;
134 #elif defined CONFIG_PCIE_BUS_PEER2PEER
135 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PEER2PEER;
137 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
141 * The default CLS is used if arch didn't set CLS explicitly and not
142 * all pci devices agree on the same value. Arch can override either
143 * the dfl or actual value as it sees fit. Don't forget this is
144 * measured in 32-bit words, not bytes.
146 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
147 u8 pci_cache_line_size;
150 * If we set up a device for bus mastering, we need to check the latency
151 * timer as certain BIOSes forget to set it properly.
153 unsigned int pcibios_max_latency = 255;
155 /* If set, the PCIe ARI capability will not be used. */
156 static bool pcie_ari_disabled;
158 /* If set, the PCIe ATS capability will not be used. */
159 static bool pcie_ats_disabled;
161 /* If set, the PCI config space of each device is printed during boot. */
164 bool pci_ats_disabled(void)
166 return pcie_ats_disabled;
168 EXPORT_SYMBOL_GPL(pci_ats_disabled);
170 /* Disable bridge_d3 for all PCIe ports */
171 static bool pci_bridge_d3_disable;
172 /* Force bridge_d3 for all PCIe ports */
173 static bool pci_bridge_d3_force;
175 static int __init pcie_port_pm_setup(char *str)
177 if (!strcmp(str, "off"))
178 pci_bridge_d3_disable = true;
179 else if (!strcmp(str, "force"))
180 pci_bridge_d3_force = true;
183 __setup("pcie_port_pm=", pcie_port_pm_setup);
186 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
187 * @bus: pointer to PCI bus structure to search
189 * Given a PCI bus, returns the highest PCI bus number present in the set
190 * including the given PCI bus and its list of child PCI buses.
192 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
195 unsigned char max, n;
197 max = bus->busn_res.end;
198 list_for_each_entry(tmp, &bus->children, node) {
199 n = pci_bus_max_busnr(tmp);
205 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
208 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
209 * @pdev: the PCI device
211 * Returns error bits set in PCI_STATUS and clears them.
213 int pci_status_get_and_clear_errors(struct pci_dev *pdev)
218 ret = pci_read_config_word(pdev, PCI_STATUS, &status);
219 if (ret != PCIBIOS_SUCCESSFUL)
222 status &= PCI_STATUS_ERROR_BITS;
224 pci_write_config_word(pdev, PCI_STATUS, status);
228 EXPORT_SYMBOL_GPL(pci_status_get_and_clear_errors);
230 #ifdef CONFIG_HAS_IOMEM
231 static void __iomem *__pci_ioremap_resource(struct pci_dev *pdev, int bar,
234 struct resource *res = &pdev->resource[bar];
235 resource_size_t start = res->start;
236 resource_size_t size = resource_size(res);
239 * Make sure the BAR is actually a memory resource, not an IO resource
241 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
242 pci_err(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
247 return ioremap_wc(start, size);
249 return ioremap(start, size);
252 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
254 return __pci_ioremap_resource(pdev, bar, false);
256 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
258 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
260 return __pci_ioremap_resource(pdev, bar, true);
262 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
266 * pci_dev_str_match_path - test if a path string matches a device
267 * @dev: the PCI device to test
268 * @path: string to match the device against
269 * @endptr: pointer to the string after the match
271 * Test if a string (typically from a kernel parameter) formatted as a
272 * path of device/function addresses matches a PCI device. The string must
275 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
277 * A path for a device can be obtained using 'lspci -t'. Using a path
278 * is more robust against bus renumbering than using only a single bus,
279 * device and function address.
281 * Returns 1 if the string matches the device, 0 if it does not and
282 * a negative error code if it fails to parse the string.
284 static int pci_dev_str_match_path(struct pci_dev *dev, const char *path,
288 unsigned int seg, bus, slot, func;
292 *endptr = strchrnul(path, ';');
294 wpath = kmemdup_nul(path, *endptr - path, GFP_ATOMIC);
299 p = strrchr(wpath, '/');
302 ret = sscanf(p, "/%x.%x%c", &slot, &func, &end);
308 if (dev->devfn != PCI_DEVFN(slot, func)) {
314 * Note: we don't need to get a reference to the upstream
315 * bridge because we hold a reference to the top level
316 * device which should hold a reference to the bridge,
319 dev = pci_upstream_bridge(dev);
328 ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot,
332 ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end);
339 ret = (seg == pci_domain_nr(dev->bus) &&
340 bus == dev->bus->number &&
341 dev->devfn == PCI_DEVFN(slot, func));
349 * pci_dev_str_match - test if a string matches a device
350 * @dev: the PCI device to test
351 * @p: string to match the device against
352 * @endptr: pointer to the string after the match
354 * Test if a string (typically from a kernel parameter) matches a specified
355 * PCI device. The string may be of one of the following formats:
357 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
358 * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
360 * The first format specifies a PCI bus/device/function address which
361 * may change if new hardware is inserted, if motherboard firmware changes,
362 * or due to changes caused in kernel parameters. If the domain is
363 * left unspecified, it is taken to be 0. In order to be robust against
364 * bus renumbering issues, a path of PCI device/function numbers may be used
365 * to address the specific device. The path for a device can be determined
366 * through the use of 'lspci -t'.
368 * The second format matches devices using IDs in the configuration
369 * space which may match multiple devices in the system. A value of 0
370 * for any field will match all devices. (Note: this differs from
371 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
372 * legacy reasons and convenience so users don't have to specify
373 * FFFFFFFFs on the command line.)
375 * Returns 1 if the string matches the device, 0 if it does not and
376 * a negative error code if the string cannot be parsed.
378 static int pci_dev_str_match(struct pci_dev *dev, const char *p,
383 unsigned short vendor, device, subsystem_vendor, subsystem_device;
385 if (strncmp(p, "pci:", 4) == 0) {
386 /* PCI vendor/device (subvendor/subdevice) IDs are specified */
388 ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device,
389 &subsystem_vendor, &subsystem_device, &count);
391 ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count);
395 subsystem_vendor = 0;
396 subsystem_device = 0;
401 if ((!vendor || vendor == dev->vendor) &&
402 (!device || device == dev->device) &&
403 (!subsystem_vendor ||
404 subsystem_vendor == dev->subsystem_vendor) &&
405 (!subsystem_device ||
406 subsystem_device == dev->subsystem_device))
410 * PCI Bus, Device, Function IDs are specified
411 * (optionally, may include a path of devfns following it)
413 ret = pci_dev_str_match_path(dev, p, &p);
428 static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
429 u8 pos, int cap, int *ttl)
434 pci_bus_read_config_byte(bus, devfn, pos, &pos);
440 pci_bus_read_config_word(bus, devfn, pos, &ent);
452 static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
455 int ttl = PCI_FIND_CAP_TTL;
457 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
460 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
462 return __pci_find_next_cap(dev->bus, dev->devfn,
463 pos + PCI_CAP_LIST_NEXT, cap);
465 EXPORT_SYMBOL_GPL(pci_find_next_capability);
467 static u8 __pci_bus_find_cap_start(struct pci_bus *bus,
468 unsigned int devfn, u8 hdr_type)
472 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
473 if (!(status & PCI_STATUS_CAP_LIST))
477 case PCI_HEADER_TYPE_NORMAL:
478 case PCI_HEADER_TYPE_BRIDGE:
479 return PCI_CAPABILITY_LIST;
480 case PCI_HEADER_TYPE_CARDBUS:
481 return PCI_CB_CAPABILITY_LIST;
488 * pci_find_capability - query for devices' capabilities
489 * @dev: PCI device to query
490 * @cap: capability code
492 * Tell if a device supports a given PCI capability.
493 * Returns the address of the requested capability structure within the
494 * device's PCI configuration space or 0 in case the device does not
495 * support it. Possible values for @cap include:
497 * %PCI_CAP_ID_PM Power Management
498 * %PCI_CAP_ID_AGP Accelerated Graphics Port
499 * %PCI_CAP_ID_VPD Vital Product Data
500 * %PCI_CAP_ID_SLOTID Slot Identification
501 * %PCI_CAP_ID_MSI Message Signalled Interrupts
502 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
503 * %PCI_CAP_ID_PCIX PCI-X
504 * %PCI_CAP_ID_EXP PCI Express
506 u8 pci_find_capability(struct pci_dev *dev, int cap)
510 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
512 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
516 EXPORT_SYMBOL(pci_find_capability);
519 * pci_bus_find_capability - query for devices' capabilities
520 * @bus: the PCI bus to query
521 * @devfn: PCI device to query
522 * @cap: capability code
524 * Like pci_find_capability() but works for PCI devices that do not have a
525 * pci_dev structure set up yet.
527 * Returns the address of the requested capability structure within the
528 * device's PCI configuration space or 0 in case the device does not
531 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
535 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
537 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & PCI_HEADER_TYPE_MASK);
539 pos = __pci_find_next_cap(bus, devfn, pos, cap);
543 EXPORT_SYMBOL(pci_bus_find_capability);
546 * pci_find_next_ext_capability - Find an extended capability
547 * @dev: PCI device to query
548 * @start: address at which to start looking (0 to start at beginning of list)
549 * @cap: capability code
551 * Returns the address of the next matching extended capability structure
552 * within the device's PCI configuration space or 0 if the device does
553 * not support it. Some capabilities can occur several times, e.g., the
554 * vendor-specific capability, and this provides a way to find them all.
556 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap)
560 u16 pos = PCI_CFG_SPACE_SIZE;
562 /* minimum 8 bytes per capability */
563 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
565 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
571 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
575 * If we have no capabilities, this is indicated by cap ID,
576 * cap version and next pointer all being 0.
582 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
585 pos = PCI_EXT_CAP_NEXT(header);
586 if (pos < PCI_CFG_SPACE_SIZE)
589 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
595 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
598 * pci_find_ext_capability - Find an extended capability
599 * @dev: PCI device to query
600 * @cap: capability code
602 * Returns the address of the requested extended capability structure
603 * within the device's PCI configuration space or 0 if the device does
604 * not support it. Possible values for @cap include:
606 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
607 * %PCI_EXT_CAP_ID_VC Virtual Channel
608 * %PCI_EXT_CAP_ID_DSN Device Serial Number
609 * %PCI_EXT_CAP_ID_PWR Power Budgeting
611 u16 pci_find_ext_capability(struct pci_dev *dev, int cap)
613 return pci_find_next_ext_capability(dev, 0, cap);
615 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
618 * pci_get_dsn - Read and return the 8-byte Device Serial Number
619 * @dev: PCI device to query
621 * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
624 * Returns the DSN, or zero if the capability does not exist.
626 u64 pci_get_dsn(struct pci_dev *dev)
632 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DSN);
637 * The Device Serial Number is two dwords offset 4 bytes from the
638 * capability position. The specification says that the first dword is
639 * the lower half, and the second dword is the upper half.
642 pci_read_config_dword(dev, pos, &dword);
644 pci_read_config_dword(dev, pos + 4, &dword);
645 dsn |= ((u64)dword) << 32;
649 EXPORT_SYMBOL_GPL(pci_get_dsn);
651 static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
653 int rc, ttl = PCI_FIND_CAP_TTL;
656 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
657 mask = HT_3BIT_CAP_MASK;
659 mask = HT_5BIT_CAP_MASK;
661 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
662 PCI_CAP_ID_HT, &ttl);
664 rc = pci_read_config_byte(dev, pos + 3, &cap);
665 if (rc != PCIBIOS_SUCCESSFUL)
668 if ((cap & mask) == ht_cap)
671 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
672 pos + PCI_CAP_LIST_NEXT,
673 PCI_CAP_ID_HT, &ttl);
680 * pci_find_next_ht_capability - query a device's HyperTransport capabilities
681 * @dev: PCI device to query
682 * @pos: Position from which to continue searching
683 * @ht_cap: HyperTransport capability code
685 * To be used in conjunction with pci_find_ht_capability() to search for
686 * all capabilities matching @ht_cap. @pos should always be a value returned
687 * from pci_find_ht_capability().
689 * NB. To be 100% safe against broken PCI devices, the caller should take
690 * steps to avoid an infinite loop.
692 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap)
694 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
696 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
699 * pci_find_ht_capability - query a device's HyperTransport capabilities
700 * @dev: PCI device to query
701 * @ht_cap: HyperTransport capability code
703 * Tell if a device supports a given HyperTransport capability.
704 * Returns an address within the device's PCI configuration space
705 * or 0 in case the device does not support the request capability.
706 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
707 * which has a HyperTransport capability matching @ht_cap.
709 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
713 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
715 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
719 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
722 * pci_find_vsec_capability - Find a vendor-specific extended capability
723 * @dev: PCI device to query
724 * @vendor: Vendor ID for which capability is defined
725 * @cap: Vendor-specific capability ID
727 * If @dev has Vendor ID @vendor, search for a VSEC capability with
728 * VSEC ID @cap. If found, return the capability offset in
729 * config space; otherwise return 0.
731 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap)
737 if (vendor != dev->vendor)
740 while ((vsec = pci_find_next_ext_capability(dev, vsec,
741 PCI_EXT_CAP_ID_VNDR))) {
742 ret = pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header);
743 if (ret != PCIBIOS_SUCCESSFUL)
746 if (PCI_VNDR_HEADER_ID(header) == cap)
752 EXPORT_SYMBOL_GPL(pci_find_vsec_capability);
755 * pci_find_dvsec_capability - Find DVSEC for vendor
756 * @dev: PCI device to query
757 * @vendor: Vendor ID to match for the DVSEC
758 * @dvsec: Designated Vendor-specific capability ID
760 * If DVSEC has Vendor ID @vendor and DVSEC ID @dvsec return the capability
761 * offset in config space; otherwise return 0.
763 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec)
767 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DVSEC);
774 pci_read_config_word(dev, pos + PCI_DVSEC_HEADER1, &v);
775 pci_read_config_word(dev, pos + PCI_DVSEC_HEADER2, &id);
776 if (vendor == v && dvsec == id)
779 pos = pci_find_next_ext_capability(dev, pos, PCI_EXT_CAP_ID_DVSEC);
784 EXPORT_SYMBOL_GPL(pci_find_dvsec_capability);
787 * pci_find_parent_resource - return resource region of parent bus of given
789 * @dev: PCI device structure contains resources to be searched
790 * @res: child resource record for which parent is sought
792 * For given resource region of given device, return the resource region of
793 * parent bus the given region is contained in.
795 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
796 struct resource *res)
798 const struct pci_bus *bus = dev->bus;
801 pci_bus_for_each_resource(bus, r) {
804 if (resource_contains(r, res)) {
807 * If the window is prefetchable but the BAR is
808 * not, the allocator made a mistake.
810 if (r->flags & IORESOURCE_PREFETCH &&
811 !(res->flags & IORESOURCE_PREFETCH))
815 * If we're below a transparent bridge, there may
816 * be both a positively-decoded aperture and a
817 * subtractively-decoded region that contain the BAR.
818 * We want the positively-decoded one, so this depends
819 * on pci_bus_for_each_resource() giving us those
827 EXPORT_SYMBOL(pci_find_parent_resource);
830 * pci_find_resource - Return matching PCI device resource
831 * @dev: PCI device to query
832 * @res: Resource to look for
834 * Goes over standard PCI resources (BARs) and checks if the given resource
835 * is partially or fully contained in any of them. In that case the
836 * matching resource is returned, %NULL otherwise.
838 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
842 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
843 struct resource *r = &dev->resource[i];
845 if (r->start && resource_contains(r, res))
851 EXPORT_SYMBOL(pci_find_resource);
854 * pci_resource_name - Return the name of the PCI resource
855 * @dev: PCI device to query
856 * @i: index of the resource
858 * Return the standard PCI resource (BAR) name according to their index.
860 const char *pci_resource_name(struct pci_dev *dev, unsigned int i)
862 static const char * const bar_name[] = {
870 #ifdef CONFIG_PCI_IOV
878 "bridge window", /* "io" included in %pR */
879 "bridge window", /* "mem" included in %pR */
880 "bridge window", /* "mem pref" included in %pR */
882 static const char * const cardbus_name[] = {
889 #ifdef CONFIG_PCI_IOV
897 "CardBus bridge window 0", /* I/O */
898 "CardBus bridge window 1", /* I/O */
899 "CardBus bridge window 0", /* mem */
900 "CardBus bridge window 1", /* mem */
903 if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS &&
904 i < ARRAY_SIZE(cardbus_name))
905 return cardbus_name[i];
907 if (i < ARRAY_SIZE(bar_name))
914 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
915 * @dev: the PCI device to operate on
916 * @pos: config space offset of status word
917 * @mask: mask of bit(s) to care about in status word
919 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
921 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
925 /* Wait for Transaction Pending bit clean */
926 for (i = 0; i < 4; i++) {
929 msleep((1 << (i - 1)) * 100);
931 pci_read_config_word(dev, pos, &status);
932 if (!(status & mask))
939 static int pci_acs_enable;
942 * pci_request_acs - ask for ACS to be enabled if supported
944 void pci_request_acs(void)
949 static const char *disable_acs_redir_param;
952 * pci_disable_acs_redir - disable ACS redirect capabilities
953 * @dev: the PCI device
955 * For only devices specified in the disable_acs_redir parameter.
957 static void pci_disable_acs_redir(struct pci_dev *dev)
964 if (!disable_acs_redir_param)
967 p = disable_acs_redir_param;
969 ret = pci_dev_str_match(dev, p, &p);
971 pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
972 disable_acs_redir_param);
975 } else if (ret == 1) {
980 if (*p != ';' && *p != ',') {
981 /* End of param or invalid format */
990 if (!pci_dev_specific_disable_acs_redir(dev))
995 pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
999 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
1001 /* P2P Request & Completion Redirect */
1002 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
1004 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
1006 pci_info(dev, "disabled ACS redirect\n");
1010 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
1011 * @dev: the PCI device
1013 static void pci_std_enable_acs(struct pci_dev *dev)
1023 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
1024 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
1026 /* Source Validation */
1027 ctrl |= (cap & PCI_ACS_SV);
1029 /* P2P Request Redirect */
1030 ctrl |= (cap & PCI_ACS_RR);
1032 /* P2P Completion Redirect */
1033 ctrl |= (cap & PCI_ACS_CR);
1035 /* Upstream Forwarding */
1036 ctrl |= (cap & PCI_ACS_UF);
1038 /* Enable Translation Blocking for external devices and noats */
1039 if (pci_ats_disabled() || dev->external_facing || dev->untrusted)
1040 ctrl |= (cap & PCI_ACS_TB);
1042 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
1046 * pci_enable_acs - enable ACS if hardware support it
1047 * @dev: the PCI device
1049 static void pci_enable_acs(struct pci_dev *dev)
1051 if (!pci_acs_enable)
1052 goto disable_acs_redir;
1054 if (!pci_dev_specific_enable_acs(dev))
1055 goto disable_acs_redir;
1057 pci_std_enable_acs(dev);
1061 * Note: pci_disable_acs_redir() must be called even if ACS was not
1062 * enabled by the kernel because it may have been enabled by
1063 * platform firmware. So if we are told to disable it, we should
1064 * always disable it after setting the kernel's default
1067 pci_disable_acs_redir(dev);
1071 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
1072 * @dev: PCI device to have its BARs restored
1074 * Restore the BAR values for a given device, so as to make it
1075 * accessible by its driver.
1077 static void pci_restore_bars(struct pci_dev *dev)
1081 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
1082 pci_update_resource(dev, i);
1085 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
1087 if (pci_use_mid_pm())
1090 return acpi_pci_power_manageable(dev);
1093 static inline int platform_pci_set_power_state(struct pci_dev *dev,
1096 if (pci_use_mid_pm())
1097 return mid_pci_set_power_state(dev, t);
1099 return acpi_pci_set_power_state(dev, t);
1102 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
1104 if (pci_use_mid_pm())
1105 return mid_pci_get_power_state(dev);
1107 return acpi_pci_get_power_state(dev);
1110 static inline void platform_pci_refresh_power_state(struct pci_dev *dev)
1112 if (!pci_use_mid_pm())
1113 acpi_pci_refresh_power_state(dev);
1116 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
1118 if (pci_use_mid_pm())
1119 return PCI_POWER_ERROR;
1121 return acpi_pci_choose_state(dev);
1124 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
1126 if (pci_use_mid_pm())
1127 return PCI_POWER_ERROR;
1129 return acpi_pci_wakeup(dev, enable);
1132 static inline bool platform_pci_need_resume(struct pci_dev *dev)
1134 if (pci_use_mid_pm())
1137 return acpi_pci_need_resume(dev);
1140 static inline bool platform_pci_bridge_d3(struct pci_dev *dev)
1142 if (pci_use_mid_pm())
1145 return acpi_pci_bridge_d3(dev);
1149 * pci_update_current_state - Read power state of given device and cache it
1150 * @dev: PCI device to handle.
1151 * @state: State to cache in case the device doesn't have the PM capability
1153 * The power state is read from the PMCSR register, which however is
1154 * inaccessible in D3cold. The platform firmware is therefore queried first
1155 * to detect accessibility of the register. In case the platform firmware
1156 * reports an incorrect state or the device isn't power manageable by the
1157 * platform at all, we try to detect D3cold by testing accessibility of the
1158 * vendor ID in config space.
1160 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
1162 if (platform_pci_get_power_state(dev) == PCI_D3cold) {
1163 dev->current_state = PCI_D3cold;
1164 } else if (dev->pm_cap) {
1167 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1168 if (PCI_POSSIBLE_ERROR(pmcsr)) {
1169 dev->current_state = PCI_D3cold;
1172 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1174 dev->current_state = state;
1179 * pci_refresh_power_state - Refresh the given device's power state data
1180 * @dev: Target PCI device.
1182 * Ask the platform to refresh the devices power state information and invoke
1183 * pci_update_current_state() to update its current PCI power state.
1185 void pci_refresh_power_state(struct pci_dev *dev)
1187 platform_pci_refresh_power_state(dev);
1188 pci_update_current_state(dev, dev->current_state);
1192 * pci_platform_power_transition - Use platform to change device power state
1193 * @dev: PCI device to handle.
1194 * @state: State to put the device into.
1196 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
1200 error = platform_pci_set_power_state(dev, state);
1202 pci_update_current_state(dev, state);
1203 else if (!dev->pm_cap) /* Fall back to PCI_D0 */
1204 dev->current_state = PCI_D0;
1208 EXPORT_SYMBOL_GPL(pci_platform_power_transition);
1210 static int pci_resume_one(struct pci_dev *pci_dev, void *ign)
1212 pm_request_resume(&pci_dev->dev);
1217 * pci_resume_bus - Walk given bus and runtime resume devices on it
1218 * @bus: Top bus of the subtree to walk.
1220 void pci_resume_bus(struct pci_bus *bus)
1223 pci_walk_bus(bus, pci_resume_one, NULL);
1226 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
1229 bool retrain = false;
1230 struct pci_dev *bridge;
1232 if (pci_is_pcie(dev)) {
1233 bridge = pci_upstream_bridge(dev);
1239 * After reset, the device should not silently discard config
1240 * requests, but it may still indicate that it needs more time by
1241 * responding to them with CRS completions. The Root Port will
1242 * generally synthesize ~0 (PCI_ERROR_RESPONSE) data to complete
1243 * the read (except when CRS SV is enabled and the read was for the
1244 * Vendor ID; in that case it synthesizes 0x0001 data).
1246 * Wait for the device to return a non-CRS completion. Read the
1247 * Command register instead of Vendor ID so we don't have to
1248 * contend with the CRS SV value.
1253 pci_read_config_dword(dev, PCI_COMMAND, &id);
1254 if (!PCI_POSSIBLE_ERROR(id))
1257 if (delay > timeout) {
1258 pci_warn(dev, "not ready %dms after %s; giving up\n",
1259 delay - 1, reset_type);
1263 if (delay > PCI_RESET_WAIT) {
1266 if (pcie_failed_link_retrain(bridge)) {
1271 pci_info(dev, "not ready %dms after %s; waiting\n",
1272 delay - 1, reset_type);
1279 if (delay > PCI_RESET_WAIT)
1280 pci_info(dev, "ready %dms after %s\n", delay - 1,
1283 pci_dbg(dev, "ready %dms after %s\n", delay - 1,
1290 * pci_power_up - Put the given device into D0
1291 * @dev: PCI device to power up
1293 * On success, return 0 or 1, depending on whether or not it is necessary to
1294 * restore the device's BARs subsequently (1 is returned in that case).
1296 * On failure, return a negative error code. Always return failure if @dev
1297 * lacks a Power Management Capability, even if the platform was able to
1298 * put the device in D0 via non-PCI means.
1300 int pci_power_up(struct pci_dev *dev)
1306 platform_pci_set_power_state(dev, PCI_D0);
1309 state = platform_pci_get_power_state(dev);
1310 if (state == PCI_UNKNOWN)
1311 dev->current_state = PCI_D0;
1313 dev->current_state = state;
1318 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1319 if (PCI_POSSIBLE_ERROR(pmcsr)) {
1320 pci_err(dev, "Unable to change power state from %s to D0, device inaccessible\n",
1321 pci_power_name(dev->current_state));
1322 dev->current_state = PCI_D3cold;
1326 state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1328 need_restore = (state == PCI_D3hot || dev->current_state >= PCI_D3hot) &&
1329 !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET);
1331 if (state == PCI_D0)
1335 * Force the entire word to 0. This doesn't affect PME_Status, disables
1336 * PME_En, and sets PowerState to 0.
1338 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, 0);
1340 /* Mandatory transition delays; see PCI PM 1.2. */
1341 if (state == PCI_D3hot)
1342 pci_dev_d3_sleep(dev);
1343 else if (state == PCI_D2)
1344 udelay(PCI_PM_D2_DELAY);
1347 dev->current_state = PCI_D0;
1355 * pci_set_full_power_state - Put a PCI device into D0 and update its state
1356 * @dev: PCI device to power up
1357 * @locked: whether pci_bus_sem is held
1359 * Call pci_power_up() to put @dev into D0, read from its PCI_PM_CTRL register
1360 * to confirm the state change, restore its BARs if they might be lost and
1361 * reconfigure ASPM in accordance with the new power state.
1363 * If pci_restore_state() is going to be called right after a power state change
1364 * to D0, it is more efficient to use pci_power_up() directly instead of this
1367 static int pci_set_full_power_state(struct pci_dev *dev, bool locked)
1372 ret = pci_power_up(dev);
1374 if (dev->current_state == PCI_D0)
1380 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1381 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1382 if (dev->current_state != PCI_D0) {
1383 pci_info_ratelimited(dev, "Refused to change power state from %s to D0\n",
1384 pci_power_name(dev->current_state));
1385 } else if (ret > 0) {
1387 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
1388 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
1389 * from D3hot to D0 _may_ perform an internal reset, thereby
1390 * going to "D0 Uninitialized" rather than "D0 Initialized".
1391 * For example, at least some versions of the 3c905B and the
1392 * 3c556B exhibit this behaviour.
1394 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
1395 * devices in a D3hot state at boot. Consequently, we need to
1396 * restore at least the BARs so that the device will be
1397 * accessible to its driver.
1399 pci_restore_bars(dev);
1403 pcie_aspm_pm_state_change(dev->bus->self, locked);
1409 * __pci_dev_set_current_state - Set current state of a PCI device
1410 * @dev: Device to handle
1411 * @data: pointer to state to be set
1413 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
1415 pci_power_t state = *(pci_power_t *)data;
1417 dev->current_state = state;
1422 * pci_bus_set_current_state - Walk given bus and set current state of devices
1423 * @bus: Top bus of the subtree to walk.
1424 * @state: state to be set
1426 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
1429 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
1432 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state, bool locked)
1438 pci_walk_bus_locked(bus, __pci_dev_set_current_state, &state);
1440 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
1444 * pci_set_low_power_state - Put a PCI device into a low-power state.
1445 * @dev: PCI device to handle.
1446 * @state: PCI power state (D1, D2, D3hot) to put the device into.
1447 * @locked: whether pci_bus_sem is held
1449 * Use the device's PCI_PM_CTRL register to put it into a low-power state.
1452 * -EINVAL if the requested state is invalid.
1453 * -EIO if device does not support PCI PM or its PM capabilities register has a
1454 * wrong version, or device doesn't support the requested state.
1455 * 0 if device already is in the requested state.
1456 * 0 if device's power state has been successfully changed.
1458 static int pci_set_low_power_state(struct pci_dev *dev, pci_power_t state, bool locked)
1466 * Validate transition: We can enter D0 from any state, but if
1467 * we're already in a low-power state, we can only go deeper. E.g.,
1468 * we can go from D1 to D3, but we can't go directly from D3 to D1;
1469 * we'd have to go from D3 to D0, then to D1.
1471 if (dev->current_state <= PCI_D3cold && dev->current_state > state) {
1472 pci_dbg(dev, "Invalid power transition (from %s to %s)\n",
1473 pci_power_name(dev->current_state),
1474 pci_power_name(state));
1478 /* Check if this device supports the desired state */
1479 if ((state == PCI_D1 && !dev->d1_support)
1480 || (state == PCI_D2 && !dev->d2_support))
1483 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1484 if (PCI_POSSIBLE_ERROR(pmcsr)) {
1485 pci_err(dev, "Unable to change power state from %s to %s, device inaccessible\n",
1486 pci_power_name(dev->current_state),
1487 pci_power_name(state));
1488 dev->current_state = PCI_D3cold;
1492 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
1495 /* Enter specified state */
1496 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1498 /* Mandatory power management transition delays; see PCI PM 1.2. */
1499 if (state == PCI_D3hot)
1500 pci_dev_d3_sleep(dev);
1501 else if (state == PCI_D2)
1502 udelay(PCI_PM_D2_DELAY);
1504 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1505 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1506 if (dev->current_state != state)
1507 pci_info_ratelimited(dev, "Refused to change power state from %s to %s\n",
1508 pci_power_name(dev->current_state),
1509 pci_power_name(state));
1512 pcie_aspm_pm_state_change(dev->bus->self, locked);
1517 static int __pci_set_power_state(struct pci_dev *dev, pci_power_t state, bool locked)
1521 /* Bound the state we're entering */
1522 if (state > PCI_D3cold)
1524 else if (state < PCI_D0)
1526 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
1529 * If the device or the parent bridge do not support PCI
1530 * PM, ignore the request if we're doing anything other
1531 * than putting it into D0 (which would only happen on
1536 /* Check if we're already there */
1537 if (dev->current_state == state)
1540 if (state == PCI_D0)
1541 return pci_set_full_power_state(dev, locked);
1544 * This device is quirked not to be put into D3, so don't put it in
1547 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
1550 if (state == PCI_D3cold) {
1552 * To put the device in D3cold, put it into D3hot in the native
1553 * way, then put it into D3cold using platform ops.
1555 error = pci_set_low_power_state(dev, PCI_D3hot, locked);
1557 if (pci_platform_power_transition(dev, PCI_D3cold))
1560 /* Powering off a bridge may power off the whole hierarchy */
1561 if (dev->current_state == PCI_D3cold)
1562 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold, locked);
1564 error = pci_set_low_power_state(dev, state, locked);
1566 if (pci_platform_power_transition(dev, state))
1574 * pci_set_power_state - Set the power state of a PCI device
1575 * @dev: PCI device to handle.
1576 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1578 * Transition a device to a new power state, using the platform firmware and/or
1579 * the device's PCI PM registers.
1582 * -EINVAL if the requested state is invalid.
1583 * -EIO if device does not support PCI PM or its PM capabilities register has a
1584 * wrong version, or device doesn't support the requested state.
1585 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1586 * 0 if device already is in the requested state.
1587 * 0 if the transition is to D3 but D3 is not supported.
1588 * 0 if device's power state has been successfully changed.
1590 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1592 return __pci_set_power_state(dev, state, false);
1594 EXPORT_SYMBOL(pci_set_power_state);
1596 int pci_set_power_state_locked(struct pci_dev *dev, pci_power_t state)
1598 lockdep_assert_held(&pci_bus_sem);
1600 return __pci_set_power_state(dev, state, true);
1602 EXPORT_SYMBOL(pci_set_power_state_locked);
1604 #define PCI_EXP_SAVE_REGS 7
1606 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
1607 u16 cap, bool extended)
1609 struct pci_cap_saved_state *tmp;
1611 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
1612 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
1618 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1620 return _pci_find_saved_cap(dev, cap, false);
1623 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1625 return _pci_find_saved_cap(dev, cap, true);
1628 static int pci_save_pcie_state(struct pci_dev *dev)
1631 struct pci_cap_saved_state *save_state;
1634 if (!pci_is_pcie(dev))
1637 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1639 pci_err(dev, "buffer not found in %s\n", __func__);
1643 cap = (u16 *)&save_state->cap.data[0];
1644 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1645 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1646 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1647 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1648 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1649 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1650 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1655 void pci_bridge_reconfigure_ltr(struct pci_dev *dev)
1657 #ifdef CONFIG_PCIEASPM
1658 struct pci_dev *bridge;
1661 bridge = pci_upstream_bridge(dev);
1662 if (bridge && bridge->ltr_path) {
1663 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl);
1664 if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) {
1665 pci_dbg(bridge, "re-enabling LTR\n");
1666 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
1667 PCI_EXP_DEVCTL2_LTR_EN);
1673 static void pci_restore_pcie_state(struct pci_dev *dev)
1676 struct pci_cap_saved_state *save_state;
1679 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1684 * Downstream ports reset the LTR enable bit when link goes down.
1685 * Check and re-configure the bit here before restoring device.
1686 * PCIe r5.0, sec 7.5.3.16.
1688 pci_bridge_reconfigure_ltr(dev);
1690 cap = (u16 *)&save_state->cap.data[0];
1691 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1692 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1693 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1694 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1695 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1696 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1697 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1700 static int pci_save_pcix_state(struct pci_dev *dev)
1703 struct pci_cap_saved_state *save_state;
1705 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1709 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1711 pci_err(dev, "buffer not found in %s\n", __func__);
1715 pci_read_config_word(dev, pos + PCI_X_CMD,
1716 (u16 *)save_state->cap.data);
1721 static void pci_restore_pcix_state(struct pci_dev *dev)
1724 struct pci_cap_saved_state *save_state;
1727 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1728 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1729 if (!save_state || !pos)
1731 cap = (u16 *)&save_state->cap.data[0];
1733 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1736 static void pci_save_ltr_state(struct pci_dev *dev)
1739 struct pci_cap_saved_state *save_state;
1742 if (!pci_is_pcie(dev))
1745 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1749 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1751 pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
1755 /* Some broken devices only support dword access to LTR */
1756 cap = &save_state->cap.data[0];
1757 pci_read_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap);
1760 static void pci_restore_ltr_state(struct pci_dev *dev)
1762 struct pci_cap_saved_state *save_state;
1766 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1767 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1768 if (!save_state || !ltr)
1771 /* Some broken devices only support dword access to LTR */
1772 cap = &save_state->cap.data[0];
1773 pci_write_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap);
1777 * pci_save_state - save the PCI configuration space of a device before
1779 * @dev: PCI device that we're dealing with
1781 int pci_save_state(struct pci_dev *dev)
1784 /* XXX: 100% dword access ok here? */
1785 for (i = 0; i < 16; i++) {
1786 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1787 pci_dbg(dev, "save config %#04x: %#010x\n",
1788 i * 4, dev->saved_config_space[i]);
1790 dev->state_saved = true;
1792 i = pci_save_pcie_state(dev);
1796 i = pci_save_pcix_state(dev);
1800 pci_save_ltr_state(dev);
1801 pci_save_dpc_state(dev);
1802 pci_save_aer_state(dev);
1803 pci_save_ptm_state(dev);
1804 return pci_save_vc_state(dev);
1806 EXPORT_SYMBOL(pci_save_state);
1808 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1809 u32 saved_val, int retry, bool force)
1813 pci_read_config_dword(pdev, offset, &val);
1814 if (!force && val == saved_val)
1818 pci_dbg(pdev, "restore config %#04x: %#010x -> %#010x\n",
1819 offset, val, saved_val);
1820 pci_write_config_dword(pdev, offset, saved_val);
1824 pci_read_config_dword(pdev, offset, &val);
1825 if (val == saved_val)
1832 static void pci_restore_config_space_range(struct pci_dev *pdev,
1833 int start, int end, int retry,
1838 for (index = end; index >= start; index--)
1839 pci_restore_config_dword(pdev, 4 * index,
1840 pdev->saved_config_space[index],
1844 static void pci_restore_config_space(struct pci_dev *pdev)
1846 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1847 pci_restore_config_space_range(pdev, 10, 15, 0, false);
1848 /* Restore BARs before the command register. */
1849 pci_restore_config_space_range(pdev, 4, 9, 10, false);
1850 pci_restore_config_space_range(pdev, 0, 3, 0, false);
1851 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1852 pci_restore_config_space_range(pdev, 12, 15, 0, false);
1855 * Force rewriting of prefetch registers to avoid S3 resume
1856 * issues on Intel PCI bridges that occur when these
1857 * registers are not explicitly written.
1859 pci_restore_config_space_range(pdev, 9, 11, 0, true);
1860 pci_restore_config_space_range(pdev, 0, 8, 0, false);
1862 pci_restore_config_space_range(pdev, 0, 15, 0, false);
1866 static void pci_restore_rebar_state(struct pci_dev *pdev)
1868 unsigned int pos, nbars, i;
1871 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
1875 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1876 nbars = FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl);
1878 for (i = 0; i < nbars; i++, pos += 8) {
1879 struct resource *res;
1882 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1883 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
1884 res = pdev->resource + bar_idx;
1885 size = pci_rebar_bytes_to_size(resource_size(res));
1886 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
1887 ctrl |= FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size);
1888 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
1893 * pci_restore_state - Restore the saved state of a PCI device
1894 * @dev: PCI device that we're dealing with
1896 void pci_restore_state(struct pci_dev *dev)
1898 if (!dev->state_saved)
1902 * Restore max latencies (in the LTR capability) before enabling
1903 * LTR itself (in the PCIe capability).
1905 pci_restore_ltr_state(dev);
1907 pci_restore_pcie_state(dev);
1908 pci_restore_pasid_state(dev);
1909 pci_restore_pri_state(dev);
1910 pci_restore_ats_state(dev);
1911 pci_restore_vc_state(dev);
1912 pci_restore_rebar_state(dev);
1913 pci_restore_dpc_state(dev);
1914 pci_restore_ptm_state(dev);
1916 pci_aer_clear_status(dev);
1917 pci_restore_aer_state(dev);
1919 pci_restore_config_space(dev);
1921 pci_restore_pcix_state(dev);
1922 pci_restore_msi_state(dev);
1924 /* Restore ACS and IOV configuration state */
1925 pci_enable_acs(dev);
1926 pci_restore_iov_state(dev);
1928 dev->state_saved = false;
1930 EXPORT_SYMBOL(pci_restore_state);
1932 struct pci_saved_state {
1933 u32 config_space[16];
1934 struct pci_cap_saved_data cap[];
1938 * pci_store_saved_state - Allocate and return an opaque struct containing
1939 * the device saved state.
1940 * @dev: PCI device that we're dealing with
1942 * Return NULL if no state or error.
1944 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1946 struct pci_saved_state *state;
1947 struct pci_cap_saved_state *tmp;
1948 struct pci_cap_saved_data *cap;
1951 if (!dev->state_saved)
1954 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1956 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1957 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1959 state = kzalloc(size, GFP_KERNEL);
1963 memcpy(state->config_space, dev->saved_config_space,
1964 sizeof(state->config_space));
1967 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1968 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1969 memcpy(cap, &tmp->cap, len);
1970 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1972 /* Empty cap_save terminates list */
1976 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1979 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1980 * @dev: PCI device that we're dealing with
1981 * @state: Saved state returned from pci_store_saved_state()
1983 int pci_load_saved_state(struct pci_dev *dev,
1984 struct pci_saved_state *state)
1986 struct pci_cap_saved_data *cap;
1988 dev->state_saved = false;
1993 memcpy(dev->saved_config_space, state->config_space,
1994 sizeof(state->config_space));
1998 struct pci_cap_saved_state *tmp;
2000 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
2001 if (!tmp || tmp->cap.size != cap->size)
2004 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
2005 cap = (struct pci_cap_saved_data *)((u8 *)cap +
2006 sizeof(struct pci_cap_saved_data) + cap->size);
2009 dev->state_saved = true;
2012 EXPORT_SYMBOL_GPL(pci_load_saved_state);
2015 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
2016 * and free the memory allocated for it.
2017 * @dev: PCI device that we're dealing with
2018 * @state: Pointer to saved state returned from pci_store_saved_state()
2020 int pci_load_and_free_saved_state(struct pci_dev *dev,
2021 struct pci_saved_state **state)
2023 int ret = pci_load_saved_state(dev, *state);
2028 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
2030 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
2032 return pci_enable_resources(dev, bars);
2035 static int do_pci_enable_device(struct pci_dev *dev, int bars)
2038 struct pci_dev *bridge;
2042 err = pci_set_power_state(dev, PCI_D0);
2043 if (err < 0 && err != -EIO)
2046 bridge = pci_upstream_bridge(dev);
2048 pcie_aspm_powersave_config_link(bridge);
2050 err = pcibios_enable_device(dev, bars);
2053 pci_fixup_device(pci_fixup_enable, dev);
2055 if (dev->msi_enabled || dev->msix_enabled)
2058 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
2060 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2061 if (cmd & PCI_COMMAND_INTX_DISABLE)
2062 pci_write_config_word(dev, PCI_COMMAND,
2063 cmd & ~PCI_COMMAND_INTX_DISABLE);
2070 * pci_reenable_device - Resume abandoned device
2071 * @dev: PCI device to be resumed
2073 * NOTE: This function is a backend of pci_default_resume() and is not supposed
2074 * to be called by normal code, write proper resume handler and use it instead.
2076 int pci_reenable_device(struct pci_dev *dev)
2078 if (pci_is_enabled(dev))
2079 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
2082 EXPORT_SYMBOL(pci_reenable_device);
2084 static void pci_enable_bridge(struct pci_dev *dev)
2086 struct pci_dev *bridge;
2089 bridge = pci_upstream_bridge(dev);
2091 pci_enable_bridge(bridge);
2093 if (pci_is_enabled(dev)) {
2094 if (!dev->is_busmaster)
2095 pci_set_master(dev);
2099 retval = pci_enable_device(dev);
2101 pci_err(dev, "Error enabling bridge (%d), continuing\n",
2103 pci_set_master(dev);
2106 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
2108 struct pci_dev *bridge;
2113 * Power state could be unknown at this point, either due to a fresh
2114 * boot or a device removal call. So get the current power state
2115 * so that things like MSI message writing will behave as expected
2116 * (e.g. if the device really is in D0 at enable time).
2118 pci_update_current_state(dev, dev->current_state);
2120 if (atomic_inc_return(&dev->enable_cnt) > 1)
2121 return 0; /* already enabled */
2123 bridge = pci_upstream_bridge(dev);
2125 pci_enable_bridge(bridge);
2127 /* only skip sriov related */
2128 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
2129 if (dev->resource[i].flags & flags)
2131 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
2132 if (dev->resource[i].flags & flags)
2135 err = do_pci_enable_device(dev, bars);
2137 atomic_dec(&dev->enable_cnt);
2142 * pci_enable_device_io - Initialize a device for use with IO space
2143 * @dev: PCI device to be initialized
2145 * Initialize device before it's used by a driver. Ask low-level code
2146 * to enable I/O resources. Wake up the device if it was suspended.
2147 * Beware, this function can fail.
2149 int pci_enable_device_io(struct pci_dev *dev)
2151 return pci_enable_device_flags(dev, IORESOURCE_IO);
2153 EXPORT_SYMBOL(pci_enable_device_io);
2156 * pci_enable_device_mem - Initialize a device for use with Memory space
2157 * @dev: PCI device to be initialized
2159 * Initialize device before it's used by a driver. Ask low-level code
2160 * to enable Memory resources. Wake up the device if it was suspended.
2161 * Beware, this function can fail.
2163 int pci_enable_device_mem(struct pci_dev *dev)
2165 return pci_enable_device_flags(dev, IORESOURCE_MEM);
2167 EXPORT_SYMBOL(pci_enable_device_mem);
2170 * pci_enable_device - Initialize device before it's used by a driver.
2171 * @dev: PCI device to be initialized
2173 * Initialize device before it's used by a driver. Ask low-level code
2174 * to enable I/O and memory. Wake up the device if it was suspended.
2175 * Beware, this function can fail.
2177 * Note we don't actually enable the device many times if we call
2178 * this function repeatedly (we just increment the count).
2180 int pci_enable_device(struct pci_dev *dev)
2182 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
2184 EXPORT_SYMBOL(pci_enable_device);
2187 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
2188 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
2189 * there's no need to track it separately. pci_devres is initialized
2190 * when a device is enabled using managed PCI device enable interface.
2193 unsigned int enabled:1;
2194 unsigned int pinned:1;
2195 unsigned int orig_intx:1;
2196 unsigned int restore_intx:1;
2201 static void pcim_release(struct device *gendev, void *res)
2203 struct pci_dev *dev = to_pci_dev(gendev);
2204 struct pci_devres *this = res;
2207 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
2208 if (this->region_mask & (1 << i))
2209 pci_release_region(dev, i);
2214 if (this->restore_intx)
2215 pci_intx(dev, this->orig_intx);
2217 if (this->enabled && !this->pinned)
2218 pci_disable_device(dev);
2221 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
2223 struct pci_devres *dr, *new_dr;
2225 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
2229 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
2232 return devres_get(&pdev->dev, new_dr, NULL, NULL);
2235 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
2237 if (pci_is_managed(pdev))
2238 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
2243 * pcim_enable_device - Managed pci_enable_device()
2244 * @pdev: PCI device to be initialized
2246 * Managed pci_enable_device().
2248 int pcim_enable_device(struct pci_dev *pdev)
2250 struct pci_devres *dr;
2253 dr = get_pci_dr(pdev);
2259 rc = pci_enable_device(pdev);
2261 pdev->is_managed = 1;
2266 EXPORT_SYMBOL(pcim_enable_device);
2269 * pcim_pin_device - Pin managed PCI device
2270 * @pdev: PCI device to pin
2272 * Pin managed PCI device @pdev. Pinned device won't be disabled on
2273 * driver detach. @pdev must have been enabled with
2274 * pcim_enable_device().
2276 void pcim_pin_device(struct pci_dev *pdev)
2278 struct pci_devres *dr;
2280 dr = find_pci_dr(pdev);
2281 WARN_ON(!dr || !dr->enabled);
2285 EXPORT_SYMBOL(pcim_pin_device);
2288 * pcibios_device_add - provide arch specific hooks when adding device dev
2289 * @dev: the PCI device being added
2291 * Permits the platform to provide architecture specific functionality when
2292 * devices are added. This is the default implementation. Architecture
2293 * implementations can override this.
2295 int __weak pcibios_device_add(struct pci_dev *dev)
2301 * pcibios_release_device - provide arch specific hooks when releasing
2303 * @dev: the PCI device being released
2305 * Permits the platform to provide architecture specific functionality when
2306 * devices are released. This is the default implementation. Architecture
2307 * implementations can override this.
2309 void __weak pcibios_release_device(struct pci_dev *dev) {}
2312 * pcibios_disable_device - disable arch specific PCI resources for device dev
2313 * @dev: the PCI device to disable
2315 * Disables architecture specific PCI resources for the device. This
2316 * is the default implementation. Architecture implementations can
2319 void __weak pcibios_disable_device(struct pci_dev *dev) {}
2322 * pcibios_penalize_isa_irq - penalize an ISA IRQ
2323 * @irq: ISA IRQ to penalize
2324 * @active: IRQ active or not
2326 * Permits the platform to provide architecture-specific functionality when
2327 * penalizing ISA IRQs. This is the default implementation. Architecture
2328 * implementations can override this.
2330 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
2332 static void do_pci_disable_device(struct pci_dev *dev)
2336 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
2337 if (pci_command & PCI_COMMAND_MASTER) {
2338 pci_command &= ~PCI_COMMAND_MASTER;
2339 pci_write_config_word(dev, PCI_COMMAND, pci_command);
2342 pcibios_disable_device(dev);
2346 * pci_disable_enabled_device - Disable device without updating enable_cnt
2347 * @dev: PCI device to disable
2349 * NOTE: This function is a backend of PCI power management routines and is
2350 * not supposed to be called drivers.
2352 void pci_disable_enabled_device(struct pci_dev *dev)
2354 if (pci_is_enabled(dev))
2355 do_pci_disable_device(dev);
2359 * pci_disable_device - Disable PCI device after use
2360 * @dev: PCI device to be disabled
2362 * Signal to the system that the PCI device is not in use by the system
2363 * anymore. This only involves disabling PCI bus-mastering, if active.
2365 * Note we don't actually disable the device until all callers of
2366 * pci_enable_device() have called pci_disable_device().
2368 void pci_disable_device(struct pci_dev *dev)
2370 struct pci_devres *dr;
2372 dr = find_pci_dr(dev);
2376 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
2377 "disabling already-disabled device");
2379 if (atomic_dec_return(&dev->enable_cnt) != 0)
2382 do_pci_disable_device(dev);
2384 dev->is_busmaster = 0;
2386 EXPORT_SYMBOL(pci_disable_device);
2389 * pcibios_set_pcie_reset_state - set reset state for device dev
2390 * @dev: the PCIe device reset
2391 * @state: Reset state to enter into
2393 * Set the PCIe reset state for the device. This is the default
2394 * implementation. Architecture implementations can override this.
2396 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
2397 enum pcie_reset_state state)
2403 * pci_set_pcie_reset_state - set reset state for device dev
2404 * @dev: the PCIe device reset
2405 * @state: Reset state to enter into
2407 * Sets the PCI reset state for the device.
2409 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
2411 return pcibios_set_pcie_reset_state(dev, state);
2413 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
2415 #ifdef CONFIG_PCIEAER
2416 void pcie_clear_device_status(struct pci_dev *dev)
2420 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta);
2421 pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta);
2426 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2427 * @dev: PCIe root port or event collector.
2429 void pcie_clear_root_pme_status(struct pci_dev *dev)
2431 pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
2435 * pci_check_pme_status - Check if given device has generated PME.
2436 * @dev: Device to check.
2438 * Check the PME status of the device and if set, clear it and clear PME enable
2439 * (if set). Return 'true' if PME status and PME enable were both set or
2440 * 'false' otherwise.
2442 bool pci_check_pme_status(struct pci_dev *dev)
2451 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
2452 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
2453 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
2456 /* Clear PME status. */
2457 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2458 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
2459 /* Disable PME to avoid interrupt flood. */
2460 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2464 pci_write_config_word(dev, pmcsr_pos, pmcsr);
2470 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2471 * @dev: Device to handle.
2472 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
2474 * Check if @dev has generated PME and queue a resume request for it in that
2477 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
2479 if (pme_poll_reset && dev->pme_poll)
2480 dev->pme_poll = false;
2482 if (pci_check_pme_status(dev)) {
2483 pci_wakeup_event(dev);
2484 pm_request_resume(&dev->dev);
2490 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2491 * @bus: Top bus of the subtree to walk.
2493 void pci_pme_wakeup_bus(struct pci_bus *bus)
2496 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
2501 * pci_pme_capable - check the capability of PCI device to generate PME#
2502 * @dev: PCI device to handle.
2503 * @state: PCI state from which device will issue PME#.
2505 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
2510 return !!(dev->pme_support & (1 << state));
2512 EXPORT_SYMBOL(pci_pme_capable);
2514 static void pci_pme_list_scan(struct work_struct *work)
2516 struct pci_pme_device *pme_dev, *n;
2518 mutex_lock(&pci_pme_list_mutex);
2519 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
2520 struct pci_dev *pdev = pme_dev->dev;
2522 if (pdev->pme_poll) {
2523 struct pci_dev *bridge = pdev->bus->self;
2524 struct device *dev = &pdev->dev;
2528 * If bridge is in low power state, the
2529 * configuration space of subordinate devices
2530 * may be not accessible
2532 if (bridge && bridge->current_state != PCI_D0)
2536 * If the device is in a low power state it
2537 * should not be polled either.
2539 pm_status = pm_runtime_get_if_active(dev, true);
2543 if (pdev->current_state != PCI_D3cold)
2544 pci_pme_wakeup(pdev, NULL);
2547 pm_runtime_put(dev);
2549 list_del(&pme_dev->list);
2553 if (!list_empty(&pci_pme_list))
2554 queue_delayed_work(system_freezable_wq, &pci_pme_work,
2555 msecs_to_jiffies(PME_TIMEOUT));
2556 mutex_unlock(&pci_pme_list_mutex);
2559 static void __pci_pme_active(struct pci_dev *dev, bool enable)
2563 if (!dev->pme_support)
2566 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2567 /* Clear PME_Status by writing 1 to it and enable PME# */
2568 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
2570 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2572 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2576 * pci_pme_restore - Restore PME configuration after config space restore.
2577 * @dev: PCI device to update.
2579 void pci_pme_restore(struct pci_dev *dev)
2583 if (!dev->pme_support)
2586 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2587 if (dev->wakeup_prepared) {
2588 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2589 pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
2591 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2592 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2594 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2598 * pci_pme_active - enable or disable PCI device's PME# function
2599 * @dev: PCI device to handle.
2600 * @enable: 'true' to enable PME# generation; 'false' to disable it.
2602 * The caller must verify that the device is capable of generating PME# before
2603 * calling this function with @enable equal to 'true'.
2605 void pci_pme_active(struct pci_dev *dev, bool enable)
2607 __pci_pme_active(dev, enable);
2610 * PCI (as opposed to PCIe) PME requires that the device have
2611 * its PME# line hooked up correctly. Not all hardware vendors
2612 * do this, so the PME never gets delivered and the device
2613 * remains asleep. The easiest way around this is to
2614 * periodically walk the list of suspended devices and check
2615 * whether any have their PME flag set. The assumption is that
2616 * we'll wake up often enough anyway that this won't be a huge
2617 * hit, and the power savings from the devices will still be a
2620 * Although PCIe uses in-band PME message instead of PME# line
2621 * to report PME, PME does not work for some PCIe devices in
2622 * reality. For example, there are devices that set their PME
2623 * status bits, but don't really bother to send a PME message;
2624 * there are PCI Express Root Ports that don't bother to
2625 * trigger interrupts when they receive PME messages from the
2626 * devices below. So PME poll is used for PCIe devices too.
2629 if (dev->pme_poll) {
2630 struct pci_pme_device *pme_dev;
2632 pme_dev = kmalloc(sizeof(struct pci_pme_device),
2635 pci_warn(dev, "can't enable PME#\n");
2639 mutex_lock(&pci_pme_list_mutex);
2640 list_add(&pme_dev->list, &pci_pme_list);
2641 if (list_is_singular(&pci_pme_list))
2642 queue_delayed_work(system_freezable_wq,
2644 msecs_to_jiffies(PME_TIMEOUT));
2645 mutex_unlock(&pci_pme_list_mutex);
2647 mutex_lock(&pci_pme_list_mutex);
2648 list_for_each_entry(pme_dev, &pci_pme_list, list) {
2649 if (pme_dev->dev == dev) {
2650 list_del(&pme_dev->list);
2655 mutex_unlock(&pci_pme_list_mutex);
2659 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
2661 EXPORT_SYMBOL(pci_pme_active);
2664 * __pci_enable_wake - enable PCI device as wakeup event source
2665 * @dev: PCI device affected
2666 * @state: PCI state from which device will issue wakeup events
2667 * @enable: True to enable event generation; false to disable
2669 * This enables the device as a wakeup event source, or disables it.
2670 * When such events involves platform-specific hooks, those hooks are
2671 * called automatically by this routine.
2673 * Devices with legacy power management (no standard PCI PM capabilities)
2674 * always require such platform hooks.
2677 * 0 is returned on success
2678 * -EINVAL is returned if device is not supposed to wake up the system
2679 * Error code depending on the platform is returned if both the platform and
2680 * the native mechanism fail to enable the generation of wake-up events
2682 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
2687 * Bridges that are not power-manageable directly only signal
2688 * wakeup on behalf of subordinate devices which is set up
2689 * elsewhere, so skip them. However, bridges that are
2690 * power-manageable may signal wakeup for themselves (for example,
2691 * on a hotplug event) and they need to be covered here.
2693 if (!pci_power_manageable(dev))
2696 /* Don't do the same thing twice in a row for one device. */
2697 if (!!enable == !!dev->wakeup_prepared)
2701 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
2702 * Anderson we should be doing PME# wake enable followed by ACPI wake
2703 * enable. To disable wake-up we call the platform first, for symmetry.
2710 * Enable PME signaling if the device can signal PME from
2711 * D3cold regardless of whether or not it can signal PME from
2712 * the current target state, because that will allow it to
2713 * signal PME when the hierarchy above it goes into D3cold and
2714 * the device itself ends up in D3cold as a result of that.
2716 if (pci_pme_capable(dev, state) || pci_pme_capable(dev, PCI_D3cold))
2717 pci_pme_active(dev, true);
2720 error = platform_pci_set_wakeup(dev, true);
2724 dev->wakeup_prepared = true;
2726 platform_pci_set_wakeup(dev, false);
2727 pci_pme_active(dev, false);
2728 dev->wakeup_prepared = false;
2735 * pci_enable_wake - change wakeup settings for a PCI device
2736 * @pci_dev: Target device
2737 * @state: PCI state from which device will issue wakeup events
2738 * @enable: Whether or not to enable event generation
2740 * If @enable is set, check device_may_wakeup() for the device before calling
2741 * __pci_enable_wake() for it.
2743 int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable)
2745 if (enable && !device_may_wakeup(&pci_dev->dev))
2748 return __pci_enable_wake(pci_dev, state, enable);
2750 EXPORT_SYMBOL(pci_enable_wake);
2753 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2754 * @dev: PCI device to prepare
2755 * @enable: True to enable wake-up event generation; false to disable
2757 * Many drivers want the device to wake up the system from D3_hot or D3_cold
2758 * and this function allows them to set that up cleanly - pci_enable_wake()
2759 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2760 * ordering constraints.
2762 * This function only returns error code if the device is not allowed to wake
2763 * up the system from sleep or it is not capable of generating PME# from both
2764 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2766 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2768 return pci_pme_capable(dev, PCI_D3cold) ?
2769 pci_enable_wake(dev, PCI_D3cold, enable) :
2770 pci_enable_wake(dev, PCI_D3hot, enable);
2772 EXPORT_SYMBOL(pci_wake_from_d3);
2775 * pci_target_state - find an appropriate low power state for a given PCI dev
2777 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2779 * Use underlying platform code to find a supported low power state for @dev.
2780 * If the platform can't manage @dev, return the deepest state from which it
2781 * can generate wake events, based on any available PME info.
2783 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2785 if (platform_pci_power_manageable(dev)) {
2787 * Call the platform to find the target state for the device.
2789 pci_power_t state = platform_pci_choose_state(dev);
2792 case PCI_POWER_ERROR:
2798 if (pci_no_d1d2(dev))
2806 * If the device is in D3cold even though it's not power-manageable by
2807 * the platform, it may have been powered down by non-standard means.
2808 * Best to let it slumber.
2810 if (dev->current_state == PCI_D3cold)
2812 else if (!dev->pm_cap)
2815 if (wakeup && dev->pme_support) {
2816 pci_power_t state = PCI_D3hot;
2819 * Find the deepest state from which the device can generate
2822 while (state && !(dev->pme_support & (1 << state)))
2827 else if (dev->pme_support & 1)
2835 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2836 * into a sleep state
2837 * @dev: Device to handle.
2839 * Choose the power state appropriate for the device depending on whether
2840 * it can wake up the system and/or is power manageable by the platform
2841 * (PCI_D3hot is the default) and put the device into that state.
2843 int pci_prepare_to_sleep(struct pci_dev *dev)
2845 bool wakeup = device_may_wakeup(&dev->dev);
2846 pci_power_t target_state = pci_target_state(dev, wakeup);
2849 if (target_state == PCI_POWER_ERROR)
2852 pci_enable_wake(dev, target_state, wakeup);
2854 error = pci_set_power_state(dev, target_state);
2857 pci_enable_wake(dev, target_state, false);
2861 EXPORT_SYMBOL(pci_prepare_to_sleep);
2864 * pci_back_from_sleep - turn PCI device on during system-wide transition
2865 * into working state
2866 * @dev: Device to handle.
2868 * Disable device's system wake-up capability and put it into D0.
2870 int pci_back_from_sleep(struct pci_dev *dev)
2872 int ret = pci_set_power_state(dev, PCI_D0);
2877 pci_enable_wake(dev, PCI_D0, false);
2880 EXPORT_SYMBOL(pci_back_from_sleep);
2883 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2884 * @dev: PCI device being suspended.
2886 * Prepare @dev to generate wake-up events at run time and put it into a low
2889 int pci_finish_runtime_suspend(struct pci_dev *dev)
2891 pci_power_t target_state;
2894 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2895 if (target_state == PCI_POWER_ERROR)
2898 __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2900 error = pci_set_power_state(dev, target_state);
2903 pci_enable_wake(dev, target_state, false);
2909 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2910 * @dev: Device to check.
2912 * Return true if the device itself is capable of generating wake-up events
2913 * (through the platform or using the native PCIe PME) or if the device supports
2914 * PME and one of its upstream bridges can generate wake-up events.
2916 bool pci_dev_run_wake(struct pci_dev *dev)
2918 struct pci_bus *bus = dev->bus;
2920 if (!dev->pme_support)
2923 /* PME-capable in principle, but not from the target power state */
2924 if (!pci_pme_capable(dev, pci_target_state(dev, true)))
2927 if (device_can_wakeup(&dev->dev))
2930 while (bus->parent) {
2931 struct pci_dev *bridge = bus->self;
2933 if (device_can_wakeup(&bridge->dev))
2939 /* We have reached the root bus. */
2941 return device_can_wakeup(bus->bridge);
2945 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2948 * pci_dev_need_resume - Check if it is necessary to resume the device.
2949 * @pci_dev: Device to check.
2951 * Return 'true' if the device is not runtime-suspended or it has to be
2952 * reconfigured due to wakeup settings difference between system and runtime
2953 * suspend, or the current power state of it is not suitable for the upcoming
2954 * (system-wide) transition.
2956 bool pci_dev_need_resume(struct pci_dev *pci_dev)
2958 struct device *dev = &pci_dev->dev;
2959 pci_power_t target_state;
2961 if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev))
2964 target_state = pci_target_state(pci_dev, device_may_wakeup(dev));
2967 * If the earlier platform check has not triggered, D3cold is just power
2968 * removal on top of D3hot, so no need to resume the device in that
2971 return target_state != pci_dev->current_state &&
2972 target_state != PCI_D3cold &&
2973 pci_dev->current_state != PCI_D3hot;
2977 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2978 * @pci_dev: Device to check.
2980 * If the device is suspended and it is not configured for system wakeup,
2981 * disable PME for it to prevent it from waking up the system unnecessarily.
2983 * Note that if the device's power state is D3cold and the platform check in
2984 * pci_dev_need_resume() has not triggered, the device's configuration need not
2987 void pci_dev_adjust_pme(struct pci_dev *pci_dev)
2989 struct device *dev = &pci_dev->dev;
2991 spin_lock_irq(&dev->power.lock);
2993 if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) &&
2994 pci_dev->current_state < PCI_D3cold)
2995 __pci_pme_active(pci_dev, false);
2997 spin_unlock_irq(&dev->power.lock);
3001 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
3002 * @pci_dev: Device to handle.
3004 * If the device is runtime suspended and wakeup-capable, enable PME for it as
3005 * it might have been disabled during the prepare phase of system suspend if
3006 * the device was not configured for system wakeup.
3008 void pci_dev_complete_resume(struct pci_dev *pci_dev)
3010 struct device *dev = &pci_dev->dev;
3012 if (!pci_dev_run_wake(pci_dev))
3015 spin_lock_irq(&dev->power.lock);
3017 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
3018 __pci_pme_active(pci_dev, true);
3020 spin_unlock_irq(&dev->power.lock);
3024 * pci_choose_state - Choose the power state of a PCI device.
3025 * @dev: Target PCI device.
3026 * @state: Target state for the whole system.
3028 * Returns PCI power state suitable for @dev and @state.
3030 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
3032 if (state.event == PM_EVENT_ON)
3035 return pci_target_state(dev, false);
3037 EXPORT_SYMBOL(pci_choose_state);
3039 void pci_config_pm_runtime_get(struct pci_dev *pdev)
3041 struct device *dev = &pdev->dev;
3042 struct device *parent = dev->parent;
3045 pm_runtime_get_sync(parent);
3046 pm_runtime_get_noresume(dev);
3048 * pdev->current_state is set to PCI_D3cold during suspending,
3049 * so wait until suspending completes
3051 pm_runtime_barrier(dev);
3053 * Only need to resume devices in D3cold, because config
3054 * registers are still accessible for devices suspended but
3057 if (pdev->current_state == PCI_D3cold)
3058 pm_runtime_resume(dev);
3061 void pci_config_pm_runtime_put(struct pci_dev *pdev)
3063 struct device *dev = &pdev->dev;
3064 struct device *parent = dev->parent;
3066 pm_runtime_put(dev);
3068 pm_runtime_put_sync(parent);
3071 static const struct dmi_system_id bridge_d3_blacklist[] = {
3075 * Gigabyte X299 root port is not marked as hotplug capable
3076 * which allows Linux to power manage it. However, this
3077 * confuses the BIOS SMI handler so don't power manage root
3078 * ports on that system.
3080 .ident = "X299 DESIGNARE EX-CF",
3082 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
3083 DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
3088 * Downstream device is not accessible after putting a root port
3089 * into D3cold and back into D0 on Elo Continental Z2 board
3091 .ident = "Elo Continental Z2",
3093 DMI_MATCH(DMI_BOARD_VENDOR, "Elo Touch Solutions"),
3094 DMI_MATCH(DMI_BOARD_NAME, "Geminilake"),
3095 DMI_MATCH(DMI_BOARD_VERSION, "Continental Z2"),
3103 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
3104 * @bridge: Bridge to check
3106 * This function checks if it is possible to move the bridge to D3.
3107 * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
3109 bool pci_bridge_d3_possible(struct pci_dev *bridge)
3111 if (!pci_is_pcie(bridge))
3114 switch (pci_pcie_type(bridge)) {
3115 case PCI_EXP_TYPE_ROOT_PORT:
3116 case PCI_EXP_TYPE_UPSTREAM:
3117 case PCI_EXP_TYPE_DOWNSTREAM:
3118 if (pci_bridge_d3_disable)
3122 * Hotplug ports handled by firmware in System Management Mode
3123 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
3125 if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge))
3128 if (pci_bridge_d3_force)
3131 /* Even the oldest 2010 Thunderbolt controller supports D3. */
3132 if (bridge->is_thunderbolt)
3135 /* Platform might know better if the bridge supports D3 */
3136 if (platform_pci_bridge_d3(bridge))
3140 * Hotplug ports handled natively by the OS were not validated
3141 * by vendors for runtime D3 at least until 2018 because there
3142 * was no OS support.
3144 if (bridge->is_hotplug_bridge)
3147 if (dmi_check_system(bridge_d3_blacklist))
3151 * It should be safe to put PCIe ports from 2015 or newer
3154 if (dmi_get_bios_year() >= 2015)
3162 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
3164 bool *d3cold_ok = data;
3166 if (/* The device needs to be allowed to go D3cold ... */
3167 dev->no_d3cold || !dev->d3cold_allowed ||
3169 /* ... and if it is wakeup capable to do so from D3cold. */
3170 (device_may_wakeup(&dev->dev) &&
3171 !pci_pme_capable(dev, PCI_D3cold)) ||
3173 /* If it is a bridge it must be allowed to go to D3. */
3174 !pci_power_manageable(dev))
3182 * pci_bridge_d3_update - Update bridge D3 capabilities
3183 * @dev: PCI device which is changed
3185 * Update upstream bridge PM capabilities accordingly depending on if the
3186 * device PM configuration was changed or the device is being removed. The
3187 * change is also propagated upstream.
3189 void pci_bridge_d3_update(struct pci_dev *dev)
3191 bool remove = !device_is_registered(&dev->dev);
3192 struct pci_dev *bridge;
3193 bool d3cold_ok = true;
3195 bridge = pci_upstream_bridge(dev);
3196 if (!bridge || !pci_bridge_d3_possible(bridge))
3200 * If D3 is currently allowed for the bridge, removing one of its
3201 * children won't change that.
3203 if (remove && bridge->bridge_d3)
3207 * If D3 is currently allowed for the bridge and a child is added or
3208 * changed, disallowance of D3 can only be caused by that child, so
3209 * we only need to check that single device, not any of its siblings.
3211 * If D3 is currently not allowed for the bridge, checking the device
3212 * first may allow us to skip checking its siblings.
3215 pci_dev_check_d3cold(dev, &d3cold_ok);
3218 * If D3 is currently not allowed for the bridge, this may be caused
3219 * either by the device being changed/removed or any of its siblings,
3220 * so we need to go through all children to find out if one of them
3221 * continues to block D3.
3223 if (d3cold_ok && !bridge->bridge_d3)
3224 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
3227 if (bridge->bridge_d3 != d3cold_ok) {
3228 bridge->bridge_d3 = d3cold_ok;
3229 /* Propagate change to upstream bridges */
3230 pci_bridge_d3_update(bridge);
3235 * pci_d3cold_enable - Enable D3cold for device
3236 * @dev: PCI device to handle
3238 * This function can be used in drivers to enable D3cold from the device
3239 * they handle. It also updates upstream PCI bridge PM capabilities
3242 void pci_d3cold_enable(struct pci_dev *dev)
3244 if (dev->no_d3cold) {
3245 dev->no_d3cold = false;
3246 pci_bridge_d3_update(dev);
3249 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
3252 * pci_d3cold_disable - Disable D3cold for device
3253 * @dev: PCI device to handle
3255 * This function can be used in drivers to disable D3cold from the device
3256 * they handle. It also updates upstream PCI bridge PM capabilities
3259 void pci_d3cold_disable(struct pci_dev *dev)
3261 if (!dev->no_d3cold) {
3262 dev->no_d3cold = true;
3263 pci_bridge_d3_update(dev);
3266 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
3269 * pci_pm_init - Initialize PM functions of given PCI device
3270 * @dev: PCI device to handle.
3272 void pci_pm_init(struct pci_dev *dev)
3278 pm_runtime_forbid(&dev->dev);
3279 pm_runtime_set_active(&dev->dev);
3280 pm_runtime_enable(&dev->dev);
3281 device_enable_async_suspend(&dev->dev);
3282 dev->wakeup_prepared = false;
3285 dev->pme_support = 0;
3287 /* find PCI PM capability in list */
3288 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3291 /* Check device's ability to generate PME# */
3292 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
3294 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
3295 pci_err(dev, "unsupported PM cap regs version (%u)\n",
3296 pmc & PCI_PM_CAP_VER_MASK);
3301 dev->d3hot_delay = PCI_PM_D3HOT_WAIT;
3302 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
3303 dev->bridge_d3 = pci_bridge_d3_possible(dev);
3304 dev->d3cold_allowed = true;
3306 dev->d1_support = false;
3307 dev->d2_support = false;
3308 if (!pci_no_d1d2(dev)) {
3309 if (pmc & PCI_PM_CAP_D1)
3310 dev->d1_support = true;
3311 if (pmc & PCI_PM_CAP_D2)
3312 dev->d2_support = true;
3314 if (dev->d1_support || dev->d2_support)
3315 pci_info(dev, "supports%s%s\n",
3316 dev->d1_support ? " D1" : "",
3317 dev->d2_support ? " D2" : "");
3320 pmc &= PCI_PM_CAP_PME_MASK;
3322 pci_info(dev, "PME# supported from%s%s%s%s%s\n",
3323 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
3324 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
3325 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
3326 (pmc & PCI_PM_CAP_PME_D3hot) ? " D3hot" : "",
3327 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
3328 dev->pme_support = FIELD_GET(PCI_PM_CAP_PME_MASK, pmc);
3329 dev->pme_poll = true;
3331 * Make device's PM flags reflect the wake-up capability, but
3332 * let the user space enable it to wake up the system as needed.
3334 device_set_wakeup_capable(&dev->dev, true);
3335 /* Disable the PME# generation functionality */
3336 pci_pme_active(dev, false);
3339 pci_read_config_word(dev, PCI_STATUS, &status);
3340 if (status & PCI_STATUS_IMM_READY)
3344 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
3346 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
3350 case PCI_EA_P_VF_MEM:
3351 flags |= IORESOURCE_MEM;
3353 case PCI_EA_P_MEM_PREFETCH:
3354 case PCI_EA_P_VF_MEM_PREFETCH:
3355 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
3358 flags |= IORESOURCE_IO;
3367 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
3370 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
3371 return &dev->resource[bei];
3372 #ifdef CONFIG_PCI_IOV
3373 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
3374 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
3375 return &dev->resource[PCI_IOV_RESOURCES +
3376 bei - PCI_EA_BEI_VF_BAR0];
3378 else if (bei == PCI_EA_BEI_ROM)
3379 return &dev->resource[PCI_ROM_RESOURCE];
3384 /* Read an Enhanced Allocation (EA) entry */
3385 static int pci_ea_read(struct pci_dev *dev, int offset)
3387 struct resource *res;
3388 const char *res_name;
3389 int ent_size, ent_offset = offset;
3390 resource_size_t start, end;
3391 unsigned long flags;
3392 u32 dw0, bei, base, max_offset;
3394 bool support_64 = (sizeof(resource_size_t) >= 8);
3396 pci_read_config_dword(dev, ent_offset, &dw0);
3399 /* Entry size field indicates DWORDs after 1st */
3400 ent_size = (FIELD_GET(PCI_EA_ES, dw0) + 1) << 2;
3402 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
3405 bei = FIELD_GET(PCI_EA_BEI, dw0);
3406 prop = FIELD_GET(PCI_EA_PP, dw0);
3409 * If the Property is in the reserved range, try the Secondary
3412 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
3413 prop = FIELD_GET(PCI_EA_SP, dw0);
3414 if (prop > PCI_EA_P_BRIDGE_IO)
3417 res = pci_ea_get_resource(dev, bei, prop);
3418 res_name = pci_resource_name(dev, bei);
3420 pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
3424 flags = pci_ea_flags(dev, prop);
3426 pci_err(dev, "Unsupported EA properties: %#x\n", prop);
3431 pci_read_config_dword(dev, ent_offset, &base);
3432 start = (base & PCI_EA_FIELD_MASK);
3435 /* Read MaxOffset */
3436 pci_read_config_dword(dev, ent_offset, &max_offset);
3439 /* Read Base MSBs (if 64-bit entry) */
3440 if (base & PCI_EA_IS_64) {
3443 pci_read_config_dword(dev, ent_offset, &base_upper);
3446 flags |= IORESOURCE_MEM_64;
3448 /* entry starts above 32-bit boundary, can't use */
3449 if (!support_64 && base_upper)
3453 start |= ((u64)base_upper << 32);
3456 end = start + (max_offset | 0x03);
3458 /* Read MaxOffset MSBs (if 64-bit entry) */
3459 if (max_offset & PCI_EA_IS_64) {
3460 u32 max_offset_upper;
3462 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
3465 flags |= IORESOURCE_MEM_64;
3467 /* entry too big, can't use */
3468 if (!support_64 && max_offset_upper)
3472 end += ((u64)max_offset_upper << 32);
3476 pci_err(dev, "EA Entry crosses address boundary\n");
3480 if (ent_size != ent_offset - offset) {
3481 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
3482 ent_size, ent_offset - offset);
3486 res->name = pci_name(dev);
3491 if (bei <= PCI_EA_BEI_BAR5)
3492 pci_info(dev, "%s %pR: from Enhanced Allocation, properties %#02x\n",
3493 res_name, res, prop);
3494 else if (bei == PCI_EA_BEI_ROM)
3495 pci_info(dev, "%s %pR: from Enhanced Allocation, properties %#02x\n",
3496 res_name, res, prop);
3497 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
3498 pci_info(dev, "%s %pR: from Enhanced Allocation, properties %#02x\n",
3499 res_name, res, prop);
3501 pci_info(dev, "BEI %d %pR: from Enhanced Allocation, properties %#02x\n",
3505 return offset + ent_size;
3508 /* Enhanced Allocation Initialization */
3509 void pci_ea_init(struct pci_dev *dev)
3516 /* find PCI EA capability in list */
3517 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
3521 /* determine the number of entries */
3522 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
3524 num_ent &= PCI_EA_NUM_ENT_MASK;
3526 offset = ea + PCI_EA_FIRST_ENT;
3528 /* Skip DWORD 2 for type 1 functions */
3529 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
3532 /* parse each EA entry */
3533 for (i = 0; i < num_ent; ++i)
3534 offset = pci_ea_read(dev, offset);
3537 static void pci_add_saved_cap(struct pci_dev *pci_dev,
3538 struct pci_cap_saved_state *new_cap)
3540 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
3544 * _pci_add_cap_save_buffer - allocate buffer for saving given
3545 * capability registers
3546 * @dev: the PCI device
3547 * @cap: the capability to allocate the buffer for
3548 * @extended: Standard or Extended capability ID
3549 * @size: requested size of the buffer
3551 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
3552 bool extended, unsigned int size)
3555 struct pci_cap_saved_state *save_state;
3558 pos = pci_find_ext_capability(dev, cap);
3560 pos = pci_find_capability(dev, cap);
3565 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
3569 save_state->cap.cap_nr = cap;
3570 save_state->cap.cap_extended = extended;
3571 save_state->cap.size = size;
3572 pci_add_saved_cap(dev, save_state);
3577 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
3579 return _pci_add_cap_save_buffer(dev, cap, false, size);
3582 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
3584 return _pci_add_cap_save_buffer(dev, cap, true, size);
3588 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3589 * @dev: the PCI device
3591 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
3595 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
3596 PCI_EXP_SAVE_REGS * sizeof(u16));
3598 pci_err(dev, "unable to preallocate PCI Express save buffer\n");
3600 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
3602 pci_err(dev, "unable to preallocate PCI-X save buffer\n");
3604 error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,
3607 pci_err(dev, "unable to allocate suspend buffer for LTR\n");
3609 pci_allocate_vc_save_buffers(dev);
3612 void pci_free_cap_save_buffers(struct pci_dev *dev)
3614 struct pci_cap_saved_state *tmp;
3615 struct hlist_node *n;
3617 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
3622 * pci_configure_ari - enable or disable ARI forwarding
3623 * @dev: the PCI device
3625 * If @dev and its upstream bridge both support ARI, enable ARI in the
3626 * bridge. Otherwise, disable ARI in the bridge.
3628 void pci_configure_ari(struct pci_dev *dev)
3631 struct pci_dev *bridge;
3633 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
3636 bridge = dev->bus->self;
3640 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3641 if (!(cap & PCI_EXP_DEVCAP2_ARI))
3644 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
3645 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
3646 PCI_EXP_DEVCTL2_ARI);
3647 bridge->ari_enabled = 1;
3649 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
3650 PCI_EXP_DEVCTL2_ARI);
3651 bridge->ari_enabled = 0;
3655 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
3660 pos = pdev->acs_cap;
3665 * Except for egress control, capabilities are either required
3666 * or only required if controllable. Features missing from the
3667 * capability field can therefore be assumed as hard-wired enabled.
3669 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
3670 acs_flags &= (cap | PCI_ACS_EC);
3672 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
3673 return (ctrl & acs_flags) == acs_flags;
3677 * pci_acs_enabled - test ACS against required flags for a given device
3678 * @pdev: device to test
3679 * @acs_flags: required PCI ACS flags
3681 * Return true if the device supports the provided flags. Automatically
3682 * filters out flags that are not implemented on multifunction devices.
3684 * Note that this interface checks the effective ACS capabilities of the
3685 * device rather than the actual capabilities. For instance, most single
3686 * function endpoints are not required to support ACS because they have no
3687 * opportunity for peer-to-peer access. We therefore return 'true'
3688 * regardless of whether the device exposes an ACS capability. This makes
3689 * it much easier for callers of this function to ignore the actual type
3690 * or topology of the device when testing ACS support.
3692 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
3696 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
3701 * Conventional PCI and PCI-X devices never support ACS, either
3702 * effectively or actually. The shared bus topology implies that
3703 * any device on the bus can receive or snoop DMA.
3705 if (!pci_is_pcie(pdev))
3708 switch (pci_pcie_type(pdev)) {
3710 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
3711 * but since their primary interface is PCI/X, we conservatively
3712 * handle them as we would a non-PCIe device.
3714 case PCI_EXP_TYPE_PCIE_BRIDGE:
3716 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
3717 * applicable... must never implement an ACS Extended Capability...".
3718 * This seems arbitrary, but we take a conservative interpretation
3719 * of this statement.
3721 case PCI_EXP_TYPE_PCI_BRIDGE:
3722 case PCI_EXP_TYPE_RC_EC:
3725 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
3726 * implement ACS in order to indicate their peer-to-peer capabilities,
3727 * regardless of whether they are single- or multi-function devices.
3729 case PCI_EXP_TYPE_DOWNSTREAM:
3730 case PCI_EXP_TYPE_ROOT_PORT:
3731 return pci_acs_flags_enabled(pdev, acs_flags);
3733 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
3734 * implemented by the remaining PCIe types to indicate peer-to-peer
3735 * capabilities, but only when they are part of a multifunction
3736 * device. The footnote for section 6.12 indicates the specific
3737 * PCIe types included here.
3739 case PCI_EXP_TYPE_ENDPOINT:
3740 case PCI_EXP_TYPE_UPSTREAM:
3741 case PCI_EXP_TYPE_LEG_END:
3742 case PCI_EXP_TYPE_RC_END:
3743 if (!pdev->multifunction)
3746 return pci_acs_flags_enabled(pdev, acs_flags);
3750 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3751 * to single function devices with the exception of downstream ports.
3757 * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3758 * @start: starting downstream device
3759 * @end: ending upstream device or NULL to search to the root bus
3760 * @acs_flags: required flags
3762 * Walk up a device tree from start to end testing PCI ACS support. If
3763 * any step along the way does not support the required flags, return false.
3765 bool pci_acs_path_enabled(struct pci_dev *start,
3766 struct pci_dev *end, u16 acs_flags)
3768 struct pci_dev *pdev, *parent = start;
3773 if (!pci_acs_enabled(pdev, acs_flags))
3776 if (pci_is_root_bus(pdev->bus))
3777 return (end == NULL);
3779 parent = pdev->bus->self;
3780 } while (pdev != end);
3786 * pci_acs_init - Initialize ACS if hardware supports it
3787 * @dev: the PCI device
3789 void pci_acs_init(struct pci_dev *dev)
3791 dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3794 * Attempt to enable ACS regardless of capability because some Root
3795 * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have
3796 * the standard ACS capability but still support ACS via those
3799 pci_enable_acs(dev);
3803 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3807 * Helper to find the position of the ctrl register for a BAR.
3808 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3809 * Returns -ENOENT if no ctrl register for the BAR could be found.
3811 static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
3813 unsigned int pos, nbars, i;
3816 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
3820 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3821 nbars = FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl);
3823 for (i = 0; i < nbars; i++, pos += 8) {
3826 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3827 bar_idx = FIELD_GET(PCI_REBAR_CTRL_BAR_IDX, ctrl);
3836 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3838 * @bar: BAR to query
3840 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3841 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3843 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3848 pos = pci_rebar_find_pos(pdev, bar);
3852 pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3853 cap = FIELD_GET(PCI_REBAR_CAP_SIZES, cap);
3855 /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */
3856 if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f &&
3857 bar == 0 && cap == 0x700)
3862 EXPORT_SYMBOL(pci_rebar_get_possible_sizes);
3865 * pci_rebar_get_current_size - get the current size of a BAR
3867 * @bar: BAR to set size to
3869 * Read the size of a BAR from the resizable BAR config.
3870 * Returns size if found or negative error code.
3872 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3877 pos = pci_rebar_find_pos(pdev, bar);
3881 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3882 return FIELD_GET(PCI_REBAR_CTRL_BAR_SIZE, ctrl);
3886 * pci_rebar_set_size - set a new size for a BAR
3888 * @bar: BAR to set size to
3889 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3891 * Set the new size of a BAR as defined in the spec.
3892 * Returns zero if resizing was successful, error code otherwise.
3894 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3899 pos = pci_rebar_find_pos(pdev, bar);
3903 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3904 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3905 ctrl |= FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size);
3906 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3911 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3912 * @dev: the PCI device
3913 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3914 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3915 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3916 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3918 * Return 0 if all upstream bridges support AtomicOp routing, egress
3919 * blocking is disabled on all upstream ports, and the root port supports
3920 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3921 * AtomicOp completion), or negative otherwise.
3923 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3925 struct pci_bus *bus = dev->bus;
3926 struct pci_dev *bridge;
3930 * Per PCIe r5.0, sec 9.3.5.10, the AtomicOp Requester Enable bit
3931 * in Device Control 2 is reserved in VFs and the PF value applies
3932 * to all associated VFs.
3937 if (!pci_is_pcie(dev))
3941 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3942 * AtomicOp requesters. For now, we only support endpoints as
3943 * requesters and root ports as completers. No endpoints as
3944 * completers, and no peer-to-peer.
3947 switch (pci_pcie_type(dev)) {
3948 case PCI_EXP_TYPE_ENDPOINT:
3949 case PCI_EXP_TYPE_LEG_END:
3950 case PCI_EXP_TYPE_RC_END:
3956 while (bus->parent) {
3959 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3961 switch (pci_pcie_type(bridge)) {
3962 /* Ensure switch ports support AtomicOp routing */
3963 case PCI_EXP_TYPE_UPSTREAM:
3964 case PCI_EXP_TYPE_DOWNSTREAM:
3965 if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
3969 /* Ensure root port supports all the sizes we care about */
3970 case PCI_EXP_TYPE_ROOT_PORT:
3971 if ((cap & cap_mask) != cap_mask)
3976 /* Ensure upstream ports don't block AtomicOps on egress */
3977 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) {
3978 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3980 if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
3987 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3988 PCI_EXP_DEVCTL2_ATOMIC_REQ);
3991 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
3994 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3995 * @dev: the PCI device
3996 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3998 * Perform INTx swizzling for a device behind one level of bridge. This is
3999 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
4000 * behind bridges on add-in cards. For devices with ARI enabled, the slot
4001 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
4002 * the PCI Express Base Specification, Revision 2.1)
4004 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
4008 if (pci_ari_enabled(dev->bus))
4011 slot = PCI_SLOT(dev->devfn);
4013 return (((pin - 1) + slot) % 4) + 1;
4016 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
4024 while (!pci_is_root_bus(dev->bus)) {
4025 pin = pci_swizzle_interrupt_pin(dev, pin);
4026 dev = dev->bus->self;
4033 * pci_common_swizzle - swizzle INTx all the way to root bridge
4034 * @dev: the PCI device
4035 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
4037 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
4038 * bridges all the way up to a PCI root bus.
4040 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
4044 while (!pci_is_root_bus(dev->bus)) {
4045 pin = pci_swizzle_interrupt_pin(dev, pin);
4046 dev = dev->bus->self;
4049 return PCI_SLOT(dev->devfn);
4051 EXPORT_SYMBOL_GPL(pci_common_swizzle);
4054 * pci_release_region - Release a PCI bar
4055 * @pdev: PCI device whose resources were previously reserved by
4056 * pci_request_region()
4057 * @bar: BAR to release
4059 * Releases the PCI I/O and memory resources previously reserved by a
4060 * successful call to pci_request_region(). Call this function only
4061 * after all use of the PCI regions has ceased.
4063 void pci_release_region(struct pci_dev *pdev, int bar)
4065 struct pci_devres *dr;
4067 if (pci_resource_len(pdev, bar) == 0)
4069 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
4070 release_region(pci_resource_start(pdev, bar),
4071 pci_resource_len(pdev, bar));
4072 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
4073 release_mem_region(pci_resource_start(pdev, bar),
4074 pci_resource_len(pdev, bar));
4076 dr = find_pci_dr(pdev);
4078 dr->region_mask &= ~(1 << bar);
4080 EXPORT_SYMBOL(pci_release_region);
4083 * __pci_request_region - Reserved PCI I/O and memory resource
4084 * @pdev: PCI device whose resources are to be reserved
4085 * @bar: BAR to be reserved
4086 * @res_name: Name to be associated with resource.
4087 * @exclusive: whether the region access is exclusive or not
4089 * Mark the PCI region associated with PCI device @pdev BAR @bar as
4090 * being reserved by owner @res_name. Do not access any
4091 * address inside the PCI regions unless this call returns
4094 * If @exclusive is set, then the region is marked so that userspace
4095 * is explicitly not allowed to map the resource via /dev/mem or
4096 * sysfs MMIO access.
4098 * Returns 0 on success, or %EBUSY on error. A warning
4099 * message is also printed on failure.
4101 static int __pci_request_region(struct pci_dev *pdev, int bar,
4102 const char *res_name, int exclusive)
4104 struct pci_devres *dr;
4106 if (pci_resource_len(pdev, bar) == 0)
4109 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
4110 if (!request_region(pci_resource_start(pdev, bar),
4111 pci_resource_len(pdev, bar), res_name))
4113 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
4114 if (!__request_mem_region(pci_resource_start(pdev, bar),
4115 pci_resource_len(pdev, bar), res_name,
4120 dr = find_pci_dr(pdev);
4122 dr->region_mask |= 1 << bar;
4127 pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
4128 &pdev->resource[bar]);
4133 * pci_request_region - Reserve PCI I/O and memory resource
4134 * @pdev: PCI device whose resources are to be reserved
4135 * @bar: BAR to be reserved
4136 * @res_name: Name to be associated with resource
4138 * Mark the PCI region associated with PCI device @pdev BAR @bar as
4139 * being reserved by owner @res_name. Do not access any
4140 * address inside the PCI regions unless this call returns
4143 * Returns 0 on success, or %EBUSY on error. A warning
4144 * message is also printed on failure.
4146 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
4148 return __pci_request_region(pdev, bar, res_name, 0);
4150 EXPORT_SYMBOL(pci_request_region);
4153 * pci_release_selected_regions - Release selected PCI I/O and memory resources
4154 * @pdev: PCI device whose resources were previously reserved
4155 * @bars: Bitmask of BARs to be released
4157 * Release selected PCI I/O and memory resources previously reserved.
4158 * Call this function only after all use of the PCI regions has ceased.
4160 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
4164 for (i = 0; i < PCI_STD_NUM_BARS; i++)
4165 if (bars & (1 << i))
4166 pci_release_region(pdev, i);
4168 EXPORT_SYMBOL(pci_release_selected_regions);
4170 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
4171 const char *res_name, int excl)
4175 for (i = 0; i < PCI_STD_NUM_BARS; i++)
4176 if (bars & (1 << i))
4177 if (__pci_request_region(pdev, i, res_name, excl))
4183 if (bars & (1 << i))
4184 pci_release_region(pdev, i);
4191 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
4192 * @pdev: PCI device whose resources are to be reserved
4193 * @bars: Bitmask of BARs to be requested
4194 * @res_name: Name to be associated with resource
4196 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
4197 const char *res_name)
4199 return __pci_request_selected_regions(pdev, bars, res_name, 0);
4201 EXPORT_SYMBOL(pci_request_selected_regions);
4203 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
4204 const char *res_name)
4206 return __pci_request_selected_regions(pdev, bars, res_name,
4207 IORESOURCE_EXCLUSIVE);
4209 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
4212 * pci_release_regions - Release reserved PCI I/O and memory resources
4213 * @pdev: PCI device whose resources were previously reserved by
4214 * pci_request_regions()
4216 * Releases all PCI I/O and memory resources previously reserved by a
4217 * successful call to pci_request_regions(). Call this function only
4218 * after all use of the PCI regions has ceased.
4221 void pci_release_regions(struct pci_dev *pdev)
4223 pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1);
4225 EXPORT_SYMBOL(pci_release_regions);
4228 * pci_request_regions - Reserve PCI I/O and memory resources
4229 * @pdev: PCI device whose resources are to be reserved
4230 * @res_name: Name to be associated with resource.
4232 * Mark all PCI regions associated with PCI device @pdev as
4233 * being reserved by owner @res_name. Do not access any
4234 * address inside the PCI regions unless this call returns
4237 * Returns 0 on success, or %EBUSY on error. A warning
4238 * message is also printed on failure.
4240 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
4242 return pci_request_selected_regions(pdev,
4243 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
4245 EXPORT_SYMBOL(pci_request_regions);
4248 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
4249 * @pdev: PCI device whose resources are to be reserved
4250 * @res_name: Name to be associated with resource.
4252 * Mark all PCI regions associated with PCI device @pdev as being reserved
4253 * by owner @res_name. Do not access any address inside the PCI regions
4254 * unless this call returns successfully.
4256 * pci_request_regions_exclusive() will mark the region so that /dev/mem
4257 * and the sysfs MMIO access will not be allowed.
4259 * Returns 0 on success, or %EBUSY on error. A warning message is also
4260 * printed on failure.
4262 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
4264 return pci_request_selected_regions_exclusive(pdev,
4265 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
4267 EXPORT_SYMBOL(pci_request_regions_exclusive);
4270 * Record the PCI IO range (expressed as CPU physical address + size).
4271 * Return a negative value if an error has occurred, zero otherwise
4273 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
4274 resource_size_t size)
4278 struct logic_pio_hwaddr *range;
4280 if (!size || addr + size < addr)
4283 range = kzalloc(sizeof(*range), GFP_ATOMIC);
4287 range->fwnode = fwnode;
4289 range->hw_start = addr;
4290 range->flags = LOGIC_PIO_CPU_MMIO;
4292 ret = logic_pio_register_range(range);
4296 /* Ignore duplicates due to deferred probing */
4304 phys_addr_t pci_pio_to_address(unsigned long pio)
4307 if (pio < MMIO_UPPER_LIMIT)
4308 return logic_pio_to_hwaddr(pio);
4311 return (phys_addr_t) OF_BAD_ADDR;
4313 EXPORT_SYMBOL_GPL(pci_pio_to_address);
4315 unsigned long __weak pci_address_to_pio(phys_addr_t address)
4318 return logic_pio_trans_cpuaddr(address);
4320 if (address > IO_SPACE_LIMIT)
4321 return (unsigned long)-1;
4323 return (unsigned long) address;
4328 * pci_remap_iospace - Remap the memory mapped I/O space
4329 * @res: Resource describing the I/O space
4330 * @phys_addr: physical address of range to be mapped
4332 * Remap the memory mapped I/O space described by the @res and the CPU
4333 * physical address @phys_addr into virtual address space. Only
4334 * architectures that have memory mapped IO functions defined (and the
4335 * PCI_IOBASE value defined) should call this function.
4337 #ifndef pci_remap_iospace
4338 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
4340 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4341 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4343 if (!(res->flags & IORESOURCE_IO))
4346 if (res->end > IO_SPACE_LIMIT)
4349 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
4350 pgprot_device(PAGE_KERNEL));
4353 * This architecture does not have memory mapped I/O space,
4354 * so this function should never be called
4356 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
4360 EXPORT_SYMBOL(pci_remap_iospace);
4364 * pci_unmap_iospace - Unmap the memory mapped I/O space
4365 * @res: resource to be unmapped
4367 * Unmap the CPU virtual address @res from virtual address space. Only
4368 * architectures that have memory mapped IO functions defined (and the
4369 * PCI_IOBASE value defined) should call this function.
4371 void pci_unmap_iospace(struct resource *res)
4373 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4374 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4376 vunmap_range(vaddr, vaddr + resource_size(res));
4379 EXPORT_SYMBOL(pci_unmap_iospace);
4381 static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
4383 struct resource **res = ptr;
4385 pci_unmap_iospace(*res);
4389 * devm_pci_remap_iospace - Managed pci_remap_iospace()
4390 * @dev: Generic device to remap IO address for
4391 * @res: Resource describing the I/O space
4392 * @phys_addr: physical address of range to be mapped
4394 * Managed pci_remap_iospace(). Map is automatically unmapped on driver
4397 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
4398 phys_addr_t phys_addr)
4400 const struct resource **ptr;
4403 ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL);
4407 error = pci_remap_iospace(res, phys_addr);
4412 devres_add(dev, ptr);
4417 EXPORT_SYMBOL(devm_pci_remap_iospace);
4420 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4421 * @dev: Generic device to remap IO address for
4422 * @offset: Resource address to map
4423 * @size: Size of map
4425 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
4428 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
4429 resource_size_t offset,
4430 resource_size_t size)
4432 void __iomem **ptr, *addr;
4434 ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
4438 addr = pci_remap_cfgspace(offset, size);
4441 devres_add(dev, ptr);
4447 EXPORT_SYMBOL(devm_pci_remap_cfgspace);
4450 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4451 * @dev: generic device to handle the resource for
4452 * @res: configuration space resource to be handled
4454 * Checks that a resource is a valid memory region, requests the memory
4455 * region and ioremaps with pci_remap_cfgspace() API that ensures the
4456 * proper PCI configuration space memory attributes are guaranteed.
4458 * All operations are managed and will be undone on driver detach.
4460 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
4461 * on failure. Usage example::
4463 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4464 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4466 * return PTR_ERR(base);
4468 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
4469 struct resource *res)
4471 resource_size_t size;
4473 void __iomem *dest_ptr;
4477 if (!res || resource_type(res) != IORESOURCE_MEM) {
4478 dev_err(dev, "invalid resource\n");
4479 return IOMEM_ERR_PTR(-EINVAL);
4482 size = resource_size(res);
4485 name = devm_kasprintf(dev, GFP_KERNEL, "%s %s", dev_name(dev),
4488 name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
4490 return IOMEM_ERR_PTR(-ENOMEM);
4492 if (!devm_request_mem_region(dev, res->start, size, name)) {
4493 dev_err(dev, "can't request region for resource %pR\n", res);
4494 return IOMEM_ERR_PTR(-EBUSY);
4497 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
4499 dev_err(dev, "ioremap failed for resource %pR\n", res);
4500 devm_release_mem_region(dev, res->start, size);
4501 dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
4506 EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
4508 static void __pci_set_master(struct pci_dev *dev, bool enable)
4512 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
4514 cmd = old_cmd | PCI_COMMAND_MASTER;
4516 cmd = old_cmd & ~PCI_COMMAND_MASTER;
4517 if (cmd != old_cmd) {
4518 pci_dbg(dev, "%s bus mastering\n",
4519 enable ? "enabling" : "disabling");
4520 pci_write_config_word(dev, PCI_COMMAND, cmd);
4522 dev->is_busmaster = enable;
4526 * pcibios_setup - process "pci=" kernel boot arguments
4527 * @str: string used to pass in "pci=" kernel boot arguments
4529 * Process kernel boot arguments. This is the default implementation.
4530 * Architecture specific implementations can override this as necessary.
4532 char * __weak __init pcibios_setup(char *str)
4538 * pcibios_set_master - enable PCI bus-mastering for device dev
4539 * @dev: the PCI device to enable
4541 * Enables PCI bus-mastering for the device. This is the default
4542 * implementation. Architecture specific implementations can override
4543 * this if necessary.
4545 void __weak pcibios_set_master(struct pci_dev *dev)
4549 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
4550 if (pci_is_pcie(dev))
4553 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
4555 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
4556 else if (lat > pcibios_max_latency)
4557 lat = pcibios_max_latency;
4561 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
4565 * pci_set_master - enables bus-mastering for device dev
4566 * @dev: the PCI device to enable
4568 * Enables bus-mastering on the device and calls pcibios_set_master()
4569 * to do the needed arch specific settings.
4571 void pci_set_master(struct pci_dev *dev)
4573 __pci_set_master(dev, true);
4574 pcibios_set_master(dev);
4576 EXPORT_SYMBOL(pci_set_master);
4579 * pci_clear_master - disables bus-mastering for device dev
4580 * @dev: the PCI device to disable
4582 void pci_clear_master(struct pci_dev *dev)
4584 __pci_set_master(dev, false);
4586 EXPORT_SYMBOL(pci_clear_master);
4589 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4590 * @dev: the PCI device for which MWI is to be enabled
4592 * Helper function for pci_set_mwi.
4593 * Originally copied from drivers/net/acenic.c.
4594 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4596 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4598 int pci_set_cacheline_size(struct pci_dev *dev)
4602 if (!pci_cache_line_size)
4605 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
4606 equal to or multiple of the right value. */
4607 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4608 if (cacheline_size >= pci_cache_line_size &&
4609 (cacheline_size % pci_cache_line_size) == 0)
4612 /* Write the correct value. */
4613 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
4615 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4616 if (cacheline_size == pci_cache_line_size)
4619 pci_dbg(dev, "cache line size of %d is not supported\n",
4620 pci_cache_line_size << 2);
4624 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
4627 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4628 * @dev: the PCI device for which MWI is enabled
4630 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4632 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4634 int pci_set_mwi(struct pci_dev *dev)
4636 #ifdef PCI_DISABLE_MWI
4642 rc = pci_set_cacheline_size(dev);
4646 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4647 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
4648 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
4649 cmd |= PCI_COMMAND_INVALIDATE;
4650 pci_write_config_word(dev, PCI_COMMAND, cmd);
4655 EXPORT_SYMBOL(pci_set_mwi);
4658 * pcim_set_mwi - a device-managed pci_set_mwi()
4659 * @dev: the PCI device for which MWI is enabled
4661 * Managed pci_set_mwi().
4663 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4665 int pcim_set_mwi(struct pci_dev *dev)
4667 struct pci_devres *dr;
4669 dr = find_pci_dr(dev);
4674 return pci_set_mwi(dev);
4676 EXPORT_SYMBOL(pcim_set_mwi);
4679 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4680 * @dev: the PCI device for which MWI is enabled
4682 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4683 * Callers are not required to check the return value.
4685 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4687 int pci_try_set_mwi(struct pci_dev *dev)
4689 #ifdef PCI_DISABLE_MWI
4692 return pci_set_mwi(dev);
4695 EXPORT_SYMBOL(pci_try_set_mwi);
4698 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4699 * @dev: the PCI device to disable
4701 * Disables PCI Memory-Write-Invalidate transaction on the device
4703 void pci_clear_mwi(struct pci_dev *dev)
4705 #ifndef PCI_DISABLE_MWI
4708 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4709 if (cmd & PCI_COMMAND_INVALIDATE) {
4710 cmd &= ~PCI_COMMAND_INVALIDATE;
4711 pci_write_config_word(dev, PCI_COMMAND, cmd);
4715 EXPORT_SYMBOL(pci_clear_mwi);
4718 * pci_disable_parity - disable parity checking for device
4719 * @dev: the PCI device to operate on
4721 * Disable parity checking for device @dev
4723 void pci_disable_parity(struct pci_dev *dev)
4727 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4728 if (cmd & PCI_COMMAND_PARITY) {
4729 cmd &= ~PCI_COMMAND_PARITY;
4730 pci_write_config_word(dev, PCI_COMMAND, cmd);
4735 * pci_intx - enables/disables PCI INTx for device dev
4736 * @pdev: the PCI device to operate on
4737 * @enable: boolean: whether to enable or disable PCI INTx
4739 * Enables/disables PCI INTx for device @pdev
4741 void pci_intx(struct pci_dev *pdev, int enable)
4743 u16 pci_command, new;
4745 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
4748 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
4750 new = pci_command | PCI_COMMAND_INTX_DISABLE;
4752 if (new != pci_command) {
4753 struct pci_devres *dr;
4755 pci_write_config_word(pdev, PCI_COMMAND, new);
4757 dr = find_pci_dr(pdev);
4758 if (dr && !dr->restore_intx) {
4759 dr->restore_intx = 1;
4760 dr->orig_intx = !enable;
4764 EXPORT_SYMBOL_GPL(pci_intx);
4766 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
4768 struct pci_bus *bus = dev->bus;
4769 bool mask_updated = true;
4770 u32 cmd_status_dword;
4771 u16 origcmd, newcmd;
4772 unsigned long flags;
4776 * We do a single dword read to retrieve both command and status.
4777 * Document assumptions that make this possible.
4779 BUILD_BUG_ON(PCI_COMMAND % 4);
4780 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
4782 raw_spin_lock_irqsave(&pci_lock, flags);
4784 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4786 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
4789 * Check interrupt status register to see whether our device
4790 * triggered the interrupt (when masking) or the next IRQ is
4791 * already pending (when unmasking).
4793 if (mask != irq_pending) {
4794 mask_updated = false;
4798 origcmd = cmd_status_dword;
4799 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
4801 newcmd |= PCI_COMMAND_INTX_DISABLE;
4802 if (newcmd != origcmd)
4803 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
4806 raw_spin_unlock_irqrestore(&pci_lock, flags);
4808 return mask_updated;
4812 * pci_check_and_mask_intx - mask INTx on pending interrupt
4813 * @dev: the PCI device to operate on
4815 * Check if the device dev has its INTx line asserted, mask it and return
4816 * true in that case. False is returned if no interrupt was pending.
4818 bool pci_check_and_mask_intx(struct pci_dev *dev)
4820 return pci_check_and_set_intx_mask(dev, true);
4822 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
4825 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4826 * @dev: the PCI device to operate on
4828 * Check if the device dev has its INTx line asserted, unmask it if not and
4829 * return true. False is returned and the mask remains active if there was
4830 * still an interrupt pending.
4832 bool pci_check_and_unmask_intx(struct pci_dev *dev)
4834 return pci_check_and_set_intx_mask(dev, false);
4836 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4839 * pci_wait_for_pending_transaction - wait for pending transaction
4840 * @dev: the PCI device to operate on
4842 * Return 0 if transaction is pending 1 otherwise.
4844 int pci_wait_for_pending_transaction(struct pci_dev *dev)
4846 if (!pci_is_pcie(dev))
4849 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4850 PCI_EXP_DEVSTA_TRPND);
4852 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
4855 * pcie_flr - initiate a PCIe function level reset
4856 * @dev: device to reset
4858 * Initiate a function level reset unconditionally on @dev without
4859 * checking any flags and DEVCAP
4861 int pcie_flr(struct pci_dev *dev)
4863 if (!pci_wait_for_pending_transaction(dev))
4864 pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4866 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4872 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4873 * 100ms, but may silently discard requests while the FLR is in
4874 * progress. Wait 100ms before trying to access the device.
4878 return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4880 EXPORT_SYMBOL_GPL(pcie_flr);
4883 * pcie_reset_flr - initiate a PCIe function level reset
4884 * @dev: device to reset
4885 * @probe: if true, return 0 if device can be reset this way
4887 * Initiate a function level reset on @dev.
4889 int pcie_reset_flr(struct pci_dev *dev, bool probe)
4891 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4894 if (!(dev->devcap & PCI_EXP_DEVCAP_FLR))
4900 return pcie_flr(dev);
4902 EXPORT_SYMBOL_GPL(pcie_reset_flr);
4904 static int pci_af_flr(struct pci_dev *dev, bool probe)
4909 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4913 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4916 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4917 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4924 * Wait for Transaction Pending bit to clear. A word-aligned test
4925 * is used, so we use the control offset rather than status and shift
4926 * the test bit to match.
4928 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4929 PCI_AF_STATUS_TP << 8))
4930 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4932 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4938 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4939 * updated 27 July 2006; a device must complete an FLR within
4940 * 100ms, but may silently discard requests while the FLR is in
4941 * progress. Wait 100ms before trying to access the device.
4945 return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4949 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4950 * @dev: Device to reset.
4951 * @probe: if true, return 0 if the device can be reset this way.
4953 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4954 * unset, it will be reinitialized internally when going from PCI_D3hot to
4955 * PCI_D0. If that's the case and the device is not in a low-power state
4956 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4958 * NOTE: This causes the caller to sleep for twice the device power transition
4959 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4960 * by default (i.e. unless the @dev's d3hot_delay field has a different value).
4961 * Moreover, only devices in D0 can be reset by this function.
4963 static int pci_pm_reset(struct pci_dev *dev, bool probe)
4967 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4970 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4971 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4977 if (dev->current_state != PCI_D0)
4980 csr &= ~PCI_PM_CTRL_STATE_MASK;
4982 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4983 pci_dev_d3_sleep(dev);
4985 csr &= ~PCI_PM_CTRL_STATE_MASK;
4987 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4988 pci_dev_d3_sleep(dev);
4990 return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS);
4994 * pcie_wait_for_link_status - Wait for link status change
4995 * @pdev: Device whose link to wait for.
4996 * @use_lt: Use the LT bit if TRUE, or the DLLLA bit if FALSE.
4997 * @active: Waiting for active or inactive?
4999 * Return 0 if successful, or -ETIMEDOUT if status has not changed within
5000 * PCIE_LINK_RETRAIN_TIMEOUT_MS milliseconds.
5002 static int pcie_wait_for_link_status(struct pci_dev *pdev,
5003 bool use_lt, bool active)
5005 u16 lnksta_mask, lnksta_match;
5006 unsigned long end_jiffies;
5009 lnksta_mask = use_lt ? PCI_EXP_LNKSTA_LT : PCI_EXP_LNKSTA_DLLLA;
5010 lnksta_match = active ? lnksta_mask : 0;
5012 end_jiffies = jiffies + msecs_to_jiffies(PCIE_LINK_RETRAIN_TIMEOUT_MS);
5014 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnksta);
5015 if ((lnksta & lnksta_mask) == lnksta_match)
5018 } while (time_before(jiffies, end_jiffies));
5024 * pcie_retrain_link - Request a link retrain and wait for it to complete
5025 * @pdev: Device whose link to retrain.
5026 * @use_lt: Use the LT bit if TRUE, or the DLLLA bit if FALSE, for status.
5028 * Retrain completion status is retrieved from the Link Status Register
5029 * according to @use_lt. It is not verified whether the use of the DLLLA
5032 * Return 0 if successful, or -ETIMEDOUT if training has not completed
5033 * within PCIE_LINK_RETRAIN_TIMEOUT_MS milliseconds.
5035 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt)
5040 * Ensure the updated LNKCTL parameters are used during link
5041 * training by checking that there is no ongoing link training to
5042 * avoid LTSSM race as recommended in Implementation Note at the
5043 * end of PCIe r6.0.1 sec 7.5.3.7.
5045 rc = pcie_wait_for_link_status(pdev, use_lt, !use_lt);
5049 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_RL);
5050 if (pdev->clear_retrain_link) {
5052 * Due to an erratum in some devices the Retrain Link bit
5053 * needs to be cleared again manually to allow the link
5054 * training to succeed.
5056 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_RL);
5059 return pcie_wait_for_link_status(pdev, use_lt, !use_lt);
5063 * pcie_wait_for_link_delay - Wait until link is active or inactive
5064 * @pdev: Bridge device
5065 * @active: waiting for active or inactive?
5066 * @delay: Delay to wait after link has become active (in ms)
5068 * Use this to wait till link becomes active or inactive.
5070 static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active,
5076 * Some controllers might not implement link active reporting. In this
5077 * case, we wait for 1000 ms + any delay requested by the caller.
5079 if (!pdev->link_active_reporting) {
5080 msleep(PCIE_LINK_RETRAIN_TIMEOUT_MS + delay);
5085 * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
5086 * after which we should expect an link active if the reset was
5087 * successful. If so, software must wait a minimum 100ms before sending
5088 * configuration requests to devices downstream this port.
5090 * If the link fails to activate, either the device was physically
5091 * removed or the link is permanently failed.
5095 rc = pcie_wait_for_link_status(pdev, false, active);
5098 rc = pcie_failed_link_retrain(pdev);
5113 * pcie_wait_for_link - Wait until link is active or inactive
5114 * @pdev: Bridge device
5115 * @active: waiting for active or inactive?
5117 * Use this to wait till link becomes active or inactive.
5119 bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
5121 return pcie_wait_for_link_delay(pdev, active, 100);
5125 * Find maximum D3cold delay required by all the devices on the bus. The
5126 * spec says 100 ms, but firmware can lower it and we allow drivers to
5127 * increase it as well.
5129 * Called with @pci_bus_sem locked for reading.
5131 static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
5133 const struct pci_dev *pdev;
5134 int min_delay = 100;
5137 list_for_each_entry(pdev, &bus->devices, bus_list) {
5138 if (pdev->d3cold_delay < min_delay)
5139 min_delay = pdev->d3cold_delay;
5140 if (pdev->d3cold_delay > max_delay)
5141 max_delay = pdev->d3cold_delay;
5144 return max(min_delay, max_delay);
5148 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
5150 * @reset_type: reset type in human-readable form
5152 * Handle necessary delays before access to the devices on the secondary
5153 * side of the bridge are permitted after D3cold to D0 transition
5154 * or Conventional Reset.
5156 * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For
5157 * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section
5160 * Return 0 on success or -ENOTTY if the first device on the secondary bus
5161 * failed to become accessible.
5163 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type)
5165 struct pci_dev *child;
5168 if (pci_dev_is_disconnected(dev))
5171 if (!pci_is_bridge(dev))
5174 down_read(&pci_bus_sem);
5177 * We only deal with devices that are present currently on the bus.
5178 * For any hot-added devices the access delay is handled in pciehp
5179 * board_added(). In case of ACPI hotplug the firmware is expected
5180 * to configure the devices before OS is notified.
5182 if (!dev->subordinate || list_empty(&dev->subordinate->devices)) {
5183 up_read(&pci_bus_sem);
5187 /* Take d3cold_delay requirements into account */
5188 delay = pci_bus_max_d3cold_delay(dev->subordinate);
5190 up_read(&pci_bus_sem);
5194 child = list_first_entry(&dev->subordinate->devices, struct pci_dev,
5196 up_read(&pci_bus_sem);
5199 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before
5200 * accessing the device after reset (that is 1000 ms + 100 ms).
5202 if (!pci_is_pcie(dev)) {
5203 pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);
5204 msleep(1000 + delay);
5209 * For PCIe downstream and root ports that do not support speeds
5210 * greater than 5 GT/s need to wait minimum 100 ms. For higher
5211 * speeds (gen3) we need to wait first for the data link layer to
5214 * However, 100 ms is the minimum and the PCIe spec says the
5215 * software must allow at least 1s before it can determine that the
5216 * device that did not respond is a broken device. Also device can
5217 * take longer than that to respond if it indicates so through Request
5218 * Retry Status completions.
5220 * Therefore we wait for 100 ms and check for the device presence
5221 * until the timeout expires.
5223 if (!pcie_downstream_port(dev))
5226 if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {
5229 pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
5232 if (!pci_dev_wait(child, reset_type, PCI_RESET_WAIT - delay))
5236 * If the port supports active link reporting we now check
5237 * whether the link is active and if not bail out early with
5238 * the assumption that the device is not present anymore.
5240 if (!dev->link_active_reporting)
5243 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &status);
5244 if (!(status & PCI_EXP_LNKSTA_DLLLA))
5247 return pci_dev_wait(child, reset_type,
5248 PCIE_RESET_READY_POLL_MS - PCI_RESET_WAIT);
5251 pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",
5253 if (!pcie_wait_for_link_delay(dev, true, delay)) {
5254 /* Did not train, no need to wait any further */
5255 pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n");
5259 return pci_dev_wait(child, reset_type,
5260 PCIE_RESET_READY_POLL_MS - delay);
5263 void pci_reset_secondary_bus(struct pci_dev *dev)
5267 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
5268 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
5269 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
5272 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
5273 * this to 2ms to ensure that we meet the minimum requirement.
5277 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
5278 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
5281 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
5283 pci_reset_secondary_bus(dev);
5287 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
5288 * @dev: Bridge device
5290 * Use the bridge control register to assert reset on the secondary bus.
5291 * Devices on the secondary bus are left in power-on state.
5293 int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
5295 pcibios_reset_secondary_bus(dev);
5297 return pci_bridge_wait_for_secondary_bus(dev, "bus reset");
5299 EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
5301 static int pci_parent_bus_reset(struct pci_dev *dev, bool probe)
5303 struct pci_dev *pdev;
5305 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
5306 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5309 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
5316 return pci_bridge_secondary_bus_reset(dev->bus->self);
5319 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, bool probe)
5323 if (!hotplug || !try_module_get(hotplug->owner))
5326 if (hotplug->ops->reset_slot)
5327 rc = hotplug->ops->reset_slot(hotplug, probe);
5329 module_put(hotplug->owner);
5334 static int pci_dev_reset_slot_function(struct pci_dev *dev, bool probe)
5336 if (dev->multifunction || dev->subordinate || !dev->slot ||
5337 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5340 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
5343 static int pci_reset_bus_function(struct pci_dev *dev, bool probe)
5347 rc = pci_dev_reset_slot_function(dev, probe);
5350 return pci_parent_bus_reset(dev, probe);
5353 void pci_dev_lock(struct pci_dev *dev)
5355 /* block PM suspend, driver probe, etc. */
5356 device_lock(&dev->dev);
5357 pci_cfg_access_lock(dev);
5359 EXPORT_SYMBOL_GPL(pci_dev_lock);
5361 /* Return 1 on successful lock, 0 on contention */
5362 int pci_dev_trylock(struct pci_dev *dev)
5364 if (device_trylock(&dev->dev)) {
5365 if (pci_cfg_access_trylock(dev))
5367 device_unlock(&dev->dev);
5372 EXPORT_SYMBOL_GPL(pci_dev_trylock);
5374 void pci_dev_unlock(struct pci_dev *dev)
5376 pci_cfg_access_unlock(dev);
5377 device_unlock(&dev->dev);
5379 EXPORT_SYMBOL_GPL(pci_dev_unlock);
5381 static void pci_dev_save_and_disable(struct pci_dev *dev)
5383 const struct pci_error_handlers *err_handler =
5384 dev->driver ? dev->driver->err_handler : NULL;
5387 * dev->driver->err_handler->reset_prepare() is protected against
5388 * races with ->remove() by the device lock, which must be held by
5391 if (err_handler && err_handler->reset_prepare)
5392 err_handler->reset_prepare(dev);
5395 * Wake-up device prior to save. PM registers default to D0 after
5396 * reset and a simple register restore doesn't reliably return
5397 * to a non-D0 state anyway.
5399 pci_set_power_state(dev, PCI_D0);
5401 pci_save_state(dev);
5403 * Disable the device by clearing the Command register, except for
5404 * INTx-disable which is set. This not only disables MMIO and I/O port
5405 * BARs, but also prevents the device from being Bus Master, preventing
5406 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
5407 * compliant devices, INTx-disable prevents legacy interrupts.
5409 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
5412 static void pci_dev_restore(struct pci_dev *dev)
5414 const struct pci_error_handlers *err_handler =
5415 dev->driver ? dev->driver->err_handler : NULL;
5417 pci_restore_state(dev);
5420 * dev->driver->err_handler->reset_done() is protected against
5421 * races with ->remove() by the device lock, which must be held by
5424 if (err_handler && err_handler->reset_done)
5425 err_handler->reset_done(dev);
5428 /* dev->reset_methods[] is a 0-terminated list of indices into this array */
5429 static const struct pci_reset_fn_method pci_reset_fn_methods[] = {
5431 { pci_dev_specific_reset, .name = "device_specific" },
5432 { pci_dev_acpi_reset, .name = "acpi" },
5433 { pcie_reset_flr, .name = "flr" },
5434 { pci_af_flr, .name = "af_flr" },
5435 { pci_pm_reset, .name = "pm" },
5436 { pci_reset_bus_function, .name = "bus" },
5439 static ssize_t reset_method_show(struct device *dev,
5440 struct device_attribute *attr, char *buf)
5442 struct pci_dev *pdev = to_pci_dev(dev);
5446 for (i = 0; i < PCI_NUM_RESET_METHODS; i++) {
5447 m = pdev->reset_methods[i];
5451 len += sysfs_emit_at(buf, len, "%s%s", len ? " " : "",
5452 pci_reset_fn_methods[m].name);
5456 len += sysfs_emit_at(buf, len, "\n");
5461 static int reset_method_lookup(const char *name)
5465 for (m = 1; m < PCI_NUM_RESET_METHODS; m++) {
5466 if (sysfs_streq(name, pci_reset_fn_methods[m].name))
5470 return 0; /* not found */
5473 static ssize_t reset_method_store(struct device *dev,
5474 struct device_attribute *attr,
5475 const char *buf, size_t count)
5477 struct pci_dev *pdev = to_pci_dev(dev);
5478 char *options, *name;
5480 u8 reset_methods[PCI_NUM_RESET_METHODS] = { 0 };
5482 if (sysfs_streq(buf, "")) {
5483 pdev->reset_methods[0] = 0;
5484 pci_warn(pdev, "All device reset methods disabled by user");
5488 if (sysfs_streq(buf, "default")) {
5489 pci_init_reset_methods(pdev);
5493 options = kstrndup(buf, count, GFP_KERNEL);
5498 while ((name = strsep(&options, " ")) != NULL) {
5499 if (sysfs_streq(name, ""))
5504 m = reset_method_lookup(name);
5506 pci_err(pdev, "Invalid reset method '%s'", name);
5510 if (pci_reset_fn_methods[m].reset_fn(pdev, PCI_RESET_PROBE)) {
5511 pci_err(pdev, "Unsupported reset method '%s'", name);
5515 if (n == PCI_NUM_RESET_METHODS - 1) {
5516 pci_err(pdev, "Too many reset methods\n");
5520 reset_methods[n++] = m;
5523 reset_methods[n] = 0;
5525 /* Warn if dev-specific supported but not highest priority */
5526 if (pci_reset_fn_methods[1].reset_fn(pdev, PCI_RESET_PROBE) == 0 &&
5527 reset_methods[0] != 1)
5528 pci_warn(pdev, "Device-specific reset disabled/de-prioritized by user");
5529 memcpy(pdev->reset_methods, reset_methods, sizeof(pdev->reset_methods));
5534 /* Leave previous methods unchanged */
5538 static DEVICE_ATTR_RW(reset_method);
5540 static struct attribute *pci_dev_reset_method_attrs[] = {
5541 &dev_attr_reset_method.attr,
5545 static umode_t pci_dev_reset_method_attr_is_visible(struct kobject *kobj,
5546 struct attribute *a, int n)
5548 struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
5550 if (!pci_reset_supported(pdev))
5556 const struct attribute_group pci_dev_reset_method_attr_group = {
5557 .attrs = pci_dev_reset_method_attrs,
5558 .is_visible = pci_dev_reset_method_attr_is_visible,
5562 * __pci_reset_function_locked - reset a PCI device function while holding
5563 * the @dev mutex lock.
5564 * @dev: PCI device to reset
5566 * Some devices allow an individual function to be reset without affecting
5567 * other functions in the same device. The PCI device must be responsive
5568 * to PCI config space in order to use this function.
5570 * The device function is presumed to be unused and the caller is holding
5571 * the device mutex lock when this function is called.
5573 * Resetting the device will make the contents of PCI configuration space
5574 * random, so any caller of this must be prepared to reinitialise the
5575 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
5578 * Returns 0 if the device function was successfully reset or negative if the
5579 * device doesn't support resetting a single function.
5581 int __pci_reset_function_locked(struct pci_dev *dev)
5588 * A reset method returns -ENOTTY if it doesn't support this device and
5589 * we should try the next method.
5591 * If it returns 0 (success), we're finished. If it returns any other
5592 * error, we're also finished: this indicates that further reset
5593 * mechanisms might be broken on the device.
5595 for (i = 0; i < PCI_NUM_RESET_METHODS; i++) {
5596 m = dev->reset_methods[i];
5600 rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_DO_RESET);
5609 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
5612 * pci_init_reset_methods - check whether device can be safely reset
5613 * and store supported reset mechanisms.
5614 * @dev: PCI device to check for reset mechanisms
5616 * Some devices allow an individual function to be reset without affecting
5617 * other functions in the same device. The PCI device must be in D0-D3hot
5620 * Stores reset mechanisms supported by device in reset_methods byte array
5621 * which is a member of struct pci_dev.
5623 void pci_init_reset_methods(struct pci_dev *dev)
5627 BUILD_BUG_ON(ARRAY_SIZE(pci_reset_fn_methods) != PCI_NUM_RESET_METHODS);
5632 for (m = 1; m < PCI_NUM_RESET_METHODS; m++) {
5633 rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_PROBE);
5635 dev->reset_methods[i++] = m;
5636 else if (rc != -ENOTTY)
5640 dev->reset_methods[i] = 0;
5644 * pci_reset_function - quiesce and reset a PCI device function
5645 * @dev: PCI device to reset
5647 * Some devices allow an individual function to be reset without affecting
5648 * other functions in the same device. The PCI device must be responsive
5649 * to PCI config space in order to use this function.
5651 * This function does not just reset the PCI portion of a device, but
5652 * clears all the state associated with the device. This function differs
5653 * from __pci_reset_function_locked() in that it saves and restores device state
5654 * over the reset and takes the PCI device lock.
5656 * Returns 0 if the device function was successfully reset or negative if the
5657 * device doesn't support resetting a single function.
5659 int pci_reset_function(struct pci_dev *dev)
5663 if (!pci_reset_supported(dev))
5667 pci_dev_save_and_disable(dev);
5669 rc = __pci_reset_function_locked(dev);
5671 pci_dev_restore(dev);
5672 pci_dev_unlock(dev);
5676 EXPORT_SYMBOL_GPL(pci_reset_function);
5679 * pci_reset_function_locked - quiesce and reset a PCI device function
5680 * @dev: PCI device to reset
5682 * Some devices allow an individual function to be reset without affecting
5683 * other functions in the same device. The PCI device must be responsive
5684 * to PCI config space in order to use this function.
5686 * This function does not just reset the PCI portion of a device, but
5687 * clears all the state associated with the device. This function differs
5688 * from __pci_reset_function_locked() in that it saves and restores device state
5689 * over the reset. It also differs from pci_reset_function() in that it
5690 * requires the PCI device lock to be held.
5692 * Returns 0 if the device function was successfully reset or negative if the
5693 * device doesn't support resetting a single function.
5695 int pci_reset_function_locked(struct pci_dev *dev)
5699 if (!pci_reset_supported(dev))
5702 pci_dev_save_and_disable(dev);
5704 rc = __pci_reset_function_locked(dev);
5706 pci_dev_restore(dev);
5710 EXPORT_SYMBOL_GPL(pci_reset_function_locked);
5713 * pci_try_reset_function - quiesce and reset a PCI device function
5714 * @dev: PCI device to reset
5716 * Same as above, except return -EAGAIN if unable to lock device.
5718 int pci_try_reset_function(struct pci_dev *dev)
5722 if (!pci_reset_supported(dev))
5725 if (!pci_dev_trylock(dev))
5728 pci_dev_save_and_disable(dev);
5729 rc = __pci_reset_function_locked(dev);
5730 pci_dev_restore(dev);
5731 pci_dev_unlock(dev);
5735 EXPORT_SYMBOL_GPL(pci_try_reset_function);
5737 /* Do any devices on or below this bus prevent a bus reset? */
5738 static bool pci_bus_resettable(struct pci_bus *bus)
5740 struct pci_dev *dev;
5743 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5746 list_for_each_entry(dev, &bus->devices, bus_list) {
5747 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5748 (dev->subordinate && !pci_bus_resettable(dev->subordinate)))
5755 /* Lock devices from the top of the tree down */
5756 static void pci_bus_lock(struct pci_bus *bus)
5758 struct pci_dev *dev;
5760 list_for_each_entry(dev, &bus->devices, bus_list) {
5762 if (dev->subordinate)
5763 pci_bus_lock(dev->subordinate);
5767 /* Unlock devices from the bottom of the tree up */
5768 static void pci_bus_unlock(struct pci_bus *bus)
5770 struct pci_dev *dev;
5772 list_for_each_entry(dev, &bus->devices, bus_list) {
5773 if (dev->subordinate)
5774 pci_bus_unlock(dev->subordinate);
5775 pci_dev_unlock(dev);
5779 /* Return 1 on successful lock, 0 on contention */
5780 static int pci_bus_trylock(struct pci_bus *bus)
5782 struct pci_dev *dev;
5784 list_for_each_entry(dev, &bus->devices, bus_list) {
5785 if (!pci_dev_trylock(dev))
5787 if (dev->subordinate) {
5788 if (!pci_bus_trylock(dev->subordinate)) {
5789 pci_dev_unlock(dev);
5797 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
5798 if (dev->subordinate)
5799 pci_bus_unlock(dev->subordinate);
5800 pci_dev_unlock(dev);
5805 /* Do any devices on or below this slot prevent a bus reset? */
5806 static bool pci_slot_resettable(struct pci_slot *slot)
5808 struct pci_dev *dev;
5810 if (slot->bus->self &&
5811 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5814 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5815 if (!dev->slot || dev->slot != slot)
5817 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5818 (dev->subordinate && !pci_bus_resettable(dev->subordinate)))
5825 /* Lock devices from the top of the tree down */
5826 static void pci_slot_lock(struct pci_slot *slot)
5828 struct pci_dev *dev;
5830 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5831 if (!dev->slot || dev->slot != slot)
5834 if (dev->subordinate)
5835 pci_bus_lock(dev->subordinate);
5839 /* Unlock devices from the bottom of the tree up */
5840 static void pci_slot_unlock(struct pci_slot *slot)
5842 struct pci_dev *dev;
5844 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5845 if (!dev->slot || dev->slot != slot)
5847 if (dev->subordinate)
5848 pci_bus_unlock(dev->subordinate);
5849 pci_dev_unlock(dev);
5853 /* Return 1 on successful lock, 0 on contention */
5854 static int pci_slot_trylock(struct pci_slot *slot)
5856 struct pci_dev *dev;
5858 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5859 if (!dev->slot || dev->slot != slot)
5861 if (!pci_dev_trylock(dev))
5863 if (dev->subordinate) {
5864 if (!pci_bus_trylock(dev->subordinate)) {
5865 pci_dev_unlock(dev);
5873 list_for_each_entry_continue_reverse(dev,
5874 &slot->bus->devices, bus_list) {
5875 if (!dev->slot || dev->slot != slot)
5877 if (dev->subordinate)
5878 pci_bus_unlock(dev->subordinate);
5879 pci_dev_unlock(dev);
5885 * Save and disable devices from the top of the tree down while holding
5886 * the @dev mutex lock for the entire tree.
5888 static void pci_bus_save_and_disable_locked(struct pci_bus *bus)
5890 struct pci_dev *dev;
5892 list_for_each_entry(dev, &bus->devices, bus_list) {
5893 pci_dev_save_and_disable(dev);
5894 if (dev->subordinate)
5895 pci_bus_save_and_disable_locked(dev->subordinate);
5900 * Restore devices from top of the tree down while holding @dev mutex lock
5901 * for the entire tree. Parent bridges need to be restored before we can
5902 * get to subordinate devices.
5904 static void pci_bus_restore_locked(struct pci_bus *bus)
5906 struct pci_dev *dev;
5908 list_for_each_entry(dev, &bus->devices, bus_list) {
5909 pci_dev_restore(dev);
5910 if (dev->subordinate)
5911 pci_bus_restore_locked(dev->subordinate);
5916 * Save and disable devices from the top of the tree down while holding
5917 * the @dev mutex lock for the entire tree.
5919 static void pci_slot_save_and_disable_locked(struct pci_slot *slot)
5921 struct pci_dev *dev;
5923 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5924 if (!dev->slot || dev->slot != slot)
5926 pci_dev_save_and_disable(dev);
5927 if (dev->subordinate)
5928 pci_bus_save_and_disable_locked(dev->subordinate);
5933 * Restore devices from top of the tree down while holding @dev mutex lock
5934 * for the entire tree. Parent bridges need to be restored before we can
5935 * get to subordinate devices.
5937 static void pci_slot_restore_locked(struct pci_slot *slot)
5939 struct pci_dev *dev;
5941 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5942 if (!dev->slot || dev->slot != slot)
5944 pci_dev_restore(dev);
5945 if (dev->subordinate)
5946 pci_bus_restore_locked(dev->subordinate);
5950 static int pci_slot_reset(struct pci_slot *slot, bool probe)
5954 if (!slot || !pci_slot_resettable(slot))
5958 pci_slot_lock(slot);
5962 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
5965 pci_slot_unlock(slot);
5971 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5972 * @slot: PCI slot to probe
5974 * Return 0 if slot can be reset, negative if a slot reset is not supported.
5976 int pci_probe_reset_slot(struct pci_slot *slot)
5978 return pci_slot_reset(slot, PCI_RESET_PROBE);
5980 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
5983 * __pci_reset_slot - Try to reset a PCI slot
5984 * @slot: PCI slot to reset
5986 * A PCI bus may host multiple slots, each slot may support a reset mechanism
5987 * independent of other slots. For instance, some slots may support slot power
5988 * control. In the case of a 1:1 bus to slot architecture, this function may
5989 * wrap the bus reset to avoid spurious slot related events such as hotplug.
5990 * Generally a slot reset should be attempted before a bus reset. All of the
5991 * function of the slot and any subordinate buses behind the slot are reset
5992 * through this function. PCI config space of all devices in the slot and
5993 * behind the slot is saved before and restored after reset.
5995 * Same as above except return -EAGAIN if the slot cannot be locked
5997 static int __pci_reset_slot(struct pci_slot *slot)
6001 rc = pci_slot_reset(slot, PCI_RESET_PROBE);
6005 if (pci_slot_trylock(slot)) {
6006 pci_slot_save_and_disable_locked(slot);
6008 rc = pci_reset_hotplug_slot(slot->hotplug, PCI_RESET_DO_RESET);
6009 pci_slot_restore_locked(slot);
6010 pci_slot_unlock(slot);
6017 static int pci_bus_reset(struct pci_bus *bus, bool probe)
6021 if (!bus->self || !pci_bus_resettable(bus))
6031 ret = pci_bridge_secondary_bus_reset(bus->self);
6033 pci_bus_unlock(bus);
6039 * pci_bus_error_reset - reset the bridge's subordinate bus
6040 * @bridge: The parent device that connects to the bus to reset
6042 * This function will first try to reset the slots on this bus if the method is
6043 * available. If slot reset fails or is not available, this will fall back to a
6044 * secondary bus reset.
6046 int pci_bus_error_reset(struct pci_dev *bridge)
6048 struct pci_bus *bus = bridge->subordinate;
6049 struct pci_slot *slot;
6054 mutex_lock(&pci_slot_mutex);
6055 if (list_empty(&bus->slots))
6058 list_for_each_entry(slot, &bus->slots, list)
6059 if (pci_probe_reset_slot(slot))
6062 list_for_each_entry(slot, &bus->slots, list)
6063 if (pci_slot_reset(slot, PCI_RESET_DO_RESET))
6066 mutex_unlock(&pci_slot_mutex);
6069 mutex_unlock(&pci_slot_mutex);
6070 return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET);
6074 * pci_probe_reset_bus - probe whether a PCI bus can be reset
6075 * @bus: PCI bus to probe
6077 * Return 0 if bus can be reset, negative if a bus reset is not supported.
6079 int pci_probe_reset_bus(struct pci_bus *bus)
6081 return pci_bus_reset(bus, PCI_RESET_PROBE);
6083 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
6086 * __pci_reset_bus - Try to reset a PCI bus
6087 * @bus: top level PCI bus to reset
6089 * Same as above except return -EAGAIN if the bus cannot be locked
6091 static int __pci_reset_bus(struct pci_bus *bus)
6095 rc = pci_bus_reset(bus, PCI_RESET_PROBE);
6099 if (pci_bus_trylock(bus)) {
6100 pci_bus_save_and_disable_locked(bus);
6102 rc = pci_bridge_secondary_bus_reset(bus->self);
6103 pci_bus_restore_locked(bus);
6104 pci_bus_unlock(bus);
6112 * pci_reset_bus - Try to reset a PCI bus
6113 * @pdev: top level PCI device to reset via slot/bus
6115 * Same as above except return -EAGAIN if the bus cannot be locked
6117 int pci_reset_bus(struct pci_dev *pdev)
6119 return (!pci_probe_reset_slot(pdev->slot)) ?
6120 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);
6122 EXPORT_SYMBOL_GPL(pci_reset_bus);
6125 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
6126 * @dev: PCI device to query
6128 * Returns mmrbc: maximum designed memory read count in bytes or
6129 * appropriate error value.
6131 int pcix_get_max_mmrbc(struct pci_dev *dev)
6136 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
6140 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
6143 return 512 << FIELD_GET(PCI_X_STATUS_MAX_READ, stat);
6145 EXPORT_SYMBOL(pcix_get_max_mmrbc);
6148 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
6149 * @dev: PCI device to query
6151 * Returns mmrbc: maximum memory read count in bytes or appropriate error
6154 int pcix_get_mmrbc(struct pci_dev *dev)
6159 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
6163 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
6166 return 512 << FIELD_GET(PCI_X_CMD_MAX_READ, cmd);
6168 EXPORT_SYMBOL(pcix_get_mmrbc);
6171 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
6172 * @dev: PCI device to query
6173 * @mmrbc: maximum memory read count in bytes
6174 * valid values are 512, 1024, 2048, 4096
6176 * If possible sets maximum memory read byte count, some bridges have errata
6177 * that prevent this.
6179 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
6185 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
6188 v = ffs(mmrbc) - 10;
6190 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
6194 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
6197 if (v > FIELD_GET(PCI_X_STATUS_MAX_READ, stat))
6200 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
6203 o = FIELD_GET(PCI_X_CMD_MAX_READ, cmd);
6205 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
6208 cmd &= ~PCI_X_CMD_MAX_READ;
6209 cmd |= FIELD_PREP(PCI_X_CMD_MAX_READ, v);
6210 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
6215 EXPORT_SYMBOL(pcix_set_mmrbc);
6218 * pcie_get_readrq - get PCI Express read request size
6219 * @dev: PCI device to query
6221 * Returns maximum memory read request in bytes or appropriate error value.
6223 int pcie_get_readrq(struct pci_dev *dev)
6227 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
6229 return 128 << FIELD_GET(PCI_EXP_DEVCTL_READRQ, ctl);
6231 EXPORT_SYMBOL(pcie_get_readrq);
6234 * pcie_set_readrq - set PCI Express maximum memory read request
6235 * @dev: PCI device to query
6236 * @rq: maximum memory read count in bytes
6237 * valid values are 128, 256, 512, 1024, 2048, 4096
6239 * If possible sets maximum memory read request in bytes
6241 int pcie_set_readrq(struct pci_dev *dev, int rq)
6245 struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus);
6247 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
6251 * If using the "performance" PCIe config, we clamp the read rq
6252 * size to the max packet size to keep the host bridge from
6253 * generating requests larger than we can cope with.
6255 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
6256 int mps = pcie_get_mps(dev);
6262 v = FIELD_PREP(PCI_EXP_DEVCTL_READRQ, ffs(rq) - 8);
6264 if (bridge->no_inc_mrrs) {
6265 int max_mrrs = pcie_get_readrq(dev);
6267 if (rq > max_mrrs) {
6268 pci_info(dev, "can't set Max_Read_Request_Size to %d; max is %d\n", rq, max_mrrs);
6273 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
6274 PCI_EXP_DEVCTL_READRQ, v);
6276 return pcibios_err_to_errno(ret);
6278 EXPORT_SYMBOL(pcie_set_readrq);
6281 * pcie_get_mps - get PCI Express maximum payload size
6282 * @dev: PCI device to query
6284 * Returns maximum payload size in bytes
6286 int pcie_get_mps(struct pci_dev *dev)
6290 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
6292 return 128 << FIELD_GET(PCI_EXP_DEVCTL_PAYLOAD, ctl);
6294 EXPORT_SYMBOL(pcie_get_mps);
6297 * pcie_set_mps - set PCI Express maximum payload size
6298 * @dev: PCI device to query
6299 * @mps: maximum payload size in bytes
6300 * valid values are 128, 256, 512, 1024, 2048, 4096
6302 * If possible sets maximum payload size
6304 int pcie_set_mps(struct pci_dev *dev, int mps)
6309 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
6313 if (v > dev->pcie_mpss)
6315 v = FIELD_PREP(PCI_EXP_DEVCTL_PAYLOAD, v);
6317 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
6318 PCI_EXP_DEVCTL_PAYLOAD, v);
6320 return pcibios_err_to_errno(ret);
6322 EXPORT_SYMBOL(pcie_set_mps);
6324 static enum pci_bus_speed to_pcie_link_speed(u16 lnksta)
6326 return pcie_link_speed[FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta)];
6329 int pcie_link_speed_mbps(struct pci_dev *pdev)
6334 err = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnksta);
6338 switch (to_pcie_link_speed(lnksta)) {
6339 case PCIE_SPEED_2_5GT:
6341 case PCIE_SPEED_5_0GT:
6343 case PCIE_SPEED_8_0GT:
6345 case PCIE_SPEED_16_0GT:
6347 case PCIE_SPEED_32_0GT:
6349 case PCIE_SPEED_64_0GT:
6357 EXPORT_SYMBOL(pcie_link_speed_mbps);
6360 * pcie_bandwidth_available - determine minimum link settings of a PCIe
6361 * device and its bandwidth limitation
6362 * @dev: PCI device to query
6363 * @limiting_dev: storage for device causing the bandwidth limitation
6364 * @speed: storage for speed of limiting device
6365 * @width: storage for width of limiting device
6367 * Walk up the PCI device chain and find the point where the minimum
6368 * bandwidth is available. Return the bandwidth available there and (if
6369 * limiting_dev, speed, and width pointers are supplied) information about
6370 * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
6373 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
6374 enum pci_bus_speed *speed,
6375 enum pcie_link_width *width)
6378 enum pci_bus_speed next_speed;
6379 enum pcie_link_width next_width;
6383 *speed = PCI_SPEED_UNKNOWN;
6385 *width = PCIE_LNK_WIDTH_UNKNOWN;
6390 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
6392 next_speed = to_pcie_link_speed(lnksta);
6393 next_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);
6395 next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
6397 /* Check if current device limits the total bandwidth */
6398 if (!bw || next_bw <= bw) {
6402 *limiting_dev = dev;
6404 *speed = next_speed;
6406 *width = next_width;
6409 dev = pci_upstream_bridge(dev);
6414 EXPORT_SYMBOL(pcie_bandwidth_available);
6417 * pcie_get_speed_cap - query for the PCI device's link speed capability
6418 * @dev: PCI device to query
6420 * Query the PCI device speed capability. Return the maximum link speed
6421 * supported by the device.
6423 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
6425 u32 lnkcap2, lnkcap;
6428 * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The
6429 * implementation note there recommends using the Supported Link
6430 * Speeds Vector in Link Capabilities 2 when supported.
6432 * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
6433 * should use the Supported Link Speeds field in Link Capabilities,
6434 * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
6436 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
6438 /* PCIe r3.0-compliant */
6440 return PCIE_LNKCAP2_SLS2SPEED(lnkcap2);
6442 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6443 if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
6444 return PCIE_SPEED_5_0GT;
6445 else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)
6446 return PCIE_SPEED_2_5GT;
6448 return PCI_SPEED_UNKNOWN;
6450 EXPORT_SYMBOL(pcie_get_speed_cap);
6453 * pcie_get_width_cap - query for the PCI device's link width capability
6454 * @dev: PCI device to query
6456 * Query the PCI device width capability. Return the maximum link width
6457 * supported by the device.
6459 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
6463 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6465 return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap);
6467 return PCIE_LNK_WIDTH_UNKNOWN;
6469 EXPORT_SYMBOL(pcie_get_width_cap);
6472 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
6474 * @speed: storage for link speed
6475 * @width: storage for link width
6477 * Calculate a PCI device's link bandwidth by querying for its link speed
6478 * and width, multiplying them, and applying encoding overhead. The result
6479 * is in Mb/s, i.e., megabits/second of raw bandwidth.
6481 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
6482 enum pcie_link_width *width)
6484 *speed = pcie_get_speed_cap(dev);
6485 *width = pcie_get_width_cap(dev);
6487 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
6490 return *width * PCIE_SPEED2MBS_ENC(*speed);
6494 * __pcie_print_link_status - Report the PCI device's link speed and width
6495 * @dev: PCI device to query
6496 * @verbose: Print info even when enough bandwidth is available
6498 * If the available bandwidth at the device is less than the device is
6499 * capable of, report the device's maximum possible bandwidth and the
6500 * upstream link that limits its performance. If @verbose, always print
6501 * the available bandwidth, even if the device isn't constrained.
6503 void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
6505 enum pcie_link_width width, width_cap;
6506 enum pci_bus_speed speed, speed_cap;
6507 struct pci_dev *limiting_dev = NULL;
6508 u32 bw_avail, bw_cap;
6510 bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
6511 bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
6513 if (bw_avail >= bw_cap && verbose)
6514 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
6515 bw_cap / 1000, bw_cap % 1000,
6516 pci_speed_string(speed_cap), width_cap);
6517 else if (bw_avail < bw_cap)
6518 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
6519 bw_avail / 1000, bw_avail % 1000,
6520 pci_speed_string(speed), width,
6521 limiting_dev ? pci_name(limiting_dev) : "<unknown>",
6522 bw_cap / 1000, bw_cap % 1000,
6523 pci_speed_string(speed_cap), width_cap);
6527 * pcie_print_link_status - Report the PCI device's link speed and width
6528 * @dev: PCI device to query
6530 * Report the available bandwidth at the device.
6532 void pcie_print_link_status(struct pci_dev *dev)
6534 __pcie_print_link_status(dev, true);
6536 EXPORT_SYMBOL(pcie_print_link_status);
6539 * pci_select_bars - Make BAR mask from the type of resource
6540 * @dev: the PCI device for which BAR mask is made
6541 * @flags: resource type mask to be selected
6543 * This helper routine makes bar mask from the type of resource.
6545 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
6548 for (i = 0; i < PCI_NUM_RESOURCES; i++)
6549 if (pci_resource_flags(dev, i) & flags)
6553 EXPORT_SYMBOL(pci_select_bars);
6555 /* Some architectures require additional programming to enable VGA */
6556 static arch_set_vga_state_t arch_set_vga_state;
6558 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
6560 arch_set_vga_state = func; /* NULL disables */
6563 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
6564 unsigned int command_bits, u32 flags)
6566 if (arch_set_vga_state)
6567 return arch_set_vga_state(dev, decode, command_bits,
6573 * pci_set_vga_state - set VGA decode state on device and parents if requested
6574 * @dev: the PCI device
6575 * @decode: true = enable decoding, false = disable decoding
6576 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
6577 * @flags: traverse ancestors and change bridges
6578 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
6580 int pci_set_vga_state(struct pci_dev *dev, bool decode,
6581 unsigned int command_bits, u32 flags)
6583 struct pci_bus *bus;
6584 struct pci_dev *bridge;
6588 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
6590 /* ARCH specific VGA enables */
6591 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
6595 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
6596 pci_read_config_word(dev, PCI_COMMAND, &cmd);
6598 cmd |= command_bits;
6600 cmd &= ~command_bits;
6601 pci_write_config_word(dev, PCI_COMMAND, cmd);
6604 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
6611 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
6614 cmd |= PCI_BRIDGE_CTL_VGA;
6616 cmd &= ~PCI_BRIDGE_CTL_VGA;
6617 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
6626 bool pci_pr3_present(struct pci_dev *pdev)
6628 struct acpi_device *adev;
6633 adev = ACPI_COMPANION(&pdev->dev);
6637 return adev->power.flags.power_resources &&
6638 acpi_has_method(adev->handle, "_PR3");
6640 EXPORT_SYMBOL_GPL(pci_pr3_present);
6644 * pci_add_dma_alias - Add a DMA devfn alias for a device
6645 * @dev: the PCI device for which alias is added
6646 * @devfn_from: alias slot and function
6647 * @nr_devfns: number of subsequent devfns to alias
6649 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6650 * which is used to program permissible bus-devfn source addresses for DMA
6651 * requests in an IOMMU. These aliases factor into IOMMU group creation
6652 * and are useful for devices generating DMA requests beyond or different
6653 * from their logical bus-devfn. Examples include device quirks where the
6654 * device simply uses the wrong devfn, as well as non-transparent bridges
6655 * where the alias may be a proxy for devices in another domain.
6657 * IOMMU group creation is performed during device discovery or addition,
6658 * prior to any potential DMA mapping and therefore prior to driver probing
6659 * (especially for userspace assigned devices where IOMMU group definition
6660 * cannot be left as a userspace activity). DMA aliases should therefore
6661 * be configured via quirks, such as the PCI fixup header quirk.
6663 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from,
6664 unsigned int nr_devfns)
6668 nr_devfns = min(nr_devfns, (unsigned int)MAX_NR_DEVFNS - devfn_from);
6669 devfn_to = devfn_from + nr_devfns - 1;
6671 if (!dev->dma_alias_mask)
6672 dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL);
6673 if (!dev->dma_alias_mask) {
6674 pci_warn(dev, "Unable to allocate DMA alias mask\n");
6678 bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns);
6681 pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
6682 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from));
6683 else if (nr_devfns > 1)
6684 pci_info(dev, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n",
6685 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from),
6686 PCI_SLOT(devfn_to), PCI_FUNC(devfn_to));
6689 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
6691 return (dev1->dma_alias_mask &&
6692 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
6693 (dev2->dma_alias_mask &&
6694 test_bit(dev1->devfn, dev2->dma_alias_mask)) ||
6695 pci_real_dma_dev(dev1) == dev2 ||
6696 pci_real_dma_dev(dev2) == dev1;
6699 bool pci_device_is_present(struct pci_dev *pdev)
6703 /* Check PF if pdev is a VF, since VF Vendor/Device IDs are 0xffff */
6704 pdev = pci_physfn(pdev);
6705 if (pci_dev_is_disconnected(pdev))
6707 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
6709 EXPORT_SYMBOL_GPL(pci_device_is_present);
6711 void pci_ignore_hotplug(struct pci_dev *dev)
6713 struct pci_dev *bridge = dev->bus->self;
6715 dev->ignore_hotplug = 1;
6716 /* Propagate the "ignore hotplug" setting to the parent bridge. */
6718 bridge->ignore_hotplug = 1;
6720 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
6723 * pci_real_dma_dev - Get PCI DMA device for PCI device
6724 * @dev: the PCI device that may have a PCI DMA alias
6726 * Permits the platform to provide architecture-specific functionality to
6727 * devices needing to alias DMA to another PCI device on another PCI bus. If
6728 * the PCI device is on the same bus, it is recommended to use
6729 * pci_add_dma_alias(). This is the default implementation. Architecture
6730 * implementations can override this.
6732 struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev)
6737 resource_size_t __weak pcibios_default_alignment(void)
6743 * Arches that don't want to expose struct resource to userland as-is in
6744 * sysfs and /proc can implement their own pci_resource_to_user().
6746 void __weak pci_resource_to_user(const struct pci_dev *dev, int bar,
6747 const struct resource *rsrc,
6748 resource_size_t *start, resource_size_t *end)
6750 *start = rsrc->start;
6754 static char *resource_alignment_param;
6755 static DEFINE_SPINLOCK(resource_alignment_lock);
6758 * pci_specified_resource_alignment - get resource alignment specified by user.
6759 * @dev: the PCI device to get
6760 * @resize: whether or not to change resources' size when reassigning alignment
6762 * RETURNS: Resource alignment if it is specified.
6763 * Zero if it is not specified.
6765 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
6768 int align_order, count;
6769 resource_size_t align = pcibios_default_alignment();
6773 spin_lock(&resource_alignment_lock);
6774 p = resource_alignment_param;
6777 if (pci_has_flag(PCI_PROBE_ONLY)) {
6779 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
6785 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
6788 if (align_order > 63) {
6789 pr_err("PCI: Invalid requested alignment (order %d)\n",
6791 align_order = PAGE_SHIFT;
6794 align_order = PAGE_SHIFT;
6797 ret = pci_dev_str_match(dev, p, &p);
6800 align = 1ULL << align_order;
6802 } else if (ret < 0) {
6803 pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
6808 if (*p != ';' && *p != ',') {
6809 /* End of param or invalid format */
6815 spin_unlock(&resource_alignment_lock);
6819 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
6820 resource_size_t align, bool resize)
6822 struct resource *r = &dev->resource[bar];
6823 const char *r_name = pci_resource_name(dev, bar);
6824 resource_size_t size;
6826 if (!(r->flags & IORESOURCE_MEM))
6829 if (r->flags & IORESOURCE_PCI_FIXED) {
6830 pci_info(dev, "%s %pR: ignoring requested alignment %#llx\n",
6831 r_name, r, (unsigned long long)align);
6835 size = resource_size(r);
6840 * Increase the alignment of the resource. There are two ways we
6843 * 1) Increase the size of the resource. BARs are aligned on their
6844 * size, so when we reallocate space for this resource, we'll
6845 * allocate it with the larger alignment. This also prevents
6846 * assignment of any other BARs inside the alignment region, so
6847 * if we're requesting page alignment, this means no other BARs
6848 * will share the page.
6850 * The disadvantage is that this makes the resource larger than
6851 * the hardware BAR, which may break drivers that compute things
6852 * based on the resource size, e.g., to find registers at a
6853 * fixed offset before the end of the BAR.
6855 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
6856 * set r->start to the desired alignment. By itself this
6857 * doesn't prevent other BARs being put inside the alignment
6858 * region, but if we realign *every* resource of every device in
6859 * the system, none of them will share an alignment region.
6861 * When the user has requested alignment for only some devices via
6862 * the "pci=resource_alignment" argument, "resize" is true and we
6863 * use the first method. Otherwise we assume we're aligning all
6864 * devices and we use the second.
6867 pci_info(dev, "%s %pR: requesting alignment to %#llx\n",
6868 r_name, r, (unsigned long long)align);
6874 r->flags &= ~IORESOURCE_SIZEALIGN;
6875 r->flags |= IORESOURCE_STARTALIGN;
6877 r->end = r->start + size - 1;
6879 r->flags |= IORESOURCE_UNSET;
6883 * This function disables memory decoding and releases memory resources
6884 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
6885 * It also rounds up size to specified alignment.
6886 * Later on, the kernel will assign page-aligned memory resource back
6889 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
6893 resource_size_t align;
6895 bool resize = false;
6898 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
6899 * 3.4.1.11. Their resources are allocated from the space
6900 * described by the VF BARx register in the PF's SR-IOV capability.
6901 * We can't influence their alignment here.
6906 /* check if specified PCI is target device to reassign */
6907 align = pci_specified_resource_alignment(dev, &resize);
6911 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
6912 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
6913 pci_warn(dev, "Can't reassign resources to host bridge\n");
6917 pci_read_config_word(dev, PCI_COMMAND, &command);
6918 command &= ~PCI_COMMAND_MEMORY;
6919 pci_write_config_word(dev, PCI_COMMAND, command);
6921 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
6922 pci_request_resource_alignment(dev, i, align, resize);
6925 * Need to disable bridge's resource window,
6926 * to enable the kernel to reassign new resource
6929 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
6930 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
6931 r = &dev->resource[i];
6932 if (!(r->flags & IORESOURCE_MEM))
6934 r->flags |= IORESOURCE_UNSET;
6935 r->end = resource_size(r) - 1;
6938 pci_disable_bridge_window(dev);
6942 static ssize_t resource_alignment_show(const struct bus_type *bus, char *buf)
6946 spin_lock(&resource_alignment_lock);
6947 if (resource_alignment_param)
6948 count = sysfs_emit(buf, "%s\n", resource_alignment_param);
6949 spin_unlock(&resource_alignment_lock);
6954 static ssize_t resource_alignment_store(const struct bus_type *bus,
6955 const char *buf, size_t count)
6957 char *param, *old, *end;
6959 if (count >= (PAGE_SIZE - 1))
6962 param = kstrndup(buf, count, GFP_KERNEL);
6966 end = strchr(param, '\n');
6970 spin_lock(&resource_alignment_lock);
6971 old = resource_alignment_param;
6972 if (strlen(param)) {
6973 resource_alignment_param = param;
6976 resource_alignment_param = NULL;
6978 spin_unlock(&resource_alignment_lock);
6985 static BUS_ATTR_RW(resource_alignment);
6987 static int __init pci_resource_alignment_sysfs_init(void)
6989 return bus_create_file(&pci_bus_type,
6990 &bus_attr_resource_alignment);
6992 late_initcall(pci_resource_alignment_sysfs_init);
6994 static void pci_no_domains(void)
6996 #ifdef CONFIG_PCI_DOMAINS
6997 pci_domains_supported = 0;
7001 #ifdef CONFIG_PCI_DOMAINS_GENERIC
7002 static DEFINE_IDA(pci_domain_nr_static_ida);
7003 static DEFINE_IDA(pci_domain_nr_dynamic_ida);
7005 static void of_pci_reserve_static_domain_nr(void)
7007 struct device_node *np;
7010 for_each_node_by_type(np, "pci") {
7011 domain_nr = of_get_pci_domain_nr(np);
7015 * Permanently allocate domain_nr in dynamic_ida
7016 * to prevent it from dynamic allocation.
7018 ida_alloc_range(&pci_domain_nr_dynamic_ida,
7019 domain_nr, domain_nr, GFP_KERNEL);
7023 static int of_pci_bus_find_domain_nr(struct device *parent)
7025 static bool static_domains_reserved = false;
7028 /* On the first call scan device tree for static allocations. */
7029 if (!static_domains_reserved) {
7030 of_pci_reserve_static_domain_nr();
7031 static_domains_reserved = true;
7036 * If domain is in DT, allocate it in static IDA. This
7037 * prevents duplicate static allocations in case of errors
7040 domain_nr = of_get_pci_domain_nr(parent->of_node);
7042 return ida_alloc_range(&pci_domain_nr_static_ida,
7043 domain_nr, domain_nr,
7048 * If domain was not specified in DT, choose a free ID from dynamic
7049 * allocations. All domain numbers from DT are permanently in
7050 * dynamic allocations to prevent assigning them to other DT nodes
7051 * without static domain.
7053 return ida_alloc(&pci_domain_nr_dynamic_ida, GFP_KERNEL);
7056 static void of_pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent)
7058 if (bus->domain_nr < 0)
7061 /* Release domain from IDA where it was allocated. */
7062 if (of_get_pci_domain_nr(parent->of_node) == bus->domain_nr)
7063 ida_free(&pci_domain_nr_static_ida, bus->domain_nr);
7065 ida_free(&pci_domain_nr_dynamic_ida, bus->domain_nr);
7068 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
7070 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
7071 acpi_pci_bus_find_domain_nr(bus);
7074 void pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent)
7078 of_pci_bus_release_domain_nr(bus, parent);
7083 * pci_ext_cfg_avail - can we access extended PCI config space?
7085 * Returns 1 if we can access PCI extended config space (offsets
7086 * greater than 0xff). This is the default implementation. Architecture
7087 * implementations can override this.
7089 int __weak pci_ext_cfg_avail(void)
7094 void __weak pci_fixup_cardbus(struct pci_bus *bus)
7097 EXPORT_SYMBOL(pci_fixup_cardbus);
7099 static int __init pci_setup(char *str)
7102 char *k = strchr(str, ',');
7105 if (*str && (str = pcibios_setup(str)) && *str) {
7106 if (!strcmp(str, "nomsi")) {
7108 } else if (!strncmp(str, "noats", 5)) {
7109 pr_info("PCIe: ATS is disabled\n");
7110 pcie_ats_disabled = true;
7111 } else if (!strcmp(str, "noaer")) {
7113 } else if (!strcmp(str, "earlydump")) {
7114 pci_early_dump = true;
7115 } else if (!strncmp(str, "realloc=", 8)) {
7116 pci_realloc_get_opt(str + 8);
7117 } else if (!strncmp(str, "realloc", 7)) {
7118 pci_realloc_get_opt("on");
7119 } else if (!strcmp(str, "nodomains")) {
7121 } else if (!strncmp(str, "noari", 5)) {
7122 pcie_ari_disabled = true;
7123 } else if (!strncmp(str, "cbiosize=", 9)) {
7124 pci_cardbus_io_size = memparse(str + 9, &str);
7125 } else if (!strncmp(str, "cbmemsize=", 10)) {
7126 pci_cardbus_mem_size = memparse(str + 10, &str);
7127 } else if (!strncmp(str, "resource_alignment=", 19)) {
7128 resource_alignment_param = str + 19;
7129 } else if (!strncmp(str, "ecrc=", 5)) {
7130 pcie_ecrc_get_policy(str + 5);
7131 } else if (!strncmp(str, "hpiosize=", 9)) {
7132 pci_hotplug_io_size = memparse(str + 9, &str);
7133 } else if (!strncmp(str, "hpmmiosize=", 11)) {
7134 pci_hotplug_mmio_size = memparse(str + 11, &str);
7135 } else if (!strncmp(str, "hpmmioprefsize=", 15)) {
7136 pci_hotplug_mmio_pref_size = memparse(str + 15, &str);
7137 } else if (!strncmp(str, "hpmemsize=", 10)) {
7138 pci_hotplug_mmio_size = memparse(str + 10, &str);
7139 pci_hotplug_mmio_pref_size = pci_hotplug_mmio_size;
7140 } else if (!strncmp(str, "hpbussize=", 10)) {
7141 pci_hotplug_bus_size =
7142 simple_strtoul(str + 10, &str, 0);
7143 if (pci_hotplug_bus_size > 0xff)
7144 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
7145 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
7146 pcie_bus_config = PCIE_BUS_TUNE_OFF;
7147 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
7148 pcie_bus_config = PCIE_BUS_SAFE;
7149 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
7150 pcie_bus_config = PCIE_BUS_PERFORMANCE;
7151 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
7152 pcie_bus_config = PCIE_BUS_PEER2PEER;
7153 } else if (!strncmp(str, "pcie_scan_all", 13)) {
7154 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
7155 } else if (!strncmp(str, "disable_acs_redir=", 18)) {
7156 disable_acs_redir_param = str + 18;
7158 pr_err("PCI: Unknown option `%s'\n", str);
7165 early_param("pci", pci_setup);
7168 * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
7169 * in pci_setup(), above, to point to data in the __initdata section which
7170 * will be freed after the init sequence is complete. We can't allocate memory
7171 * in pci_setup() because some architectures do not have any memory allocation
7172 * service available during an early_param() call. So we allocate memory and
7173 * copy the variable here before the init section is freed.
7176 static int __init pci_realloc_setup_params(void)
7178 resource_alignment_param = kstrdup(resource_alignment_param,
7180 disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL);
7184 pure_initcall(pci_realloc_setup_params);