2 * Standard PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/config.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/types.h>
34 #include <linux/slab.h>
35 #include <linux/vmalloc.h>
36 #include <linux/interrupt.h>
37 #include <linux/spinlock.h>
38 #include <linux/delay.h>
39 #include <linux/pci.h>
40 #include <asm/system.h>
44 #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
45 #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
46 #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
47 #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
48 #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
49 #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
50 /* Redefine this flagword to set debug level */
51 #define DEBUG_LEVEL DBG_K_STANDARD
53 #define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
55 #define DBG_PRINT( dbg_flags, args... ) \
57 if ( DEBUG_LEVEL & ( dbg_flags ) ) \
60 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
61 __FILE__, __LINE__, __FUNCTION__ ); \
62 sprintf( __dbg_str_buf + len, args ); \
63 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
67 #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
68 #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
70 #define DEFINE_DBG_BUFFER
71 #define DBG_ENTER_ROUTINE
72 #define DBG_LEAVE_ROUTINE
75 /* Slot Available Register I field definition */
76 #define SLOT_33MHZ 0x0000001f
77 #define SLOT_66MHZ_PCIX 0x00001f00
78 #define SLOT_100MHZ_PCIX 0x001f0000
79 #define SLOT_133MHZ_PCIX 0x1f000000
81 /* Slot Available Register II field definition */
82 #define SLOT_66MHZ 0x0000001f
83 #define SLOT_66MHZ_PCIX_266 0x00000f00
84 #define SLOT_100MHZ_PCIX_266 0x0000f000
85 #define SLOT_133MHZ_PCIX_266 0x000f0000
86 #define SLOT_66MHZ_PCIX_533 0x00f00000
87 #define SLOT_100MHZ_PCIX_533 0x0f000000
88 #define SLOT_133MHZ_PCIX_533 0xf0000000
91 /* Secondary Bus Configuration Register */
92 /* For PI = 1, Bits 0 to 2 have been encoded as follows to show current bus speed/mode */
95 #define PCIX_66MHZ 0x2
96 #define PCIX_100MHZ 0x3
97 #define PCIX_133MHZ 0x4
99 /* For PI = 2, Bits 0 to 3 have been encoded as follows to show current bus speed/mode */
100 #define PCI_33MHZ 0x0
101 #define PCI_66MHZ 0x1
102 #define PCIX_66MHZ 0x2
103 #define PCIX_100MHZ 0x3
104 #define PCIX_133MHZ 0x4
105 #define PCIX_66MHZ_ECC 0x5
106 #define PCIX_100MHZ_ECC 0x6
107 #define PCIX_133MHZ_ECC 0x7
108 #define PCIX_66MHZ_266 0x9
109 #define PCIX_100MHZ_266 0xa
110 #define PCIX_133MHZ_266 0xb
111 #define PCIX_66MHZ_533 0x11
112 #define PCIX_100MHZ_533 0x12
113 #define PCIX_133MHZ_533 0x13
115 /* Slot Configuration */
116 #define SLOT_NUM 0x0000001F
117 #define FIRST_DEV_NUM 0x00001F00
118 #define PSN 0x07FF0000
119 #define UPDOWN 0x20000000
120 #define MRLSENSOR 0x40000000
121 #define ATTN_BUTTON 0x80000000
123 /* Slot Status Field Definitions */
125 #define PWR_ONLY 0x0001
126 #define ENABLED 0x0002
127 #define DISABLED 0x0003
129 /* Power Indicator State */
130 #define PWR_LED_ON 0x0004
131 #define PWR_LED_BLINK 0x0008
132 #define PWR_LED_OFF 0x000c
134 /* Attention Indicator State */
135 #define ATTEN_LED_ON 0x0010
136 #define ATTEN_LED_BLINK 0x0020
137 #define ATTEN_LED_OFF 0x0030
140 #define pwr_fault 0x0040
142 /* Attention Button */
143 #define ATTEN_BUTTON 0x0080
146 #define MRL_SENSOR 0x0100
149 #define IS_66MHZ_CAP 0x0200
151 /* PRSNT1#/PRSNT2# */
152 #define SLOT_EMP 0x0c00
154 /* PCI-X Capability */
155 #define NON_PCIX 0x0000
156 #define PCIX_66 0x1000
157 #define PCIX_133 0x3000
158 #define PCIX_266 0x4000 /* For PI = 2 only */
159 #define PCIX_533 0x5000 /* For PI = 2 only */
161 /* SHPC 'write' operations/commands */
163 /* Slot operation - 0x00h to 0x3Fh */
165 #define NO_CHANGE 0x00
167 /* Slot state - Bits 0 & 1 of controller command register */
168 #define SET_SLOT_PWR 0x01
169 #define SET_SLOT_ENABLE 0x02
170 #define SET_SLOT_DISABLE 0x03
172 /* Power indicator state - Bits 2 & 3 of controller command register*/
173 #define SET_PWR_ON 0x04
174 #define SET_PWR_BLINK 0x08
175 #define SET_PWR_OFF 0x0C
177 /* Attention indicator state - Bits 4 & 5 of controller command register*/
178 #define SET_ATTN_ON 0x010
179 #define SET_ATTN_BLINK 0x020
180 #define SET_ATTN_OFF 0x030
182 /* Set bus speed/mode A - 0x40h to 0x47h */
183 #define SETA_PCI_33MHZ 0x40
184 #define SETA_PCI_66MHZ 0x41
185 #define SETA_PCIX_66MHZ 0x42
186 #define SETA_PCIX_100MHZ 0x43
187 #define SETA_PCIX_133MHZ 0x44
188 #define RESERV_1 0x45
189 #define RESERV_2 0x46
190 #define RESERV_3 0x47
192 /* Set bus speed/mode B - 0x50h to 0x5fh */
193 #define SETB_PCI_33MHZ 0x50
194 #define SETB_PCI_66MHZ 0x51
195 #define SETB_PCIX_66MHZ_PM 0x52
196 #define SETB_PCIX_100MHZ_PM 0x53
197 #define SETB_PCIX_133MHZ_PM 0x54
198 #define SETB_PCIX_66MHZ_EM 0x55
199 #define SETB_PCIX_100MHZ_EM 0x56
200 #define SETB_PCIX_133MHZ_EM 0x57
201 #define SETB_PCIX_66MHZ_266 0x58
202 #define SETB_PCIX_100MHZ_266 0x59
203 #define SETB_PCIX_133MHZ_266 0x5a
204 #define SETB_PCIX_66MHZ_533 0x5b
205 #define SETB_PCIX_100MHZ_533 0x5c
206 #define SETB_PCIX_133MHZ_533 0x5d
209 /* Power-on all slots - 0x48h */
210 #define SET_PWR_ON_ALL 0x48
212 /* Enable all slots - 0x49h */
213 #define SET_ENABLE_ALL 0x49
215 /* SHPC controller command error code */
216 #define SWITCH_OPEN 0x1
217 #define INVALID_CMD 0x2
218 #define INVALID_SPEED_MODE 0x4
220 /* For accessing SHPC Working Register Set */
221 #define DWORD_SELECT 0x2
222 #define DWORD_DATA 0x4
223 #define BASE_OFFSET 0x0
225 /* Field Offset in Logical Slot Register - byte boundary */
226 #define SLOT_EVENT_LATCH 0x2
227 #define SLOT_SERR_INT_MASK 0x3
229 static spinlock_t hpc_event_lock;
231 DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
232 static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */
233 static int ctlr_seq_num = 0; /* Controller sequenc # */
234 static spinlock_t list_lock;
236 static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs);
238 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds);
240 /* This is the interrupt polling timeout function. */
241 static void int_poll_timeout(unsigned long lphp_ctlr)
243 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr;
248 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
252 /* Poll for interrupt events. regs == NULL => polling */
253 shpc_isr( 0, (void *)php_ctlr, NULL );
255 init_timer(&php_ctlr->int_poll_timer);
256 if (!shpchp_poll_time)
257 shpchp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
259 start_int_poll_timer(php_ctlr, shpchp_poll_time);
264 /* This function starts the interrupt polling timer. */
265 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds)
268 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
272 if ( ( seconds <= 0 ) || ( seconds > 60 ) )
273 seconds = 2; /* Clamp to sane value */
275 php_ctlr->int_poll_timer.function = &int_poll_timeout;
276 php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; /* Instance data */
277 php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ;
278 add_timer(&php_ctlr->int_poll_timer);
283 static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
285 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
294 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
298 for (i = 0; i < 10; i++) {
299 cmd_status = readw(php_ctlr->creg + CMD_STATUS);
301 if (!(cmd_status & 0x1))
303 /* Check every 0.1 sec for a total of 1 sec*/
307 cmd_status = readw(php_ctlr->creg + CMD_STATUS);
309 if (cmd_status & 0x1) {
310 /* After 1 sec and and the controller is still busy */
311 err("%s : Controller is still busy after 1 sec.\n", __FUNCTION__);
316 temp_word = (t_slot << 8) | (cmd & 0xFF);
317 dbg("%s: t_slot %x cmd %x\n", __FUNCTION__, t_slot, cmd);
319 /* To make sure the Controller Busy bit is 0 before we send out the
322 writew(temp_word, php_ctlr->creg + CMD);
323 dbg("%s: temp_word written %x\n", __FUNCTION__, temp_word);
329 static int hpc_check_cmd_status(struct controller *ctrl)
331 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) ctrl->hpc_ctlr_handle;
337 if (!ctrl->hpc_ctlr_handle) {
338 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
342 cmd_status = readw(php_ctlr->creg + CMD_STATUS) & 0x000F;
344 switch (cmd_status >> 1) {
349 retval = SWITCH_OPEN;
350 err("%s: Switch opened!\n", __FUNCTION__);
353 retval = INVALID_CMD;
354 err("%s: Invalid HPC command!\n", __FUNCTION__);
357 retval = INVALID_SPEED_MODE;
358 err("%s: Invalid bus speed/mode!\n", __FUNCTION__);
369 static int hpc_get_attention_status(struct slot *slot, u8 *status)
371 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
378 if (!slot->ctrl->hpc_ctlr_handle) {
379 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
383 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
384 slot_status = (u16) slot_reg;
385 atten_led_state = (slot_status & 0x0030) >> 4;
387 switch (atten_led_state) {
389 *status = 0xFF; /* Reserved */
392 *status = 1; /* On */
395 *status = 2; /* Blink */
398 *status = 0; /* Off */
409 static int hpc_get_power_status(struct slot * slot, u8 *status)
411 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
419 if (!slot->ctrl->hpc_ctlr_handle) {
420 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
424 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
425 slot_status = (u16) slot_reg;
426 slot_state = (slot_status & 0x0003);
428 switch (slot_state) {
433 *status = 2; /* Powered only */
436 *status = 1; /* Enabled */
439 *status = 0; /* Disabled */
451 static int hpc_get_latch_status(struct slot *slot, u8 *status)
453 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
459 if (!slot->ctrl->hpc_ctlr_handle) {
460 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
464 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
465 slot_status = (u16)slot_reg;
467 *status = ((slot_status & 0x0100) == 0) ? 0 : 1; /* 0 -> close; 1 -> open */
474 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
476 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
483 if (!slot->ctrl->hpc_ctlr_handle) {
484 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
488 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
489 slot_status = (u16)slot_reg;
490 card_state = (u8)((slot_status & 0x0C00) >> 10);
491 *status = (card_state != 0x3) ? 1 : 0;
497 static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
499 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
503 if (!slot->ctrl->hpc_ctlr_handle) {
504 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
508 *prog_int = readb(php_ctlr->creg + PROG_INTERFACE);
514 static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
516 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
518 u16 slot_status, sec_bus_status;
519 u8 m66_cap, pcix_cap, pi;
524 if (!slot->ctrl->hpc_ctlr_handle) {
525 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
529 if (slot->hp_slot >= php_ctlr->num_slots) {
530 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
534 pi = readb(php_ctlr->creg + PROG_INTERFACE);
535 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
536 dbg("%s: pi = %d, slot_reg = %x\n", __FUNCTION__, pi, slot_reg);
537 slot_status = (u16) slot_reg;
538 dbg("%s: slot_status = %x\n", __FUNCTION__, slot_status);
539 sec_bus_status = readw(php_ctlr->creg + SEC_BUS_CONFIG);
541 pcix_cap = (u8) ((slot_status & 0x3000) >> 12);
542 dbg("%s: pcix_cap = %x\n", __FUNCTION__, pcix_cap);
543 m66_cap = (u8) ((slot_status & 0x0200) >> 9);
544 dbg("%s: m66_cap = %x\n", __FUNCTION__, m66_cap);
550 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
553 *value = PCI_SPEED_66MHz_PCIX;
556 *value = PCI_SPEED_133MHz_PCIX;
559 *value = PCI_SPEED_133MHz_PCIX_266;
562 *value = PCI_SPEED_133MHz_PCIX_533;
564 case 2: /* Reserved */
566 *value = PCI_SPEED_UNKNOWN;
573 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
576 *value = PCI_SPEED_66MHz_PCIX;
579 *value = PCI_SPEED_133MHz_PCIX;
581 case 2: /* Reserved */
583 *value = PCI_SPEED_UNKNOWN;
589 dbg("Adapter speed = %d\n", *value);
595 static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
597 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
604 if (!slot->ctrl->hpc_ctlr_handle) {
605 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
609 pi = readb(php_ctlr->creg + PROG_INTERFACE);
610 sec_bus_status = readw(php_ctlr->creg + SEC_BUS_CONFIG);
613 *mode = (sec_bus_status & 0x0100) >> 7;
618 dbg("Mode 1 ECC cap = %d\n", *mode);
624 static int hpc_query_power_fault(struct slot * slot)
626 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
629 u8 pwr_fault_state, status;
633 if (!slot->ctrl->hpc_ctlr_handle) {
634 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
638 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
639 slot_status = (u16) slot_reg;
640 pwr_fault_state = (slot_status & 0x0040) >> 7;
641 status = (pwr_fault_state == 1) ? 0 : 1;
644 /* Note: Logic 0 => fault */
648 static int hpc_set_attention_status(struct slot *slot, u8 value)
650 struct php_ctlr_state_s *php_ctlr =(struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
654 if (!slot->ctrl->hpc_ctlr_handle) {
655 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
659 if (slot->hp_slot >= php_ctlr->num_slots) {
660 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
666 slot_cmd = 0x30; /* OFF */
669 slot_cmd = 0x10; /* ON */
672 slot_cmd = 0x20; /* BLINK */
678 shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
684 static void hpc_set_green_led_on(struct slot *slot)
686 struct php_ctlr_state_s *php_ctlr =(struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
689 if (!slot->ctrl->hpc_ctlr_handle) {
690 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
694 if (slot->hp_slot >= php_ctlr->num_slots) {
695 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
701 shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
706 static void hpc_set_green_led_off(struct slot *slot)
708 struct php_ctlr_state_s *php_ctlr =(struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
711 if (!slot->ctrl->hpc_ctlr_handle) {
712 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
716 if (slot->hp_slot >= php_ctlr->num_slots) {
717 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
723 shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
728 static void hpc_set_green_led_blink(struct slot *slot)
730 struct php_ctlr_state_s *php_ctlr =(struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
733 if (!slot->ctrl->hpc_ctlr_handle) {
734 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
738 if (slot->hp_slot >= php_ctlr->num_slots) {
739 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
745 shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
750 int shpc_get_ctlr_slot_config(struct controller *ctrl,
751 int *num_ctlr_slots, /* number of slots in this HPC */
752 int *first_device_num, /* PCI dev num of the first slot in this SHPC */
753 int *physical_slot_num, /* phy slot num of the first slot in this SHPC */
754 int *updown, /* physical_slot_num increament: 1 or -1 */
757 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) ctrl->hpc_ctlr_handle;
761 if (!ctrl->hpc_ctlr_handle) {
762 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
766 *first_device_num = php_ctlr->slot_device_offset; /* Obtained in shpc_init() */
767 *num_ctlr_slots = php_ctlr->num_slots; /* Obtained in shpc_init() */
769 *physical_slot_num = (readl(php_ctlr->creg + SLOT_CONFIG) & PSN) >> 16;
770 dbg("%s: physical_slot_num = %x\n", __FUNCTION__, *physical_slot_num);
771 *updown = ((readl(php_ctlr->creg + SLOT_CONFIG) & UPDOWN ) >> 29) ? 1 : -1;
777 static void hpc_release_ctlr(struct controller *ctrl)
779 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) ctrl->hpc_ctlr_handle;
780 struct php_ctlr_state_s *p, *p_prev;
784 if (!ctrl->hpc_ctlr_handle) {
785 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
789 if (shpchp_poll_mode) {
790 del_timer(&php_ctlr->int_poll_timer);
793 free_irq(php_ctlr->irq, ctrl);
795 pci_disable_msi(php_ctlr->pci_dev);
798 if (php_ctlr->pci_dev) {
799 dbg("%s: before calling iounmap & release_mem_region\n", __FUNCTION__);
800 iounmap(php_ctlr->creg);
801 release_mem_region(pci_resource_start(php_ctlr->pci_dev, 0), pci_resource_len(php_ctlr->pci_dev, 0));
802 dbg("%s: before calling iounmap & release_mem_region\n", __FUNCTION__);
803 php_ctlr->pci_dev = NULL;
806 spin_lock(&list_lock);
807 p = php_ctlr_list_head;
812 p_prev->pnext = p->pnext;
814 php_ctlr_list_head = p->pnext;
821 spin_unlock(&list_lock);
829 static int hpc_power_on_slot(struct slot * slot)
831 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
837 if (!slot->ctrl->hpc_ctlr_handle) {
838 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
842 if (slot->hp_slot >= php_ctlr->num_slots) {
843 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
848 retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
851 err("%s: Write command failed!\n", __FUNCTION__);
860 static int hpc_slot_enable(struct slot * slot)
862 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
868 if (!slot->ctrl->hpc_ctlr_handle) {
869 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
873 if (slot->hp_slot >= php_ctlr->num_slots) {
874 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
877 /* 3A => Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
880 retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
883 err("%s: Write command failed!\n", __FUNCTION__);
891 static int hpc_slot_disable(struct slot * slot)
893 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
899 if (!slot->ctrl->hpc_ctlr_handle) {
900 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
904 if (slot->hp_slot >= php_ctlr->num_slots) {
905 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
909 /* 1F => Slot - Disable, Power Indicator - Off, Attention Indicator - On */
912 retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
915 err("%s: Write command failed!\n", __FUNCTION__);
923 static int hpc_enable_all_slots( struct slot *slot )
929 if (!slot->ctrl->hpc_ctlr_handle) {
930 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
934 retval = shpc_write_cmd(slot, 0, SET_ENABLE_ALL);
936 err("%s: Write command failed!\n", __FUNCTION__);
945 static int hpc_pwr_on_all_slots(struct slot *slot)
951 retval = shpc_write_cmd(slot, 0, SET_PWR_ON_ALL);
954 err("%s: Write command failed!\n", __FUNCTION__);
962 static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
967 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
971 if (!slot->ctrl->hpc_ctlr_handle) {
972 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
976 pi = readb(php_ctlr->creg + PROG_INTERFACE);
981 slot_cmd = SETA_PCI_33MHZ;
984 slot_cmd = SETA_PCI_66MHZ;
987 slot_cmd = SETA_PCIX_66MHZ;
990 slot_cmd = SETA_PCIX_100MHZ;
993 slot_cmd = SETA_PCIX_133MHZ;
996 slot_cmd = PCI_SPEED_UNKNOWN;
1003 slot_cmd = SETB_PCI_33MHZ;
1006 slot_cmd = SETB_PCI_66MHZ;
1009 slot_cmd = SETB_PCIX_66MHZ_PM;
1012 slot_cmd = SETB_PCIX_100MHZ_PM;
1015 slot_cmd = SETB_PCIX_133MHZ_PM;
1018 slot_cmd = SETB_PCIX_66MHZ_EM;
1021 slot_cmd = SETB_PCIX_100MHZ_EM;
1024 slot_cmd = SETB_PCIX_133MHZ_EM;
1027 slot_cmd = SETB_PCIX_66MHZ_266;
1030 slot_cmd = SETB_PCIX_100MHZ_266;
1033 slot_cmd = SETB_PCIX_133MHZ_266;
1036 slot_cmd = SETB_PCIX_66MHZ_533;
1039 slot_cmd = SETB_PCIX_100MHZ_533;
1042 slot_cmd = SETB_PCIX_133MHZ_533;
1045 slot_cmd = PCI_SPEED_UNKNOWN;
1051 retval = shpc_write_cmd(slot, 0, slot_cmd);
1053 err("%s: Write command failed!\n", __FUNCTION__);
1061 static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
1063 struct controller *ctrl = NULL;
1064 struct php_ctlr_state_s *php_ctlr;
1065 u8 schedule_flag = 0;
1067 u32 temp_dword, intr_loc, intr_loc2;
1073 if (!shpchp_poll_mode) {
1074 ctrl = (struct controller *)dev_id;
1075 php_ctlr = ctrl->hpc_ctlr_handle;
1077 php_ctlr = (struct php_ctlr_state_s *) dev_id;
1078 ctrl = (struct controller *)php_ctlr->callback_instance_id;
1084 if (!php_ctlr || !php_ctlr->creg)
1087 /* Check to see if it was our interrupt */
1088 intr_loc = readl(php_ctlr->creg + INTR_LOC);
1092 dbg("%s: shpc_isr proceeds\n", __FUNCTION__);
1093 dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc);
1095 if(!shpchp_poll_mode) {
1096 /* Mask Global Interrupt Mask - see implementation note on p. 139 */
1097 /* of SHPC spec rev 1.0*/
1098 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1099 dbg("%s: Before masking global interrupt, temp_dword = %x\n",
1100 __FUNCTION__, temp_dword);
1101 temp_dword |= 0x00000001;
1102 dbg("%s: After masking global interrupt, temp_dword = %x\n",
1103 __FUNCTION__, temp_dword);
1104 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
1106 intr_loc2 = readl(php_ctlr->creg + INTR_LOC);
1107 dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
1110 if (intr_loc & 0x0001) {
1112 * Command Complete Interrupt Pending
1113 * RO only - clear by writing 0 to the Command Completion
1114 * Detect bit in Controller SERR-INT register
1116 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1117 dbg("%s: Before clearing CCIP, temp_dword = %x\n",
1118 __FUNCTION__, temp_dword);
1119 temp_dword &= 0xfffeffff;
1120 dbg("%s: After clearing CCIP, temp_dword = %x\n",
1121 __FUNCTION__, temp_dword);
1122 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
1123 wake_up_interruptible(&ctrl->queue);
1126 if ((intr_loc = (intr_loc >> 1)) == 0) {
1127 /* Unmask Global Interrupt Mask */
1128 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1129 dbg("%s: 1-Before unmasking global interrupt, temp_dword = %x\n",
1130 __FUNCTION__, temp_dword);
1131 temp_dword &= 0xfffffffe;
1132 dbg("%s: 1-After unmasking global interrupt, temp_dword = %x\n",
1133 __FUNCTION__, temp_dword);
1134 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
1139 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1140 /* To find out which slot has interrupt pending */
1141 if ((intr_loc >> hp_slot) & 0x01) {
1142 temp_dword = readl(php_ctlr->creg + SLOT1 + (4*hp_slot));
1143 dbg("%s: Slot %x with intr, temp_dword = %x\n",
1144 __FUNCTION__, hp_slot, temp_dword);
1145 temp_byte = (temp_dword >> 16) & 0xFF;
1146 dbg("%s: Slot with intr, temp_byte = %x\n",
1147 __FUNCTION__, temp_byte);
1148 if ((php_ctlr->switch_change_callback) && (temp_byte & 0x08))
1149 schedule_flag += php_ctlr->switch_change_callback(
1150 hp_slot, php_ctlr->callback_instance_id);
1151 if ((php_ctlr->attention_button_callback) && (temp_byte & 0x04))
1152 schedule_flag += php_ctlr->attention_button_callback(
1153 hp_slot, php_ctlr->callback_instance_id);
1154 if ((php_ctlr->presence_change_callback) && (temp_byte & 0x01))
1155 schedule_flag += php_ctlr->presence_change_callback(
1156 hp_slot , php_ctlr->callback_instance_id);
1157 if ((php_ctlr->power_fault_callback) && (temp_byte & 0x12))
1158 schedule_flag += php_ctlr->power_fault_callback(
1159 hp_slot, php_ctlr->callback_instance_id);
1161 /* Clear all slot events */
1162 temp_dword = 0xe01f3fff;
1163 dbg("%s: Clearing slot events, temp_dword = %x\n",
1164 __FUNCTION__, temp_dword);
1165 writel(temp_dword, php_ctlr->creg + SLOT1 + (4*hp_slot));
1167 intr_loc2 = readl(php_ctlr->creg + INTR_LOC);
1168 dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
1171 if (!shpchp_poll_mode) {
1172 /* Unmask Global Interrupt Mask */
1173 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1174 dbg("%s: 2-Before unmasking global interrupt, temp_dword = %x\n",
1175 __FUNCTION__, temp_dword);
1176 temp_dword &= 0xfffffffe;
1177 dbg("%s: 2-After unmasking global interrupt, temp_dword = %x\n",
1178 __FUNCTION__, temp_dword);
1179 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
1185 static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
1187 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
1188 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
1191 u32 slot_avail1, slot_avail2;
1196 if (!slot->ctrl->hpc_ctlr_handle) {
1197 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1201 if (slot->hp_slot >= php_ctlr->num_slots) {
1202 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1206 pi = readb(php_ctlr->creg + PROG_INTERFACE);
1207 slot_avail1 = readl(php_ctlr->creg + SLOT_AVAIL1);
1208 slot_avail2 = readl(php_ctlr->creg + SLOT_AVAIL2);
1211 if ((slot_num = ((slot_avail2 & SLOT_133MHZ_PCIX_533) >> 27) ) != 0 )
1212 bus_speed = PCIX_133MHZ_533;
1213 else if ((slot_num = ((slot_avail2 & SLOT_100MHZ_PCIX_533) >> 23) ) != 0 )
1214 bus_speed = PCIX_100MHZ_533;
1215 else if ((slot_num = ((slot_avail2 & SLOT_66MHZ_PCIX_533) >> 19) ) != 0 )
1216 bus_speed = PCIX_66MHZ_533;
1217 else if ((slot_num = ((slot_avail2 & SLOT_133MHZ_PCIX_266) >> 15) ) != 0 )
1218 bus_speed = PCIX_133MHZ_266;
1219 else if ((slot_num = ((slot_avail2 & SLOT_100MHZ_PCIX_266) >> 11) ) != 0 )
1220 bus_speed = PCIX_100MHZ_266;
1221 else if ((slot_num = ((slot_avail2 & SLOT_66MHZ_PCIX_266) >> 7) ) != 0 )
1222 bus_speed = PCIX_66MHZ_266;
1223 else if ((slot_num = ((slot_avail1 & SLOT_133MHZ_PCIX) >> 23) ) != 0 )
1224 bus_speed = PCIX_133MHZ;
1225 else if ((slot_num = ((slot_avail1 & SLOT_100MHZ_PCIX) >> 15) ) != 0 )
1226 bus_speed = PCIX_100MHZ;
1227 else if ((slot_num = ((slot_avail1 & SLOT_66MHZ_PCIX) >> 7) ) != 0 )
1228 bus_speed = PCIX_66MHZ;
1229 else if ((slot_num = (slot_avail2 & SLOT_66MHZ)) != 0 )
1230 bus_speed = PCI_66MHZ;
1231 else if ((slot_num = (slot_avail1 & SLOT_33MHZ)) != 0 )
1232 bus_speed = PCI_33MHZ;
1233 else bus_speed = PCI_SPEED_UNKNOWN;
1235 if ((slot_num = ((slot_avail1 & SLOT_133MHZ_PCIX) >> 23) ) != 0 )
1236 bus_speed = PCIX_133MHZ;
1237 else if ((slot_num = ((slot_avail1 & SLOT_100MHZ_PCIX) >> 15) ) != 0 )
1238 bus_speed = PCIX_100MHZ;
1239 else if ((slot_num = ((slot_avail1 & SLOT_66MHZ_PCIX) >> 7) ) != 0 )
1240 bus_speed = PCIX_66MHZ;
1241 else if ((slot_num = (slot_avail2 & SLOT_66MHZ)) != 0 )
1242 bus_speed = PCI_66MHZ;
1243 else if ((slot_num = (slot_avail1 & SLOT_33MHZ)) != 0 )
1244 bus_speed = PCI_33MHZ;
1245 else bus_speed = PCI_SPEED_UNKNOWN;
1249 dbg("Max bus speed = %d\n", bus_speed);
1254 static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value)
1256 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
1257 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
1264 if (!slot->ctrl->hpc_ctlr_handle) {
1265 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1269 if (slot->hp_slot >= php_ctlr->num_slots) {
1270 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1274 pi = readb(php_ctlr->creg + PROG_INTERFACE);
1275 sec_bus_status = readw(php_ctlr->creg + SEC_BUS_CONFIG);
1278 switch (sec_bus_status & 0x000f) {
1280 bus_speed = PCI_SPEED_33MHz;
1283 bus_speed = PCI_SPEED_66MHz;
1286 bus_speed = PCI_SPEED_66MHz_PCIX;
1289 bus_speed = PCI_SPEED_100MHz_PCIX;
1292 bus_speed = PCI_SPEED_133MHz_PCIX;
1295 bus_speed = PCI_SPEED_66MHz_PCIX_ECC;
1298 bus_speed = PCI_SPEED_100MHz_PCIX_ECC;
1301 bus_speed = PCI_SPEED_133MHz_PCIX_ECC;
1304 bus_speed = PCI_SPEED_66MHz_PCIX_266;
1307 bus_speed = PCI_SPEED_100MHz_PCIX_266;
1310 bus_speed = PCI_SPEED_133MHz_PCIX_266;
1313 bus_speed = PCI_SPEED_66MHz_PCIX_533;
1316 bus_speed = PCI_SPEED_100MHz_PCIX_533;
1319 bus_speed = PCI_SPEED_133MHz_PCIX_533;
1324 bus_speed = PCI_SPEED_UNKNOWN;
1328 /* In the case where pi is undefined, default it to 1 */
1329 switch (sec_bus_status & 0x0007) {
1331 bus_speed = PCI_SPEED_33MHz;
1334 bus_speed = PCI_SPEED_66MHz;
1337 bus_speed = PCI_SPEED_66MHz_PCIX;
1340 bus_speed = PCI_SPEED_100MHz_PCIX;
1343 bus_speed = PCI_SPEED_133MHz_PCIX;
1346 bus_speed = PCI_SPEED_UNKNOWN; /* Reserved */
1349 bus_speed = PCI_SPEED_UNKNOWN; /* Reserved */
1352 bus_speed = PCI_SPEED_UNKNOWN; /* Reserved */
1355 bus_speed = PCI_SPEED_UNKNOWN;
1361 dbg("Current bus speed = %d\n", bus_speed);
1366 static struct hpc_ops shpchp_hpc_ops = {
1367 .power_on_slot = hpc_power_on_slot,
1368 .slot_enable = hpc_slot_enable,
1369 .slot_disable = hpc_slot_disable,
1370 .enable_all_slots = hpc_enable_all_slots,
1371 .pwr_on_all_slots = hpc_pwr_on_all_slots,
1372 .set_bus_speed_mode = hpc_set_bus_speed_mode,
1373 .set_attention_status = hpc_set_attention_status,
1374 .get_power_status = hpc_get_power_status,
1375 .get_attention_status = hpc_get_attention_status,
1376 .get_latch_status = hpc_get_latch_status,
1377 .get_adapter_status = hpc_get_adapter_status,
1379 .get_max_bus_speed = hpc_get_max_bus_speed,
1380 .get_cur_bus_speed = hpc_get_cur_bus_speed,
1381 .get_adapter_speed = hpc_get_adapter_speed,
1382 .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap,
1383 .get_prog_int = hpc_get_prog_int,
1385 .query_power_fault = hpc_query_power_fault,
1386 .green_led_on = hpc_set_green_led_on,
1387 .green_led_off = hpc_set_green_led_off,
1388 .green_led_blink = hpc_set_green_led_blink,
1390 .release_ctlr = hpc_release_ctlr,
1391 .check_cmd_status = hpc_check_cmd_status,
1394 int shpc_init(struct controller * ctrl,
1395 struct pci_dev * pdev,
1396 php_intr_callback_t attention_button_callback,
1397 php_intr_callback_t switch_change_callback,
1398 php_intr_callback_t presence_change_callback,
1399 php_intr_callback_t power_fault_callback)
1401 struct php_ctlr_state_s *php_ctlr, *p;
1402 void *instance_id = ctrl;
1405 static int first = 1;
1406 u32 shpc_cap_offset, shpc_base_offset;
1407 u32 tempdword, slot_reg;
1408 u16 vendor_id, device_id;
1413 spin_lock_init(&list_lock);
1414 php_ctlr = (struct php_ctlr_state_s *) kmalloc(sizeof(struct php_ctlr_state_s), GFP_KERNEL);
1416 if (!php_ctlr) { /* allocate controller state data */
1417 err("%s: HPC controller memory allocation error!\n", __FUNCTION__);
1421 memset(php_ctlr, 0, sizeof(struct php_ctlr_state_s));
1423 php_ctlr->pci_dev = pdev; /* save pci_dev in context */
1425 rc = pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor_id);
1426 dbg("%s: Vendor ID: %x\n",__FUNCTION__, vendor_id);
1428 err("%s: unable to read PCI configuration data\n", __FUNCTION__);
1429 goto abort_free_ctlr;
1432 rc = pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
1433 dbg("%s: Device ID: %x\n",__FUNCTION__, device_id);
1435 err("%s: unable to read PCI configuration data\n", __FUNCTION__);
1436 goto abort_free_ctlr;
1439 if ((vendor_id == PCI_VENDOR_ID_AMD) || (device_id == PCI_DEVICE_ID_AMD_GOLAM_7450)) {
1440 shpc_base_offset = 0; /* amd shpc driver doesn't use this; assume 0 */
1442 if ((shpc_cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC)) == 0) {
1443 err("%s : shpc_cap_offset == 0\n", __FUNCTION__);
1444 goto abort_free_ctlr;
1446 dbg("%s: shpc_cap_offset = %x\n", __FUNCTION__, shpc_cap_offset);
1448 rc = pci_write_config_byte(pdev, (u8)shpc_cap_offset + DWORD_SELECT , BASE_OFFSET);
1450 err("%s : pci_word_config_byte failed\n", __FUNCTION__);
1451 goto abort_free_ctlr;
1454 rc = pci_read_config_dword(pdev, (u8)shpc_cap_offset + DWORD_DATA, &shpc_base_offset);
1456 err("%s : pci_read_config_dword failed\n", __FUNCTION__);
1457 goto abort_free_ctlr;
1460 for (i = 0; i <= 14; i++) {
1461 rc = pci_write_config_byte(pdev, (u8)shpc_cap_offset + DWORD_SELECT , i);
1463 err("%s : pci_word_config_byte failed\n", __FUNCTION__);
1464 goto abort_free_ctlr;
1467 rc = pci_read_config_dword(pdev, (u8)shpc_cap_offset + DWORD_DATA, &tempdword);
1469 err("%s : pci_read_config_dword failed\n", __FUNCTION__);
1470 goto abort_free_ctlr;
1472 dbg("%s: offset %d: tempdword %x\n", __FUNCTION__,i, tempdword);
1477 spin_lock_init(&hpc_event_lock);
1481 dbg("pdev = %p: b:d:f:irq=0x%x:%x:%x:%x\n", pdev, pdev->bus->number, PCI_SLOT(pdev->devfn),
1482 PCI_FUNC(pdev->devfn), pdev->irq);
1483 for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1484 if (pci_resource_len(pdev, rc) > 0)
1485 dbg("pci resource[%d] start=0x%lx(len=0x%lx), shpc_base_offset %x\n", rc,
1486 pci_resource_start(pdev, rc), pci_resource_len(pdev, rc), shpc_base_offset);
1488 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor,
1489 pdev->subsystem_device);
1491 if (pci_enable_device(pdev))
1492 goto abort_free_ctlr;
1494 if (!request_mem_region(pci_resource_start(pdev, 0) + shpc_base_offset, pci_resource_len(pdev, 0), MY_NAME)) {
1495 err("%s: cannot reserve MMIO region\n", __FUNCTION__);
1496 goto abort_free_ctlr;
1499 php_ctlr->creg = ioremap(pci_resource_start(pdev, 0) + shpc_base_offset, pci_resource_len(pdev, 0));
1500 if (!php_ctlr->creg) {
1501 err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__, pci_resource_len(pdev, 0),
1502 pci_resource_start(pdev, 0) + shpc_base_offset);
1503 release_mem_region(pci_resource_start(pdev, 0) + shpc_base_offset, pci_resource_len(pdev, 0));
1504 goto abort_free_ctlr;
1506 dbg("%s: php_ctlr->creg %p\n", __FUNCTION__, php_ctlr->creg);
1507 dbg("%s: physical addr %p\n", __FUNCTION__, (void*)pci_resource_start(pdev, 0));
1509 init_MUTEX(&ctrl->crit_sect);
1510 /* Setup wait queue */
1511 init_waitqueue_head(&ctrl->queue);
1514 php_ctlr->irq = pdev->irq;
1515 dbg("HPC interrupt = %d\n", php_ctlr->irq);
1517 /* Save interrupt callback info */
1518 php_ctlr->attention_button_callback = attention_button_callback;
1519 php_ctlr->switch_change_callback = switch_change_callback;
1520 php_ctlr->presence_change_callback = presence_change_callback;
1521 php_ctlr->power_fault_callback = power_fault_callback;
1522 php_ctlr->callback_instance_id = instance_id;
1524 /* Return PCI Controller Info */
1525 php_ctlr->slot_device_offset = (readl(php_ctlr->creg + SLOT_CONFIG) & FIRST_DEV_NUM ) >> 8;
1526 php_ctlr->num_slots = readl(php_ctlr->creg + SLOT_CONFIG) & SLOT_NUM;
1527 dbg("%s: slot_device_offset %x\n", __FUNCTION__, php_ctlr->slot_device_offset);
1528 dbg("%s: num_slots %x\n", __FUNCTION__, php_ctlr->num_slots);
1530 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
1531 tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1532 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1533 tempdword = 0x0003000f;
1534 writel(tempdword, php_ctlr->creg + SERR_INTR_ENABLE);
1535 tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1536 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1538 /* Mask the MRL sensor SERR Mask of individual slot in
1539 * Slot SERR-INT Mask & clear all the existing event if any
1541 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
1542 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*hp_slot );
1543 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1545 tempdword = 0xffff3fff;
1546 writel(tempdword, php_ctlr->creg + SLOT1 + (4*hp_slot));
1549 if (shpchp_poll_mode) {/* Install interrupt polling code */
1550 /* Install and start the interrupt polling timer */
1551 init_timer(&php_ctlr->int_poll_timer);
1552 start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */
1554 /* Installs the interrupt handler */
1555 rc = pci_enable_msi(pdev);
1557 info("Can't get msi for the hotplug controller\n");
1558 info("Use INTx for the hotplug controller\n");
1559 dbg("%s: rc = %x\n", __FUNCTION__, rc);
1561 php_ctlr->irq = pdev->irq;
1563 rc = request_irq(php_ctlr->irq, shpc_isr, SA_SHIRQ, MY_NAME, (void *) ctrl);
1564 dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc);
1566 err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq);
1567 goto abort_free_ctlr;
1570 get_hp_hw_control_from_firmware(pdev);
1571 dbg("%s: Before adding HPC to HPC list\n", __FUNCTION__);
1573 /* Add this HPC instance into the HPC list */
1574 spin_lock(&list_lock);
1575 if (php_ctlr_list_head == 0) {
1576 php_ctlr_list_head = php_ctlr;
1577 p = php_ctlr_list_head;
1580 p = php_ctlr_list_head;
1585 p->pnext = php_ctlr;
1587 spin_unlock(&list_lock);
1591 ctrl->hpc_ctlr_handle = php_ctlr;
1592 ctrl->hpc_ops = &shpchp_hpc_ops;
1594 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
1595 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*hp_slot );
1596 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1598 tempdword = 0xe01f3fff;
1599 writel(tempdword, php_ctlr->creg + SLOT1 + (4*hp_slot));
1601 if (!shpchp_poll_mode) {
1602 /* Unmask all general input interrupts and SERR */
1603 tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1604 tempdword = 0x0000000a;
1605 writel(tempdword, php_ctlr->creg + SERR_INTR_ENABLE);
1606 tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1607 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1610 dbg("%s: Leaving shpc_init\n", __FUNCTION__);
1614 /* We end up here for the many possible ways to fail this API. */