2 * PCI Express PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
39 #include <linux/slab.h>
44 static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
46 return ctrl->pcie->port;
49 static irqreturn_t pcie_isr(int irq, void *dev_id);
50 static void start_int_poll_timer(struct controller *ctrl, int sec);
52 /* This is the interrupt polling timeout function. */
53 static void int_poll_timeout(unsigned long data)
55 struct controller *ctrl = (struct controller *)data;
57 /* Poll for interrupt events. regs == NULL => polling */
60 init_timer(&ctrl->poll_timer);
61 if (!pciehp_poll_time)
62 pciehp_poll_time = 2; /* default polling interval is 2 sec */
64 start_int_poll_timer(ctrl, pciehp_poll_time);
67 /* This function starts the interrupt polling timer. */
68 static void start_int_poll_timer(struct controller *ctrl, int sec)
70 /* Clamp to sane value */
71 if ((sec <= 0) || (sec > 60))
74 ctrl->poll_timer.function = &int_poll_timeout;
75 ctrl->poll_timer.data = (unsigned long)ctrl;
76 ctrl->poll_timer.expires = jiffies + sec * HZ;
77 add_timer(&ctrl->poll_timer);
80 static inline int pciehp_request_irq(struct controller *ctrl)
82 int retval, irq = ctrl->pcie->irq;
84 /* Install interrupt polling timer. Start with 10 sec delay */
85 if (pciehp_poll_mode) {
86 init_timer(&ctrl->poll_timer);
87 start_int_poll_timer(ctrl, 10);
91 /* Installs the interrupt handler */
92 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
94 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
99 static inline void pciehp_free_irq(struct controller *ctrl)
101 if (pciehp_poll_mode)
102 del_timer_sync(&ctrl->poll_timer);
104 free_irq(ctrl->pcie->irq, ctrl);
107 static int pcie_poll_cmd(struct controller *ctrl, int timeout)
109 struct pci_dev *pdev = ctrl_dev(ctrl);
112 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
113 if (slot_status & PCI_EXP_SLTSTA_CC) {
114 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
118 while (timeout > 0) {
121 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
122 if (slot_status & PCI_EXP_SLTSTA_CC) {
123 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
128 return 0; /* timeout */
131 static void pcie_wait_cmd(struct controller *ctrl)
133 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
134 unsigned long duration = msecs_to_jiffies(msecs);
135 unsigned long cmd_timeout = ctrl->cmd_started + duration;
136 unsigned long now, timeout;
140 * If the controller does not generate notifications for command
141 * completions, we never need to wait between writes.
143 if (NO_CMD_CMPL(ctrl))
150 * Even if the command has already timed out, we want to call
151 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
154 if (time_before_eq(cmd_timeout, now))
157 timeout = cmd_timeout - now;
159 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
160 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
161 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
163 rc = pcie_poll_cmd(ctrl, timeout);
166 * Controllers with errata like Intel CF118 don't generate
167 * completion notifications unless the power/indicator/interlock
168 * control bits are changed. On such controllers, we'll emit this
169 * timeout message when we wait for completion of commands that
170 * don't change those bits, e.g., commands that merely enable
174 ctrl_info(ctrl, "Timeout on hotplug command %#010x (issued %u msec ago)\n",
176 jiffies_to_msecs(now - ctrl->cmd_started));
180 * pcie_write_cmd - Issue controller command
181 * @ctrl: controller to which the command is issued
182 * @cmd: command value written to slot control register
183 * @mask: bitmask of slot control register to be modified
185 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
187 struct pci_dev *pdev = ctrl_dev(ctrl);
190 mutex_lock(&ctrl->ctrl_lock);
192 /* Wait for any previous command that might still be in progress */
195 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
197 slot_ctrl |= (cmd & mask);
200 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
201 ctrl->cmd_started = jiffies;
202 ctrl->slot_ctrl = slot_ctrl;
204 mutex_unlock(&ctrl->ctrl_lock);
207 bool pciehp_check_link_active(struct controller *ctrl)
209 struct pci_dev *pdev = ctrl_dev(ctrl);
213 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
214 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
217 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
222 static void __pcie_wait_link_active(struct controller *ctrl, bool active)
226 if (pciehp_check_link_active(ctrl) == active)
228 while (timeout > 0) {
231 if (pciehp_check_link_active(ctrl) == active)
234 ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
235 active ? "set" : "cleared");
238 static void pcie_wait_link_active(struct controller *ctrl)
240 __pcie_wait_link_active(ctrl, true);
243 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
247 int delay = 1000, step = 20;
251 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
261 if (count > 1 && pciehp_debug)
262 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
263 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
264 PCI_FUNC(devfn), count, step, l);
269 int pciehp_check_link_status(struct controller *ctrl)
271 struct pci_dev *pdev = ctrl_dev(ctrl);
276 * Data Link Layer Link Active Reporting must be capable for
277 * hot-plug capable downstream port. But old controller might
278 * not implement it. In this case, we wait for 1000 ms.
280 if (ctrl->link_active_reporting)
281 pcie_wait_link_active(ctrl);
285 /* wait 100ms before read pci conf, and try in 1s */
287 found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
290 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
291 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
292 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
293 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
294 ctrl_err(ctrl, "Link Training Error occurs\n");
298 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
306 static int __pciehp_link_set(struct controller *ctrl, bool enable)
308 struct pci_dev *pdev = ctrl_dev(ctrl);
311 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
314 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
316 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
318 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
319 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
323 static int pciehp_link_enable(struct controller *ctrl)
325 return __pciehp_link_set(ctrl, true);
328 void pciehp_get_attention_status(struct slot *slot, u8 *status)
330 struct controller *ctrl = slot->ctrl;
331 struct pci_dev *pdev = ctrl_dev(ctrl);
334 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
335 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
336 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
338 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
339 case PCI_EXP_SLTCTL_ATTN_IND_ON:
340 *status = 1; /* On */
342 case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
343 *status = 2; /* Blink */
345 case PCI_EXP_SLTCTL_ATTN_IND_OFF:
346 *status = 0; /* Off */
354 void pciehp_get_power_status(struct slot *slot, u8 *status)
356 struct controller *ctrl = slot->ctrl;
357 struct pci_dev *pdev = ctrl_dev(ctrl);
360 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
361 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
362 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
364 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
365 case PCI_EXP_SLTCTL_PWR_ON:
366 *status = 1; /* On */
368 case PCI_EXP_SLTCTL_PWR_OFF:
369 *status = 0; /* Off */
377 void pciehp_get_latch_status(struct slot *slot, u8 *status)
379 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
382 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
383 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
386 void pciehp_get_adapter_status(struct slot *slot, u8 *status)
388 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
391 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
392 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
395 int pciehp_query_power_fault(struct slot *slot)
397 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
400 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
401 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
404 void pciehp_set_attention_status(struct slot *slot, u8 value)
406 struct controller *ctrl = slot->ctrl;
413 case 0: /* turn off */
414 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF;
416 case 1: /* turn on */
417 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON;
419 case 2: /* turn blink */
420 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK;
425 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
426 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
427 pcie_write_cmd(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
430 void pciehp_green_led_on(struct slot *slot)
432 struct controller *ctrl = slot->ctrl;
437 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON, PCI_EXP_SLTCTL_PIC);
438 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
439 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
440 PCI_EXP_SLTCTL_PWR_IND_ON);
443 void pciehp_green_led_off(struct slot *slot)
445 struct controller *ctrl = slot->ctrl;
450 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, PCI_EXP_SLTCTL_PIC);
451 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
452 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
453 PCI_EXP_SLTCTL_PWR_IND_OFF);
456 void pciehp_green_led_blink(struct slot *slot)
458 struct controller *ctrl = slot->ctrl;
463 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK, PCI_EXP_SLTCTL_PIC);
464 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
465 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
466 PCI_EXP_SLTCTL_PWR_IND_BLINK);
469 int pciehp_power_on_slot(struct slot *slot)
471 struct controller *ctrl = slot->ctrl;
472 struct pci_dev *pdev = ctrl_dev(ctrl);
476 /* Clear sticky power-fault bit from previous power failures */
477 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
478 if (slot_status & PCI_EXP_SLTSTA_PFD)
479 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
481 ctrl->power_fault_detected = 0;
483 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
484 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
485 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
486 PCI_EXP_SLTCTL_PWR_ON);
488 retval = pciehp_link_enable(ctrl);
490 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
495 void pciehp_power_off_slot(struct slot *slot)
497 struct controller *ctrl = slot->ctrl;
499 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
500 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
501 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
502 PCI_EXP_SLTCTL_PWR_OFF);
505 static irqreturn_t pcie_isr(int irq, void *dev_id)
507 struct controller *ctrl = (struct controller *)dev_id;
508 struct pci_dev *pdev = ctrl_dev(ctrl);
509 struct slot *slot = ctrl->slot;
510 u16 detected, intr_loc;
513 * In order to guarantee that all interrupt events are
514 * serviced, we need to re-inspect Slot Status register after
515 * clearing what is presumed to be the last pending interrupt.
519 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &detected);
521 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
522 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
523 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
524 detected &= ~intr_loc;
525 intr_loc |= detected;
529 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
533 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
535 /* Check Command Complete Interrupt Pending */
536 if (intr_loc & PCI_EXP_SLTSTA_CC) {
539 wake_up(&ctrl->queue);
542 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
545 /* Check MRL Sensor Changed */
546 if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
547 pciehp_handle_switch_change(slot);
549 /* Check Attention Button Pressed */
550 if (intr_loc & PCI_EXP_SLTSTA_ABP)
551 pciehp_handle_attention_button(slot);
553 /* Check Presence Detect Changed */
554 if (intr_loc & PCI_EXP_SLTSTA_PDC)
555 pciehp_handle_presence_change(slot);
557 /* Check Power Fault Detected */
558 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
559 ctrl->power_fault_detected = 1;
560 pciehp_handle_power_fault(slot);
563 if (intr_loc & PCI_EXP_SLTSTA_DLLSC)
564 pciehp_handle_linkstate_change(slot);
569 void pcie_enable_notification(struct controller *ctrl)
574 * TBD: Power fault detected software notification support.
576 * Power fault detected software notification is not enabled
577 * now, because it caused power fault detected interrupt storm
578 * on some machines. On those machines, power fault detected
579 * bit in the slot status register was set again immediately
580 * when it is cleared in the interrupt service routine, and
581 * next power fault detected interrupt was notified again.
585 * Always enable link events: thus link-up and link-down shall
586 * always be treated as hotplug and unplug respectively. Enable
587 * presence detect only if Attention Button is not present.
589 cmd = PCI_EXP_SLTCTL_DLLSCE;
590 if (ATTN_BUTTN(ctrl))
591 cmd |= PCI_EXP_SLTCTL_ABPE;
593 cmd |= PCI_EXP_SLTCTL_PDCE;
595 cmd |= PCI_EXP_SLTCTL_MRLSCE;
596 if (!pciehp_poll_mode)
597 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
599 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
600 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
601 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
602 PCI_EXP_SLTCTL_DLLSCE);
604 pcie_write_cmd(ctrl, cmd, mask);
607 static void pcie_disable_notification(struct controller *ctrl)
611 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
612 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
613 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
614 PCI_EXP_SLTCTL_DLLSCE);
615 pcie_write_cmd(ctrl, 0, mask);
619 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
620 * bus reset of the bridge, but at the same time we want to ensure that it is
621 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
622 * disable link state notification and presence detection change notification
623 * momentarily, if we see that they could interfere. Also, clear any spurious
626 int pciehp_reset_slot(struct slot *slot, int probe)
628 struct controller *ctrl = slot->ctrl;
629 struct pci_dev *pdev = ctrl_dev(ctrl);
630 u16 stat_mask = 0, ctrl_mask = 0;
635 if (!ATTN_BUTTN(ctrl)) {
636 ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
637 stat_mask |= PCI_EXP_SLTSTA_PDC;
639 ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
640 stat_mask |= PCI_EXP_SLTSTA_DLLSC;
642 pcie_write_cmd(ctrl, 0, ctrl_mask);
643 if (pciehp_poll_mode)
644 del_timer_sync(&ctrl->poll_timer);
646 pci_reset_bridge_secondary_bus(ctrl->pcie->port);
648 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
649 pcie_write_cmd(ctrl, ctrl_mask, ctrl_mask);
650 if (pciehp_poll_mode)
651 int_poll_timeout(ctrl->poll_timer.data);
656 int pcie_init_notification(struct controller *ctrl)
658 if (pciehp_request_irq(ctrl))
660 pcie_enable_notification(ctrl);
661 ctrl->notification_enabled = 1;
665 static void pcie_shutdown_notification(struct controller *ctrl)
667 if (ctrl->notification_enabled) {
668 pcie_disable_notification(ctrl);
669 pciehp_free_irq(ctrl);
670 ctrl->notification_enabled = 0;
674 static int pcie_init_slot(struct controller *ctrl)
678 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
682 slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl));
687 mutex_init(&slot->lock);
688 mutex_init(&slot->hotplug_lock);
689 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
697 static void pcie_cleanup_slot(struct controller *ctrl)
699 struct slot *slot = ctrl->slot;
700 cancel_delayed_work(&slot->work);
701 destroy_workqueue(slot->wq);
705 static inline void dbg_ctrl(struct controller *ctrl)
709 struct pci_dev *pdev = ctrl->pcie->port;
714 ctrl_info(ctrl, "Hotplug Controller:\n");
715 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
716 pci_name(pdev), pdev->irq);
717 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor);
718 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device);
719 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n",
720 pdev->subsystem_device);
721 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
722 pdev->subsystem_vendor);
723 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n",
725 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
726 if (!pci_resource_len(pdev, i))
728 ctrl_info(ctrl, " PCI resource [%d] : %pR\n",
729 i, &pdev->resource[i]);
731 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
732 ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl));
733 ctrl_info(ctrl, " Attention Button : %3s\n",
734 ATTN_BUTTN(ctrl) ? "yes" : "no");
735 ctrl_info(ctrl, " Power Controller : %3s\n",
736 POWER_CTRL(ctrl) ? "yes" : "no");
737 ctrl_info(ctrl, " MRL Sensor : %3s\n",
738 MRL_SENS(ctrl) ? "yes" : "no");
739 ctrl_info(ctrl, " Attention Indicator : %3s\n",
740 ATTN_LED(ctrl) ? "yes" : "no");
741 ctrl_info(ctrl, " Power Indicator : %3s\n",
742 PWR_LED(ctrl) ? "yes" : "no");
743 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n",
744 HP_SUPR_RM(ctrl) ? "yes" : "no");
745 ctrl_info(ctrl, " EMI Present : %3s\n",
746 EMI(ctrl) ? "yes" : "no");
747 ctrl_info(ctrl, " Command Completed : %3s\n",
748 NO_CMD_CMPL(ctrl) ? "no" : "yes");
749 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16);
750 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
751 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16);
752 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
755 #define FLAG(x, y) (((x) & (y)) ? '+' : '-')
757 struct controller *pcie_init(struct pcie_device *dev)
759 struct controller *ctrl;
760 u32 slot_cap, link_cap;
761 struct pci_dev *pdev = dev->port;
763 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
765 dev_err(&dev->device, "%s: Out of memory\n", __func__);
769 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
770 ctrl->slot_cap = slot_cap;
771 mutex_init(&ctrl->ctrl_lock);
772 init_waitqueue_head(&ctrl->queue);
775 /* Check if Data Link Layer Link Active Reporting is implemented */
776 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
777 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
778 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
779 ctrl->link_active_reporting = 1;
782 /* Clear all remaining event bits in Slot Status register */
783 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
784 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
785 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
786 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
788 /* Disable software notification */
789 pcie_disable_notification(ctrl);
791 ctrl_info(ctrl, "Slot #%d AttnBtn%c AttnInd%c PwrInd%c PwrCtrl%c MRL%c Interlock%c NoCompl%c LLActRep%c\n",
792 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
793 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
794 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
795 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
796 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
797 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
798 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
799 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
800 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC));
802 if (pcie_init_slot(ctrl))
813 void pciehp_release_ctrl(struct controller *ctrl)
815 pcie_shutdown_notification(ctrl);
816 pcie_cleanup_slot(ctrl);