2 * Rockchip AXI PCIe host controller driver
4 * Copyright (c) 2016 Rockchip, Inc.
6 * Author: Shawn Lin <shawn.lin@rock-chips.com>
7 * Wenrui Li <wenrui.li@rock-chips.com>
9 * Bits taken from Synopsys Designware Host controller driver and
10 * ARM PCI Host generic driver.
12 * This program is free software: you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation, either version 2 of the License, or
15 * (at your option) any later version.
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/irqchip/chained_irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/kernel.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/of_address.h>
29 #include <linux/of_device.h>
30 #include <linux/of_pci.h>
31 #include <linux/of_platform.h>
32 #include <linux/of_irq.h>
33 #include <linux/pci.h>
34 #include <linux/pci_ids.h>
35 #include <linux/phy/phy.h>
36 #include <linux/platform_device.h>
37 #include <linux/reset.h>
38 #include <linux/regmap.h>
41 * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16
42 * bits. This allows atomic updates of the register without locking.
44 #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
45 #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
47 #define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
49 #define PCIE_CLIENT_BASE 0x0
50 #define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
51 #define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
52 #define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
53 #define PCIE_CLIENT_ARI_ENABLE HIWORD_UPDATE_BIT(0x0008)
54 #define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
55 #define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
56 #define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080)
57 #define PCIE_CLIENT_BASIC_STATUS1 (PCIE_CLIENT_BASE + 0x48)
58 #define PCIE_CLIENT_LINK_STATUS_UP 0x00300000
59 #define PCIE_CLIENT_LINK_STATUS_MASK 0x00300000
60 #define PCIE_CLIENT_INT_MASK (PCIE_CLIENT_BASE + 0x4c)
61 #define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50)
62 #define PCIE_CLIENT_INTR_MASK GENMASK(8, 5)
63 #define PCIE_CLIENT_INTR_SHIFT 5
64 #define PCIE_CLIENT_INT_LEGACY_DONE BIT(15)
65 #define PCIE_CLIENT_INT_MSG BIT(14)
66 #define PCIE_CLIENT_INT_HOT_RST BIT(13)
67 #define PCIE_CLIENT_INT_DPA BIT(12)
68 #define PCIE_CLIENT_INT_FATAL_ERR BIT(11)
69 #define PCIE_CLIENT_INT_NFATAL_ERR BIT(10)
70 #define PCIE_CLIENT_INT_CORR_ERR BIT(9)
71 #define PCIE_CLIENT_INT_INTD BIT(8)
72 #define PCIE_CLIENT_INT_INTC BIT(7)
73 #define PCIE_CLIENT_INT_INTB BIT(6)
74 #define PCIE_CLIENT_INT_INTA BIT(5)
75 #define PCIE_CLIENT_INT_LOCAL BIT(4)
76 #define PCIE_CLIENT_INT_UDMA BIT(3)
77 #define PCIE_CLIENT_INT_PHY BIT(2)
78 #define PCIE_CLIENT_INT_HOT_PLUG BIT(1)
79 #define PCIE_CLIENT_INT_PWR_STCG BIT(0)
81 #define PCIE_CLIENT_INT_LEGACY \
82 (PCIE_CLIENT_INT_INTA | PCIE_CLIENT_INT_INTB | \
83 PCIE_CLIENT_INT_INTC | PCIE_CLIENT_INT_INTD)
85 #define PCIE_CLIENT_INT_CLI \
86 (PCIE_CLIENT_INT_CORR_ERR | PCIE_CLIENT_INT_NFATAL_ERR | \
87 PCIE_CLIENT_INT_FATAL_ERR | PCIE_CLIENT_INT_DPA | \
88 PCIE_CLIENT_INT_HOT_RST | PCIE_CLIENT_INT_MSG | \
89 PCIE_CLIENT_INT_LEGACY_DONE | PCIE_CLIENT_INT_LEGACY | \
92 #define PCIE_CORE_CTRL_MGMT_BASE 0x900000
93 #define PCIE_CORE_CTRL (PCIE_CORE_CTRL_MGMT_BASE + 0x000)
94 #define PCIE_CORE_PL_CONF_SPEED_5G 0x00000008
95 #define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018
96 #define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006
97 #define PCIE_CORE_PL_CONF_LANE_SHIFT 1
98 #define PCIE_CORE_INT_STATUS (PCIE_CORE_CTRL_MGMT_BASE + 0x20c)
99 #define PCIE_CORE_INT_PRFPE BIT(0)
100 #define PCIE_CORE_INT_CRFPE BIT(1)
101 #define PCIE_CORE_INT_RRPE BIT(2)
102 #define PCIE_CORE_INT_PRFO BIT(3)
103 #define PCIE_CORE_INT_CRFO BIT(4)
104 #define PCIE_CORE_INT_RT BIT(5)
105 #define PCIE_CORE_INT_RTR BIT(6)
106 #define PCIE_CORE_INT_PE BIT(7)
107 #define PCIE_CORE_INT_MTR BIT(8)
108 #define PCIE_CORE_INT_UCR BIT(9)
109 #define PCIE_CORE_INT_FCE BIT(10)
110 #define PCIE_CORE_INT_CT BIT(11)
111 #define PCIE_CORE_INT_UTC BIT(18)
112 #define PCIE_CORE_INT_MMVC BIT(19)
113 #define PCIE_CORE_INT_MASK (PCIE_CORE_CTRL_MGMT_BASE + 0x210)
114 #define PCIE_RC_BAR_CONF (PCIE_CORE_CTRL_MGMT_BASE + 0x300)
116 #define PCIE_CORE_INT \
117 (PCIE_CORE_INT_PRFPE | PCIE_CORE_INT_CRFPE | \
118 PCIE_CORE_INT_RRPE | PCIE_CORE_INT_CRFO | \
119 PCIE_CORE_INT_RT | PCIE_CORE_INT_RTR | \
120 PCIE_CORE_INT_PE | PCIE_CORE_INT_MTR | \
121 PCIE_CORE_INT_UCR | PCIE_CORE_INT_FCE | \
122 PCIE_CORE_INT_CT | PCIE_CORE_INT_UTC | \
125 #define PCIE_RC_CONFIG_BASE 0xa00000
126 #define PCIE_RC_CONFIG_VENDOR (PCIE_RC_CONFIG_BASE + 0x00)
127 #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
128 #define PCIE_RC_CONFIG_SCC_SHIFT 16
129 #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
130 #define PCIE_RC_CONFIG_LCS_RETRAIN_LINK BIT(5)
131 #define PCIE_RC_CONFIG_LCS_LBMIE BIT(10)
132 #define PCIE_RC_CONFIG_LCS_LABIE BIT(11)
133 #define PCIE_RC_CONFIG_LCS_LBMS BIT(30)
134 #define PCIE_RC_CONFIG_LCS_LAMS BIT(31)
135 #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)
137 #define PCIE_CORE_AXI_CONF_BASE 0xc00000
138 #define PCIE_CORE_OB_REGION_ADDR0 (PCIE_CORE_AXI_CONF_BASE + 0x0)
139 #define PCIE_CORE_OB_REGION_ADDR0_NUM_BITS 0x3f
140 #define PCIE_CORE_OB_REGION_ADDR0_LO_ADDR 0xffffff00
141 #define PCIE_CORE_OB_REGION_ADDR1 (PCIE_CORE_AXI_CONF_BASE + 0x4)
142 #define PCIE_CORE_OB_REGION_DESC0 (PCIE_CORE_AXI_CONF_BASE + 0x8)
143 #define PCIE_CORE_OB_REGION_DESC1 (PCIE_CORE_AXI_CONF_BASE + 0xc)
145 #define PCIE_CORE_AXI_INBOUND_BASE 0xc00800
146 #define PCIE_RP_IB_ADDR0 (PCIE_CORE_AXI_INBOUND_BASE + 0x0)
147 #define PCIE_CORE_IB_REGION_ADDR0_NUM_BITS 0x3f
148 #define PCIE_CORE_IB_REGION_ADDR0_LO_ADDR 0xffffff00
149 #define PCIE_RP_IB_ADDR1 (PCIE_CORE_AXI_INBOUND_BASE + 0x4)
151 /* Size of one AXI Region (not Region 0) */
152 #define AXI_REGION_SIZE BIT(20)
153 /* Size of Region 0, equal to sum of sizes of other regions */
154 #define AXI_REGION_0_SIZE (32 * (0x1 << 20))
155 #define OB_REG_SIZE_SHIFT 5
156 #define IB_ROOT_PORT_REG_SIZE_SHIFT 3
157 #define AXI_WRAPPER_IO_WRITE 0x6
158 #define AXI_WRAPPER_MEM_WRITE 0x2
160 #define MAX_AXI_IB_ROOTPORT_REGION_NUM 3
161 #define MIN_AXI_ADDR_BITS_PASSED 8
162 #define ROCKCHIP_VENDOR_ID 0x1d87
163 #define PCIE_ECAM_BUS(x) (((x) & 0xff) << 20)
164 #define PCIE_ECAM_DEV(x) (((x) & 0x1f) << 15)
165 #define PCIE_ECAM_FUNC(x) (((x) & 0x7) << 12)
166 #define PCIE_ECAM_REG(x) (((x) & 0xfff) << 0)
167 #define PCIE_ECAM_ADDR(bus, dev, func, reg) \
168 (PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \
169 PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg))
171 #define RC_REGION_0_ADDR_TRANS_H 0x00000000
172 #define RC_REGION_0_ADDR_TRANS_L 0x00000000
173 #define RC_REGION_0_PASS_BITS (25 - 1)
174 #define MAX_AXI_WRAPPER_REGION_NUM 33
176 struct rockchip_pcie {
177 void __iomem *reg_base; /* DT axi-base */
178 void __iomem *apb_base; /* DT apb-base */
180 struct reset_control *core_rst;
181 struct reset_control *mgmt_rst;
182 struct reset_control *mgmt_sticky_rst;
183 struct reset_control *pipe_rst;
184 struct clk *aclk_pcie;
185 struct clk *aclk_perf_pcie;
186 struct clk *hclk_pcie;
187 struct clk *clk_pcie_pm;
188 struct regulator *vpcie3v3; /* 3.3V power supply */
189 struct regulator *vpcie1v8; /* 1.8V power supply */
190 struct regulator *vpcie0v9; /* 0.9V power supply */
191 struct gpio_desc *ep_gpio;
195 struct irq_domain *irq_domain;
198 static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)
200 return readl(rockchip->apb_base + reg);
203 static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val,
206 writel(val, rockchip->apb_base + reg);
209 static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
213 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
214 status |= (PCIE_RC_CONFIG_LCS_LBMIE | PCIE_RC_CONFIG_LCS_LABIE);
215 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
218 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
222 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
223 status |= (PCIE_RC_CONFIG_LCS_LBMS | PCIE_RC_CONFIG_LCS_LAMS);
224 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
227 static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
228 struct pci_bus *bus, int dev)
230 /* access only one slot on each root port */
231 if (bus->number == rockchip->root_bus_nr && dev > 0)
235 * do not read more than one device on the bus directly attached
236 * to RC's downstream side.
238 if (bus->primary == rockchip->root_bus_nr && dev > 0)
244 static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip,
245 int where, int size, u32 *val)
247 void __iomem *addr = rockchip->apb_base + PCIE_RC_CONFIG_BASE + where;
249 if (!IS_ALIGNED((uintptr_t)addr, size)) {
251 return PCIBIOS_BAD_REGISTER_NUMBER;
256 } else if (size == 2) {
258 } else if (size == 1) {
262 return PCIBIOS_BAD_REGISTER_NUMBER;
264 return PCIBIOS_SUCCESSFUL;
267 static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip,
268 int where, int size, u32 val)
270 u32 mask, tmp, offset;
272 offset = where & ~0x3;
275 writel(val, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
276 return PCIBIOS_SUCCESSFUL;
279 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
282 * N.B. This read/modify/write isn't safe in general because it can
283 * corrupt RW1C bits in adjacent registers. But the hardware
284 * doesn't support smaller writes.
286 tmp = readl(rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset) & mask;
287 tmp |= val << ((where & 0x3) * 8);
288 writel(tmp, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
290 return PCIBIOS_SUCCESSFUL;
293 static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip,
294 struct pci_bus *bus, u32 devfn,
295 int where, int size, u32 *val)
299 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
300 PCI_FUNC(devfn), where);
302 if (!IS_ALIGNED(busdev, size)) {
304 return PCIBIOS_BAD_REGISTER_NUMBER;
308 *val = readl(rockchip->reg_base + busdev);
309 } else if (size == 2) {
310 *val = readw(rockchip->reg_base + busdev);
311 } else if (size == 1) {
312 *val = readb(rockchip->reg_base + busdev);
315 return PCIBIOS_BAD_REGISTER_NUMBER;
317 return PCIBIOS_SUCCESSFUL;
320 static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip,
321 struct pci_bus *bus, u32 devfn,
322 int where, int size, u32 val)
326 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
327 PCI_FUNC(devfn), where);
328 if (!IS_ALIGNED(busdev, size))
329 return PCIBIOS_BAD_REGISTER_NUMBER;
332 writel(val, rockchip->reg_base + busdev);
334 writew(val, rockchip->reg_base + busdev);
336 writeb(val, rockchip->reg_base + busdev);
338 return PCIBIOS_BAD_REGISTER_NUMBER;
340 return PCIBIOS_SUCCESSFUL;
343 static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
346 struct rockchip_pcie *rockchip = bus->sysdata;
348 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn))) {
350 return PCIBIOS_DEVICE_NOT_FOUND;
353 if (bus->number == rockchip->root_bus_nr)
354 return rockchip_pcie_rd_own_conf(rockchip, where, size, val);
356 return rockchip_pcie_rd_other_conf(rockchip, bus, devfn, where, size, val);
359 static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
360 int where, int size, u32 val)
362 struct rockchip_pcie *rockchip = bus->sysdata;
364 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn)))
365 return PCIBIOS_DEVICE_NOT_FOUND;
367 if (bus->number == rockchip->root_bus_nr)
368 return rockchip_pcie_wr_own_conf(rockchip, where, size, val);
370 return rockchip_pcie_wr_other_conf(rockchip, bus, devfn, where, size, val);
373 static struct pci_ops rockchip_pcie_ops = {
374 .read = rockchip_pcie_rd_conf,
375 .write = rockchip_pcie_wr_conf,
379 * rockchip_pcie_init_port - Initialize hardware
380 * @rockchip: PCIe port information
382 static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
384 struct device *dev = rockchip->dev;
387 unsigned long timeout;
389 gpiod_set_value(rockchip->ep_gpio, 0);
391 err = phy_init(rockchip->phy);
393 dev_err(dev, "fail to init phy, err %d\n", err);
397 err = reset_control_assert(rockchip->core_rst);
399 dev_err(dev, "assert core_rst err %d\n", err);
403 err = reset_control_assert(rockchip->mgmt_rst);
405 dev_err(dev, "assert mgmt_rst err %d\n", err);
409 err = reset_control_assert(rockchip->mgmt_sticky_rst);
411 dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
415 err = reset_control_assert(rockchip->pipe_rst);
417 dev_err(dev, "assert pipe_rst err %d\n", err);
421 rockchip_pcie_write(rockchip,
422 PCIE_CLIENT_CONF_ENABLE |
423 PCIE_CLIENT_LINK_TRAIN_ENABLE |
424 PCIE_CLIENT_ARI_ENABLE |
425 PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes) |
426 PCIE_CLIENT_MODE_RC |
427 PCIE_CLIENT_GEN_SEL_2,
430 err = phy_power_on(rockchip->phy);
432 dev_err(dev, "fail to power on phy, err %d\n", err);
436 err = reset_control_deassert(rockchip->core_rst);
438 dev_err(dev, "deassert core_rst err %d\n", err);
442 err = reset_control_deassert(rockchip->mgmt_rst);
444 dev_err(dev, "deassert mgmt_rst err %d\n", err);
448 err = reset_control_deassert(rockchip->mgmt_sticky_rst);
450 dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
454 err = reset_control_deassert(rockchip->pipe_rst);
456 dev_err(dev, "deassert pipe_rst err %d\n", err);
461 * We need to read/write PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 before
462 * enabling ASPM. Otherwise L1PwrOnSc and L1PwrOnVal isn't
463 * reliable and enabling ASPM doesn't work. This is a controller
464 * bug we need to work around.
466 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
467 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
469 /* Enable Gen1 training */
470 rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
473 gpiod_set_value(rockchip->ep_gpio, 1);
475 /* 500ms timeout value should be enough for Gen1/2 training */
476 timeout = jiffies + msecs_to_jiffies(500);
479 status = rockchip_pcie_read(rockchip,
480 PCIE_CLIENT_BASIC_STATUS1);
481 if ((status & PCIE_CLIENT_LINK_STATUS_MASK) ==
482 PCIE_CLIENT_LINK_STATUS_UP) {
483 dev_dbg(dev, "PCIe link training gen1 pass!\n");
487 if (time_after(jiffies, timeout)) {
488 dev_err(dev, "PCIe link training gen1 timeout!\n");
496 * Enable retrain for gen2. This should be configured only after
499 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
500 status |= PCIE_RC_CONFIG_LCS_RETRAIN_LINK;
501 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
503 timeout = jiffies + msecs_to_jiffies(500);
505 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
506 if ((status & PCIE_CORE_PL_CONF_SPEED_MASK) ==
507 PCIE_CORE_PL_CONF_SPEED_5G) {
508 dev_dbg(dev, "PCIe link training gen2 pass!\n");
512 if (time_after(jiffies, timeout)) {
513 dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
520 /* Check the final link width from negotiated lane counter from MGMT */
521 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
522 status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
523 PCIE_CORE_PL_CONF_LANE_MASK);
524 dev_dbg(dev, "current link width is x%d\n", status);
526 rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
527 PCIE_RC_CONFIG_VENDOR);
528 rockchip_pcie_write(rockchip,
529 PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
530 PCIE_RC_CONFIG_RID_CCR);
531 rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
533 rockchip_pcie_write(rockchip,
534 (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
535 PCIE_CORE_OB_REGION_ADDR0);
536 rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,
537 PCIE_CORE_OB_REGION_ADDR1);
538 rockchip_pcie_write(rockchip, 0x0080000a, PCIE_CORE_OB_REGION_DESC0);
539 rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
544 static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
546 struct rockchip_pcie *rockchip = arg;
547 struct device *dev = rockchip->dev;
551 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
552 if (reg & PCIE_CLIENT_INT_LOCAL) {
553 dev_dbg(dev, "local interrupt received\n");
554 sub_reg = rockchip_pcie_read(rockchip, PCIE_CORE_INT_STATUS);
555 if (sub_reg & PCIE_CORE_INT_PRFPE)
556 dev_dbg(dev, "parity error detected while reading from the PNP receive FIFO RAM\n");
558 if (sub_reg & PCIE_CORE_INT_CRFPE)
559 dev_dbg(dev, "parity error detected while reading from the Completion Receive FIFO RAM\n");
561 if (sub_reg & PCIE_CORE_INT_RRPE)
562 dev_dbg(dev, "parity error detected while reading from replay buffer RAM\n");
564 if (sub_reg & PCIE_CORE_INT_PRFO)
565 dev_dbg(dev, "overflow occurred in the PNP receive FIFO\n");
567 if (sub_reg & PCIE_CORE_INT_CRFO)
568 dev_dbg(dev, "overflow occurred in the completion receive FIFO\n");
570 if (sub_reg & PCIE_CORE_INT_RT)
571 dev_dbg(dev, "replay timer timed out\n");
573 if (sub_reg & PCIE_CORE_INT_RTR)
574 dev_dbg(dev, "replay timer rolled over after 4 transmissions of the same TLP\n");
576 if (sub_reg & PCIE_CORE_INT_PE)
577 dev_dbg(dev, "phy error detected on receive side\n");
579 if (sub_reg & PCIE_CORE_INT_MTR)
580 dev_dbg(dev, "malformed TLP received from the link\n");
582 if (sub_reg & PCIE_CORE_INT_UCR)
583 dev_dbg(dev, "malformed TLP received from the link\n");
585 if (sub_reg & PCIE_CORE_INT_FCE)
586 dev_dbg(dev, "an error was observed in the flow control advertisements from the other side\n");
588 if (sub_reg & PCIE_CORE_INT_CT)
589 dev_dbg(dev, "a request timed out waiting for completion\n");
591 if (sub_reg & PCIE_CORE_INT_UTC)
592 dev_dbg(dev, "unmapped TC error\n");
594 if (sub_reg & PCIE_CORE_INT_MMVC)
595 dev_dbg(dev, "MSI mask register changes\n");
597 rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
598 } else if (reg & PCIE_CLIENT_INT_PHY) {
599 dev_dbg(dev, "phy link changes\n");
600 rockchip_pcie_clr_bw_int(rockchip);
603 rockchip_pcie_write(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
604 PCIE_CLIENT_INT_STATUS);
609 static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
611 struct rockchip_pcie *rockchip = arg;
612 struct device *dev = rockchip->dev;
615 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
616 if (reg & PCIE_CLIENT_INT_LEGACY_DONE)
617 dev_dbg(dev, "legacy done interrupt received\n");
619 if (reg & PCIE_CLIENT_INT_MSG)
620 dev_dbg(dev, "message done interrupt received\n");
622 if (reg & PCIE_CLIENT_INT_HOT_RST)
623 dev_dbg(dev, "hot reset interrupt received\n");
625 if (reg & PCIE_CLIENT_INT_DPA)
626 dev_dbg(dev, "dpa interrupt received\n");
628 if (reg & PCIE_CLIENT_INT_FATAL_ERR)
629 dev_dbg(dev, "fatal error interrupt received\n");
631 if (reg & PCIE_CLIENT_INT_NFATAL_ERR)
632 dev_dbg(dev, "no fatal error interrupt received\n");
634 if (reg & PCIE_CLIENT_INT_CORR_ERR)
635 dev_dbg(dev, "correctable error interrupt received\n");
637 if (reg & PCIE_CLIENT_INT_PHY)
638 dev_dbg(dev, "phy interrupt received\n");
640 rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
641 PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
642 PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
643 PCIE_CLIENT_INT_NFATAL_ERR |
644 PCIE_CLIENT_INT_CORR_ERR |
645 PCIE_CLIENT_INT_PHY),
646 PCIE_CLIENT_INT_STATUS);
651 static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
653 struct irq_chip *chip = irq_desc_get_chip(desc);
654 struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
655 struct device *dev = rockchip->dev;
660 chained_irq_enter(chip, desc);
662 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
663 reg = (reg & PCIE_CLIENT_INTR_MASK) >> PCIE_CLIENT_INTR_SHIFT;
666 hwirq = ffs(reg) - 1;
669 virq = irq_find_mapping(rockchip->irq_domain, hwirq);
671 generic_handle_irq(virq);
673 dev_err(dev, "unexpected IRQ, INT%d\n", hwirq);
676 chained_irq_exit(chip, desc);
681 * rockchip_pcie_parse_dt - Parse Device Tree
682 * @rockchip: PCIe port information
684 * Return: '0' on success and error value on failure
686 static int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
688 struct device *dev = rockchip->dev;
689 struct platform_device *pdev = to_platform_device(dev);
690 struct device_node *node = dev->of_node;
691 struct resource *regs;
695 regs = platform_get_resource_byname(pdev,
698 rockchip->reg_base = devm_ioremap_resource(dev, regs);
699 if (IS_ERR(rockchip->reg_base))
700 return PTR_ERR(rockchip->reg_base);
702 regs = platform_get_resource_byname(pdev,
705 rockchip->apb_base = devm_ioremap_resource(dev, regs);
706 if (IS_ERR(rockchip->apb_base))
707 return PTR_ERR(rockchip->apb_base);
709 rockchip->phy = devm_phy_get(dev, "pcie-phy");
710 if (IS_ERR(rockchip->phy)) {
711 if (PTR_ERR(rockchip->phy) != -EPROBE_DEFER)
712 dev_err(dev, "missing phy\n");
713 return PTR_ERR(rockchip->phy);
717 err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
718 if (!err && (rockchip->lanes == 0 ||
719 rockchip->lanes == 3 ||
720 rockchip->lanes > 4)) {
721 dev_warn(dev, "invalid num-lanes, default to use one lane\n");
725 rockchip->core_rst = devm_reset_control_get(dev, "core");
726 if (IS_ERR(rockchip->core_rst)) {
727 if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)
728 dev_err(dev, "missing core reset property in node\n");
729 return PTR_ERR(rockchip->core_rst);
732 rockchip->mgmt_rst = devm_reset_control_get(dev, "mgmt");
733 if (IS_ERR(rockchip->mgmt_rst)) {
734 if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)
735 dev_err(dev, "missing mgmt reset property in node\n");
736 return PTR_ERR(rockchip->mgmt_rst);
739 rockchip->mgmt_sticky_rst = devm_reset_control_get(dev, "mgmt-sticky");
740 if (IS_ERR(rockchip->mgmt_sticky_rst)) {
741 if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
742 dev_err(dev, "missing mgmt-sticky reset property in node\n");
743 return PTR_ERR(rockchip->mgmt_sticky_rst);
746 rockchip->pipe_rst = devm_reset_control_get(dev, "pipe");
747 if (IS_ERR(rockchip->pipe_rst)) {
748 if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
749 dev_err(dev, "missing pipe reset property in node\n");
750 return PTR_ERR(rockchip->pipe_rst);
753 rockchip->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH);
754 if (IS_ERR(rockchip->ep_gpio)) {
755 dev_err(dev, "missing ep-gpios property in node\n");
756 return PTR_ERR(rockchip->ep_gpio);
759 rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
760 if (IS_ERR(rockchip->aclk_pcie)) {
761 dev_err(dev, "aclk clock not found\n");
762 return PTR_ERR(rockchip->aclk_pcie);
765 rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
766 if (IS_ERR(rockchip->aclk_perf_pcie)) {
767 dev_err(dev, "aclk_perf clock not found\n");
768 return PTR_ERR(rockchip->aclk_perf_pcie);
771 rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
772 if (IS_ERR(rockchip->hclk_pcie)) {
773 dev_err(dev, "hclk clock not found\n");
774 return PTR_ERR(rockchip->hclk_pcie);
777 rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
778 if (IS_ERR(rockchip->clk_pcie_pm)) {
779 dev_err(dev, "pm clock not found\n");
780 return PTR_ERR(rockchip->clk_pcie_pm);
783 irq = platform_get_irq_byname(pdev, "sys");
785 dev_err(dev, "missing sys IRQ resource\n");
789 err = devm_request_irq(dev, irq, rockchip_pcie_subsys_irq_handler,
790 IRQF_SHARED, "pcie-sys", rockchip);
792 dev_err(dev, "failed to request PCIe subsystem IRQ\n");
796 irq = platform_get_irq_byname(pdev, "legacy");
798 dev_err(dev, "missing legacy IRQ resource\n");
802 irq_set_chained_handler_and_data(irq,
803 rockchip_pcie_legacy_int_handler,
806 irq = platform_get_irq_byname(pdev, "client");
808 dev_err(dev, "missing client IRQ resource\n");
812 err = devm_request_irq(dev, irq, rockchip_pcie_client_irq_handler,
813 IRQF_SHARED, "pcie-client", rockchip);
815 dev_err(dev, "failed to request PCIe client IRQ\n");
819 rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
820 if (IS_ERR(rockchip->vpcie3v3)) {
821 if (PTR_ERR(rockchip->vpcie3v3) == -EPROBE_DEFER)
822 return -EPROBE_DEFER;
823 dev_info(dev, "no vpcie3v3 regulator found\n");
826 rockchip->vpcie1v8 = devm_regulator_get_optional(dev, "vpcie1v8");
827 if (IS_ERR(rockchip->vpcie1v8)) {
828 if (PTR_ERR(rockchip->vpcie1v8) == -EPROBE_DEFER)
829 return -EPROBE_DEFER;
830 dev_info(dev, "no vpcie1v8 regulator found\n");
833 rockchip->vpcie0v9 = devm_regulator_get_optional(dev, "vpcie0v9");
834 if (IS_ERR(rockchip->vpcie0v9)) {
835 if (PTR_ERR(rockchip->vpcie0v9) == -EPROBE_DEFER)
836 return -EPROBE_DEFER;
837 dev_info(dev, "no vpcie0v9 regulator found\n");
843 static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip)
845 struct device *dev = rockchip->dev;
848 if (!IS_ERR(rockchip->vpcie3v3)) {
849 err = regulator_enable(rockchip->vpcie3v3);
851 dev_err(dev, "fail to enable vpcie3v3 regulator\n");
856 if (!IS_ERR(rockchip->vpcie1v8)) {
857 err = regulator_enable(rockchip->vpcie1v8);
859 dev_err(dev, "fail to enable vpcie1v8 regulator\n");
860 goto err_disable_3v3;
864 if (!IS_ERR(rockchip->vpcie0v9)) {
865 err = regulator_enable(rockchip->vpcie0v9);
867 dev_err(dev, "fail to enable vpcie0v9 regulator\n");
868 goto err_disable_1v8;
875 if (!IS_ERR(rockchip->vpcie1v8))
876 regulator_disable(rockchip->vpcie1v8);
878 if (!IS_ERR(rockchip->vpcie3v3))
879 regulator_disable(rockchip->vpcie3v3);
884 static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip)
886 rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
887 (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK);
888 rockchip_pcie_write(rockchip, (u32)(~PCIE_CORE_INT),
891 rockchip_pcie_enable_bw_int(rockchip);
894 static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
895 irq_hw_number_t hwirq)
897 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
898 irq_set_chip_data(irq, domain->host_data);
903 static const struct irq_domain_ops intx_domain_ops = {
904 .map = rockchip_pcie_intx_map,
907 static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
909 struct device *dev = rockchip->dev;
910 struct device_node *intc = of_get_next_child(dev->of_node, NULL);
913 dev_err(dev, "missing child interrupt-controller node\n");
917 rockchip->irq_domain = irq_domain_add_linear(intc, 4,
918 &intx_domain_ops, rockchip);
919 if (!rockchip->irq_domain) {
920 dev_err(dev, "failed to get a INTx IRQ domain\n");
927 static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip,
928 int region_no, int type, u8 num_pass_bits,
929 u32 lower_addr, u32 upper_addr)
936 if (region_no >= MAX_AXI_WRAPPER_REGION_NUM)
938 if (num_pass_bits + 1 < 8)
940 if (num_pass_bits > 63)
942 if (region_no == 0) {
943 if (AXI_REGION_0_SIZE < (2ULL << num_pass_bits))
946 if (region_no != 0) {
947 if (AXI_REGION_SIZE < (2ULL << num_pass_bits))
951 aw_offset = (region_no << OB_REG_SIZE_SHIFT);
953 ob_addr_0 = num_pass_bits & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS;
954 ob_addr_0 |= lower_addr & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR;
955 ob_addr_1 = upper_addr;
956 ob_desc_0 = (1 << 23 | type);
958 rockchip_pcie_write(rockchip, ob_addr_0,
959 PCIE_CORE_OB_REGION_ADDR0 + aw_offset);
960 rockchip_pcie_write(rockchip, ob_addr_1,
961 PCIE_CORE_OB_REGION_ADDR1 + aw_offset);
962 rockchip_pcie_write(rockchip, ob_desc_0,
963 PCIE_CORE_OB_REGION_DESC0 + aw_offset);
964 rockchip_pcie_write(rockchip, 0,
965 PCIE_CORE_OB_REGION_DESC1 + aw_offset);
970 static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
971 int region_no, u8 num_pass_bits,
972 u32 lower_addr, u32 upper_addr)
978 if (region_no > MAX_AXI_IB_ROOTPORT_REGION_NUM)
980 if (num_pass_bits + 1 < MIN_AXI_ADDR_BITS_PASSED)
982 if (num_pass_bits > 63)
985 aw_offset = (region_no << IB_ROOT_PORT_REG_SIZE_SHIFT);
987 ib_addr_0 = num_pass_bits & PCIE_CORE_IB_REGION_ADDR0_NUM_BITS;
988 ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR;
989 ib_addr_1 = upper_addr;
991 rockchip_pcie_write(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
992 rockchip_pcie_write(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
997 static int rockchip_pcie_probe(struct platform_device *pdev)
999 struct rockchip_pcie *rockchip;
1000 struct device *dev = &pdev->dev;
1001 struct pci_bus *bus, *child;
1002 struct resource_entry *win;
1003 resource_size_t io_base;
1004 struct resource *mem;
1005 struct resource *io;
1006 phys_addr_t io_bus_addr = 0;
1008 phys_addr_t mem_bus_addr = 0;
1019 rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
1023 rockchip->dev = dev;
1025 err = rockchip_pcie_parse_dt(rockchip);
1029 err = clk_prepare_enable(rockchip->aclk_pcie);
1031 dev_err(dev, "unable to enable aclk_pcie clock\n");
1035 err = clk_prepare_enable(rockchip->aclk_perf_pcie);
1037 dev_err(dev, "unable to enable aclk_perf_pcie clock\n");
1038 goto err_aclk_perf_pcie;
1041 err = clk_prepare_enable(rockchip->hclk_pcie);
1043 dev_err(dev, "unable to enable hclk_pcie clock\n");
1047 err = clk_prepare_enable(rockchip->clk_pcie_pm);
1049 dev_err(dev, "unable to enable hclk_pcie clock\n");
1053 err = rockchip_pcie_set_vpcie(rockchip);
1055 dev_err(dev, "failed to set vpcie regulator\n");
1059 err = rockchip_pcie_init_port(rockchip);
1063 platform_set_drvdata(pdev, rockchip);
1065 rockchip_pcie_enable_interrupts(rockchip);
1067 err = rockchip_pcie_init_irq_domain(rockchip);
1071 err = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff,
1076 err = devm_request_pci_bus_resources(dev, &res);
1080 /* Get the I/O and memory ranges from DT */
1082 resource_list_for_each_entry(win, &res) {
1083 switch (resource_type(win->res)) {
1087 io_size = resource_size(io);
1088 io_bus_addr = io->start - win->offset;
1089 err = pci_remap_iospace(io, io_base);
1091 dev_warn(dev, "error %d: failed to map resource %pR\n",
1096 case IORESOURCE_MEM:
1099 mem_size = resource_size(mem);
1100 mem_bus_addr = mem->start - win->offset;
1102 case IORESOURCE_BUS:
1103 rockchip->root_bus_nr = win->res->start;
1111 for (reg_no = 0; reg_no < (mem_size >> 20); reg_no++) {
1112 err = rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1,
1113 AXI_WRAPPER_MEM_WRITE,
1119 dev_err(dev, "program RC mem outbound ATU failed\n");
1125 err = rockchip_pcie_prog_ib_atu(rockchip, 2, 32 - 1, 0x0, 0);
1127 dev_err(dev, "program RC mem inbound ATU failed\n");
1131 offset = mem_size >> 20;
1134 for (reg_no = 0; reg_no < (io_size >> 20); reg_no++) {
1135 err = rockchip_pcie_prog_ob_atu(rockchip,
1136 reg_no + 1 + offset,
1137 AXI_WRAPPER_IO_WRITE,
1143 dev_err(dev, "program RC io outbound ATU failed\n");
1149 bus = pci_scan_root_bus(&pdev->dev, 0, &rockchip_pcie_ops, rockchip, &res);
1155 pci_bus_size_bridges(bus);
1156 pci_bus_assign_resources(bus);
1157 list_for_each_entry(child, &bus->children, node)
1158 pcie_bus_configure_settings(child);
1160 pci_bus_add_devices(bus);
1162 dev_warn(dev, "only 32-bit config accesses supported; smaller writes may corrupt adjacent RW1C fields\n");
1167 if (!IS_ERR(rockchip->vpcie3v3))
1168 regulator_disable(rockchip->vpcie3v3);
1169 if (!IS_ERR(rockchip->vpcie1v8))
1170 regulator_disable(rockchip->vpcie1v8);
1171 if (!IS_ERR(rockchip->vpcie0v9))
1172 regulator_disable(rockchip->vpcie0v9);
1174 clk_disable_unprepare(rockchip->clk_pcie_pm);
1176 clk_disable_unprepare(rockchip->hclk_pcie);
1178 clk_disable_unprepare(rockchip->aclk_perf_pcie);
1180 clk_disable_unprepare(rockchip->aclk_pcie);
1185 static const struct of_device_id rockchip_pcie_of_match[] = {
1186 { .compatible = "rockchip,rk3399-pcie", },
1190 static struct platform_driver rockchip_pcie_driver = {
1192 .name = "rockchip-pcie",
1193 .of_match_table = rockchip_pcie_of_match,
1195 .probe = rockchip_pcie_probe,
1198 builtin_platform_driver(rockchip_pcie_driver);