1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
5 * Author: Ley Foon Tan <lftan@altera.com>
6 * Description: Altera PCIe host controller driver
9 #include <linux/delay.h>
10 #include <linux/interrupt.h>
11 #include <linux/irqchip/chained_irq.h>
12 #include <linux/init.h>
13 #include <linux/of_address.h>
14 #include <linux/of_irq.h>
15 #include <linux/of_pci.h>
16 #include <linux/pci.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
20 #define RP_TX_REG0 0x2000
21 #define RP_TX_REG1 0x2004
22 #define RP_TX_CNTRL 0x2008
25 #define RP_RXCPL_STATUS 0x2010
26 #define RP_RXCPL_EOP 0x2
27 #define RP_RXCPL_SOP 0x1
28 #define RP_RXCPL_REG0 0x2014
29 #define RP_RXCPL_REG1 0x2018
30 #define P2A_INT_STATUS 0x3060
31 #define P2A_INT_STS_ALL 0xf
32 #define P2A_INT_ENABLE 0x3070
33 #define P2A_INT_ENA_ALL 0xf
34 #define RP_LTSSM 0x3c64
35 #define RP_LTSSM_MASK 0x1f
38 #define PCIE_CAP_OFFSET 0x80
39 /* TLP configuration type 0 and 1 */
40 #define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */
41 #define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */
42 #define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */
43 #define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */
44 #define TLP_PAYLOAD_SIZE 0x01
45 #define TLP_READ_TAG 0x1d
46 #define TLP_WRITE_TAG 0x10
48 #define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
49 #define TLP_CFGRD_DW0(pcie, bus) \
50 ((((bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0 \
51 : TLP_FMTTYPE_CFGRD1) << 24) | \
53 #define TLP_CFGWR_DW0(pcie, bus) \
54 ((((bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0 \
55 : TLP_FMTTYPE_CFGWR1) << 24) | \
57 #define TLP_CFG_DW1(pcie, tag, be) \
58 (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
59 #define TLP_CFG_DW2(bus, devfn, offset) \
60 (((bus) << 24) | ((devfn) << 16) | (offset))
61 #define TLP_COMP_STATUS(s) (((s) >> 13) & 7)
62 #define TLP_HDR_SIZE 3
65 #define LINK_UP_TIMEOUT HZ
66 #define LINK_RETRAIN_TIMEOUT HZ
71 struct platform_device *pdev;
72 void __iomem *cra_base; /* DT Cra */
75 struct irq_domain *irq_domain;
76 struct resource bus_range;
77 struct list_head resources;
80 struct tlp_rp_regpair_t {
86 static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
89 writel_relaxed(value, pcie->cra_base + reg);
92 static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
94 return readl_relaxed(pcie->cra_base + reg);
97 static bool altera_pcie_link_up(struct altera_pcie *pcie)
99 return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
103 * Altera PCIe port uses BAR0 of RC's configuration space as the translation
104 * from PCI bus to native BUS. Entire DDR region is mapped into PCIe space
105 * using these registers, so it can be reached by DMA from EP devices.
106 * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt
107 * from EP devices, eventually trigger interrupt to GIC. The BAR0 of bridge
108 * should be hidden during enumeration to avoid the sizing and resource
109 * allocation by PCIe core.
111 static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn,
114 if (pci_is_root_bus(bus) && (devfn == 0) &&
115 (offset == PCI_BASE_ADDRESS_0))
121 static void tlp_write_tx(struct altera_pcie *pcie,
122 struct tlp_rp_regpair_t *tlp_rp_regdata)
124 cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0);
125 cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1);
126 cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);
129 static bool altera_pcie_valid_device(struct altera_pcie *pcie,
130 struct pci_bus *bus, int dev)
132 /* If there is no link, then there is no device */
133 if (bus->number != pcie->root_bus_nr) {
134 if (!altera_pcie_link_up(pcie))
138 /* access only one slot on each root port */
139 if (bus->number == pcie->root_bus_nr && dev > 0)
145 static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
154 * Minimum 2 loops to read TLP headers and 1 loop to read data
157 for (i = 0; i < TLP_LOOP; i++) {
158 ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
159 if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) {
160 reg0 = cra_readl(pcie, RP_RXCPL_REG0);
161 reg1 = cra_readl(pcie, RP_RXCPL_REG1);
163 if (ctrl & RP_RXCPL_SOP) {
165 comp_status = TLP_COMP_STATUS(reg1);
168 if (ctrl & RP_RXCPL_EOP) {
170 return PCIBIOS_DEVICE_NOT_FOUND;
175 return PCIBIOS_SUCCESSFUL;
181 return PCIBIOS_DEVICE_NOT_FOUND;
184 static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
185 u32 data, bool align)
187 struct tlp_rp_regpair_t tlp_rp_regdata;
189 tlp_rp_regdata.reg0 = headers[0];
190 tlp_rp_regdata.reg1 = headers[1];
191 tlp_rp_regdata.ctrl = RP_TX_SOP;
192 tlp_write_tx(pcie, &tlp_rp_regdata);
195 tlp_rp_regdata.reg0 = headers[2];
196 tlp_rp_regdata.reg1 = 0;
197 tlp_rp_regdata.ctrl = 0;
198 tlp_write_tx(pcie, &tlp_rp_regdata);
200 tlp_rp_regdata.reg0 = data;
201 tlp_rp_regdata.reg1 = 0;
203 tlp_rp_regdata.reg0 = headers[2];
204 tlp_rp_regdata.reg1 = data;
207 tlp_rp_regdata.ctrl = RP_TX_EOP;
208 tlp_write_tx(pcie, &tlp_rp_regdata);
211 static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
212 int where, u8 byte_en, u32 *value)
214 u32 headers[TLP_HDR_SIZE];
216 headers[0] = TLP_CFGRD_DW0(pcie, bus);
217 headers[1] = TLP_CFG_DW1(pcie, TLP_READ_TAG, byte_en);
218 headers[2] = TLP_CFG_DW2(bus, devfn, where);
220 tlp_write_packet(pcie, headers, 0, false);
222 return tlp_read_packet(pcie, value);
225 static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
226 int where, u8 byte_en, u32 value)
228 u32 headers[TLP_HDR_SIZE];
231 headers[0] = TLP_CFGWR_DW0(pcie, bus);
232 headers[1] = TLP_CFG_DW1(pcie, TLP_WRITE_TAG, byte_en);
233 headers[2] = TLP_CFG_DW2(bus, devfn, where);
235 /* check alignment to Qword */
236 if ((where & 0x7) == 0)
237 tlp_write_packet(pcie, headers, value, true);
239 tlp_write_packet(pcie, headers, value, false);
241 ret = tlp_read_packet(pcie, NULL);
242 if (ret != PCIBIOS_SUCCESSFUL)
246 * Monitor changes to PCI_PRIMARY_BUS register on root port
247 * and update local copy of root bus number accordingly.
249 if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS))
250 pcie->root_bus_nr = (u8)(value);
252 return PCIBIOS_SUCCESSFUL;
255 static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno,
256 unsigned int devfn, int where, int size,
265 byte_en = 1 << (where & 3);
268 byte_en = 3 << (where & 3);
275 ret = tlp_cfg_dword_read(pcie, busno, devfn,
276 (where & ~DWORD_MASK), byte_en, &data);
277 if (ret != PCIBIOS_SUCCESSFUL)
282 *value = (data >> (8 * (where & 0x3))) & 0xff;
285 *value = (data >> (8 * (where & 0x2))) & 0xffff;
292 return PCIBIOS_SUCCESSFUL;
295 static int _altera_pcie_cfg_write(struct altera_pcie *pcie, u8 busno,
296 unsigned int devfn, int where, int size,
300 u32 shift = 8 * (where & 3);
305 data32 = (value & 0xff) << shift;
306 byte_en = 1 << (where & 3);
309 data32 = (value & 0xffff) << shift;
310 byte_en = 3 << (where & 3);
318 return tlp_cfg_dword_write(pcie, busno, devfn, (where & ~DWORD_MASK),
322 static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
323 int where, int size, u32 *value)
325 struct altera_pcie *pcie = bus->sysdata;
327 if (altera_pcie_hide_rc_bar(bus, devfn, where))
328 return PCIBIOS_BAD_REGISTER_NUMBER;
330 if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn))) {
332 return PCIBIOS_DEVICE_NOT_FOUND;
335 return _altera_pcie_cfg_read(pcie, bus->number, devfn, where, size,
339 static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
340 int where, int size, u32 value)
342 struct altera_pcie *pcie = bus->sysdata;
344 if (altera_pcie_hide_rc_bar(bus, devfn, where))
345 return PCIBIOS_BAD_REGISTER_NUMBER;
347 if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn)))
348 return PCIBIOS_DEVICE_NOT_FOUND;
350 return _altera_pcie_cfg_write(pcie, bus->number, devfn, where, size,
354 static struct pci_ops altera_pcie_ops = {
355 .read = altera_pcie_cfg_read,
356 .write = altera_pcie_cfg_write,
359 static int altera_read_cap_word(struct altera_pcie *pcie, u8 busno,
360 unsigned int devfn, int offset, u16 *value)
365 ret = _altera_pcie_cfg_read(pcie, busno, devfn,
366 PCIE_CAP_OFFSET + offset, sizeof(*value),
372 static int altera_write_cap_word(struct altera_pcie *pcie, u8 busno,
373 unsigned int devfn, int offset, u16 value)
375 return _altera_pcie_cfg_write(pcie, busno, devfn,
376 PCIE_CAP_OFFSET + offset, sizeof(value),
380 static void altera_wait_link_retrain(struct altera_pcie *pcie)
382 struct device *dev = &pcie->pdev->dev;
384 unsigned long start_jiffies;
386 /* Wait for link training end. */
387 start_jiffies = jiffies;
389 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
390 PCI_EXP_LNKSTA, ®16);
391 if (!(reg16 & PCI_EXP_LNKSTA_LT))
394 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {
395 dev_err(dev, "link retrain timeout\n");
401 /* Wait for link is up */
402 start_jiffies = jiffies;
404 if (altera_pcie_link_up(pcie))
407 if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {
408 dev_err(dev, "link up timeout\n");
415 static void altera_pcie_retrain(struct altera_pcie *pcie)
417 u16 linkcap, linkstat, linkctl;
419 if (!altera_pcie_link_up(pcie))
423 * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
424 * current speed is 2.5 GB/s.
426 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKCAP,
428 if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
431 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKSTA,
433 if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
434 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
435 PCI_EXP_LNKCTL, &linkctl);
436 linkctl |= PCI_EXP_LNKCTL_RL;
437 altera_write_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
438 PCI_EXP_LNKCTL, linkctl);
440 altera_wait_link_retrain(pcie);
444 static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
445 irq_hw_number_t hwirq)
447 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
448 irq_set_chip_data(irq, domain->host_data);
452 static const struct irq_domain_ops intx_domain_ops = {
453 .map = altera_pcie_intx_map,
454 .xlate = pci_irqd_intx_xlate,
457 static void altera_pcie_isr(struct irq_desc *desc)
459 struct irq_chip *chip = irq_desc_get_chip(desc);
460 struct altera_pcie *pcie;
462 unsigned long status;
466 chained_irq_enter(chip, desc);
467 pcie = irq_desc_get_handler_data(desc);
468 dev = &pcie->pdev->dev;
470 while ((status = cra_readl(pcie, P2A_INT_STATUS)
471 & P2A_INT_STS_ALL) != 0) {
472 for_each_set_bit(bit, &status, PCI_NUM_INTX) {
473 /* clear interrupts */
474 cra_writel(pcie, 1 << bit, P2A_INT_STATUS);
476 virq = irq_find_mapping(pcie->irq_domain, bit);
478 generic_handle_irq(virq);
480 dev_err(dev, "unexpected IRQ, INT%d\n", bit);
484 chained_irq_exit(chip, desc);
487 static int altera_pcie_parse_request_of_pci_ranges(struct altera_pcie *pcie)
489 int err, res_valid = 0;
490 struct device *dev = &pcie->pdev->dev;
491 struct resource_entry *win;
493 err = of_pci_get_host_bridge_resources(dev, 0, 0xff,
494 &pcie->resources, NULL);
498 err = devm_request_pci_bus_resources(dev, &pcie->resources);
500 goto out_release_res;
502 resource_list_for_each_entry(win, &pcie->resources) {
503 struct resource *res = win->res;
505 if (resource_type(res) == IORESOURCE_MEM)
506 res_valid |= !(res->flags & IORESOURCE_PREFETCH);
512 dev_err(dev, "non-prefetchable memory resource required\n");
516 pci_free_resource_list(&pcie->resources);
520 static int altera_pcie_init_irq_domain(struct altera_pcie *pcie)
522 struct device *dev = &pcie->pdev->dev;
523 struct device_node *node = dev->of_node;
526 pcie->irq_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
527 &intx_domain_ops, pcie);
528 if (!pcie->irq_domain) {
529 dev_err(dev, "Failed to get a INTx IRQ domain\n");
536 static int altera_pcie_parse_dt(struct altera_pcie *pcie)
538 struct device *dev = &pcie->pdev->dev;
539 struct platform_device *pdev = pcie->pdev;
540 struct resource *cra;
542 cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra");
543 pcie->cra_base = devm_ioremap_resource(dev, cra);
544 if (IS_ERR(pcie->cra_base))
545 return PTR_ERR(pcie->cra_base);
548 pcie->irq = platform_get_irq(pdev, 0);
550 dev_err(dev, "failed to get IRQ: %d\n", pcie->irq);
554 irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie);
558 static void altera_pcie_host_init(struct altera_pcie *pcie)
560 altera_pcie_retrain(pcie);
563 static int altera_pcie_probe(struct platform_device *pdev)
565 struct device *dev = &pdev->dev;
566 struct altera_pcie *pcie;
568 struct pci_bus *child;
569 struct pci_host_bridge *bridge;
572 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
576 pcie = pci_host_bridge_priv(bridge);
579 ret = altera_pcie_parse_dt(pcie);
581 dev_err(dev, "Parsing DT failed\n");
585 INIT_LIST_HEAD(&pcie->resources);
587 ret = altera_pcie_parse_request_of_pci_ranges(pcie);
589 dev_err(dev, "Failed add resources\n");
593 ret = altera_pcie_init_irq_domain(pcie);
595 dev_err(dev, "Failed creating IRQ Domain\n");
599 /* clear all interrupts */
600 cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
601 /* enable all interrupts */
602 cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
603 altera_pcie_host_init(pcie);
605 list_splice_init(&pcie->resources, &bridge->windows);
606 bridge->dev.parent = dev;
607 bridge->sysdata = pcie;
608 bridge->busnr = pcie->root_bus_nr;
609 bridge->ops = &altera_pcie_ops;
610 bridge->map_irq = of_irq_parse_and_map_pci;
611 bridge->swizzle_irq = pci_common_swizzle;
613 ret = pci_scan_root_bus_bridge(bridge);
619 pci_assign_unassigned_bus_resources(bus);
621 /* Configure PCI Express setting. */
622 list_for_each_entry(child, &bus->children, node)
623 pcie_bus_configure_settings(child);
625 pci_bus_add_devices(bus);
629 static const struct of_device_id altera_pcie_of_match[] = {
630 { .compatible = "altr,pcie-root-port-1.0", },
634 static struct platform_driver altera_pcie_driver = {
635 .probe = altera_pcie_probe,
637 .name = "altera-pcie",
638 .of_match_table = altera_pcie_of_match,
639 .suppress_bind_attrs = true,
643 builtin_platform_driver(altera_pcie_driver);