2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program. If not, see <http://www.gnu.org/licenses/>.
14 * Copyright (C) 2015 - 2016 Cavium, Inc.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/of_address.h>
20 #include <linux/of_pci.h>
21 #include <linux/platform_device.h>
25 #define PEM_CFG_WR 0x28
26 #define PEM_CFG_RD 0x30
28 struct thunder_pem_pci {
30 void __iomem *pem_reg_base;
33 static int thunder_pem_bridge_read(struct pci_bus *bus, unsigned int devfn,
34 int where, int size, u32 *val)
37 struct pci_config_window *cfg = bus->sysdata;
38 struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
40 if (devfn != 0 || where >= 2048) {
42 return PCIBIOS_DEVICE_NOT_FOUND;
46 * 32-bit accesses only. Write the address to the low order
47 * bits of PEM_CFG_RD, then trigger the read by reading back.
48 * The config data lands in the upper 32-bits of PEM_CFG_RD.
50 read_val = where & ~3ull;
51 writeq(read_val, pem_pci->pem_reg_base + PEM_CFG_RD);
52 read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
56 * The config space contains some garbage, fix it up. Also
57 * synthesize an EA capability for the BAR used by MSI-X.
61 read_val &= 0xffff00ff;
62 read_val |= 0x00007000; /* Skip MSI CAP */
64 case 0x70: /* Express Cap */
65 /* PME interrupt on vector 2*/
66 read_val |= (2u << 25);
68 case 0xb0: /* MSI-X Cap */
69 /* TableSize=4, Next Cap is EA */
70 read_val &= 0xc00000ff;
71 read_val |= 0x0003bc00;
74 /* Table offset=0, BIR=0 */
75 read_val = 0x00000000;
78 /* BPA offset=0xf0000, BIR=0 */
79 read_val = 0x000f0000;
82 /* EA, 1 entry, no next Cap */
83 read_val = 0x00010014;
87 read_val = 0x00000000;
90 /* Entry BEI=0, PP=0x00, SP=0xff, ES=3 */
91 read_val = 0x80ff0003;
94 read_val = pem_pci->ea_entry[0];
97 read_val = pem_pci->ea_entry[1];
100 read_val = pem_pci->ea_entry[2];
105 read_val >>= (8 * (where & 3));
117 return PCIBIOS_SUCCESSFUL;
120 static int thunder_pem_config_read(struct pci_bus *bus, unsigned int devfn,
121 int where, int size, u32 *val)
123 struct pci_config_window *cfg = bus->sysdata;
125 if (bus->number < cfg->busr.start ||
126 bus->number > cfg->busr.end)
127 return PCIBIOS_DEVICE_NOT_FOUND;
130 * The first device on the bus is the PEM PCIe bridge.
131 * Special case its config access.
133 if (bus->number == cfg->busr.start)
134 return thunder_pem_bridge_read(bus, devfn, where, size, val);
136 return pci_generic_config_read(bus, devfn, where, size, val);
140 * Some of the w1c_bits below also include read-only or non-writable
141 * reserved bits, this makes the code simpler and is OK as the bits
142 * are not affected by writing zeros to them.
144 static u32 thunder_pem_bridge_w1c_bits(u64 where_aligned)
148 switch (where_aligned) {
149 case 0x04: /* Command/Status */
150 case 0x1c: /* Base and I/O Limit/Secondary Status */
151 w1c_bits = 0xff000000;
153 case 0x44: /* Power Management Control and Status */
154 w1c_bits = 0xfffffe00;
156 case 0x78: /* Device Control/Device Status */
157 case 0x80: /* Link Control/Link Status */
158 case 0x88: /* Slot Control/Slot Status */
159 case 0x90: /* Root Status */
160 case 0xa0: /* Link Control 2 Registers/Link Status 2 */
161 w1c_bits = 0xffff0000;
163 case 0x104: /* Uncorrectable Error Status */
164 case 0x110: /* Correctable Error Status */
165 case 0x130: /* Error Status */
166 case 0x160: /* Link Control 4 */
167 w1c_bits = 0xffffffff;
175 /* Some bits must be written to one so they appear to be read-only. */
176 static u32 thunder_pem_bridge_w1_bits(u64 where_aligned)
180 switch (where_aligned) {
181 case 0x1c: /* I/O Base / I/O Limit, Secondary Status */
182 /* Force 32-bit I/O addressing. */
185 case 0x24: /* Prefetchable Memory Base / Prefetchable Memory Limit */
186 /* Force 64-bit addressing */
187 w1_bits = 0x00010001;
196 static int thunder_pem_bridge_write(struct pci_bus *bus, unsigned int devfn,
197 int where, int size, u32 val)
199 struct pci_config_window *cfg = bus->sysdata;
200 struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
201 u64 write_val, read_val;
202 u64 where_aligned = where & ~3ull;
206 if (devfn != 0 || where >= 2048)
207 return PCIBIOS_DEVICE_NOT_FOUND;
210 * 32-bit accesses only. If the write is for a size smaller
211 * than 32-bits, we must first read the 32-bit value and merge
212 * in the desired bits and then write the whole 32-bits back
217 writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);
218 read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
220 mask = ~(0xff << (8 * (where & 3)));
222 val = (val & 0xff) << (8 * (where & 3));
223 val |= (u32)read_val;
226 writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);
227 read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
229 mask = ~(0xffff << (8 * (where & 3)));
231 val = (val & 0xffff) << (8 * (where & 3));
232 val |= (u32)read_val;
239 * By expanding the write width to 32 bits, we may
240 * inadvertently hit some W1C bits that were not intended to
241 * be written. Calculate the mask that must be applied to the
242 * data to be written to avoid these cases.
245 u32 w1c_bits = thunder_pem_bridge_w1c_bits(where);
254 * Some bits must be read-only with value of one. Since the
255 * access method allows these to be cleared if a zero is
256 * written, force them to one before writing.
258 val |= thunder_pem_bridge_w1_bits(where_aligned);
261 * Low order bits are the config address, the high order 32
262 * bits are the data to be written.
264 write_val = (((u64)val) << 32) | where_aligned;
265 writeq(write_val, pem_pci->pem_reg_base + PEM_CFG_WR);
266 return PCIBIOS_SUCCESSFUL;
269 static int thunder_pem_config_write(struct pci_bus *bus, unsigned int devfn,
270 int where, int size, u32 val)
272 struct pci_config_window *cfg = bus->sysdata;
274 if (bus->number < cfg->busr.start ||
275 bus->number > cfg->busr.end)
276 return PCIBIOS_DEVICE_NOT_FOUND;
278 * The first device on the bus is the PEM PCIe bridge.
279 * Special case its config access.
281 if (bus->number == cfg->busr.start)
282 return thunder_pem_bridge_write(bus, devfn, where, size, val);
285 return pci_generic_config_write(bus, devfn, where, size, val);
288 static int thunder_pem_init(struct device *dev, struct pci_config_window *cfg)
290 resource_size_t bar4_start;
291 struct resource *res_pem;
292 struct thunder_pem_pci *pem_pci;
293 struct platform_device *pdev;
295 /* Only OF support for now */
299 pem_pci = devm_kzalloc(dev, sizeof(*pem_pci), GFP_KERNEL);
303 pdev = to_platform_device(dev);
306 * The second register range is the PEM bridge to the PCIe
307 * bus. It has a different config access method than those
308 * devices behind the bridge.
310 res_pem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
312 dev_err(dev, "missing \"reg[1]\"property\n");
316 pem_pci->pem_reg_base = devm_ioremap(dev, res_pem->start, 0x10000);
317 if (!pem_pci->pem_reg_base)
321 * The MSI-X BAR for the PEM and AER interrupts is located at
322 * a fixed offset from the PEM register base. Generate a
323 * fragment of the synthesized Enhanced Allocation capability
324 * structure here for the BAR.
326 bar4_start = res_pem->start + 0xf00000;
327 pem_pci->ea_entry[0] = (u32)bar4_start | 2;
328 pem_pci->ea_entry[1] = (u32)(res_pem->end - bar4_start) & ~3u;
329 pem_pci->ea_entry[2] = (u32)(bar4_start >> 32);
335 static struct pci_ecam_ops pci_thunder_pem_ops = {
337 .init = thunder_pem_init,
339 .map_bus = pci_ecam_map_bus,
340 .read = thunder_pem_config_read,
341 .write = thunder_pem_config_write,
345 static const struct of_device_id thunder_pem_of_match[] = {
346 { .compatible = "cavium,pci-host-thunder-pem" },
349 MODULE_DEVICE_TABLE(of, thunder_pem_of_match);
351 static int thunder_pem_probe(struct platform_device *pdev)
353 return pci_host_common_probe(pdev, &pci_thunder_pem_ops);
356 static struct platform_driver thunder_pem_driver = {
358 .name = KBUILD_MODNAME,
359 .of_match_table = thunder_pem_of_match,
361 .probe = thunder_pem_probe,
363 module_platform_driver(thunder_pem_driver);
365 MODULE_DESCRIPTION("Thunder PEM PCIe host driver");
366 MODULE_LICENSE("GPL v2");