1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
6 * Copyright (C) 2016 Marvell
8 * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com>
11 #include <linux/delay.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/pci-ecam.h>
20 #include <linux/init.h>
21 #include <linux/phy/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/msi.h>
24 #include <linux/of_address.h>
25 #include <linux/of_gpio.h>
26 #include <linux/of_pci.h>
29 #include "../pci-bridge-emul.h"
31 /* PCIe core registers */
32 #define PCIE_CORE_DEV_ID_REG 0x0
33 #define PCIE_CORE_CMD_STATUS_REG 0x4
34 #define PCIE_CORE_DEV_REV_REG 0x8
35 #define PCIE_CORE_PCIEXP_CAP 0xc0
36 #define PCIE_CORE_ERR_CAPCTL_REG 0x118
37 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
38 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
39 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7)
40 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8)
41 /* PIO registers base address and register offsets */
42 #define PIO_BASE_ADDR 0x4000
43 #define PIO_CTRL (PIO_BASE_ADDR + 0x0)
44 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
45 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
46 #define PIO_STAT (PIO_BASE_ADDR + 0x4)
47 #define PIO_COMPLETION_STATUS_SHIFT 7
48 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
49 #define PIO_COMPLETION_STATUS_OK 0
50 #define PIO_COMPLETION_STATUS_UR 1
51 #define PIO_COMPLETION_STATUS_CRS 2
52 #define PIO_COMPLETION_STATUS_CA 4
53 #define PIO_NON_POSTED_REQ BIT(10)
54 #define PIO_ERR_STATUS BIT(11)
55 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
56 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
57 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
58 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
59 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
60 #define PIO_START (PIO_BASE_ADDR + 0x1c)
61 #define PIO_ISR (PIO_BASE_ADDR + 0x20)
62 #define PIO_ISRM (PIO_BASE_ADDR + 0x24)
64 /* Aardvark Control registers */
65 #define CONTROL_BASE_ADDR 0x4800
66 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
67 #define PCIE_GEN_SEL_MSK 0x3
68 #define PCIE_GEN_SEL_SHIFT 0x0
74 #define LANE_CNT_MSK 0x18
75 #define LANE_CNT_SHIFT 0x3
76 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
77 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
78 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
79 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
80 #define LINK_TRAINING_EN BIT(6)
81 #define LEGACY_INTA BIT(28)
82 #define LEGACY_INTB BIT(29)
83 #define LEGACY_INTC BIT(30)
84 #define LEGACY_INTD BIT(31)
85 #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4)
86 #define HOT_RESET_GEN BIT(0)
87 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
88 #define PCIE_CORE_CTRL2_RESERVED 0x7
89 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
90 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
91 #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6)
92 #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10)
93 #define PCIE_CORE_REF_CLK_REG (CONTROL_BASE_ADDR + 0x14)
94 #define PCIE_CORE_REF_CLK_TX_ENABLE BIT(1)
95 #define PCIE_CORE_REF_CLK_RX_ENABLE BIT(2)
96 #define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30)
97 #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40)
98 #define PCIE_MSG_PM_PME_MASK BIT(7)
99 #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44)
100 #define PCIE_ISR0_MSI_INT_PENDING BIT(24)
101 #define PCIE_ISR0_CORR_ERR BIT(11)
102 #define PCIE_ISR0_NFAT_ERR BIT(12)
103 #define PCIE_ISR0_FAT_ERR BIT(13)
104 #define PCIE_ISR0_ERR_MASK GENMASK(13, 11)
105 #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val))
106 #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val))
107 #define PCIE_ISR0_ALL_MASK GENMASK(31, 0)
108 #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48)
109 #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
110 #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
111 #define PCIE_ISR1_FLUSH BIT(5)
112 #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val))
113 #define PCIE_ISR1_ALL_MASK GENMASK(31, 0)
114 #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
115 #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
116 #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
117 #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C)
118 #define PCIE_MSI_ALL_MASK GENMASK(31, 0)
119 #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C)
120 #define PCIE_MSI_DATA_MASK GENMASK(15, 0)
122 /* PCIe window configuration */
123 #define OB_WIN_BASE_ADDR 0x4c00
124 #define OB_WIN_BLOCK_SIZE 0x20
125 #define OB_WIN_COUNT 8
126 #define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \
127 OB_WIN_BLOCK_SIZE * (win) + \
129 #define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00)
130 #define OB_WIN_ENABLE BIT(0)
131 #define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04)
132 #define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08)
133 #define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c)
134 #define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10)
135 #define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14)
136 #define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18)
137 #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
138 #define OB_WIN_FUNC_NUM_MASK GENMASK(31, 24)
139 #define OB_WIN_FUNC_NUM_SHIFT 24
140 #define OB_WIN_FUNC_NUM_ENABLE BIT(23)
141 #define OB_WIN_BUS_NUM_BITS_MASK GENMASK(22, 20)
142 #define OB_WIN_BUS_NUM_BITS_SHIFT 20
143 #define OB_WIN_MSG_CODE_ENABLE BIT(22)
144 #define OB_WIN_MSG_CODE_MASK GENMASK(21, 14)
145 #define OB_WIN_MSG_CODE_SHIFT 14
146 #define OB_WIN_MSG_PAYLOAD_LEN BIT(12)
147 #define OB_WIN_ATTR_ENABLE BIT(11)
148 #define OB_WIN_ATTR_TC_MASK GENMASK(10, 8)
149 #define OB_WIN_ATTR_TC_SHIFT 8
150 #define OB_WIN_ATTR_RELAXED BIT(7)
151 #define OB_WIN_ATTR_NOSNOOP BIT(6)
152 #define OB_WIN_ATTR_POISON BIT(5)
153 #define OB_WIN_ATTR_IDO BIT(4)
154 #define OB_WIN_TYPE_MASK GENMASK(3, 0)
155 #define OB_WIN_TYPE_SHIFT 0
156 #define OB_WIN_TYPE_MEM 0x0
157 #define OB_WIN_TYPE_IO 0x4
158 #define OB_WIN_TYPE_CONFIG_TYPE0 0x8
159 #define OB_WIN_TYPE_CONFIG_TYPE1 0x9
160 #define OB_WIN_TYPE_MSG 0xc
162 /* LMI registers base address and register offsets */
163 #define LMI_BASE_ADDR 0x6000
164 #define CFG_REG (LMI_BASE_ADDR + 0x0)
165 #define LTSSM_SHIFT 24
166 #define LTSSM_MASK 0x3f
167 #define RC_BAR_CONFIG 0x300
169 /* LTSSM values in CFG_REG */
171 LTSSM_DETECT_QUIET = 0x0,
172 LTSSM_DETECT_ACTIVE = 0x1,
173 LTSSM_POLLING_ACTIVE = 0x2,
174 LTSSM_POLLING_COMPLIANCE = 0x3,
175 LTSSM_POLLING_CONFIGURATION = 0x4,
176 LTSSM_CONFIG_LINKWIDTH_START = 0x5,
177 LTSSM_CONFIG_LINKWIDTH_ACCEPT = 0x6,
178 LTSSM_CONFIG_LANENUM_ACCEPT = 0x7,
179 LTSSM_CONFIG_LANENUM_WAIT = 0x8,
180 LTSSM_CONFIG_COMPLETE = 0x9,
181 LTSSM_CONFIG_IDLE = 0xa,
182 LTSSM_RECOVERY_RCVR_LOCK = 0xb,
183 LTSSM_RECOVERY_SPEED = 0xc,
184 LTSSM_RECOVERY_RCVR_CFG = 0xd,
185 LTSSM_RECOVERY_IDLE = 0xe,
187 LTSSM_RX_L0S_ENTRY = 0x11,
188 LTSSM_RX_L0S_IDLE = 0x12,
189 LTSSM_RX_L0S_FTS = 0x13,
190 LTSSM_TX_L0S_ENTRY = 0x14,
191 LTSSM_TX_L0S_IDLE = 0x15,
192 LTSSM_TX_L0S_FTS = 0x16,
193 LTSSM_L1_ENTRY = 0x17,
194 LTSSM_L1_IDLE = 0x18,
195 LTSSM_L2_IDLE = 0x19,
196 LTSSM_L2_TRANSMIT_WAKE = 0x1a,
197 LTSSM_DISABLED = 0x20,
198 LTSSM_LOOPBACK_ENTRY_MASTER = 0x21,
199 LTSSM_LOOPBACK_ACTIVE_MASTER = 0x22,
200 LTSSM_LOOPBACK_EXIT_MASTER = 0x23,
201 LTSSM_LOOPBACK_ENTRY_SLAVE = 0x24,
202 LTSSM_LOOPBACK_ACTIVE_SLAVE = 0x25,
203 LTSSM_LOOPBACK_EXIT_SLAVE = 0x26,
204 LTSSM_HOT_RESET = 0x27,
205 LTSSM_RECOVERY_EQUALIZATION_PHASE0 = 0x28,
206 LTSSM_RECOVERY_EQUALIZATION_PHASE1 = 0x29,
207 LTSSM_RECOVERY_EQUALIZATION_PHASE2 = 0x2a,
208 LTSSM_RECOVERY_EQUALIZATION_PHASE3 = 0x2b,
211 #define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44)
213 /* PCIe core controller registers */
214 #define CTRL_CORE_BASE_ADDR 0x18000
215 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
216 #define CTRL_MODE_SHIFT 0x0
217 #define CTRL_MODE_MASK 0x1
218 #define PCIE_CORE_MODE_DIRECT 0x0
219 #define PCIE_CORE_MODE_COMMAND 0x1
221 /* PCIe Central Interrupts Registers */
222 #define CENTRAL_INT_BASE_ADDR 0x1b000
223 #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0)
224 #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4)
225 #define PCIE_IRQ_CMDQ_INT BIT(0)
226 #define PCIE_IRQ_MSI_STATUS_INT BIT(1)
227 #define PCIE_IRQ_CMD_SENT_DONE BIT(3)
228 #define PCIE_IRQ_DMA_INT BIT(4)
229 #define PCIE_IRQ_IB_DXFERDONE BIT(5)
230 #define PCIE_IRQ_OB_DXFERDONE BIT(6)
231 #define PCIE_IRQ_OB_RXFERDONE BIT(7)
232 #define PCIE_IRQ_COMPQ_INT BIT(12)
233 #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13)
234 #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14)
235 #define PCIE_IRQ_CORE_INT BIT(16)
236 #define PCIE_IRQ_CORE_INT_PIO BIT(17)
237 #define PCIE_IRQ_DPMU_INT BIT(18)
238 #define PCIE_IRQ_PCIE_MIS_INT BIT(19)
239 #define PCIE_IRQ_MSI_INT1_DET BIT(20)
240 #define PCIE_IRQ_MSI_INT2_DET BIT(21)
241 #define PCIE_IRQ_RC_DBELL_DET BIT(22)
242 #define PCIE_IRQ_EP_STATUS BIT(23)
243 #define PCIE_IRQ_ALL_MASK GENMASK(31, 0)
244 #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT
246 /* Transaction types */
247 #define PCIE_CONFIG_RD_TYPE0 0x8
248 #define PCIE_CONFIG_RD_TYPE1 0x9
249 #define PCIE_CONFIG_WR_TYPE0 0xa
250 #define PCIE_CONFIG_WR_TYPE1 0xb
252 #define PIO_RETRY_CNT 750000 /* 1.5 s */
253 #define PIO_RETRY_DELAY 2 /* 2 us*/
255 #define LINK_WAIT_MAX_RETRIES 10
256 #define LINK_WAIT_USLEEP_MIN 90000
257 #define LINK_WAIT_USLEEP_MAX 100000
258 #define RETRAIN_WAIT_MAX_RETRIES 10
259 #define RETRAIN_WAIT_USLEEP_US 2000
261 #define MSI_IRQ_NUM 32
263 #define CFG_RD_CRS_VAL 0xffff0001
266 struct platform_device *pdev;
273 } wins[OB_WIN_COUNT];
276 struct irq_domain *irq_domain;
277 struct irq_chip irq_chip;
278 raw_spinlock_t irq_lock;
279 struct irq_domain *msi_domain;
280 struct irq_domain *msi_inner_domain;
281 raw_spinlock_t msi_irq_lock;
282 DECLARE_BITMAP(msi_used, MSI_IRQ_NUM);
283 struct mutex msi_used_lock;
285 struct pci_bridge_emul bridge;
286 struct gpio_desc *reset_gpio;
290 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg)
292 writel(val, pcie->base + reg);
295 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg)
297 return readl(pcie->base + reg);
300 static u8 advk_pcie_ltssm_state(struct advk_pcie *pcie)
305 val = advk_readl(pcie, CFG_REG);
306 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
310 static inline bool advk_pcie_link_up(struct advk_pcie *pcie)
312 /* check if LTSSM is in normal operation - some L* state */
313 u8 ltssm_state = advk_pcie_ltssm_state(pcie);
314 return ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED;
317 static inline bool advk_pcie_link_active(struct advk_pcie *pcie)
320 * According to PCIe Base specification 3.0, Table 4-14: Link
321 * Status Mapped to the LTSSM, and 4.2.6.3.6 Configuration.Idle
322 * is Link Up mapped to LTSSM Configuration.Idle, Recovery, L0,
323 * L0s, L1 and L2 states. And according to 3.2.1. Data Link
324 * Control and Management State Machine Rules is DL Up status
325 * reported in DL Active state.
327 u8 ltssm_state = advk_pcie_ltssm_state(pcie);
328 return ltssm_state >= LTSSM_CONFIG_IDLE && ltssm_state < LTSSM_DISABLED;
331 static inline bool advk_pcie_link_training(struct advk_pcie *pcie)
334 * According to PCIe Base specification 3.0, Table 4-14: Link
335 * Status Mapped to the LTSSM is Link Training mapped to LTSSM
336 * Configuration and Recovery states.
338 u8 ltssm_state = advk_pcie_ltssm_state(pcie);
339 return ((ltssm_state >= LTSSM_CONFIG_LINKWIDTH_START &&
340 ltssm_state < LTSSM_L0) ||
341 (ltssm_state >= LTSSM_RECOVERY_EQUALIZATION_PHASE0 &&
342 ltssm_state <= LTSSM_RECOVERY_EQUALIZATION_PHASE3));
345 static int advk_pcie_wait_for_link(struct advk_pcie *pcie)
349 /* check if the link is up or not */
350 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
351 if (advk_pcie_link_up(pcie))
354 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
360 static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie)
364 for (retries = 0; retries < RETRAIN_WAIT_MAX_RETRIES; ++retries) {
365 if (advk_pcie_link_training(pcie))
367 udelay(RETRAIN_WAIT_USLEEP_US);
371 static void advk_pcie_issue_perst(struct advk_pcie *pcie)
373 if (!pcie->reset_gpio)
376 /* 10ms delay is needed for some cards */
377 dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n");
378 gpiod_set_value_cansleep(pcie->reset_gpio, 1);
379 usleep_range(10000, 11000);
380 gpiod_set_value_cansleep(pcie->reset_gpio, 0);
383 static void advk_pcie_train_link(struct advk_pcie *pcie)
385 struct device *dev = &pcie->pdev->dev;
390 * Setup PCIe rev / gen compliance based on device tree property
391 * 'max-link-speed' which also forces maximal link speed.
393 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
394 reg &= ~PCIE_GEN_SEL_MSK;
395 if (pcie->link_gen == 3)
397 else if (pcie->link_gen == 2)
401 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
404 * Set maximal link speed value also into PCIe Link Control 2 register.
405 * Armada 3700 Functional Specification says that default value is based
406 * on SPEED_GEN but tests showed that default value is always 8.0 GT/s.
408 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2);
409 reg &= ~PCI_EXP_LNKCTL2_TLS;
410 if (pcie->link_gen == 3)
411 reg |= PCI_EXP_LNKCTL2_TLS_8_0GT;
412 else if (pcie->link_gen == 2)
413 reg |= PCI_EXP_LNKCTL2_TLS_5_0GT;
415 reg |= PCI_EXP_LNKCTL2_TLS_2_5GT;
416 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2);
418 /* Enable link training after selecting PCIe generation */
419 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
420 reg |= LINK_TRAINING_EN;
421 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
424 * Reset PCIe card via PERST# signal. Some cards are not detected
425 * during link training when they are in some non-initial state.
427 advk_pcie_issue_perst(pcie);
430 * PERST# signal could have been asserted by pinctrl subsystem before
431 * probe() callback has been called or issued explicitly by reset gpio
432 * function advk_pcie_issue_perst(), making the endpoint going into
433 * fundamental reset. As required by PCI Express spec (PCI Express
434 * Base Specification, REV. 4.0 PCI Express, February 19 2014, 6.6.1
435 * Conventional Reset) a delay for at least 100ms after such a reset
436 * before sending a Configuration Request to the device is needed.
437 * So wait until PCIe link is up. Function advk_pcie_wait_for_link()
438 * waits for link at least 900ms.
440 ret = advk_pcie_wait_for_link(pcie);
442 dev_err(dev, "link never came up\n");
444 dev_info(dev, "link up\n");
448 * Set PCIe address window register which could be used for memory
451 static void advk_pcie_set_ob_win(struct advk_pcie *pcie, u8 win_num,
452 phys_addr_t match, phys_addr_t remap,
453 phys_addr_t mask, u32 actions)
455 advk_writel(pcie, OB_WIN_ENABLE |
456 lower_32_bits(match), OB_WIN_MATCH_LS(win_num));
457 advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num));
458 advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num));
459 advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num));
460 advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num));
461 advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num));
462 advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num));
465 static void advk_pcie_disable_ob_win(struct advk_pcie *pcie, u8 win_num)
467 advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num));
468 advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num));
469 advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num));
470 advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num));
471 advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num));
472 advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num));
473 advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num));
476 static void advk_pcie_setup_hw(struct advk_pcie *pcie)
478 phys_addr_t msi_addr;
483 * Configure PCIe Reference clock. Direction is from the PCIe
484 * controller to the endpoint card, so enable transmitting of
485 * Reference clock differential signal off-chip and disable
486 * receiving off-chip differential signal.
488 reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG);
489 reg |= PCIE_CORE_REF_CLK_TX_ENABLE;
490 reg &= ~PCIE_CORE_REF_CLK_RX_ENABLE;
491 advk_writel(pcie, reg, PCIE_CORE_REF_CLK_REG);
493 /* Set to Direct mode */
494 reg = advk_readl(pcie, CTRL_CONFIG_REG);
495 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
496 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
497 advk_writel(pcie, reg, CTRL_CONFIG_REG);
499 /* Set PCI global control register to RC mode */
500 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
501 reg |= (IS_RC_MSK << IS_RC_SHIFT);
502 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
505 * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab.
506 * VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor
507 * id in high 16 bits. Updating this register changes readback value of
508 * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround
509 * for erratum 4.1: "The value of device and vendor ID is incorrect".
511 reg = (PCI_VENDOR_ID_MARVELL << 16) | PCI_VENDOR_ID_MARVELL;
512 advk_writel(pcie, reg, VENDOR_ID_REG);
515 * Change Class Code of PCI Bridge device to PCI Bridge (0x600400),
516 * because the default value is Mass storage controller (0x010400).
518 * Note that this Aardvark PCI Bridge does not have compliant Type 1
519 * Configuration Space and it even cannot be accessed via Aardvark's
520 * PCI config space access method. Something like config space is
521 * available in internal Aardvark registers starting at offset 0x0
522 * and is reported as Type 0. In range 0x10 - 0x34 it has totally
523 * different registers.
525 * Therefore driver uses emulation of PCI Bridge which emulates
526 * access to configuration space via internal Aardvark registers or
527 * emulated configuration buffer.
529 reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG);
531 reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;
532 advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG);
534 /* Disable Root Bridge I/O space, memory space and bus mastering */
535 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
536 reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
537 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
539 /* Set Advanced Error Capabilities and Control PF0 register */
540 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
541 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
542 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK |
543 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV;
544 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
546 /* Set PCIe Device Control register */
547 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
548 reg &= ~PCI_EXP_DEVCTL_RELAX_EN;
549 reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
550 reg &= ~PCI_EXP_DEVCTL_PAYLOAD;
551 reg &= ~PCI_EXP_DEVCTL_READRQ;
552 reg |= PCI_EXP_DEVCTL_PAYLOAD_512B;
553 reg |= PCI_EXP_DEVCTL_READRQ_512B;
554 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
556 /* Program PCIe Control 2 to disable strict ordering */
557 reg = PCIE_CORE_CTRL2_RESERVED |
558 PCIE_CORE_CTRL2_TD_ENABLE;
559 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
562 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
563 reg &= ~LANE_CNT_MSK;
565 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
567 /* Set MSI address */
568 msi_addr = virt_to_phys(pcie);
569 advk_writel(pcie, lower_32_bits(msi_addr), PCIE_MSI_ADDR_LOW_REG);
570 advk_writel(pcie, upper_32_bits(msi_addr), PCIE_MSI_ADDR_HIGH_REG);
573 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
574 reg |= PCIE_CORE_CTRL2_MSI_ENABLE;
575 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
577 /* Clear all interrupts */
578 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG);
579 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
580 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
581 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
583 /* Disable All ISR0/1 and MSI Sources */
584 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG);
585 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
586 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
588 /* Unmask summary MSI interrupt */
589 reg = advk_readl(pcie, PCIE_ISR0_MASK_REG);
590 reg &= ~PCIE_ISR0_MSI_INT_PENDING;
591 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
593 /* Unmask PME interrupt for processing of PME requester */
594 reg = advk_readl(pcie, PCIE_ISR0_MASK_REG);
595 reg &= ~PCIE_MSG_PM_PME_MASK;
596 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
598 /* Enable summary interrupt for GIC SPI source */
599 reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
600 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);
603 * Enable AXI address window location generation:
604 * When it is enabled, the default outbound window
605 * configurations (Default User Field: 0xD0074CFC)
606 * are used to transparent address translation for
607 * the outbound transactions. Thus, PCIe address
608 * windows are not required for transparent memory
609 * access when default outbound window configuration
610 * is set for memory access.
612 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
613 reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE;
614 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
617 * Set memory access in Default User Field so it
618 * is not required to configure PCIe address for
619 * transparent memory access.
621 advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS);
624 * Bypass the address window mapping for PIO:
625 * Since PIO access already contains all required
626 * info over AXI interface by PIO registers, the
627 * address window is not required.
629 reg = advk_readl(pcie, PIO_CTRL);
630 reg |= PIO_CTRL_ADDR_WIN_DISABLE;
631 advk_writel(pcie, reg, PIO_CTRL);
634 * Configure PCIe address windows for non-memory or
635 * non-transparent access as by default PCIe uses
636 * transparent memory access.
638 for (i = 0; i < pcie->wins_count; i++)
639 advk_pcie_set_ob_win(pcie, i,
640 pcie->wins[i].match, pcie->wins[i].remap,
641 pcie->wins[i].mask, pcie->wins[i].actions);
643 /* Disable remaining PCIe outbound windows */
644 for (i = pcie->wins_count; i < OB_WIN_COUNT; i++)
645 advk_pcie_disable_ob_win(pcie, i);
647 advk_pcie_train_link(pcie);
650 static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u32 *val)
652 struct device *dev = &pcie->pdev->dev;
655 char *strcomp_status, *str_posted;
658 reg = advk_readl(pcie, PIO_STAT);
659 status = (reg & PIO_COMPLETION_STATUS_MASK) >>
660 PIO_COMPLETION_STATUS_SHIFT;
663 * According to HW spec, the PIO status check sequence as below:
664 * 1) even if COMPLETION_STATUS(bit9:7) indicates successful,
665 * it still needs to check Error Status(bit11), only when this bit
666 * indicates no error happen, the operation is successful.
667 * 2) value Unsupported Request(1) of COMPLETION_STATUS(bit9:7) only
668 * means a PIO write error, and for PIO read it is successful with
669 * a read value of 0xFFFFFFFF.
670 * 3) value Completion Retry Status(CRS) of COMPLETION_STATUS(bit9:7)
671 * only means a PIO write error, and for PIO read it is successful
672 * with a read value of 0xFFFF0001.
673 * 4) value Completer Abort (CA) of COMPLETION_STATUS(bit9:7) means
674 * error for both PIO read and PIO write operation.
675 * 5) other errors are indicated as 'unknown'.
678 case PIO_COMPLETION_STATUS_OK:
679 if (reg & PIO_ERR_STATUS) {
680 strcomp_status = "COMP_ERR";
684 /* Get the read result */
686 *val = advk_readl(pcie, PIO_RD_DATA);
688 strcomp_status = NULL;
691 case PIO_COMPLETION_STATUS_UR:
692 strcomp_status = "UR";
695 case PIO_COMPLETION_STATUS_CRS:
696 if (allow_crs && val) {
697 /* PCIe r4.0, sec 2.3.2, says:
698 * If CRS Software Visibility is enabled:
699 * For a Configuration Read Request that includes both
700 * bytes of the Vendor ID field of a device Function's
701 * Configuration Space Header, the Root Complex must
702 * complete the Request to the host by returning a
703 * read-data value of 0001h for the Vendor ID field and
704 * all '1's for any additional bytes included in the
707 * So CRS in this case is not an error status.
709 *val = CFG_RD_CRS_VAL;
710 strcomp_status = NULL;
714 /* PCIe r4.0, sec 2.3.2, says:
715 * If CRS Software Visibility is not enabled, the Root Complex
716 * must re-issue the Configuration Request as a new Request.
717 * If CRS Software Visibility is enabled: For a Configuration
718 * Write Request or for any other Configuration Read Request,
719 * the Root Complex must re-issue the Configuration Request as
721 * A Root Complex implementation may choose to limit the number
722 * of Configuration Request/CRS Completion Status loops before
723 * determining that something is wrong with the target of the
724 * Request and taking appropriate action, e.g., complete the
725 * Request to the host as a failed transaction.
727 * So return -EAGAIN and caller (pci-aardvark.c driver) will
728 * re-issue request again up to the PIO_RETRY_CNT retries.
730 strcomp_status = "CRS";
733 case PIO_COMPLETION_STATUS_CA:
734 strcomp_status = "CA";
738 strcomp_status = "Unknown";
746 if (reg & PIO_NON_POSTED_REQ)
747 str_posted = "Non-posted";
749 str_posted = "Posted";
751 dev_dbg(dev, "%s PIO Response Status: %s, %#x @ %#x\n",
752 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS));
757 static int advk_pcie_wait_pio(struct advk_pcie *pcie)
759 struct device *dev = &pcie->pdev->dev;
762 for (i = 1; i <= PIO_RETRY_CNT; i++) {
765 start = advk_readl(pcie, PIO_START);
766 isr = advk_readl(pcie, PIO_ISR);
769 udelay(PIO_RETRY_DELAY);
772 dev_err(dev, "PIO read/write transfer time out\n");
776 static pci_bridge_emul_read_status_t
777 advk_pci_bridge_emul_base_conf_read(struct pci_bridge_emul *bridge,
780 struct advk_pcie *pcie = bridge->data;
784 *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
785 return PCI_BRIDGE_EMUL_HANDLED;
787 case PCI_INTERRUPT_LINE: {
789 * From the whole 32bit register we support reading from HW only
790 * two bits: PCI_BRIDGE_CTL_BUS_RESET and PCI_BRIDGE_CTL_SERR.
791 * Other bits are retrieved only from emulated config buffer.
793 __le32 *cfgspace = (__le32 *)&bridge->conf;
794 u32 val = le32_to_cpu(cfgspace[PCI_INTERRUPT_LINE / 4]);
795 if (advk_readl(pcie, PCIE_ISR0_MASK_REG) & PCIE_ISR0_ERR_MASK)
796 val &= ~(PCI_BRIDGE_CTL_SERR << 16);
798 val |= PCI_BRIDGE_CTL_SERR << 16;
799 if (advk_readl(pcie, PCIE_CORE_CTRL1_REG) & HOT_RESET_GEN)
800 val |= PCI_BRIDGE_CTL_BUS_RESET << 16;
802 val &= ~(PCI_BRIDGE_CTL_BUS_RESET << 16);
804 return PCI_BRIDGE_EMUL_HANDLED;
808 return PCI_BRIDGE_EMUL_NOT_HANDLED;
813 advk_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
814 int reg, u32 old, u32 new, u32 mask)
816 struct advk_pcie *pcie = bridge->data;
820 advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG);
823 case PCI_INTERRUPT_LINE:
825 * According to Figure 6-3: Pseudo Logic Diagram for Error
826 * Message Controls in PCIe base specification, SERR# Enable bit
827 * in Bridge Control register enable receiving of ERR_* messages
829 if (mask & (PCI_BRIDGE_CTL_SERR << 16)) {
830 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);
831 if (new & (PCI_BRIDGE_CTL_SERR << 16))
832 val &= ~PCIE_ISR0_ERR_MASK;
834 val |= PCIE_ISR0_ERR_MASK;
835 advk_writel(pcie, val, PCIE_ISR0_MASK_REG);
837 if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) {
838 u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG);
839 if (new & (PCI_BRIDGE_CTL_BUS_RESET << 16))
840 val |= HOT_RESET_GEN;
842 val &= ~HOT_RESET_GEN;
843 advk_writel(pcie, val, PCIE_CORE_CTRL1_REG);
852 static pci_bridge_emul_read_status_t
853 advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
856 struct advk_pcie *pcie = bridge->data;
861 *value = PCI_EXP_SLTSTA_PDS << 16;
862 return PCI_BRIDGE_EMUL_HANDLED;
865 * PCI_EXP_RTCTL and PCI_EXP_RTSTA are also supported, but do not need
866 * to be handled here, because their values are stored in emulated
867 * config space buffer, and we read them from there when needed.
870 case PCI_EXP_LNKCAP: {
871 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);
873 * PCI_EXP_LNKCAP_DLLLARC bit is hardwired in aardvark HW to 0.
874 * But support for PCI_EXP_LNKSTA_DLLLA is emulated via ltssm
875 * state so explicitly enable PCI_EXP_LNKCAP_DLLLARC flag.
877 val |= PCI_EXP_LNKCAP_DLLLARC;
879 return PCI_BRIDGE_EMUL_HANDLED;
882 case PCI_EXP_LNKCTL: {
883 /* u32 contains both PCI_EXP_LNKCTL and PCI_EXP_LNKSTA */
884 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) &
885 ~(PCI_EXP_LNKSTA_LT << 16);
886 if (advk_pcie_link_training(pcie))
887 val |= (PCI_EXP_LNKSTA_LT << 16);
888 if (advk_pcie_link_active(pcie))
889 val |= (PCI_EXP_LNKSTA_DLLLA << 16);
891 return PCI_BRIDGE_EMUL_HANDLED;
896 case PCI_EXP_DEVCAP2:
897 case PCI_EXP_DEVCTL2:
898 case PCI_EXP_LNKCAP2:
899 case PCI_EXP_LNKCTL2:
900 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);
901 return PCI_BRIDGE_EMUL_HANDLED;
904 return PCI_BRIDGE_EMUL_NOT_HANDLED;
910 advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
911 int reg, u32 old, u32 new, u32 mask)
913 struct advk_pcie *pcie = bridge->data;
917 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
918 if (new & PCI_EXP_LNKCTL_RL)
919 advk_pcie_wait_for_retrain(pcie);
922 case PCI_EXP_RTCTL: {
923 u16 rootctl = le16_to_cpu(bridge->pcie_conf.rootctl);
924 /* Only emulation of PMEIE and CRSSVE bits is provided */
925 rootctl &= PCI_EXP_RTCTL_PMEIE | PCI_EXP_RTCTL_CRSSVE;
926 bridge->pcie_conf.rootctl = cpu_to_le16(rootctl);
931 * PCI_EXP_RTSTA is also supported, but does not need to be handled
932 * here, because its value is stored in emulated config space buffer,
933 * and we write it there when needed.
937 case PCI_EXP_DEVCTL2:
938 case PCI_EXP_LNKCTL2:
939 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
947 static struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = {
948 .read_base = advk_pci_bridge_emul_base_conf_read,
949 .write_base = advk_pci_bridge_emul_base_conf_write,
950 .read_pcie = advk_pci_bridge_emul_pcie_conf_read,
951 .write_pcie = advk_pci_bridge_emul_pcie_conf_write,
955 * Initialize the configuration space of the PCI-to-PCI bridge
956 * associated with the given PCIe interface.
958 static int advk_sw_pci_bridge_init(struct advk_pcie *pcie)
960 struct pci_bridge_emul *bridge = &pcie->bridge;
962 bridge->conf.vendor =
963 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff);
964 bridge->conf.device =
965 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16);
966 bridge->conf.class_revision =
967 cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff);
969 /* Support 32 bits I/O addressing */
970 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32;
971 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
973 /* Support 64 bits memory pref */
974 bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
975 bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
977 /* Support interrupt A for MSI feature */
978 bridge->conf.intpin = PCI_INTERRUPT_INTA;
980 /* Aardvark HW provides PCIe Capability structure in version 2 */
981 bridge->pcie_conf.cap = cpu_to_le16(2);
983 /* Indicates supports for Completion Retry Status */
984 bridge->pcie_conf.rootcap = cpu_to_le16(PCI_EXP_RTCAP_CRSVIS);
986 bridge->has_pcie = true;
988 bridge->ops = &advk_pci_bridge_emul_ops;
990 return pci_bridge_emul_init(bridge, 0);
993 static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus,
996 if (pci_is_root_bus(bus) && PCI_SLOT(devfn) != 0)
1000 * If the link goes down after we check for link-up, nothing bad
1001 * happens but the config access times out.
1003 if (!pci_is_root_bus(bus) && !advk_pcie_link_up(pcie))
1009 static bool advk_pcie_pio_is_running(struct advk_pcie *pcie)
1011 struct device *dev = &pcie->pdev->dev;
1014 * Trying to start a new PIO transfer when previous has not completed
1015 * cause External Abort on CPU which results in kernel panic:
1017 * SError Interrupt on CPU0, code 0xbf000002 -- SError
1018 * Kernel panic - not syncing: Asynchronous SError Interrupt
1020 * Functions advk_pcie_rd_conf() and advk_pcie_wr_conf() are protected
1021 * by raw_spin_lock_irqsave() at pci_lock_config() level to prevent
1022 * concurrent calls at the same time. But because PIO transfer may take
1023 * about 1.5s when link is down or card is disconnected, it means that
1024 * advk_pcie_wait_pio() does not always have to wait for completion.
1026 * Some versions of ARM Trusted Firmware handles this External Abort at
1027 * EL3 level and mask it to prevent kernel panic. Relevant TF-A commit:
1028 * https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7dcdac5c50
1030 if (advk_readl(pcie, PIO_START)) {
1031 dev_err(dev, "Previous PIO read/write transfer is still running\n");
1038 static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
1039 int where, int size, u32 *val)
1041 struct advk_pcie *pcie = bus->sysdata;
1047 if (!advk_pcie_valid_device(pcie, bus, devfn))
1048 return PCIBIOS_DEVICE_NOT_FOUND;
1050 if (pci_is_root_bus(bus))
1051 return pci_bridge_emul_conf_read(&pcie->bridge, where,
1055 * Completion Retry Status is possible to return only when reading all
1056 * 4 bytes from PCI_VENDOR_ID and PCI_DEVICE_ID registers at once and
1057 * CRSSVE flag on Root Bridge is enabled.
1059 allow_crs = (where == PCI_VENDOR_ID) && (size == 4) &&
1060 (le16_to_cpu(pcie->bridge.pcie_conf.rootctl) &
1061 PCI_EXP_RTCTL_CRSSVE);
1063 if (advk_pcie_pio_is_running(pcie))
1066 /* Program the control register */
1067 reg = advk_readl(pcie, PIO_CTRL);
1068 reg &= ~PIO_CTRL_TYPE_MASK;
1069 if (pci_is_root_bus(bus->parent))
1070 reg |= PCIE_CONFIG_RD_TYPE0;
1072 reg |= PCIE_CONFIG_RD_TYPE1;
1073 advk_writel(pcie, reg, PIO_CTRL);
1075 /* Program the address registers */
1076 reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4);
1077 advk_writel(pcie, reg, PIO_ADDR_LS);
1078 advk_writel(pcie, 0, PIO_ADDR_MS);
1080 /* Program the data strobe */
1081 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB);
1085 /* Clear PIO DONE ISR and start the transfer */
1086 advk_writel(pcie, 1, PIO_ISR);
1087 advk_writel(pcie, 1, PIO_START);
1089 ret = advk_pcie_wait_pio(pcie);
1095 /* Check PIO status and get the read result */
1096 ret = advk_pcie_check_pio_status(pcie, allow_crs, val);
1097 } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT);
1103 *val = (*val >> (8 * (where & 3))) & 0xff;
1105 *val = (*val >> (8 * (where & 3))) & 0xffff;
1107 return PCIBIOS_SUCCESSFUL;
1111 * If it is possible, return Completion Retry Status so that caller
1112 * tries to issue the request again instead of failing.
1115 *val = CFG_RD_CRS_VAL;
1116 return PCIBIOS_SUCCESSFUL;
1121 return PCIBIOS_SET_FAILED;
1124 static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
1125 int where, int size, u32 val)
1127 struct advk_pcie *pcie = bus->sysdata;
1129 u32 data_strobe = 0x0;
1134 if (!advk_pcie_valid_device(pcie, bus, devfn))
1135 return PCIBIOS_DEVICE_NOT_FOUND;
1137 if (pci_is_root_bus(bus))
1138 return pci_bridge_emul_conf_write(&pcie->bridge, where,
1142 return PCIBIOS_SET_FAILED;
1144 if (advk_pcie_pio_is_running(pcie))
1145 return PCIBIOS_SET_FAILED;
1147 /* Program the control register */
1148 reg = advk_readl(pcie, PIO_CTRL);
1149 reg &= ~PIO_CTRL_TYPE_MASK;
1150 if (pci_is_root_bus(bus->parent))
1151 reg |= PCIE_CONFIG_WR_TYPE0;
1153 reg |= PCIE_CONFIG_WR_TYPE1;
1154 advk_writel(pcie, reg, PIO_CTRL);
1156 /* Program the address registers */
1157 reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4);
1158 advk_writel(pcie, reg, PIO_ADDR_LS);
1159 advk_writel(pcie, 0, PIO_ADDR_MS);
1161 /* Calculate the write strobe */
1162 offset = where & 0x3;
1163 reg = val << (8 * offset);
1164 data_strobe = GENMASK(size - 1, 0) << offset;
1166 /* Program the data register */
1167 advk_writel(pcie, reg, PIO_WR_DATA);
1169 /* Program the data strobe */
1170 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB);
1174 /* Clear PIO DONE ISR and start the transfer */
1175 advk_writel(pcie, 1, PIO_ISR);
1176 advk_writel(pcie, 1, PIO_START);
1178 ret = advk_pcie_wait_pio(pcie);
1180 return PCIBIOS_SET_FAILED;
1184 ret = advk_pcie_check_pio_status(pcie, false, NULL);
1185 } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT);
1187 return ret < 0 ? PCIBIOS_SET_FAILED : PCIBIOS_SUCCESSFUL;
1190 static struct pci_ops advk_pcie_ops = {
1191 .read = advk_pcie_rd_conf,
1192 .write = advk_pcie_wr_conf,
1195 static void advk_msi_irq_compose_msi_msg(struct irq_data *data,
1196 struct msi_msg *msg)
1198 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data);
1199 phys_addr_t msi_addr = virt_to_phys(pcie);
1201 msg->address_lo = lower_32_bits(msi_addr);
1202 msg->address_hi = upper_32_bits(msi_addr);
1203 msg->data = data->hwirq;
1206 static int advk_msi_set_affinity(struct irq_data *irq_data,
1207 const struct cpumask *mask, bool force)
1212 static void advk_msi_irq_mask(struct irq_data *d)
1214 struct advk_pcie *pcie = d->domain->host_data;
1215 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1216 unsigned long flags;
1219 raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags);
1220 mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
1222 advk_writel(pcie, mask, PCIE_MSI_MASK_REG);
1223 raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags);
1226 static void advk_msi_irq_unmask(struct irq_data *d)
1228 struct advk_pcie *pcie = d->domain->host_data;
1229 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1230 unsigned long flags;
1233 raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags);
1234 mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
1235 mask &= ~BIT(hwirq);
1236 advk_writel(pcie, mask, PCIE_MSI_MASK_REG);
1237 raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags);
1240 static void advk_msi_top_irq_mask(struct irq_data *d)
1242 pci_msi_mask_irq(d);
1243 irq_chip_mask_parent(d);
1246 static void advk_msi_top_irq_unmask(struct irq_data *d)
1248 pci_msi_unmask_irq(d);
1249 irq_chip_unmask_parent(d);
1252 static struct irq_chip advk_msi_bottom_irq_chip = {
1254 .irq_compose_msi_msg = advk_msi_irq_compose_msi_msg,
1255 .irq_set_affinity = advk_msi_set_affinity,
1256 .irq_mask = advk_msi_irq_mask,
1257 .irq_unmask = advk_msi_irq_unmask,
1260 static int advk_msi_irq_domain_alloc(struct irq_domain *domain,
1262 unsigned int nr_irqs, void *args)
1264 struct advk_pcie *pcie = domain->host_data;
1267 mutex_lock(&pcie->msi_used_lock);
1268 hwirq = bitmap_find_free_region(pcie->msi_used, MSI_IRQ_NUM,
1269 order_base_2(nr_irqs));
1270 mutex_unlock(&pcie->msi_used_lock);
1274 for (i = 0; i < nr_irqs; i++)
1275 irq_domain_set_info(domain, virq + i, hwirq + i,
1276 &advk_msi_bottom_irq_chip,
1277 domain->host_data, handle_simple_irq,
1283 static void advk_msi_irq_domain_free(struct irq_domain *domain,
1284 unsigned int virq, unsigned int nr_irqs)
1286 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
1287 struct advk_pcie *pcie = domain->host_data;
1289 mutex_lock(&pcie->msi_used_lock);
1290 bitmap_release_region(pcie->msi_used, d->hwirq, order_base_2(nr_irqs));
1291 mutex_unlock(&pcie->msi_used_lock);
1294 static const struct irq_domain_ops advk_msi_domain_ops = {
1295 .alloc = advk_msi_irq_domain_alloc,
1296 .free = advk_msi_irq_domain_free,
1299 static void advk_pcie_irq_mask(struct irq_data *d)
1301 struct advk_pcie *pcie = d->domain->host_data;
1302 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1303 unsigned long flags;
1306 raw_spin_lock_irqsave(&pcie->irq_lock, flags);
1307 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
1308 mask |= PCIE_ISR1_INTX_ASSERT(hwirq);
1309 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
1310 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
1313 static void advk_pcie_irq_unmask(struct irq_data *d)
1315 struct advk_pcie *pcie = d->domain->host_data;
1316 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1317 unsigned long flags;
1320 raw_spin_lock_irqsave(&pcie->irq_lock, flags);
1321 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
1322 mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);
1323 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
1324 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
1327 static int advk_pcie_irq_map(struct irq_domain *h,
1328 unsigned int virq, irq_hw_number_t hwirq)
1330 struct advk_pcie *pcie = h->host_data;
1332 advk_pcie_irq_mask(irq_get_irq_data(virq));
1333 irq_set_status_flags(virq, IRQ_LEVEL);
1334 irq_set_chip_and_handler(virq, &pcie->irq_chip,
1336 irq_set_chip_data(virq, pcie);
1341 static const struct irq_domain_ops advk_pcie_irq_domain_ops = {
1342 .map = advk_pcie_irq_map,
1343 .xlate = irq_domain_xlate_onecell,
1346 static struct irq_chip advk_msi_irq_chip = {
1348 .irq_mask = advk_msi_top_irq_mask,
1349 .irq_unmask = advk_msi_top_irq_unmask,
1352 static struct msi_domain_info advk_msi_domain_info = {
1353 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
1354 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
1355 .chip = &advk_msi_irq_chip,
1358 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)
1360 struct device *dev = &pcie->pdev->dev;
1362 raw_spin_lock_init(&pcie->msi_irq_lock);
1363 mutex_init(&pcie->msi_used_lock);
1365 pcie->msi_inner_domain =
1366 irq_domain_add_linear(NULL, MSI_IRQ_NUM,
1367 &advk_msi_domain_ops, pcie);
1368 if (!pcie->msi_inner_domain)
1372 pci_msi_create_irq_domain(dev_fwnode(dev),
1373 &advk_msi_domain_info,
1374 pcie->msi_inner_domain);
1375 if (!pcie->msi_domain) {
1376 irq_domain_remove(pcie->msi_inner_domain);
1383 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie)
1385 irq_domain_remove(pcie->msi_domain);
1386 irq_domain_remove(pcie->msi_inner_domain);
1389 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie)
1391 struct device *dev = &pcie->pdev->dev;
1392 struct device_node *node = dev->of_node;
1393 struct device_node *pcie_intc_node;
1394 struct irq_chip *irq_chip;
1397 raw_spin_lock_init(&pcie->irq_lock);
1399 pcie_intc_node = of_get_next_child(node, NULL);
1400 if (!pcie_intc_node) {
1401 dev_err(dev, "No PCIe Intc node found\n");
1405 irq_chip = &pcie->irq_chip;
1407 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq",
1409 if (!irq_chip->name) {
1414 irq_chip->irq_mask = advk_pcie_irq_mask;
1415 irq_chip->irq_mask_ack = advk_pcie_irq_mask;
1416 irq_chip->irq_unmask = advk_pcie_irq_unmask;
1419 irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
1420 &advk_pcie_irq_domain_ops, pcie);
1421 if (!pcie->irq_domain) {
1422 dev_err(dev, "Failed to get a INTx IRQ domain\n");
1428 of_node_put(pcie_intc_node);
1432 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie)
1434 irq_domain_remove(pcie->irq_domain);
1437 static void advk_pcie_handle_pme(struct advk_pcie *pcie)
1439 u32 requester = advk_readl(pcie, PCIE_MSG_LOG_REG) >> 16;
1441 advk_writel(pcie, PCIE_MSG_PM_PME_MASK, PCIE_ISR0_REG);
1444 * PCIE_MSG_LOG_REG contains the last inbound message, so store
1445 * the requester ID only when PME was not asserted yet.
1446 * Also do not trigger PME interrupt when PME is still asserted.
1448 if (!(le32_to_cpu(pcie->bridge.pcie_conf.rootsta) & PCI_EXP_RTSTA_PME)) {
1449 pcie->bridge.pcie_conf.rootsta = cpu_to_le32(requester | PCI_EXP_RTSTA_PME);
1452 * Trigger PME interrupt only if PMEIE bit in Root Control is set.
1453 * Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ, so use PCIe interrupt 0.
1455 if (!(le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & PCI_EXP_RTCTL_PMEIE))
1458 if (generic_handle_domain_irq(pcie->irq_domain, 0) == -EINVAL)
1459 dev_err_ratelimited(&pcie->pdev->dev, "unhandled PME IRQ\n");
1463 static void advk_pcie_handle_msi(struct advk_pcie *pcie)
1465 u32 msi_val, msi_mask, msi_status, msi_idx;
1467 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
1468 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
1469 msi_status = msi_val & ((~msi_mask) & PCIE_MSI_ALL_MASK);
1471 for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {
1472 if (!(BIT(msi_idx) & msi_status))
1475 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG);
1476 if (generic_handle_domain_irq(pcie->msi_inner_domain, msi_idx) == -EINVAL)
1477 dev_err_ratelimited(&pcie->pdev->dev, "unexpected MSI 0x%02x\n", msi_idx);
1480 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,
1484 static void advk_pcie_handle_int(struct advk_pcie *pcie)
1486 u32 isr0_val, isr0_mask, isr0_status;
1487 u32 isr1_val, isr1_mask, isr1_status;
1490 isr0_val = advk_readl(pcie, PCIE_ISR0_REG);
1491 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
1492 isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK);
1494 isr1_val = advk_readl(pcie, PCIE_ISR1_REG);
1495 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
1496 isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);
1498 /* Process PME interrupt as the first one to do not miss PME requester id */
1499 if (isr0_status & PCIE_MSG_PM_PME_MASK)
1500 advk_pcie_handle_pme(pcie);
1502 /* Process ERR interrupt */
1503 if (isr0_status & PCIE_ISR0_ERR_MASK) {
1504 advk_writel(pcie, PCIE_ISR0_ERR_MASK, PCIE_ISR0_REG);
1507 * Aardvark HW returns zero for PCI_ERR_ROOT_AER_IRQ, so use
1510 if (generic_handle_domain_irq(pcie->irq_domain, 0) == -EINVAL)
1511 dev_err_ratelimited(&pcie->pdev->dev, "unhandled ERR IRQ\n");
1514 /* Process MSI interrupts */
1515 if (isr0_status & PCIE_ISR0_MSI_INT_PENDING)
1516 advk_pcie_handle_msi(pcie);
1518 /* Process legacy interrupts */
1519 for (i = 0; i < PCI_NUM_INTX; i++) {
1520 if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i)))
1523 advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
1526 if (generic_handle_domain_irq(pcie->irq_domain, i) == -EINVAL)
1527 dev_err_ratelimited(&pcie->pdev->dev, "unexpected INT%c IRQ\n",
1532 static void advk_pcie_irq_handler(struct irq_desc *desc)
1534 struct advk_pcie *pcie = irq_desc_get_handler_data(desc);
1535 struct irq_chip *chip = irq_desc_get_chip(desc);
1536 u32 val, mask, status;
1538 chained_irq_enter(chip, desc);
1540 val = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
1541 mask = advk_readl(pcie, HOST_CTRL_INT_MASK_REG);
1542 status = val & ((~mask) & PCIE_IRQ_ALL_MASK);
1544 if (status & PCIE_IRQ_CORE_INT) {
1545 advk_pcie_handle_int(pcie);
1547 /* Clear interrupt */
1548 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG);
1551 chained_irq_exit(chip, desc);
1554 static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie)
1556 phy_power_off(pcie->phy);
1557 phy_exit(pcie->phy);
1560 static int advk_pcie_enable_phy(struct advk_pcie *pcie)
1567 ret = phy_init(pcie->phy);
1571 ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE);
1573 phy_exit(pcie->phy);
1577 ret = phy_power_on(pcie->phy);
1578 if (ret == -EOPNOTSUPP) {
1579 dev_warn(&pcie->pdev->dev, "PHY unsupported by firmware\n");
1581 phy_exit(pcie->phy);
1588 static int advk_pcie_setup_phy(struct advk_pcie *pcie)
1590 struct device *dev = &pcie->pdev->dev;
1591 struct device_node *node = dev->of_node;
1594 pcie->phy = devm_of_phy_get(dev, node, NULL);
1595 if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) == -EPROBE_DEFER))
1596 return PTR_ERR(pcie->phy);
1598 /* Old bindings miss the PHY handle */
1599 if (IS_ERR(pcie->phy)) {
1600 dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy));
1605 ret = advk_pcie_enable_phy(pcie);
1607 dev_err(dev, "Failed to initialize PHY (%d)\n", ret);
1612 static int advk_pcie_probe(struct platform_device *pdev)
1614 struct device *dev = &pdev->dev;
1615 struct advk_pcie *pcie;
1616 struct pci_host_bridge *bridge;
1617 struct resource_entry *entry;
1620 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie));
1624 pcie = pci_host_bridge_priv(bridge);
1626 platform_set_drvdata(pdev, pcie);
1628 resource_list_for_each_entry(entry, &bridge->windows) {
1629 resource_size_t start = entry->res->start;
1630 resource_size_t size = resource_size(entry->res);
1631 unsigned long type = resource_type(entry->res);
1635 * Aardvark hardware allows to configure also PCIe window
1636 * for config type 0 and type 1 mapping, but driver uses
1637 * only PIO for issuing configuration transfers which does
1638 * not use PCIe window configuration.
1640 if (type != IORESOURCE_MEM && type != IORESOURCE_IO)
1644 * Skip transparent memory resources. Default outbound access
1645 * configuration is set to transparent memory access so it
1646 * does not need window configuration.
1648 if (type == IORESOURCE_MEM && entry->offset == 0)
1652 * The n-th PCIe window is configured by tuple (match, remap, mask)
1653 * and an access to address A uses this window if A matches the
1654 * match with given mask.
1655 * So every PCIe window size must be a power of two and every start
1656 * address must be aligned to window size. Minimal size is 64 KiB
1657 * because lower 16 bits of mask must be zero. Remapped address
1658 * may have set only bits from the mask.
1660 while (pcie->wins_count < OB_WIN_COUNT && size > 0) {
1661 /* Calculate the largest aligned window size */
1662 win_size = (1ULL << (fls64(size)-1)) |
1663 (start ? (1ULL << __ffs64(start)) : 0);
1664 win_size = 1ULL << __ffs64(win_size);
1665 if (win_size < 0x10000)
1669 "Configuring PCIe window %d: [0x%llx-0x%llx] as %lu\n",
1670 pcie->wins_count, (unsigned long long)start,
1671 (unsigned long long)start + win_size, type);
1673 if (type == IORESOURCE_IO) {
1674 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_IO;
1675 pcie->wins[pcie->wins_count].match = pci_pio_to_address(start);
1677 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_MEM;
1678 pcie->wins[pcie->wins_count].match = start;
1680 pcie->wins[pcie->wins_count].remap = start - entry->offset;
1681 pcie->wins[pcie->wins_count].mask = ~(win_size - 1);
1683 if (pcie->wins[pcie->wins_count].remap & (win_size - 1))
1692 dev_err(&pcie->pdev->dev,
1693 "Invalid PCIe region [0x%llx-0x%llx]\n",
1694 (unsigned long long)entry->res->start,
1695 (unsigned long long)entry->res->end + 1);
1700 pcie->base = devm_platform_ioremap_resource(pdev, 0);
1701 if (IS_ERR(pcie->base))
1702 return PTR_ERR(pcie->base);
1704 pcie->irq = platform_get_irq(pdev, 0);
1708 pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node,
1712 ret = PTR_ERR_OR_ZERO(pcie->reset_gpio);
1714 if (ret == -ENOENT) {
1715 pcie->reset_gpio = NULL;
1717 if (ret != -EPROBE_DEFER)
1718 dev_err(dev, "Failed to get reset-gpio: %i\n",
1724 ret = of_pci_get_max_link_speed(dev->of_node);
1725 if (ret <= 0 || ret > 3)
1728 pcie->link_gen = ret;
1730 ret = advk_pcie_setup_phy(pcie);
1734 advk_pcie_setup_hw(pcie);
1736 ret = advk_sw_pci_bridge_init(pcie);
1738 dev_err(dev, "Failed to register emulated root PCI bridge\n");
1742 ret = advk_pcie_init_irq_domain(pcie);
1744 dev_err(dev, "Failed to initialize irq\n");
1748 ret = advk_pcie_init_msi_irq_domain(pcie);
1750 dev_err(dev, "Failed to initialize irq\n");
1751 advk_pcie_remove_irq_domain(pcie);
1755 irq_set_chained_handler_and_data(pcie->irq, advk_pcie_irq_handler, pcie);
1757 bridge->sysdata = pcie;
1758 bridge->ops = &advk_pcie_ops;
1760 ret = pci_host_probe(bridge);
1762 irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
1763 advk_pcie_remove_msi_irq_domain(pcie);
1764 advk_pcie_remove_irq_domain(pcie);
1771 static int advk_pcie_remove(struct platform_device *pdev)
1773 struct advk_pcie *pcie = platform_get_drvdata(pdev);
1774 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
1778 /* Remove PCI bus with all devices */
1779 pci_lock_rescan_remove();
1780 pci_stop_root_bus(bridge->bus);
1781 pci_remove_root_bus(bridge->bus);
1782 pci_unlock_rescan_remove();
1784 /* Disable Root Bridge I/O space, memory space and bus mastering */
1785 val = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
1786 val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1787 advk_writel(pcie, val, PCIE_CORE_CMD_STATUS_REG);
1790 val = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
1791 val &= ~PCIE_CORE_CTRL2_MSI_ENABLE;
1792 advk_writel(pcie, val, PCIE_CORE_CTRL2_REG);
1794 /* Clear MSI address */
1795 advk_writel(pcie, 0, PCIE_MSI_ADDR_LOW_REG);
1796 advk_writel(pcie, 0, PCIE_MSI_ADDR_HIGH_REG);
1798 /* Mask all interrupts */
1799 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
1800 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG);
1801 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
1802 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_MASK_REG);
1804 /* Clear all interrupts */
1805 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG);
1806 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
1807 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
1808 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
1810 /* Remove IRQ handler */
1811 irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
1813 /* Remove IRQ domains */
1814 advk_pcie_remove_msi_irq_domain(pcie);
1815 advk_pcie_remove_irq_domain(pcie);
1817 /* Free config space for emulated root bridge */
1818 pci_bridge_emul_cleanup(&pcie->bridge);
1820 /* Assert PERST# signal which prepares PCIe card for power down */
1821 if (pcie->reset_gpio)
1822 gpiod_set_value_cansleep(pcie->reset_gpio, 1);
1824 /* Disable link training */
1825 val = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
1826 val &= ~LINK_TRAINING_EN;
1827 advk_writel(pcie, val, PCIE_CORE_CTRL0_REG);
1829 /* Disable outbound address windows mapping */
1830 for (i = 0; i < OB_WIN_COUNT; i++)
1831 advk_pcie_disable_ob_win(pcie, i);
1834 advk_pcie_disable_phy(pcie);
1839 static const struct of_device_id advk_pcie_of_match_table[] = {
1840 { .compatible = "marvell,armada-3700-pcie", },
1843 MODULE_DEVICE_TABLE(of, advk_pcie_of_match_table);
1845 static struct platform_driver advk_pcie_driver = {
1847 .name = "advk-pcie",
1848 .of_match_table = advk_pcie_of_match_table,
1850 .probe = advk_pcie_probe,
1851 .remove = advk_pcie_remove,
1853 module_platform_driver(advk_pcie_driver);
1855 MODULE_DESCRIPTION("Aardvark PCIe controller");
1856 MODULE_LICENSE("GPL v2");