1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm PCIe root complex driver
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 * Copyright 2015 Linaro Limited.
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
11 #include <linux/clk.h>
12 #include <linux/crc8.h>
13 #include <linux/delay.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/interrupt.h>
17 #include <linux/iopoll.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/of_device.h>
21 #include <linux/of_gpio.h>
22 #include <linux/pci.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/platform_device.h>
25 #include <linux/phy/phy.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/reset.h>
28 #include <linux/slab.h>
29 #include <linux/types.h>
31 #include "../../pci.h"
32 #include "pcie-designware.h"
34 #define PCIE20_PARF_SYS_CTRL 0x00
35 #define MST_WAKEUP_EN BIT(13)
36 #define SLV_WAKEUP_EN BIT(12)
37 #define MSTR_ACLK_CGC_DIS BIT(10)
38 #define SLV_ACLK_CGC_DIS BIT(9)
39 #define CORE_CLK_CGC_DIS BIT(6)
40 #define AUX_PWR_DET BIT(4)
41 #define L23_CLK_RMV_DIS BIT(2)
42 #define L1_CLK_RMV_DIS BIT(1)
44 #define PCIE20_PARF_PHY_CTRL 0x40
45 #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
46 #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16)
48 #define PCIE20_PARF_PHY_REFCLK 0x4C
49 #define PHY_REFCLK_SSP_EN BIT(16)
50 #define PHY_REFCLK_USE_PAD BIT(12)
52 #define PCIE20_PARF_DBI_BASE_ADDR 0x168
53 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
54 #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
55 #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
56 #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8
57 #define PCIE20_PARF_LTSSM 0x1B0
58 #define PCIE20_PARF_SID_OFFSET 0x234
59 #define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C
60 #define PCIE20_PARF_DEVICE_TYPE 0x1000
61 #define PCIE20_PARF_BDF_TO_SID_TABLE_N 0x2000
63 #define PCIE20_ELBI_SYS_CTRL 0x04
64 #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)
66 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818
67 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4
68 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5
69 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
70 #define CFG_BRIDGE_SB_INIT BIT(0)
72 #define PCIE_CAP_LINK1_VAL 0x2FD7F
74 #define PCIE20_PARF_Q2A_FLUSH 0x1AC
76 #define PCIE20_MISC_CONTROL_1_REG 0x8BC
77 #define DBI_RO_WR_EN 1
79 #define PERST_DELAY_US 1000
81 #define PCIE20_PARF_PCS_DEEMPH 0x34
82 #define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16)
83 #define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8)
84 #define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0)
86 #define PCIE20_PARF_PCS_SWING 0x38
87 #define PCS_SWING_TX_SWING_FULL(x) ((x) << 8)
88 #define PCS_SWING_TX_SWING_LOW(x) ((x) << 0)
90 #define PCIE20_PARF_CONFIG_BITS 0x50
91 #define PHY_RX0_EQ(x) ((x) << 24)
93 #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
94 #define SLV_ADDR_SPACE_SZ 0x10000000
96 #define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0
98 #define DEVICE_TYPE_RC 0x4
100 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
101 #define QCOM_PCIE_2_1_0_MAX_CLOCKS 5
103 #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0))
105 struct qcom_pcie_resources_2_1_0 {
106 struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS];
107 struct reset_control *pci_reset;
108 struct reset_control *axi_reset;
109 struct reset_control *ahb_reset;
110 struct reset_control *por_reset;
111 struct reset_control *phy_reset;
112 struct reset_control *ext_reset;
113 struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
116 struct qcom_pcie_resources_1_0_0 {
119 struct clk *master_bus;
120 struct clk *slave_bus;
121 struct reset_control *core;
122 struct regulator *vdda;
125 #define QCOM_PCIE_2_3_2_MAX_SUPPLY 2
126 struct qcom_pcie_resources_2_3_2 {
128 struct clk *master_clk;
129 struct clk *slave_clk;
131 struct clk *pipe_clk;
132 struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY];
135 #define QCOM_PCIE_2_4_0_MAX_CLOCKS 4
136 struct qcom_pcie_resources_2_4_0 {
137 struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS];
139 struct reset_control *axi_m_reset;
140 struct reset_control *axi_s_reset;
141 struct reset_control *pipe_reset;
142 struct reset_control *axi_m_vmid_reset;
143 struct reset_control *axi_s_xpu_reset;
144 struct reset_control *parf_reset;
145 struct reset_control *phy_reset;
146 struct reset_control *axi_m_sticky_reset;
147 struct reset_control *pipe_sticky_reset;
148 struct reset_control *pwr_reset;
149 struct reset_control *ahb_reset;
150 struct reset_control *phy_ahb_reset;
153 struct qcom_pcie_resources_2_3_3 {
155 struct clk *axi_m_clk;
156 struct clk *axi_s_clk;
159 struct reset_control *rst[7];
162 /* 6 clocks typically, 7 for sm8250 */
163 struct qcom_pcie_resources_2_7_0 {
164 struct clk_bulk_data clks[9];
166 struct regulator_bulk_data supplies[2];
167 struct reset_control *pci_reset;
168 struct clk *pipe_clk;
169 struct clk *pipe_clk_src;
170 struct clk *phy_pipe_clk;
171 struct clk *ref_clk_src;
174 union qcom_pcie_resources {
175 struct qcom_pcie_resources_1_0_0 v1_0_0;
176 struct qcom_pcie_resources_2_1_0 v2_1_0;
177 struct qcom_pcie_resources_2_3_2 v2_3_2;
178 struct qcom_pcie_resources_2_3_3 v2_3_3;
179 struct qcom_pcie_resources_2_4_0 v2_4_0;
180 struct qcom_pcie_resources_2_7_0 v2_7_0;
185 struct qcom_pcie_ops {
186 int (*get_resources)(struct qcom_pcie *pcie);
187 int (*init)(struct qcom_pcie *pcie);
188 int (*post_init)(struct qcom_pcie *pcie);
189 void (*deinit)(struct qcom_pcie *pcie);
190 void (*post_deinit)(struct qcom_pcie *pcie);
191 void (*ltssm_enable)(struct qcom_pcie *pcie);
192 int (*config_sid)(struct qcom_pcie *pcie);
195 struct qcom_pcie_cfg {
196 const struct qcom_pcie_ops *ops;
197 unsigned int pipe_clk_need_muxing:1;
198 unsigned int has_tbu_clk:1;
199 unsigned int has_ddrss_sf_tbu_clk:1;
200 unsigned int has_aggre0_clk:1;
201 unsigned int has_aggre1_clk:1;
206 void __iomem *parf; /* DT parf */
207 void __iomem *elbi; /* DT elbi */
208 union qcom_pcie_resources res;
210 struct gpio_desc *reset;
211 const struct qcom_pcie_cfg *cfg;
214 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
216 static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
218 gpiod_set_value_cansleep(pcie->reset, 1);
219 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
222 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
224 /* Ensure that PERST has been asserted for at least 100 ms */
226 gpiod_set_value_cansleep(pcie->reset, 0);
227 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
230 static int qcom_pcie_start_link(struct dw_pcie *pci)
232 struct qcom_pcie *pcie = to_qcom_pcie(pci);
234 /* Enable Link Training state machine */
235 if (pcie->cfg->ops->ltssm_enable)
236 pcie->cfg->ops->ltssm_enable(pcie);
241 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)
245 /* enable link training */
246 val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL);
247 val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE;
248 writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
251 static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
253 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
254 struct dw_pcie *pci = pcie->pci;
255 struct device *dev = pci->dev;
258 res->supplies[0].supply = "vdda";
259 res->supplies[1].supply = "vdda_phy";
260 res->supplies[2].supply = "vdda_refclk";
261 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
266 res->clks[0].id = "iface";
267 res->clks[1].id = "core";
268 res->clks[2].id = "phy";
269 res->clks[3].id = "aux";
270 res->clks[4].id = "ref";
272 /* iface, core, phy are required */
273 ret = devm_clk_bulk_get(dev, 3, res->clks);
277 /* aux, ref are optional */
278 ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3);
282 res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
283 if (IS_ERR(res->pci_reset))
284 return PTR_ERR(res->pci_reset);
286 res->axi_reset = devm_reset_control_get_exclusive(dev, "axi");
287 if (IS_ERR(res->axi_reset))
288 return PTR_ERR(res->axi_reset);
290 res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
291 if (IS_ERR(res->ahb_reset))
292 return PTR_ERR(res->ahb_reset);
294 res->por_reset = devm_reset_control_get_exclusive(dev, "por");
295 if (IS_ERR(res->por_reset))
296 return PTR_ERR(res->por_reset);
298 res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext");
299 if (IS_ERR(res->ext_reset))
300 return PTR_ERR(res->ext_reset);
302 res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
303 return PTR_ERR_OR_ZERO(res->phy_reset);
306 static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
308 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
310 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
311 reset_control_assert(res->pci_reset);
312 reset_control_assert(res->axi_reset);
313 reset_control_assert(res->ahb_reset);
314 reset_control_assert(res->por_reset);
315 reset_control_assert(res->ext_reset);
316 reset_control_assert(res->phy_reset);
318 writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL);
320 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
323 static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
325 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
326 struct dw_pcie *pci = pcie->pci;
327 struct device *dev = pci->dev;
328 struct device_node *node = dev->of_node;
332 /* reset the PCIe interface as uboot can leave it undefined state */
333 reset_control_assert(res->pci_reset);
334 reset_control_assert(res->axi_reset);
335 reset_control_assert(res->ahb_reset);
336 reset_control_assert(res->por_reset);
337 reset_control_assert(res->ext_reset);
338 reset_control_assert(res->phy_reset);
340 writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL);
342 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
344 dev_err(dev, "cannot enable regulators\n");
348 ret = reset_control_deassert(res->ahb_reset);
350 dev_err(dev, "cannot deassert ahb reset\n");
351 goto err_deassert_ahb;
354 ret = reset_control_deassert(res->ext_reset);
356 dev_err(dev, "cannot deassert ext reset\n");
357 goto err_deassert_ext;
360 ret = reset_control_deassert(res->phy_reset);
362 dev_err(dev, "cannot deassert phy reset\n");
363 goto err_deassert_phy;
366 ret = reset_control_deassert(res->pci_reset);
368 dev_err(dev, "cannot deassert pci reset\n");
369 goto err_deassert_pci;
372 ret = reset_control_deassert(res->por_reset);
374 dev_err(dev, "cannot deassert por reset\n");
375 goto err_deassert_por;
378 ret = reset_control_deassert(res->axi_reset);
380 dev_err(dev, "cannot deassert axi reset\n");
381 goto err_deassert_axi;
384 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
388 /* enable PCIe clocks and resets */
389 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
391 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
393 if (of_device_is_compatible(node, "qcom,pcie-ipq8064") ||
394 of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) {
395 writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
396 PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
397 PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
398 pcie->parf + PCIE20_PARF_PCS_DEEMPH);
399 writel(PCS_SWING_TX_SWING_FULL(120) |
400 PCS_SWING_TX_SWING_LOW(120),
401 pcie->parf + PCIE20_PARF_PCS_SWING);
402 writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
405 if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
406 /* set TX termination offset */
407 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
408 val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK;
409 val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7);
410 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
413 /* enable external reference clock */
414 val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
415 /* USE_PAD is required only for ipq806x */
416 if (!of_device_is_compatible(node, "qcom,pcie-apq8064"))
417 val &= ~PHY_REFCLK_USE_PAD;
418 val |= PHY_REFCLK_SSP_EN;
419 writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
421 /* wait for clock acquisition */
422 usleep_range(1000, 1500);
424 /* Set the Max TLP size to 2K, instead of using default of 4K */
425 writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
426 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
427 writel(CFG_BRIDGE_SB_INIT,
428 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
433 reset_control_assert(res->axi_reset);
435 reset_control_assert(res->por_reset);
437 reset_control_assert(res->pci_reset);
439 reset_control_assert(res->phy_reset);
441 reset_control_assert(res->ext_reset);
443 reset_control_assert(res->ahb_reset);
445 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
450 static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie)
452 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
453 struct dw_pcie *pci = pcie->pci;
454 struct device *dev = pci->dev;
456 res->vdda = devm_regulator_get(dev, "vdda");
457 if (IS_ERR(res->vdda))
458 return PTR_ERR(res->vdda);
460 res->iface = devm_clk_get(dev, "iface");
461 if (IS_ERR(res->iface))
462 return PTR_ERR(res->iface);
464 res->aux = devm_clk_get(dev, "aux");
465 if (IS_ERR(res->aux))
466 return PTR_ERR(res->aux);
468 res->master_bus = devm_clk_get(dev, "master_bus");
469 if (IS_ERR(res->master_bus))
470 return PTR_ERR(res->master_bus);
472 res->slave_bus = devm_clk_get(dev, "slave_bus");
473 if (IS_ERR(res->slave_bus))
474 return PTR_ERR(res->slave_bus);
476 res->core = devm_reset_control_get_exclusive(dev, "core");
477 return PTR_ERR_OR_ZERO(res->core);
480 static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie)
482 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
484 reset_control_assert(res->core);
485 clk_disable_unprepare(res->slave_bus);
486 clk_disable_unprepare(res->master_bus);
487 clk_disable_unprepare(res->iface);
488 clk_disable_unprepare(res->aux);
489 regulator_disable(res->vdda);
492 static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie)
494 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
495 struct dw_pcie *pci = pcie->pci;
496 struct device *dev = pci->dev;
499 ret = reset_control_deassert(res->core);
501 dev_err(dev, "cannot deassert core reset\n");
505 ret = clk_prepare_enable(res->aux);
507 dev_err(dev, "cannot prepare/enable aux clock\n");
511 ret = clk_prepare_enable(res->iface);
513 dev_err(dev, "cannot prepare/enable iface clock\n");
517 ret = clk_prepare_enable(res->master_bus);
519 dev_err(dev, "cannot prepare/enable master_bus clock\n");
523 ret = clk_prepare_enable(res->slave_bus);
525 dev_err(dev, "cannot prepare/enable slave_bus clock\n");
529 ret = regulator_enable(res->vdda);
531 dev_err(dev, "cannot enable vdda regulator\n");
535 /* change DBI base address */
536 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
538 if (IS_ENABLED(CONFIG_PCI_MSI)) {
539 u32 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
542 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
547 clk_disable_unprepare(res->slave_bus);
549 clk_disable_unprepare(res->master_bus);
551 clk_disable_unprepare(res->iface);
553 clk_disable_unprepare(res->aux);
555 reset_control_assert(res->core);
560 static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)
564 /* enable link training */
565 val = readl(pcie->parf + PCIE20_PARF_LTSSM);
567 writel(val, pcie->parf + PCIE20_PARF_LTSSM);
570 static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)
572 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
573 struct dw_pcie *pci = pcie->pci;
574 struct device *dev = pci->dev;
577 res->supplies[0].supply = "vdda";
578 res->supplies[1].supply = "vddpe-3v3";
579 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
584 res->aux_clk = devm_clk_get(dev, "aux");
585 if (IS_ERR(res->aux_clk))
586 return PTR_ERR(res->aux_clk);
588 res->cfg_clk = devm_clk_get(dev, "cfg");
589 if (IS_ERR(res->cfg_clk))
590 return PTR_ERR(res->cfg_clk);
592 res->master_clk = devm_clk_get(dev, "bus_master");
593 if (IS_ERR(res->master_clk))
594 return PTR_ERR(res->master_clk);
596 res->slave_clk = devm_clk_get(dev, "bus_slave");
597 if (IS_ERR(res->slave_clk))
598 return PTR_ERR(res->slave_clk);
600 res->pipe_clk = devm_clk_get(dev, "pipe");
601 return PTR_ERR_OR_ZERO(res->pipe_clk);
604 static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)
606 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
608 clk_disable_unprepare(res->slave_clk);
609 clk_disable_unprepare(res->master_clk);
610 clk_disable_unprepare(res->cfg_clk);
611 clk_disable_unprepare(res->aux_clk);
613 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
616 static void qcom_pcie_post_deinit_2_3_2(struct qcom_pcie *pcie)
618 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
620 clk_disable_unprepare(res->pipe_clk);
623 static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
625 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
626 struct dw_pcie *pci = pcie->pci;
627 struct device *dev = pci->dev;
631 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
633 dev_err(dev, "cannot enable regulators\n");
637 ret = clk_prepare_enable(res->aux_clk);
639 dev_err(dev, "cannot prepare/enable aux clock\n");
643 ret = clk_prepare_enable(res->cfg_clk);
645 dev_err(dev, "cannot prepare/enable cfg clock\n");
649 ret = clk_prepare_enable(res->master_clk);
651 dev_err(dev, "cannot prepare/enable master clock\n");
655 ret = clk_prepare_enable(res->slave_clk);
657 dev_err(dev, "cannot prepare/enable slave clock\n");
661 /* enable PCIe clocks and resets */
662 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
664 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
666 /* change DBI base address */
667 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
669 /* MAC PHY_POWERDOWN MUX DISABLE */
670 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
672 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
674 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
676 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
678 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
680 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
685 clk_disable_unprepare(res->master_clk);
687 clk_disable_unprepare(res->cfg_clk);
689 clk_disable_unprepare(res->aux_clk);
692 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
697 static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
699 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
700 struct dw_pcie *pci = pcie->pci;
701 struct device *dev = pci->dev;
704 ret = clk_prepare_enable(res->pipe_clk);
706 dev_err(dev, "cannot prepare/enable pipe clock\n");
713 static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
715 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
716 struct dw_pcie *pci = pcie->pci;
717 struct device *dev = pci->dev;
718 bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019");
721 res->clks[0].id = "aux";
722 res->clks[1].id = "master_bus";
723 res->clks[2].id = "slave_bus";
724 res->clks[3].id = "iface";
726 /* qcom,pcie-ipq4019 is defined without "iface" */
727 res->num_clks = is_ipq ? 3 : 4;
729 ret = devm_clk_bulk_get(dev, res->num_clks, res->clks);
733 res->axi_m_reset = devm_reset_control_get_exclusive(dev, "axi_m");
734 if (IS_ERR(res->axi_m_reset))
735 return PTR_ERR(res->axi_m_reset);
737 res->axi_s_reset = devm_reset_control_get_exclusive(dev, "axi_s");
738 if (IS_ERR(res->axi_s_reset))
739 return PTR_ERR(res->axi_s_reset);
743 * These resources relates to the PHY or are secure clocks, but
744 * are controlled here for IPQ4019
746 res->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe");
747 if (IS_ERR(res->pipe_reset))
748 return PTR_ERR(res->pipe_reset);
750 res->axi_m_vmid_reset = devm_reset_control_get_exclusive(dev,
752 if (IS_ERR(res->axi_m_vmid_reset))
753 return PTR_ERR(res->axi_m_vmid_reset);
755 res->axi_s_xpu_reset = devm_reset_control_get_exclusive(dev,
757 if (IS_ERR(res->axi_s_xpu_reset))
758 return PTR_ERR(res->axi_s_xpu_reset);
760 res->parf_reset = devm_reset_control_get_exclusive(dev, "parf");
761 if (IS_ERR(res->parf_reset))
762 return PTR_ERR(res->parf_reset);
764 res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
765 if (IS_ERR(res->phy_reset))
766 return PTR_ERR(res->phy_reset);
769 res->axi_m_sticky_reset = devm_reset_control_get_exclusive(dev,
771 if (IS_ERR(res->axi_m_sticky_reset))
772 return PTR_ERR(res->axi_m_sticky_reset);
774 res->pipe_sticky_reset = devm_reset_control_get_exclusive(dev,
776 if (IS_ERR(res->pipe_sticky_reset))
777 return PTR_ERR(res->pipe_sticky_reset);
779 res->pwr_reset = devm_reset_control_get_exclusive(dev, "pwr");
780 if (IS_ERR(res->pwr_reset))
781 return PTR_ERR(res->pwr_reset);
783 res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
784 if (IS_ERR(res->ahb_reset))
785 return PTR_ERR(res->ahb_reset);
788 res->phy_ahb_reset = devm_reset_control_get_exclusive(dev, "phy_ahb");
789 if (IS_ERR(res->phy_ahb_reset))
790 return PTR_ERR(res->phy_ahb_reset);
796 static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie)
798 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
800 reset_control_assert(res->axi_m_reset);
801 reset_control_assert(res->axi_s_reset);
802 reset_control_assert(res->pipe_reset);
803 reset_control_assert(res->pipe_sticky_reset);
804 reset_control_assert(res->phy_reset);
805 reset_control_assert(res->phy_ahb_reset);
806 reset_control_assert(res->axi_m_sticky_reset);
807 reset_control_assert(res->pwr_reset);
808 reset_control_assert(res->ahb_reset);
809 clk_bulk_disable_unprepare(res->num_clks, res->clks);
812 static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
814 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
815 struct dw_pcie *pci = pcie->pci;
816 struct device *dev = pci->dev;
820 ret = reset_control_assert(res->axi_m_reset);
822 dev_err(dev, "cannot assert axi master reset\n");
826 ret = reset_control_assert(res->axi_s_reset);
828 dev_err(dev, "cannot assert axi slave reset\n");
832 usleep_range(10000, 12000);
834 ret = reset_control_assert(res->pipe_reset);
836 dev_err(dev, "cannot assert pipe reset\n");
840 ret = reset_control_assert(res->pipe_sticky_reset);
842 dev_err(dev, "cannot assert pipe sticky reset\n");
846 ret = reset_control_assert(res->phy_reset);
848 dev_err(dev, "cannot assert phy reset\n");
852 ret = reset_control_assert(res->phy_ahb_reset);
854 dev_err(dev, "cannot assert phy ahb reset\n");
858 usleep_range(10000, 12000);
860 ret = reset_control_assert(res->axi_m_sticky_reset);
862 dev_err(dev, "cannot assert axi master sticky reset\n");
866 ret = reset_control_assert(res->pwr_reset);
868 dev_err(dev, "cannot assert power reset\n");
872 ret = reset_control_assert(res->ahb_reset);
874 dev_err(dev, "cannot assert ahb reset\n");
878 usleep_range(10000, 12000);
880 ret = reset_control_deassert(res->phy_ahb_reset);
882 dev_err(dev, "cannot deassert phy ahb reset\n");
886 ret = reset_control_deassert(res->phy_reset);
888 dev_err(dev, "cannot deassert phy reset\n");
892 ret = reset_control_deassert(res->pipe_reset);
894 dev_err(dev, "cannot deassert pipe reset\n");
898 ret = reset_control_deassert(res->pipe_sticky_reset);
900 dev_err(dev, "cannot deassert pipe sticky reset\n");
901 goto err_rst_pipe_sticky;
904 usleep_range(10000, 12000);
906 ret = reset_control_deassert(res->axi_m_reset);
908 dev_err(dev, "cannot deassert axi master reset\n");
912 ret = reset_control_deassert(res->axi_m_sticky_reset);
914 dev_err(dev, "cannot deassert axi master sticky reset\n");
915 goto err_rst_axi_m_sticky;
918 ret = reset_control_deassert(res->axi_s_reset);
920 dev_err(dev, "cannot deassert axi slave reset\n");
924 ret = reset_control_deassert(res->pwr_reset);
926 dev_err(dev, "cannot deassert power reset\n");
930 ret = reset_control_deassert(res->ahb_reset);
932 dev_err(dev, "cannot deassert ahb reset\n");
936 usleep_range(10000, 12000);
938 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
942 /* enable PCIe clocks and resets */
943 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
945 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
947 /* change DBI base address */
948 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
950 /* MAC PHY_POWERDOWN MUX DISABLE */
951 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
953 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
955 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
957 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
959 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
961 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
966 reset_control_assert(res->ahb_reset);
968 reset_control_assert(res->pwr_reset);
970 reset_control_assert(res->axi_s_reset);
972 reset_control_assert(res->axi_m_sticky_reset);
973 err_rst_axi_m_sticky:
974 reset_control_assert(res->axi_m_reset);
976 reset_control_assert(res->pipe_sticky_reset);
978 reset_control_assert(res->pipe_reset);
980 reset_control_assert(res->phy_reset);
982 reset_control_assert(res->phy_ahb_reset);
986 static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)
988 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
989 struct dw_pcie *pci = pcie->pci;
990 struct device *dev = pci->dev;
992 const char *rst_names[] = { "axi_m", "axi_s", "pipe",
993 "axi_m_sticky", "sticky",
996 res->iface = devm_clk_get(dev, "iface");
997 if (IS_ERR(res->iface))
998 return PTR_ERR(res->iface);
1000 res->axi_m_clk = devm_clk_get(dev, "axi_m");
1001 if (IS_ERR(res->axi_m_clk))
1002 return PTR_ERR(res->axi_m_clk);
1004 res->axi_s_clk = devm_clk_get(dev, "axi_s");
1005 if (IS_ERR(res->axi_s_clk))
1006 return PTR_ERR(res->axi_s_clk);
1008 res->ahb_clk = devm_clk_get(dev, "ahb");
1009 if (IS_ERR(res->ahb_clk))
1010 return PTR_ERR(res->ahb_clk);
1012 res->aux_clk = devm_clk_get(dev, "aux");
1013 if (IS_ERR(res->aux_clk))
1014 return PTR_ERR(res->aux_clk);
1016 for (i = 0; i < ARRAY_SIZE(rst_names); i++) {
1017 res->rst[i] = devm_reset_control_get(dev, rst_names[i]);
1018 if (IS_ERR(res->rst[i]))
1019 return PTR_ERR(res->rst[i]);
1025 static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)
1027 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
1029 clk_disable_unprepare(res->iface);
1030 clk_disable_unprepare(res->axi_m_clk);
1031 clk_disable_unprepare(res->axi_s_clk);
1032 clk_disable_unprepare(res->ahb_clk);
1033 clk_disable_unprepare(res->aux_clk);
1036 static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
1038 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
1039 struct dw_pcie *pci = pcie->pci;
1040 struct device *dev = pci->dev;
1041 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1045 for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
1046 ret = reset_control_assert(res->rst[i]);
1048 dev_err(dev, "reset #%d assert failed (%d)\n", i, ret);
1053 usleep_range(2000, 2500);
1055 for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
1056 ret = reset_control_deassert(res->rst[i]);
1058 dev_err(dev, "reset #%d deassert failed (%d)\n", i,
1065 * Don't have a way to see if the reset has completed.
1066 * Wait for some time.
1068 usleep_range(2000, 2500);
1070 ret = clk_prepare_enable(res->iface);
1072 dev_err(dev, "cannot prepare/enable core clock\n");
1076 ret = clk_prepare_enable(res->axi_m_clk);
1078 dev_err(dev, "cannot prepare/enable core clock\n");
1082 ret = clk_prepare_enable(res->axi_s_clk);
1084 dev_err(dev, "cannot prepare/enable axi slave clock\n");
1088 ret = clk_prepare_enable(res->ahb_clk);
1090 dev_err(dev, "cannot prepare/enable ahb clock\n");
1094 ret = clk_prepare_enable(res->aux_clk);
1096 dev_err(dev, "cannot prepare/enable aux clock\n");
1100 writel(SLV_ADDR_SPACE_SZ,
1101 pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
1103 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
1105 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
1107 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
1109 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS
1110 | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
1111 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
1112 pcie->parf + PCIE20_PARF_SYS_CTRL);
1113 writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
1115 writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
1116 writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
1117 writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
1119 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
1120 val &= ~PCI_EXP_LNKCAP_ASPMS;
1121 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
1123 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
1129 clk_disable_unprepare(res->ahb_clk);
1131 clk_disable_unprepare(res->axi_s_clk);
1133 clk_disable_unprepare(res->axi_m_clk);
1135 clk_disable_unprepare(res->iface);
1138 * Not checking for failure, will anyway return
1139 * the original failure in 'ret'.
1141 for (i = 0; i < ARRAY_SIZE(res->rst); i++)
1142 reset_control_assert(res->rst[i]);
1147 static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
1149 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1150 struct dw_pcie *pci = pcie->pci;
1151 struct device *dev = pci->dev;
1155 res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
1156 if (IS_ERR(res->pci_reset))
1157 return PTR_ERR(res->pci_reset);
1159 res->supplies[0].supply = "vdda";
1160 res->supplies[1].supply = "vddpe-3v3";
1161 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
1167 res->clks[idx++].id = "aux";
1168 res->clks[idx++].id = "cfg";
1169 res->clks[idx++].id = "bus_master";
1170 res->clks[idx++].id = "bus_slave";
1171 res->clks[idx++].id = "slave_q2a";
1172 if (pcie->cfg->has_tbu_clk)
1173 res->clks[idx++].id = "tbu";
1174 if (pcie->cfg->has_ddrss_sf_tbu_clk)
1175 res->clks[idx++].id = "ddrss_sf_tbu";
1176 if (pcie->cfg->has_aggre0_clk)
1177 res->clks[idx++].id = "aggre0";
1178 if (pcie->cfg->has_aggre1_clk)
1179 res->clks[idx++].id = "aggre1";
1181 res->num_clks = idx;
1183 ret = devm_clk_bulk_get(dev, res->num_clks, res->clks);
1187 if (pcie->cfg->pipe_clk_need_muxing) {
1188 res->pipe_clk_src = devm_clk_get(dev, "pipe_mux");
1189 if (IS_ERR(res->pipe_clk_src))
1190 return PTR_ERR(res->pipe_clk_src);
1192 res->phy_pipe_clk = devm_clk_get(dev, "phy_pipe");
1193 if (IS_ERR(res->phy_pipe_clk))
1194 return PTR_ERR(res->phy_pipe_clk);
1196 res->ref_clk_src = devm_clk_get(dev, "ref");
1197 if (IS_ERR(res->ref_clk_src))
1198 return PTR_ERR(res->ref_clk_src);
1201 res->pipe_clk = devm_clk_get(dev, "pipe");
1202 return PTR_ERR_OR_ZERO(res->pipe_clk);
1205 static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
1207 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1208 struct dw_pcie *pci = pcie->pci;
1209 struct device *dev = pci->dev;
1213 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
1215 dev_err(dev, "cannot enable regulators\n");
1219 /* Set TCXO as clock source for pcie_pipe_clk_src */
1220 if (pcie->cfg->pipe_clk_need_muxing)
1221 clk_set_parent(res->pipe_clk_src, res->ref_clk_src);
1223 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
1225 goto err_disable_regulators;
1227 ret = reset_control_assert(res->pci_reset);
1229 dev_err(dev, "cannot deassert pci reset\n");
1230 goto err_disable_clocks;
1233 usleep_range(1000, 1500);
1235 ret = reset_control_deassert(res->pci_reset);
1237 dev_err(dev, "cannot deassert pci reset\n");
1238 goto err_disable_clocks;
1241 ret = clk_prepare_enable(res->pipe_clk);
1243 dev_err(dev, "cannot prepare/enable pipe clock\n");
1244 goto err_disable_clocks;
1247 /* Wait for reset to complete, required on SM8450 */
1248 usleep_range(1000, 1500);
1250 /* configure PCIe to RC mode */
1251 writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
1253 /* enable PCIe clocks and resets */
1254 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
1256 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
1258 /* change DBI base address */
1259 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
1261 /* MAC PHY_POWERDOWN MUX DISABLE */
1262 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
1264 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
1266 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
1268 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
1270 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1271 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
1273 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
1278 clk_bulk_disable_unprepare(res->num_clks, res->clks);
1279 err_disable_regulators:
1280 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
1285 static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)
1287 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1289 clk_bulk_disable_unprepare(res->num_clks, res->clks);
1290 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
1293 static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
1295 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1297 /* Set pipe clock as clock source for pcie_pipe_clk_src */
1298 if (pcie->cfg->pipe_clk_need_muxing)
1299 clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk);
1301 return clk_prepare_enable(res->pipe_clk);
1304 static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie)
1306 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1308 clk_disable_unprepare(res->pipe_clk);
1311 static int qcom_pcie_link_up(struct dw_pcie *pci)
1313 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1314 u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
1316 return !!(val & PCI_EXP_LNKSTA_DLLLA);
1319 static int qcom_pcie_config_sid_sm8250(struct qcom_pcie *pcie)
1321 /* iommu map structure */
1328 void __iomem *bdf_to_sid_base = pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N;
1329 struct device *dev = pcie->pci->dev;
1330 u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE];
1331 int i, nr_map, size = 0;
1334 of_get_property(dev->of_node, "iommu-map", &size);
1338 map = kzalloc(size, GFP_KERNEL);
1342 of_property_read_u32_array(dev->of_node,
1343 "iommu-map", (u32 *)map, size / sizeof(u32));
1345 nr_map = size / (sizeof(*map));
1347 crc8_populate_msb(qcom_pcie_crc8_table, QCOM_PCIE_CRC8_POLYNOMIAL);
1349 /* Registers need to be zero out first */
1350 memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32));
1352 /* Extract the SMMU SID base from the first entry of iommu-map */
1353 smmu_sid_base = map[0].smmu_sid;
1355 /* Look for an available entry to hold the mapping */
1356 for (i = 0; i < nr_map; i++) {
1357 __be16 bdf_be = cpu_to_be16(map[i].bdf);
1361 hash = crc8(qcom_pcie_crc8_table, (u8 *)&bdf_be, sizeof(bdf_be),
1364 val = readl(bdf_to_sid_base + hash * sizeof(u32));
1366 /* If the register is already populated, look for next available entry */
1368 u8 current_hash = hash++;
1369 u8 next_mask = 0xff;
1371 /* If NEXT field is NULL then update it with next hash */
1372 if (!(val & next_mask)) {
1374 writel(val, bdf_to_sid_base + current_hash * sizeof(u32));
1377 val = readl(bdf_to_sid_base + hash * sizeof(u32));
1380 /* BDF [31:16] | SID [15:8] | NEXT [7:0] */
1381 val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0;
1382 writel(val, bdf_to_sid_base + hash * sizeof(u32));
1390 static int qcom_pcie_host_init(struct pcie_port *pp)
1392 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1393 struct qcom_pcie *pcie = to_qcom_pcie(pci);
1396 qcom_ep_reset_assert(pcie);
1398 ret = pcie->cfg->ops->init(pcie);
1402 ret = phy_power_on(pcie->phy);
1406 if (pcie->cfg->ops->post_init) {
1407 ret = pcie->cfg->ops->post_init(pcie);
1409 goto err_disable_phy;
1412 qcom_ep_reset_deassert(pcie);
1414 if (pcie->cfg->ops->config_sid) {
1415 ret = pcie->cfg->ops->config_sid(pcie);
1423 qcom_ep_reset_assert(pcie);
1424 if (pcie->cfg->ops->post_deinit)
1425 pcie->cfg->ops->post_deinit(pcie);
1427 phy_power_off(pcie->phy);
1429 pcie->cfg->ops->deinit(pcie);
1434 static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
1435 .host_init = qcom_pcie_host_init,
1438 /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */
1439 static const struct qcom_pcie_ops ops_2_1_0 = {
1440 .get_resources = qcom_pcie_get_resources_2_1_0,
1441 .init = qcom_pcie_init_2_1_0,
1442 .deinit = qcom_pcie_deinit_2_1_0,
1443 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1446 /* Qcom IP rev.: 1.0.0 Synopsys IP rev.: 4.11a */
1447 static const struct qcom_pcie_ops ops_1_0_0 = {
1448 .get_resources = qcom_pcie_get_resources_1_0_0,
1449 .init = qcom_pcie_init_1_0_0,
1450 .deinit = qcom_pcie_deinit_1_0_0,
1451 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1454 /* Qcom IP rev.: 2.3.2 Synopsys IP rev.: 4.21a */
1455 static const struct qcom_pcie_ops ops_2_3_2 = {
1456 .get_resources = qcom_pcie_get_resources_2_3_2,
1457 .init = qcom_pcie_init_2_3_2,
1458 .post_init = qcom_pcie_post_init_2_3_2,
1459 .deinit = qcom_pcie_deinit_2_3_2,
1460 .post_deinit = qcom_pcie_post_deinit_2_3_2,
1461 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1464 /* Qcom IP rev.: 2.4.0 Synopsys IP rev.: 4.20a */
1465 static const struct qcom_pcie_ops ops_2_4_0 = {
1466 .get_resources = qcom_pcie_get_resources_2_4_0,
1467 .init = qcom_pcie_init_2_4_0,
1468 .deinit = qcom_pcie_deinit_2_4_0,
1469 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1472 /* Qcom IP rev.: 2.3.3 Synopsys IP rev.: 4.30a */
1473 static const struct qcom_pcie_ops ops_2_3_3 = {
1474 .get_resources = qcom_pcie_get_resources_2_3_3,
1475 .init = qcom_pcie_init_2_3_3,
1476 .deinit = qcom_pcie_deinit_2_3_3,
1477 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1480 /* Qcom IP rev.: 2.7.0 Synopsys IP rev.: 4.30a */
1481 static const struct qcom_pcie_ops ops_2_7_0 = {
1482 .get_resources = qcom_pcie_get_resources_2_7_0,
1483 .init = qcom_pcie_init_2_7_0,
1484 .deinit = qcom_pcie_deinit_2_7_0,
1485 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1486 .post_init = qcom_pcie_post_init_2_7_0,
1487 .post_deinit = qcom_pcie_post_deinit_2_7_0,
1490 /* Qcom IP rev.: 1.9.0 */
1491 static const struct qcom_pcie_ops ops_1_9_0 = {
1492 .get_resources = qcom_pcie_get_resources_2_7_0,
1493 .init = qcom_pcie_init_2_7_0,
1494 .deinit = qcom_pcie_deinit_2_7_0,
1495 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1496 .post_init = qcom_pcie_post_init_2_7_0,
1497 .post_deinit = qcom_pcie_post_deinit_2_7_0,
1498 .config_sid = qcom_pcie_config_sid_sm8250,
1501 static const struct qcom_pcie_cfg apq8084_cfg = {
1505 static const struct qcom_pcie_cfg ipq8064_cfg = {
1509 static const struct qcom_pcie_cfg msm8996_cfg = {
1513 static const struct qcom_pcie_cfg ipq8074_cfg = {
1517 static const struct qcom_pcie_cfg ipq4019_cfg = {
1521 static const struct qcom_pcie_cfg sdm845_cfg = {
1523 .has_tbu_clk = true,
1526 static const struct qcom_pcie_cfg sm8250_cfg = {
1528 .has_tbu_clk = true,
1529 .has_ddrss_sf_tbu_clk = true,
1532 static const struct qcom_pcie_cfg sm8450_pcie0_cfg = {
1534 .has_ddrss_sf_tbu_clk = true,
1535 .pipe_clk_need_muxing = true,
1536 .has_aggre0_clk = true,
1537 .has_aggre1_clk = true,
1540 static const struct qcom_pcie_cfg sm8450_pcie1_cfg = {
1542 .has_ddrss_sf_tbu_clk = true,
1543 .pipe_clk_need_muxing = true,
1544 .has_aggre1_clk = true,
1547 static const struct qcom_pcie_cfg sc7280_cfg = {
1549 .has_tbu_clk = true,
1550 .pipe_clk_need_muxing = true,
1553 static const struct qcom_pcie_cfg sc8180x_cfg = {
1555 .has_tbu_clk = true,
1558 static const struct dw_pcie_ops dw_pcie_ops = {
1559 .link_up = qcom_pcie_link_up,
1560 .start_link = qcom_pcie_start_link,
1563 static int qcom_pcie_probe(struct platform_device *pdev)
1565 struct device *dev = &pdev->dev;
1566 struct pcie_port *pp;
1567 struct dw_pcie *pci;
1568 struct qcom_pcie *pcie;
1569 const struct qcom_pcie_cfg *pcie_cfg;
1572 pcie_cfg = of_device_get_match_data(dev);
1573 if (!pcie_cfg || !pcie_cfg->ops) {
1574 dev_err(dev, "Invalid platform data\n");
1578 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
1582 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
1586 pm_runtime_enable(dev);
1587 ret = pm_runtime_get_sync(dev);
1589 goto err_pm_runtime_put;
1592 pci->ops = &dw_pcie_ops;
1597 pcie->cfg = pcie_cfg;
1599 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
1600 if (IS_ERR(pcie->reset)) {
1601 ret = PTR_ERR(pcie->reset);
1602 goto err_pm_runtime_put;
1605 pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
1606 if (IS_ERR(pcie->parf)) {
1607 ret = PTR_ERR(pcie->parf);
1608 goto err_pm_runtime_put;
1611 pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi");
1612 if (IS_ERR(pcie->elbi)) {
1613 ret = PTR_ERR(pcie->elbi);
1614 goto err_pm_runtime_put;
1617 pcie->phy = devm_phy_optional_get(dev, "pciephy");
1618 if (IS_ERR(pcie->phy)) {
1619 ret = PTR_ERR(pcie->phy);
1620 goto err_pm_runtime_put;
1623 ret = pcie->cfg->ops->get_resources(pcie);
1625 goto err_pm_runtime_put;
1627 pp->ops = &qcom_pcie_dw_ops;
1629 ret = phy_init(pcie->phy);
1631 pm_runtime_disable(&pdev->dev);
1632 goto err_pm_runtime_put;
1635 platform_set_drvdata(pdev, pcie);
1637 ret = dw_pcie_host_init(pp);
1639 dev_err(dev, "cannot initialize host\n");
1640 pm_runtime_disable(&pdev->dev);
1641 goto err_pm_runtime_put;
1647 pm_runtime_put(dev);
1648 pm_runtime_disable(dev);
1653 static const struct of_device_id qcom_pcie_match[] = {
1654 { .compatible = "qcom,pcie-apq8084", .data = &apq8084_cfg },
1655 { .compatible = "qcom,pcie-ipq8064", .data = &ipq8064_cfg },
1656 { .compatible = "qcom,pcie-ipq8064-v2", .data = &ipq8064_cfg },
1657 { .compatible = "qcom,pcie-apq8064", .data = &ipq8064_cfg },
1658 { .compatible = "qcom,pcie-msm8996", .data = &msm8996_cfg },
1659 { .compatible = "qcom,pcie-ipq8074", .data = &ipq8074_cfg },
1660 { .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg },
1661 { .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg },
1662 { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },
1663 { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
1664 { .compatible = "qcom,pcie-sc8180x", .data = &sc8180x_cfg },
1665 { .compatible = "qcom,pcie-sm8450-pcie0", .data = &sm8450_pcie0_cfg },
1666 { .compatible = "qcom,pcie-sm8450-pcie1", .data = &sm8450_pcie1_cfg },
1667 { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg },
1671 static void qcom_fixup_class(struct pci_dev *dev)
1673 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
1675 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0101, qcom_fixup_class);
1676 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0104, qcom_fixup_class);
1677 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0106, qcom_fixup_class);
1678 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0107, qcom_fixup_class);
1679 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0302, qcom_fixup_class);
1680 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1000, qcom_fixup_class);
1681 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1001, qcom_fixup_class);
1683 static struct platform_driver qcom_pcie_driver = {
1684 .probe = qcom_pcie_probe,
1686 .name = "qcom-pcie",
1687 .suppress_bind_attrs = true,
1688 .of_match_table = qcom_pcie_match,
1691 builtin_platform_driver(qcom_pcie_driver);