1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Freescale i.MX6 SoCs
5 * Copyright (C) 2013 Kosagi
6 * http://www.kosagi.com
8 * Author: Sean Cross <xobs@kosagi.com>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/gpio.h>
14 #include <linux/kernel.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
17 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
18 #include <linux/module.h>
19 #include <linux/of_gpio.h>
20 #include <linux/of_device.h>
21 #include <linux/pci.h>
22 #include <linux/platform_device.h>
23 #include <linux/regmap.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/resource.h>
26 #include <linux/signal.h>
27 #include <linux/types.h>
28 #include <linux/interrupt.h>
29 #include <linux/reset.h>
31 #include "pcie-designware.h"
33 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
35 enum imx6_pcie_variants {
45 bool gpio_active_high;
48 struct clk *pcie_inbound_axi;
50 struct regmap *iomuxc_gpr;
51 struct reset_control *pciephy_reset;
52 struct reset_control *apps_reset;
53 struct reset_control *turnoff_reset;
54 enum imx6_pcie_variants variant;
56 u32 tx_deemph_gen2_3p5db;
57 u32 tx_deemph_gen2_6db;
61 struct regulator *vpcie;
64 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
65 #define PHY_PLL_LOCK_WAIT_MAX_RETRIES 2000
66 #define PHY_PLL_LOCK_WAIT_USLEEP_MIN 50
67 #define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200
69 /* PCIe Root Complex registers (memory-mapped) */
70 #define PCIE_RC_LCR 0x7c
71 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1
72 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
73 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
75 #define PCIE_RC_LCSR 0x80
77 /* PCIe Port Logic registers (memory-mapped) */
78 #define PL_OFFSET 0x700
79 #define PCIE_PL_PFLR (PL_OFFSET + 0x08)
80 #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
81 #define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
82 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
83 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
85 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
86 #define PCIE_PHY_CTRL_DATA_LOC 0
87 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
88 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
89 #define PCIE_PHY_CTRL_WR_LOC 18
90 #define PCIE_PHY_CTRL_RD_LOC 19
92 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
93 #define PCIE_PHY_STAT_ACK_LOC 16
95 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
96 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
98 /* PHY registers (not memory-mapped) */
99 #define PCIE_PHY_ATEOVRD 0x10
100 #define PCIE_PHY_ATEOVRD_EN (0x1 << 2)
101 #define PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT 0
102 #define PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK 0x1
104 #define PCIE_PHY_MPLL_OVRD_IN_LO 0x11
105 #define PCIE_PHY_MPLL_MULTIPLIER_SHIFT 2
106 #define PCIE_PHY_MPLL_MULTIPLIER_MASK 0x7f
107 #define PCIE_PHY_MPLL_MULTIPLIER_OVRD (0x1 << 9)
109 #define PCIE_PHY_RX_ASIC_OUT 0x100D
110 #define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0)
112 #define PHY_RX_OVRD_IN_LO 0x1005
113 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
114 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
116 static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
118 struct dw_pcie *pci = imx6_pcie->pci;
120 u32 max_iterations = 10;
121 u32 wait_counter = 0;
124 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
125 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
132 } while (wait_counter < max_iterations);
137 static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
139 struct dw_pcie *pci = imx6_pcie->pci;
143 val = addr << PCIE_PHY_CTRL_DATA_LOC;
144 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
146 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
147 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
149 ret = pcie_phy_poll_ack(imx6_pcie, 1);
153 val = addr << PCIE_PHY_CTRL_DATA_LOC;
154 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
156 return pcie_phy_poll_ack(imx6_pcie, 0);
159 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
160 static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
162 struct dw_pcie *pci = imx6_pcie->pci;
166 ret = pcie_phy_wait_ack(imx6_pcie, addr);
170 /* assert Read signal */
171 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
172 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
174 ret = pcie_phy_poll_ack(imx6_pcie, 1);
178 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
179 *data = val & 0xffff;
181 /* deassert Read signal */
182 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
184 return pcie_phy_poll_ack(imx6_pcie, 0);
187 static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
189 struct dw_pcie *pci = imx6_pcie->pci;
195 ret = pcie_phy_wait_ack(imx6_pcie, addr);
199 var = data << PCIE_PHY_CTRL_DATA_LOC;
200 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
203 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
204 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
206 ret = pcie_phy_poll_ack(imx6_pcie, 1);
210 /* deassert cap data */
211 var = data << PCIE_PHY_CTRL_DATA_LOC;
212 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
214 /* wait for ack de-assertion */
215 ret = pcie_phy_poll_ack(imx6_pcie, 0);
219 /* assert wr signal */
220 var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
221 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
224 ret = pcie_phy_poll_ack(imx6_pcie, 1);
228 /* deassert wr signal */
229 var = data << PCIE_PHY_CTRL_DATA_LOC;
230 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
232 /* wait for ack de-assertion */
233 ret = pcie_phy_poll_ack(imx6_pcie, 0);
237 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0);
242 static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
246 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
247 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
248 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
249 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
251 usleep_range(2000, 3000);
253 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
254 tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
255 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
256 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
259 /* Added for PCI abort handling */
260 static int imx6q_pcie_abort_handler(unsigned long addr,
261 unsigned int fsr, struct pt_regs *regs)
263 unsigned long pc = instruction_pointer(regs);
264 unsigned long instr = *(unsigned long *)pc;
265 int reg = (instr >> 12) & 15;
268 * If the instruction being executed was a read,
269 * make it look like it read all-ones.
271 if ((instr & 0x0c100000) == 0x04100000) {
274 if (instr & 0x00400000)
279 regs->uregs[reg] = val;
284 if ((instr & 0x0e100090) == 0x00100090) {
285 regs->uregs[reg] = -1;
293 static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
295 struct device *dev = imx6_pcie->pci->dev;
297 switch (imx6_pcie->variant) {
299 reset_control_assert(imx6_pcie->pciephy_reset);
300 reset_control_assert(imx6_pcie->apps_reset);
303 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
304 IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
305 IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
306 /* Force PCIe PHY reset */
307 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
308 IMX6SX_GPR5_PCIE_BTNRST_RESET,
309 IMX6SX_GPR5_PCIE_BTNRST_RESET);
312 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
313 IMX6Q_GPR1_PCIE_SW_RST,
314 IMX6Q_GPR1_PCIE_SW_RST);
317 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
318 IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
319 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
320 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
324 if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
325 int ret = regulator_disable(imx6_pcie->vpcie);
328 dev_err(dev, "failed to disable vpcie regulator: %d\n",
333 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
335 struct dw_pcie *pci = imx6_pcie->pci;
336 struct device *dev = pci->dev;
339 switch (imx6_pcie->variant) {
341 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
343 dev_err(dev, "unable to enable pcie_axi clock\n");
347 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
348 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
350 case IMX6QP: /* FALLTHROUGH */
352 /* power up core phy and enable ref clock */
353 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
354 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
356 * the async reset input need ref clock to sync internally,
357 * when the ref clock comes after reset, internal synced
358 * reset time is too short, cannot meet the requirement.
359 * add one ~10us delay here.
362 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
363 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
372 static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
375 unsigned int retries;
376 struct device *dev = imx6_pcie->pci->dev;
378 for (retries = 0; retries < PHY_PLL_LOCK_WAIT_MAX_RETRIES; retries++) {
379 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR22, &val);
381 if (val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED)
384 usleep_range(PHY_PLL_LOCK_WAIT_USLEEP_MIN,
385 PHY_PLL_LOCK_WAIT_USLEEP_MAX);
388 dev_err(dev, "PCIe PLL lock timeout\n");
391 static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
393 struct dw_pcie *pci = imx6_pcie->pci;
394 struct device *dev = pci->dev;
397 if (imx6_pcie->vpcie && !regulator_is_enabled(imx6_pcie->vpcie)) {
398 ret = regulator_enable(imx6_pcie->vpcie);
400 dev_err(dev, "failed to enable vpcie regulator: %d\n",
406 ret = clk_prepare_enable(imx6_pcie->pcie_phy);
408 dev_err(dev, "unable to enable pcie_phy clock\n");
412 ret = clk_prepare_enable(imx6_pcie->pcie_bus);
414 dev_err(dev, "unable to enable pcie_bus clock\n");
418 ret = clk_prepare_enable(imx6_pcie->pcie);
420 dev_err(dev, "unable to enable pcie clock\n");
424 ret = imx6_pcie_enable_ref_clk(imx6_pcie);
426 dev_err(dev, "unable to enable pcie ref clock\n");
430 /* allow the clocks to stabilize */
431 usleep_range(200, 500);
433 /* Some boards don't have PCIe reset GPIO. */
434 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
435 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
436 imx6_pcie->gpio_active_high);
438 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
439 !imx6_pcie->gpio_active_high);
442 switch (imx6_pcie->variant) {
444 reset_control_deassert(imx6_pcie->pciephy_reset);
445 imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
448 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
449 IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
452 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
453 IMX6Q_GPR1_PCIE_SW_RST, 0);
455 usleep_range(200, 500);
457 case IMX6Q: /* Nothing to do */
464 clk_disable_unprepare(imx6_pcie->pcie);
466 clk_disable_unprepare(imx6_pcie->pcie_bus);
468 clk_disable_unprepare(imx6_pcie->pcie_phy);
470 if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
471 ret = regulator_disable(imx6_pcie->vpcie);
473 dev_err(dev, "failed to disable vpcie regulator: %d\n",
478 static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
480 switch (imx6_pcie->variant) {
482 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
483 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
486 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
487 IMX6SX_GPR12_PCIE_RX_EQ_MASK,
488 IMX6SX_GPR12_PCIE_RX_EQ_2);
491 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
492 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
494 /* configure constant input signal to the pcie ctrl and phy */
495 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
496 IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
498 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
499 IMX6Q_GPR8_TX_DEEMPH_GEN1,
500 imx6_pcie->tx_deemph_gen1 << 0);
501 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
502 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
503 imx6_pcie->tx_deemph_gen2_3p5db << 6);
504 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
505 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
506 imx6_pcie->tx_deemph_gen2_6db << 12);
507 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
508 IMX6Q_GPR8_TX_SWING_FULL,
509 imx6_pcie->tx_swing_full << 18);
510 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
511 IMX6Q_GPR8_TX_SWING_LOW,
512 imx6_pcie->tx_swing_low << 25);
516 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
517 IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
520 static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
522 unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy);
529 * The default settings of the MPLL are for a 125MHz input
530 * clock, so no need to reconfigure anything in that case.
542 dev_err(imx6_pcie->pci->dev,
543 "Unsupported PHY reference clock rate %lu\n", phy_rate);
547 pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val);
548 val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK <<
549 PCIE_PHY_MPLL_MULTIPLIER_SHIFT);
550 val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT;
551 val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD;
552 pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val);
554 pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val);
555 val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK <<
556 PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT);
557 val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT;
558 val |= PCIE_PHY_ATEOVRD_EN;
559 pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val);
564 static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
566 struct dw_pcie *pci = imx6_pcie->pci;
567 struct device *dev = pci->dev;
569 /* check if the link is up or not */
570 if (!dw_pcie_wait_for_link(pci))
573 dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
574 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
575 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
579 static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
581 struct dw_pcie *pci = imx6_pcie->pci;
582 struct device *dev = pci->dev;
584 unsigned int retries;
586 for (retries = 0; retries < 200; retries++) {
587 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
588 /* Test if the speed change finished. */
589 if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
591 usleep_range(100, 1000);
594 dev_err(dev, "Speed change timeout\n");
598 static void imx6_pcie_ltssm_enable(struct device *dev)
600 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
602 switch (imx6_pcie->variant) {
606 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
607 IMX6Q_GPR12_PCIE_CTL_2,
608 IMX6Q_GPR12_PCIE_CTL_2);
611 reset_control_deassert(imx6_pcie->apps_reset);
616 static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
618 struct dw_pcie *pci = imx6_pcie->pci;
619 struct device *dev = pci->dev;
624 * Force Gen1 operation when starting the link. In case the link is
625 * started in Gen2 mode, there is a possibility the devices on the
626 * bus will not be detected at all. This happens with PCIe switches.
628 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
629 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
630 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
631 dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
634 imx6_pcie_ltssm_enable(dev);
636 ret = imx6_pcie_wait_for_link(imx6_pcie);
640 if (imx6_pcie->link_gen == 2) {
641 /* Allow Gen2 mode after the link is up. */
642 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
643 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
644 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
645 dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
648 * Start Directed Speed Change so the best possible
649 * speed both link partners support can be negotiated.
651 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
652 tmp |= PORT_LOGIC_SPEED_CHANGE;
653 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
655 if (imx6_pcie->variant != IMX7D) {
657 * On i.MX7, DIRECT_SPEED_CHANGE behaves differently
658 * from i.MX6 family when no link speed transition
659 * occurs and we go Gen1 -> yep, Gen1. The difference
660 * is that, in such case, it will not be cleared by HW
661 * which will cause the following code to report false
665 ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
667 dev_err(dev, "Failed to bring link up!\n");
672 /* Make sure link training is finished as well! */
673 ret = imx6_pcie_wait_for_link(imx6_pcie);
675 dev_err(dev, "Failed to bring link up!\n");
679 dev_info(dev, "Link: Gen2 disabled\n");
682 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCSR);
683 dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);
687 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
688 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
689 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
690 imx6_pcie_reset_phy(imx6_pcie);
694 static int imx6_pcie_host_init(struct pcie_port *pp)
696 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
697 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
699 imx6_pcie_assert_core_reset(imx6_pcie);
700 imx6_pcie_init_phy(imx6_pcie);
701 imx6_pcie_deassert_core_reset(imx6_pcie);
702 imx6_setup_phy_mpll(imx6_pcie);
703 dw_pcie_setup_rc(pp);
704 imx6_pcie_establish_link(imx6_pcie);
706 if (IS_ENABLED(CONFIG_PCI_MSI))
707 dw_pcie_msi_init(pp);
712 static const struct dw_pcie_host_ops imx6_pcie_host_ops = {
713 .host_init = imx6_pcie_host_init,
716 static int imx6_add_pcie_port(struct imx6_pcie *imx6_pcie,
717 struct platform_device *pdev)
719 struct dw_pcie *pci = imx6_pcie->pci;
720 struct pcie_port *pp = &pci->pp;
721 struct device *dev = &pdev->dev;
724 if (IS_ENABLED(CONFIG_PCI_MSI)) {
725 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
726 if (pp->msi_irq <= 0) {
727 dev_err(dev, "failed to get MSI irq\n");
732 pp->ops = &imx6_pcie_host_ops;
734 ret = dw_pcie_host_init(pp);
736 dev_err(dev, "failed to initialize host\n");
743 static const struct dw_pcie_ops dw_pcie_ops = {
744 /* No special ops needed, but pcie-designware still expects this struct */
747 #ifdef CONFIG_PM_SLEEP
748 static void imx6_pcie_ltssm_disable(struct device *dev)
750 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
752 switch (imx6_pcie->variant) {
755 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
756 IMX6Q_GPR12_PCIE_CTL_2, 0);
759 reset_control_assert(imx6_pcie->apps_reset);
762 dev_err(dev, "ltssm_disable not supported\n");
766 static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
768 reset_control_assert(imx6_pcie->turnoff_reset);
769 reset_control_deassert(imx6_pcie->turnoff_reset);
772 * Components with an upstream port must respond to
773 * PME_Turn_Off with PME_TO_Ack but we can't check.
775 * The standard recommends a 1-10ms timeout after which to
776 * proceed anyway as if acks were received.
778 usleep_range(1000, 10000);
781 static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
783 clk_disable_unprepare(imx6_pcie->pcie);
784 clk_disable_unprepare(imx6_pcie->pcie_phy);
785 clk_disable_unprepare(imx6_pcie->pcie_bus);
787 if (imx6_pcie->variant == IMX7D) {
788 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
789 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
790 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
794 static int imx6_pcie_suspend_noirq(struct device *dev)
796 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
798 if (imx6_pcie->variant != IMX7D)
801 imx6_pcie_pm_turnoff(imx6_pcie);
802 imx6_pcie_clk_disable(imx6_pcie);
803 imx6_pcie_ltssm_disable(dev);
808 static int imx6_pcie_resume_noirq(struct device *dev)
811 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
812 struct pcie_port *pp = &imx6_pcie->pci->pp;
814 if (imx6_pcie->variant != IMX7D)
817 imx6_pcie_assert_core_reset(imx6_pcie);
818 imx6_pcie_init_phy(imx6_pcie);
819 imx6_pcie_deassert_core_reset(imx6_pcie);
820 dw_pcie_setup_rc(pp);
822 ret = imx6_pcie_establish_link(imx6_pcie);
824 dev_info(dev, "pcie link is down after resume.\n");
830 static const struct dev_pm_ops imx6_pcie_pm_ops = {
831 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq,
832 imx6_pcie_resume_noirq)
835 static int imx6_pcie_probe(struct platform_device *pdev)
837 struct device *dev = &pdev->dev;
839 struct imx6_pcie *imx6_pcie;
840 struct resource *dbi_base;
841 struct device_node *node = dev->of_node;
844 imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
848 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
853 pci->ops = &dw_pcie_ops;
855 imx6_pcie->pci = pci;
857 (enum imx6_pcie_variants)of_device_get_match_data(dev);
859 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
860 pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
861 if (IS_ERR(pci->dbi_base))
862 return PTR_ERR(pci->dbi_base);
865 imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
866 imx6_pcie->gpio_active_high = of_property_read_bool(node,
867 "reset-gpio-active-high");
868 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
869 ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
870 imx6_pcie->gpio_active_high ?
871 GPIOF_OUT_INIT_HIGH :
875 dev_err(dev, "unable to get reset gpio\n");
878 } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
879 return imx6_pcie->reset_gpio;
883 imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
884 if (IS_ERR(imx6_pcie->pcie_phy)) {
885 dev_err(dev, "pcie_phy clock source missing or invalid\n");
886 return PTR_ERR(imx6_pcie->pcie_phy);
889 imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");
890 if (IS_ERR(imx6_pcie->pcie_bus)) {
891 dev_err(dev, "pcie_bus clock source missing or invalid\n");
892 return PTR_ERR(imx6_pcie->pcie_bus);
895 imx6_pcie->pcie = devm_clk_get(dev, "pcie");
896 if (IS_ERR(imx6_pcie->pcie)) {
897 dev_err(dev, "pcie clock source missing or invalid\n");
898 return PTR_ERR(imx6_pcie->pcie);
901 switch (imx6_pcie->variant) {
903 imx6_pcie->pcie_inbound_axi = devm_clk_get(dev,
905 if (IS_ERR(imx6_pcie->pcie_inbound_axi)) {
906 dev_err(dev, "pcie_inbound_axi clock missing or invalid\n");
907 return PTR_ERR(imx6_pcie->pcie_inbound_axi);
911 imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev,
913 if (IS_ERR(imx6_pcie->pciephy_reset)) {
914 dev_err(dev, "Failed to get PCIEPHY reset control\n");
915 return PTR_ERR(imx6_pcie->pciephy_reset);
918 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev,
920 if (IS_ERR(imx6_pcie->apps_reset)) {
921 dev_err(dev, "Failed to get PCIE APPS reset control\n");
922 return PTR_ERR(imx6_pcie->apps_reset);
929 /* Grab turnoff reset */
930 imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff");
931 if (IS_ERR(imx6_pcie->turnoff_reset)) {
932 dev_err(dev, "Failed to get TURNOFF reset control\n");
933 return PTR_ERR(imx6_pcie->turnoff_reset);
936 /* Grab GPR config register range */
937 imx6_pcie->iomuxc_gpr =
938 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
939 if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
940 dev_err(dev, "unable to find iomuxc registers\n");
941 return PTR_ERR(imx6_pcie->iomuxc_gpr);
944 /* Grab PCIe PHY Tx Settings */
945 if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
946 &imx6_pcie->tx_deemph_gen1))
947 imx6_pcie->tx_deemph_gen1 = 0;
949 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
950 &imx6_pcie->tx_deemph_gen2_3p5db))
951 imx6_pcie->tx_deemph_gen2_3p5db = 0;
953 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
954 &imx6_pcie->tx_deemph_gen2_6db))
955 imx6_pcie->tx_deemph_gen2_6db = 20;
957 if (of_property_read_u32(node, "fsl,tx-swing-full",
958 &imx6_pcie->tx_swing_full))
959 imx6_pcie->tx_swing_full = 127;
961 if (of_property_read_u32(node, "fsl,tx-swing-low",
962 &imx6_pcie->tx_swing_low))
963 imx6_pcie->tx_swing_low = 127;
965 /* Limit link speed */
966 ret = of_property_read_u32(node, "fsl,max-link-speed",
967 &imx6_pcie->link_gen);
969 imx6_pcie->link_gen = 1;
971 imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
972 if (IS_ERR(imx6_pcie->vpcie)) {
973 if (PTR_ERR(imx6_pcie->vpcie) == -EPROBE_DEFER)
974 return -EPROBE_DEFER;
975 imx6_pcie->vpcie = NULL;
978 platform_set_drvdata(pdev, imx6_pcie);
980 ret = imx6_add_pcie_port(imx6_pcie, pdev);
987 static void imx6_pcie_shutdown(struct platform_device *pdev)
989 struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
991 /* bring down link, so bootloader gets clean state in case of reboot */
992 imx6_pcie_assert_core_reset(imx6_pcie);
995 static const struct of_device_id imx6_pcie_of_match[] = {
996 { .compatible = "fsl,imx6q-pcie", .data = (void *)IMX6Q, },
997 { .compatible = "fsl,imx6sx-pcie", .data = (void *)IMX6SX, },
998 { .compatible = "fsl,imx6qp-pcie", .data = (void *)IMX6QP, },
999 { .compatible = "fsl,imx7d-pcie", .data = (void *)IMX7D, },
1003 static struct platform_driver imx6_pcie_driver = {
1005 .name = "imx6q-pcie",
1006 .of_match_table = imx6_pcie_of_match,
1007 .suppress_bind_attrs = true,
1008 .pm = &imx6_pcie_pm_ops,
1010 .probe = imx6_pcie_probe,
1011 .shutdown = imx6_pcie_shutdown,
1014 static int __init imx6_pcie_init(void)
1017 * Since probe() can be deferred we need to make sure that
1018 * hook_fault_code is not called after __init memory is freed
1019 * by kernel and since imx6q_pcie_abort_handler() is a no-op,
1020 * we can install the handler here without risking it
1021 * accessing some uninitialized driver state.
1023 hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0,
1024 "external abort on non-linefetch");
1026 return platform_driver_register(&imx6_pcie_driver);
1028 device_initcall(imx6_pcie_init);