1 #include <linux/delay.h>
3 #include <linux/module.h>
4 #include <linux/sched/signal.h>
5 #include <linux/slab.h>
6 #include <linux/ioport.h>
7 #include <linux/wait.h>
12 * This interrupt-safe spinlock protects all accesses to PCI
13 * configuration space.
16 DEFINE_RAW_SPINLOCK(pci_lock);
19 * Wrappers for all PCI configuration access functions. They just check
20 * alignment, do locking and call the low-level functions pointed to
24 #define PCI_byte_BAD 0
25 #define PCI_word_BAD (pos & 1)
26 #define PCI_dword_BAD (pos & 3)
28 #ifdef CONFIG_PCI_LOCKLESS_CONFIG
29 # define pci_lock_config(f) do { (void)(f); } while (0)
30 # define pci_unlock_config(f) do { (void)(f); } while (0)
32 # define pci_lock_config(f) raw_spin_lock_irqsave(&pci_lock, f)
33 # define pci_unlock_config(f) raw_spin_unlock_irqrestore(&pci_lock, f)
36 #define PCI_OP_READ(size, type, len) \
37 int pci_bus_read_config_##size \
38 (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
41 unsigned long flags; \
43 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
44 pci_lock_config(flags); \
45 res = bus->ops->read(bus, devfn, pos, len, &data); \
46 *value = (type)data; \
47 pci_unlock_config(flags); \
51 #define PCI_OP_WRITE(size, type, len) \
52 int pci_bus_write_config_##size \
53 (struct pci_bus *bus, unsigned int devfn, int pos, type value) \
56 unsigned long flags; \
57 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
58 pci_lock_config(flags); \
59 res = bus->ops->write(bus, devfn, pos, len, value); \
60 pci_unlock_config(flags); \
64 PCI_OP_READ(byte, u8, 1)
65 PCI_OP_READ(word, u16, 2)
66 PCI_OP_READ(dword, u32, 4)
67 PCI_OP_WRITE(byte, u8, 1)
68 PCI_OP_WRITE(word, u16, 2)
69 PCI_OP_WRITE(dword, u32, 4)
71 EXPORT_SYMBOL(pci_bus_read_config_byte);
72 EXPORT_SYMBOL(pci_bus_read_config_word);
73 EXPORT_SYMBOL(pci_bus_read_config_dword);
74 EXPORT_SYMBOL(pci_bus_write_config_byte);
75 EXPORT_SYMBOL(pci_bus_write_config_word);
76 EXPORT_SYMBOL(pci_bus_write_config_dword);
78 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
79 int where, int size, u32 *val)
83 addr = bus->ops->map_bus(bus, devfn, where);
86 return PCIBIOS_DEVICE_NOT_FOUND;
96 return PCIBIOS_SUCCESSFUL;
98 EXPORT_SYMBOL_GPL(pci_generic_config_read);
100 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
101 int where, int size, u32 val)
105 addr = bus->ops->map_bus(bus, devfn, where);
107 return PCIBIOS_DEVICE_NOT_FOUND;
116 return PCIBIOS_SUCCESSFUL;
118 EXPORT_SYMBOL_GPL(pci_generic_config_write);
120 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
121 int where, int size, u32 *val)
125 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
128 return PCIBIOS_DEVICE_NOT_FOUND;
134 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
136 return PCIBIOS_SUCCESSFUL;
138 EXPORT_SYMBOL_GPL(pci_generic_config_read32);
140 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
141 int where, int size, u32 val)
146 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
148 return PCIBIOS_DEVICE_NOT_FOUND;
152 return PCIBIOS_SUCCESSFUL;
156 * In general, hardware that supports only 32-bit writes on PCI is
157 * not spec-compliant. For example, software may perform a 16-bit
158 * write. If the hardware only supports 32-bit accesses, we must
159 * do a 32-bit read, merge in the 16 bits we intend to write,
160 * followed by a 32-bit write. If the 16 bits we *don't* intend to
161 * write happen to have any RW1C (write-one-to-clear) bits set, we
162 * just inadvertently cleared something we shouldn't have.
164 dev_warn_ratelimited(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n",
165 size, pci_domain_nr(bus), bus->number,
166 PCI_SLOT(devfn), PCI_FUNC(devfn), where);
168 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
169 tmp = readl(addr) & mask;
170 tmp |= val << ((where & 0x3) * 8);
173 return PCIBIOS_SUCCESSFUL;
175 EXPORT_SYMBOL_GPL(pci_generic_config_write32);
178 * pci_bus_set_ops - Set raw operations of pci bus
179 * @bus: pci bus struct
180 * @ops: new raw operations
182 * Return previous raw operations
184 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
186 struct pci_ops *old_ops;
189 raw_spin_lock_irqsave(&pci_lock, flags);
192 raw_spin_unlock_irqrestore(&pci_lock, flags);
195 EXPORT_SYMBOL(pci_bus_set_ops);
198 * The following routines are to prevent the user from accessing PCI config
199 * space when it's unsafe to do so. Some devices require this during BIST and
200 * we're required to prevent it during D-state transitions.
202 * We have a bit per device to indicate it's blocked and a global wait queue
203 * for callers to sleep on until devices are unblocked.
205 static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
207 static noinline void pci_wait_cfg(struct pci_dev *dev)
209 DECLARE_WAITQUEUE(wait, current);
211 __add_wait_queue(&pci_cfg_wait, &wait);
213 set_current_state(TASK_UNINTERRUPTIBLE);
214 raw_spin_unlock_irq(&pci_lock);
216 raw_spin_lock_irq(&pci_lock);
217 } while (dev->block_cfg_access);
218 __remove_wait_queue(&pci_cfg_wait, &wait);
221 /* Returns 0 on success, negative values indicate error. */
222 #define PCI_USER_READ_CONFIG(size, type) \
223 int pci_user_read_config_##size \
224 (struct pci_dev *dev, int pos, type *val) \
226 int ret = PCIBIOS_SUCCESSFUL; \
228 if (PCI_##size##_BAD) \
230 raw_spin_lock_irq(&pci_lock); \
231 if (unlikely(dev->block_cfg_access)) \
233 ret = dev->bus->ops->read(dev->bus, dev->devfn, \
234 pos, sizeof(type), &data); \
235 raw_spin_unlock_irq(&pci_lock); \
237 return pcibios_err_to_errno(ret); \
239 EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
241 /* Returns 0 on success, negative values indicate error. */
242 #define PCI_USER_WRITE_CONFIG(size, type) \
243 int pci_user_write_config_##size \
244 (struct pci_dev *dev, int pos, type val) \
246 int ret = PCIBIOS_SUCCESSFUL; \
247 if (PCI_##size##_BAD) \
249 raw_spin_lock_irq(&pci_lock); \
250 if (unlikely(dev->block_cfg_access)) \
252 ret = dev->bus->ops->write(dev->bus, dev->devfn, \
253 pos, sizeof(type), val); \
254 raw_spin_unlock_irq(&pci_lock); \
255 return pcibios_err_to_errno(ret); \
257 EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
259 PCI_USER_READ_CONFIG(byte, u8)
260 PCI_USER_READ_CONFIG(word, u16)
261 PCI_USER_READ_CONFIG(dword, u32)
262 PCI_USER_WRITE_CONFIG(byte, u8)
263 PCI_USER_WRITE_CONFIG(word, u16)
264 PCI_USER_WRITE_CONFIG(dword, u32)
266 /* VPD access through PCI 2.2+ VPD capability */
269 * pci_read_vpd - Read one entry from Vital Product Data
270 * @dev: pci device struct
271 * @pos: offset in vpd space
272 * @count: number of bytes to read
273 * @buf: pointer to where to store result
275 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
277 if (!dev->vpd || !dev->vpd->ops)
279 return dev->vpd->ops->read(dev, pos, count, buf);
281 EXPORT_SYMBOL(pci_read_vpd);
284 * pci_write_vpd - Write entry to Vital Product Data
285 * @dev: pci device struct
286 * @pos: offset in vpd space
287 * @count: number of bytes to write
288 * @buf: buffer containing write data
290 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
292 if (!dev->vpd || !dev->vpd->ops)
294 return dev->vpd->ops->write(dev, pos, count, buf);
296 EXPORT_SYMBOL(pci_write_vpd);
299 * pci_set_vpd_size - Set size of Vital Product Data space
300 * @dev: pci device struct
301 * @len: size of vpd space
303 int pci_set_vpd_size(struct pci_dev *dev, size_t len)
305 if (!dev->vpd || !dev->vpd->ops)
307 return dev->vpd->ops->set_size(dev, len);
309 EXPORT_SYMBOL(pci_set_vpd_size);
311 #define PCI_VPD_MAX_SIZE (PCI_VPD_ADDR_MASK + 1)
314 * pci_vpd_size - determine actual size of Vital Product Data
315 * @dev: pci device struct
316 * @old_size: current assumed size, also maximum allowed size
318 static size_t pci_vpd_size(struct pci_dev *dev, size_t old_size)
321 unsigned char header[1+2]; /* 1 byte tag, 2 bytes length */
323 while (off < old_size &&
324 pci_read_vpd(dev, off, 1, header) == 1) {
327 if (header[0] & PCI_VPD_LRDT) {
328 /* Large Resource Data Type Tag */
329 tag = pci_vpd_lrdt_tag(header);
330 /* Only read length from known tag items */
331 if ((tag == PCI_VPD_LTIN_ID_STRING) ||
332 (tag == PCI_VPD_LTIN_RO_DATA) ||
333 (tag == PCI_VPD_LTIN_RW_DATA)) {
334 if (pci_read_vpd(dev, off+1, 2,
337 "invalid large VPD tag %02x size at offset %zu",
341 off += PCI_VPD_LRDT_TAG_SIZE +
342 pci_vpd_lrdt_size(header);
345 /* Short Resource Data Type Tag */
346 off += PCI_VPD_SRDT_TAG_SIZE +
347 pci_vpd_srdt_size(header);
348 tag = pci_vpd_srdt_tag(header);
351 if (tag == PCI_VPD_STIN_END) /* End tag descriptor */
354 if ((tag != PCI_VPD_LTIN_ID_STRING) &&
355 (tag != PCI_VPD_LTIN_RO_DATA) &&
356 (tag != PCI_VPD_LTIN_RW_DATA)) {
358 "invalid %s VPD tag %02x at offset %zu",
359 (header[0] & PCI_VPD_LRDT) ? "large" : "short",
368 * Wait for last operation to complete.
369 * This code has to spin since there is no other notification from the PCI
370 * hardware. Since the VPD is often implemented by serial attachment to an
371 * EEPROM, it may take many milliseconds to complete.
373 * Returns 0 on success, negative values indicate error.
375 static int pci_vpd_wait(struct pci_dev *dev)
377 struct pci_vpd *vpd = dev->vpd;
378 unsigned long timeout = jiffies + msecs_to_jiffies(125);
379 unsigned long max_sleep = 16;
386 while (time_before(jiffies, timeout)) {
387 ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
392 if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
397 if (fatal_signal_pending(current))
400 usleep_range(10, max_sleep);
401 if (max_sleep < 1024)
405 dev_warn(&dev->dev, "VPD access failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update\n");
409 static ssize_t pci_vpd_read(struct pci_dev *dev, loff_t pos, size_t count,
412 struct pci_vpd *vpd = dev->vpd;
414 loff_t end = pos + count;
422 vpd->len = pci_vpd_size(dev, vpd->len);
431 if (end > vpd->len) {
436 if (mutex_lock_killable(&vpd->lock))
439 ret = pci_vpd_wait(dev);
445 unsigned int i, skip;
447 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
452 vpd->flag = PCI_VPD_ADDR_F;
453 ret = pci_vpd_wait(dev);
457 ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
462 for (i = 0; i < sizeof(u32); i++) {
472 mutex_unlock(&vpd->lock);
473 return ret ? ret : count;
476 static ssize_t pci_vpd_write(struct pci_dev *dev, loff_t pos, size_t count,
479 struct pci_vpd *vpd = dev->vpd;
481 loff_t end = pos + count;
484 if (pos < 0 || (pos & 3) || (count & 3))
489 vpd->len = pci_vpd_size(dev, vpd->len);
498 if (mutex_lock_killable(&vpd->lock))
501 ret = pci_vpd_wait(dev);
513 ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
516 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
517 pos | PCI_VPD_ADDR_F);
523 ret = pci_vpd_wait(dev);
530 mutex_unlock(&vpd->lock);
531 return ret ? ret : count;
534 static int pci_vpd_set_size(struct pci_dev *dev, size_t len)
536 struct pci_vpd *vpd = dev->vpd;
538 if (len == 0 || len > PCI_VPD_MAX_SIZE)
547 static const struct pci_vpd_ops pci_vpd_ops = {
548 .read = pci_vpd_read,
549 .write = pci_vpd_write,
550 .set_size = pci_vpd_set_size,
553 static ssize_t pci_vpd_f0_read(struct pci_dev *dev, loff_t pos, size_t count,
556 struct pci_dev *tdev = pci_get_slot(dev->bus,
557 PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
563 ret = pci_read_vpd(tdev, pos, count, arg);
568 static ssize_t pci_vpd_f0_write(struct pci_dev *dev, loff_t pos, size_t count,
571 struct pci_dev *tdev = pci_get_slot(dev->bus,
572 PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
578 ret = pci_write_vpd(tdev, pos, count, arg);
583 static int pci_vpd_f0_set_size(struct pci_dev *dev, size_t len)
585 struct pci_dev *tdev = pci_get_slot(dev->bus,
586 PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
592 ret = pci_set_vpd_size(tdev, len);
597 static const struct pci_vpd_ops pci_vpd_f0_ops = {
598 .read = pci_vpd_f0_read,
599 .write = pci_vpd_f0_write,
600 .set_size = pci_vpd_f0_set_size,
603 int pci_vpd_init(struct pci_dev *dev)
608 cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
612 vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
616 vpd->len = PCI_VPD_MAX_SIZE;
617 if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0)
618 vpd->ops = &pci_vpd_f0_ops;
620 vpd->ops = &pci_vpd_ops;
621 mutex_init(&vpd->lock);
629 void pci_vpd_release(struct pci_dev *dev)
635 * pci_cfg_access_lock - Lock PCI config reads/writes
636 * @dev: pci device struct
638 * When access is locked, any userspace reads or writes to config
639 * space and concurrent lock requests will sleep until access is
640 * allowed via pci_cfg_access_unlock() again.
642 void pci_cfg_access_lock(struct pci_dev *dev)
646 raw_spin_lock_irq(&pci_lock);
647 if (dev->block_cfg_access)
649 dev->block_cfg_access = 1;
650 raw_spin_unlock_irq(&pci_lock);
652 EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
655 * pci_cfg_access_trylock - try to lock PCI config reads/writes
656 * @dev: pci device struct
658 * Same as pci_cfg_access_lock, but will return 0 if access is
659 * already locked, 1 otherwise. This function can be used from
662 bool pci_cfg_access_trylock(struct pci_dev *dev)
667 raw_spin_lock_irqsave(&pci_lock, flags);
668 if (dev->block_cfg_access)
671 dev->block_cfg_access = 1;
672 raw_spin_unlock_irqrestore(&pci_lock, flags);
676 EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
679 * pci_cfg_access_unlock - Unlock PCI config reads/writes
680 * @dev: pci device struct
682 * This function allows PCI config accesses to resume.
684 void pci_cfg_access_unlock(struct pci_dev *dev)
688 raw_spin_lock_irqsave(&pci_lock, flags);
690 /* This indicates a problem in the caller, but we don't need
691 * to kill them, unlike a double-block above. */
692 WARN_ON(!dev->block_cfg_access);
694 dev->block_cfg_access = 0;
695 raw_spin_unlock_irqrestore(&pci_lock, flags);
697 wake_up_all(&pci_cfg_wait);
699 EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
701 static inline int pcie_cap_version(const struct pci_dev *dev)
703 return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
706 static bool pcie_downstream_port(const struct pci_dev *dev)
708 int type = pci_pcie_type(dev);
710 return type == PCI_EXP_TYPE_ROOT_PORT ||
711 type == PCI_EXP_TYPE_DOWNSTREAM ||
712 type == PCI_EXP_TYPE_PCIE_BRIDGE;
715 bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
717 int type = pci_pcie_type(dev);
719 return type == PCI_EXP_TYPE_ENDPOINT ||
720 type == PCI_EXP_TYPE_LEG_END ||
721 type == PCI_EXP_TYPE_ROOT_PORT ||
722 type == PCI_EXP_TYPE_UPSTREAM ||
723 type == PCI_EXP_TYPE_DOWNSTREAM ||
724 type == PCI_EXP_TYPE_PCI_BRIDGE ||
725 type == PCI_EXP_TYPE_PCIE_BRIDGE;
728 static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
730 return pcie_downstream_port(dev) &&
731 pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
734 static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
736 int type = pci_pcie_type(dev);
738 return type == PCI_EXP_TYPE_ROOT_PORT ||
739 type == PCI_EXP_TYPE_RC_EC;
742 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
744 if (!pci_is_pcie(dev))
757 return pcie_cap_has_lnkctl(dev);
761 return pcie_cap_has_sltctl(dev);
765 return pcie_cap_has_rtctl(dev);
766 case PCI_EXP_DEVCAP2:
767 case PCI_EXP_DEVCTL2:
768 case PCI_EXP_LNKCAP2:
769 case PCI_EXP_LNKCTL2:
770 case PCI_EXP_LNKSTA2:
771 return pcie_cap_version(dev) > 1;
778 * Note that these accessor functions are only for the "PCI Express
779 * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
780 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
782 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
790 if (pcie_capability_reg_implemented(dev, pos)) {
791 ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
793 * Reset *val to 0 if pci_read_config_word() fails, it may
794 * have been written as 0xFFFF if hardware error happens
795 * during pci_read_config_word().
803 * For Functions that do not implement the Slot Capabilities,
804 * Slot Status, and Slot Control registers, these spaces must
805 * be hardwired to 0b, with the exception of the Presence Detect
806 * State bit in the Slot Status register of Downstream Ports,
807 * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
809 if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
810 pos == PCI_EXP_SLTSTA)
811 *val = PCI_EXP_SLTSTA_PDS;
815 EXPORT_SYMBOL(pcie_capability_read_word);
817 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
825 if (pcie_capability_reg_implemented(dev, pos)) {
826 ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
828 * Reset *val to 0 if pci_read_config_dword() fails, it may
829 * have been written as 0xFFFFFFFF if hardware error happens
830 * during pci_read_config_dword().
837 if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
838 pos == PCI_EXP_SLTSTA)
839 *val = PCI_EXP_SLTSTA_PDS;
843 EXPORT_SYMBOL(pcie_capability_read_dword);
845 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
850 if (!pcie_capability_reg_implemented(dev, pos))
853 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
855 EXPORT_SYMBOL(pcie_capability_write_word);
857 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
862 if (!pcie_capability_reg_implemented(dev, pos))
865 return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
867 EXPORT_SYMBOL(pcie_capability_write_dword);
869 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
875 ret = pcie_capability_read_word(dev, pos, &val);
879 ret = pcie_capability_write_word(dev, pos, val);
884 EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
886 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
892 ret = pcie_capability_read_dword(dev, pos, &val);
896 ret = pcie_capability_write_dword(dev, pos, val);
901 EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);
903 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
905 if (pci_dev_is_disconnected(dev)) {
907 return PCIBIOS_DEVICE_NOT_FOUND;
909 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
911 EXPORT_SYMBOL(pci_read_config_byte);
913 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
915 if (pci_dev_is_disconnected(dev)) {
917 return PCIBIOS_DEVICE_NOT_FOUND;
919 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
921 EXPORT_SYMBOL(pci_read_config_word);
923 int pci_read_config_dword(const struct pci_dev *dev, int where,
926 if (pci_dev_is_disconnected(dev)) {
928 return PCIBIOS_DEVICE_NOT_FOUND;
930 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
932 EXPORT_SYMBOL(pci_read_config_dword);
934 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
936 if (pci_dev_is_disconnected(dev))
937 return PCIBIOS_DEVICE_NOT_FOUND;
938 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
940 EXPORT_SYMBOL(pci_write_config_byte);
942 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
944 if (pci_dev_is_disconnected(dev))
945 return PCIBIOS_DEVICE_NOT_FOUND;
946 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
948 EXPORT_SYMBOL(pci_write_config_word);
950 int pci_write_config_dword(const struct pci_dev *dev, int where,
953 if (pci_dev_is_disconnected(dev))
954 return PCIBIOS_DEVICE_NOT_FOUND;
955 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
957 EXPORT_SYMBOL(pci_write_config_dword);