1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Andrew-CT Chen <andrew-ct.chen@mediatek.com>
7 #include <linux/device.h>
8 #include <linux/module.h>
9 #include <linux/mod_devicetable.h>
11 #include <linux/nvmem-provider.h>
12 #include <linux/platform_device.h>
13 #include <linux/property.h>
15 struct mtk_efuse_pdata {
16 bool uses_post_processing;
19 struct mtk_efuse_priv {
23 static int mtk_reg_read(void *context,
24 unsigned int reg, void *_val, size_t bytes)
26 struct mtk_efuse_priv *priv = context;
27 void __iomem *addr = priv->base + reg;
31 for (i = 0; i < bytes; i++, val++)
32 *val = readb(addr + i);
37 static int mtk_efuse_gpu_speedbin_pp(void *context, const char *id, int index,
38 unsigned int offset, void *data, size_t bytes)
48 static void mtk_efuse_fixup_dt_cell_info(struct nvmem_device *nvmem,
49 struct nvmem_cell_info *cell)
51 size_t sz = strlen(cell->name);
54 * On some SoCs, the GPU speedbin is not read as bitmask but as
55 * a number with range [0-7] (max 3 bits): post process to use
56 * it in OPP tables to describe supported-hw.
58 if (cell->nbits <= 3 &&
59 strncmp(cell->name, "gpu-speedbin", min(sz, strlen("gpu-speedbin"))) == 0)
60 cell->read_post_process = mtk_efuse_gpu_speedbin_pp;
63 static int mtk_efuse_probe(struct platform_device *pdev)
65 struct device *dev = &pdev->dev;
67 struct nvmem_device *nvmem;
68 struct nvmem_config econfig = {};
69 struct mtk_efuse_priv *priv;
70 const struct mtk_efuse_pdata *pdata;
72 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
76 priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
77 if (IS_ERR(priv->base))
78 return PTR_ERR(priv->base);
80 pdata = device_get_match_data(dev);
81 econfig.add_legacy_fixed_of_cells = true;
83 econfig.word_size = 1;
84 econfig.reg_read = mtk_reg_read;
85 econfig.size = resource_size(res);
88 if (pdata->uses_post_processing)
89 econfig.fixup_dt_cell_info = &mtk_efuse_fixup_dt_cell_info;
90 nvmem = devm_nvmem_register(dev, &econfig);
92 return PTR_ERR_OR_ZERO(nvmem);
95 static const struct mtk_efuse_pdata mtk_mt8186_efuse_pdata = {
96 .uses_post_processing = true,
99 static const struct mtk_efuse_pdata mtk_efuse_pdata = {
100 .uses_post_processing = false,
103 static const struct of_device_id mtk_efuse_of_match[] = {
104 { .compatible = "mediatek,mt8173-efuse", .data = &mtk_efuse_pdata },
105 { .compatible = "mediatek,mt8186-efuse", .data = &mtk_mt8186_efuse_pdata },
106 { .compatible = "mediatek,efuse", .data = &mtk_efuse_pdata },
109 MODULE_DEVICE_TABLE(of, mtk_efuse_of_match);
111 static struct platform_driver mtk_efuse_driver = {
112 .probe = mtk_efuse_probe,
114 .name = "mediatek,efuse",
115 .of_match_table = mtk_efuse_of_match,
119 static int __init mtk_efuse_init(void)
123 ret = platform_driver_register(&mtk_efuse_driver);
125 pr_err("Failed to register efuse driver\n");
132 static void __exit mtk_efuse_exit(void)
134 return platform_driver_unregister(&mtk_efuse_driver);
137 subsys_initcall(mtk_efuse_init);
138 module_exit(mtk_efuse_exit);
140 MODULE_AUTHOR("Andrew-CT Chen <andrew-ct.chen@mediatek.com>");
141 MODULE_DESCRIPTION("Mediatek EFUSE driver");
142 MODULE_LICENSE("GPL v2");