drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/bitops.h>
  16 #include <linux/blkdev.h>
  17 #include <linux/blk-mq.h>
  18 #include <linux/cpu.h>
  19 #include <linux/delay.h>
  20 #include <linux/errno.h>
  21 #include <linux/fs.h>
  22 #include <linux/genhd.h>
  23 #include <linux/hdreg.h>
  24 #include <linux/idr.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kdev_t.h>
  29 #include <linux/kthread.h>
  30 #include <linux/kernel.h>
  31 #include <linux/mm.h>
  32 #include <linux/module.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/mutex.h>
  35 #include <linux/pci.h>
  36 #include <linux/poison.h>
  37 #include <linux/ptrace.h>
  38 #include <linux/sched.h>
  39 #include <linux/slab.h>
  40 #include <linux/t10-pi.h>
  41 #include <linux/types.h>
  42 #include <linux/io-64-nonatomic-lo-hi.h>
  43 #include <asm/unaligned.h>
  44
  45 #include "nvme.h"
  46
  47 #define NVME_Q_DEPTH            1024
  48 #define NVME_AQ_DEPTH           256
  49 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  50 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  51
  52 /*
  53  * We handle AEN commands ourselves and don't even let the
  54  * block layer know about them.
  55  */
  56 #define NVME_NR_AEN_COMMANDS    1
  57 #define NVME_AQ_BLKMQ_DEPTH     (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
  58
  59 unsigned char admin_timeout = 60;
  60 module_param(admin_timeout, byte, 0644);
  61 MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
  62
  63 unsigned char nvme_io_timeout = 30;
  64 module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
  65 MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
  66
  67 unsigned char shutdown_timeout = 5;
  68 module_param(shutdown_timeout, byte, 0644);
  69 MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
  70
  71 static int use_threaded_interrupts;
  72 module_param(use_threaded_interrupts, int, 0);
  73
  74 static bool use_cmb_sqes = true;
  75 module_param(use_cmb_sqes, bool, 0644);
  76 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  77
  78 static LIST_HEAD(dev_list);
  79 static struct task_struct *nvme_thread;
  80 static struct workqueue_struct *nvme_workq;
  81 static wait_queue_head_t nvme_kthread_wait;
  82
  83 struct nvme_dev;
  84 struct nvme_queue;
  85
  86 static int nvme_reset(struct nvme_dev *dev);
  87 static void nvme_process_cq(struct nvme_queue *nvmeq);
  88 static void nvme_remove_dead_ctrl(struct nvme_dev *dev);
  89 static void nvme_dev_shutdown(struct nvme_dev *dev);
  90
  91 struct async_cmd_info {
  92         struct kthread_work work;
  93         struct kthread_worker *worker;
  94         int status;
  95         void *ctx;
  96 };
  97
  98 /*
  99  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
 100  */
 101 struct nvme_dev {
 102         struct list_head node;
 103         struct nvme_queue **queues;
 104         struct blk_mq_tag_set tagset;
 105         struct blk_mq_tag_set admin_tagset;
 106         u32 __iomem *dbs;
 107         struct device *dev;
 108         struct dma_pool *prp_page_pool;
 109         struct dma_pool *prp_small_pool;
 110         unsigned queue_count;
 111         unsigned online_queues;
 112         unsigned max_qid;
 113         int q_depth;
 114         u32 db_stride;
 115         struct msix_entry *entry;
 116         void __iomem *bar;
 117         struct work_struct reset_work;
 118         struct work_struct scan_work;
 119         struct work_struct remove_work;
 120         struct mutex shutdown_lock;
 121         bool subsystem;
 122         void __iomem *cmb;
 123         dma_addr_t cmb_dma_addr;
 124         u64 cmb_size;
 125         u32 cmbsz;
 126         unsigned long flags;
 127 #define NVME_CTRL_RESETTING    0
 128
 129         struct nvme_ctrl ctrl;
 130 };
 131
 132 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 133 {
 134         return container_of(ctrl, struct nvme_dev, ctrl);
 135 }
 136
 137 /*
 138  * An NVM Express queue.  Each device has at least two (one for admin
 139  * commands and one for I/O commands).
 140  */
 141 struct nvme_queue {
 142         struct device *q_dmadev;
 143         struct nvme_dev *dev;
 144         char irqname[24];       /* nvme4294967295-65535\0 */
 145         spinlock_t q_lock;
 146         struct nvme_command *sq_cmds;
 147         struct nvme_command __iomem *sq_cmds_io;
 148         volatile struct nvme_completion *cqes;
 149         struct blk_mq_tags **tags;
 150         dma_addr_t sq_dma_addr;
 151         dma_addr_t cq_dma_addr;
 152         u32 __iomem *q_db;
 153         u16 q_depth;
 154         s16 cq_vector;
 155         u16 sq_head;
 156         u16 sq_tail;
 157         u16 cq_head;
 158         u16 qid;
 159         u8 cq_phase;
 160         u8 cqe_seen;
 161         struct async_cmd_info cmdinfo;
 162 };
 163
 164 /*
 165  * The nvme_iod describes the data in an I/O, including the list of PRP
 166  * entries.  You can't see it in this data structure because C doesn't let
 167  * me express that.  Use nvme_alloc_iod to ensure there's enough space
 168  * allocated to store the PRP list.
 169  */
 170 struct nvme_iod {
 171         unsigned long private;  /* For the use of the submitter of the I/O */
 172         int npages;             /* In the PRP list. 0 means small pool in use */
 173         int offset;             /* Of PRP list */
 174         int nents;              /* Used in scatterlist */
 175         int length;             /* Of data, in bytes */
 176         dma_addr_t first_dma;
 177         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 178         struct scatterlist sg[0];
 179 };
 180
 181 /*
 182  * Check we didin't inadvertently grow the command struct
 183  */
 184 static inline void _nvme_check_size(void)
 185 {
 186         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 187         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 188         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 189         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 190         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 191         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 192         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 193         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 194         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 195         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 196         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 197         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 198 }
 199
 200 struct nvme_cmd_info {
 201         int aborted;
 202         struct nvme_queue *nvmeq;
 203         struct nvme_iod *iod;
 204         struct nvme_iod __iod;
 205 };
 206
 207 /*
 208  * Max size of iod being embedded in the request payload
 209  */
 210 #define NVME_INT_PAGES          2
 211 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 212 #define NVME_INT_MASK           0x01
 213
 214 /*
 215  * Will slightly overestimate the number of pages needed.  This is OK
 216  * as it only leads to a small amount of wasted memory for the lifetime of
 217  * the I/O.
 218  */
 219 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 220 {
 221         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 222                                       dev->ctrl.page_size);
 223         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 224 }
 225
 226 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 227 {
 228         unsigned int ret = sizeof(struct nvme_cmd_info);
 229
 230         ret += sizeof(struct nvme_iod);
 231         ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
 232         ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
 233
 234         return ret;
 235 }
 236
 237 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 238                                 unsigned int hctx_idx)
 239 {
 240         struct nvme_dev *dev = data;
 241         struct nvme_queue *nvmeq = dev->queues[0];
 242
 243         WARN_ON(hctx_idx != 0);
 244         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 245         WARN_ON(nvmeq->tags);
 246
 247         hctx->driver_data = nvmeq;
 248         nvmeq->tags = &dev->admin_tagset.tags[0];
 249         return 0;
 250 }
 251
 252 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 253 {
 254         struct nvme_queue *nvmeq = hctx->driver_data;
 255
 256         nvmeq->tags = NULL;
 257 }
 258
 259 static int nvme_admin_init_request(void *data, struct request *req,
 260                                 unsigned int hctx_idx, unsigned int rq_idx,
 261                                 unsigned int numa_node)
 262 {
 263         struct nvme_dev *dev = data;
 264         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
 265         struct nvme_queue *nvmeq = dev->queues[0];
 266
 267         BUG_ON(!nvmeq);
 268         cmd->nvmeq = nvmeq;
 269         return 0;
 270 }
 271
 272 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 273                           unsigned int hctx_idx)
 274 {
 275         struct nvme_dev *dev = data;
 276         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 277
 278         if (!nvmeq->tags)
 279                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 280
 281         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 282         hctx->driver_data = nvmeq;
 283         return 0;
 284 }
 285
 286 static int nvme_init_request(void *data, struct request *req,
 287                                 unsigned int hctx_idx, unsigned int rq_idx,
 288                                 unsigned int numa_node)
 289 {
 290         struct nvme_dev *dev = data;
 291         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
 292         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 293
 294         BUG_ON(!nvmeq);
 295         cmd->nvmeq = nvmeq;
 296         return 0;
 297 }
 298
 299 static void *iod_get_private(struct nvme_iod *iod)
 300 {
 301         return (void *) (iod->private & ~0x1UL);
 302 }
 303
 304 /*
 305  * If bit 0 is set, the iod is embedded in the request payload.
 306  */
 307 static bool iod_should_kfree(struct nvme_iod *iod)
 308 {
 309         return (iod->private & NVME_INT_MASK) == 0;
 310 }
 311
 312 static void nvme_complete_async_event(struct nvme_dev *dev,
 313                 struct nvme_completion *cqe)
 314 {
 315         u16 status = le16_to_cpu(cqe->status) >> 1;
 316         u32 result = le32_to_cpu(cqe->result);
 317
 318         if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
 319                 ++dev->ctrl.event_limit;
 320         if (status != NVME_SC_SUCCESS)
 321                 return;
 322
 323         switch (result & 0xff07) {
 324         case NVME_AER_NOTICE_NS_CHANGED:
 325                 dev_info(dev->dev, "rescanning\n");
 326                 queue_work(nvme_workq, &dev->scan_work);
 327         default:
 328                 dev_warn(dev->dev, "async event result %08x\n", result);
 329         }
 330 }
 331
 332 /**
 333  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 334  * @nvmeq: The queue to use
 335  * @cmd: The command to send
 336  *
 337  * Safe to use from interrupt context
 338  */
 339 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 340                                                 struct nvme_command *cmd)
 341 {
 342         u16 tail = nvmeq->sq_tail;
 343
 344         if (nvmeq->sq_cmds_io)
 345                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 346         else
 347                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 348
 349         if (++tail == nvmeq->q_depth)
 350                 tail = 0;
 351         writel(tail, nvmeq->q_db);
 352         nvmeq->sq_tail = tail;
 353 }
 354
 355 static __le64 **iod_list(struct nvme_iod *iod)
 356 {
 357         return ((void *)iod) + iod->offset;
 358 }
 359
 360 static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
 361                             unsigned nseg, unsigned long private)
 362 {
 363         iod->private = private;
 364         iod->offset = offsetof(struct nvme_iod, sg[nseg]);
 365         iod->npages = -1;
 366         iod->length = nbytes;
 367         iod->nents = 0;
 368 }
 369
 370 static struct nvme_iod *
 371 __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
 372                  unsigned long priv, gfp_t gfp)
 373 {
 374         struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
 375                                 sizeof(__le64 *) * nvme_npages(bytes, dev) +
 376                                 sizeof(struct scatterlist) * nseg, gfp);
 377
 378         if (iod)
 379                 iod_init(iod, bytes, nseg, priv);
 380
 381         return iod;
 382 }
 383
 384 static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
 385                                        gfp_t gfp)
 386 {
 387         unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
 388                                                 sizeof(struct nvme_dsm_range);
 389         struct nvme_iod *iod;
 390
 391         if (rq->nr_phys_segments <= NVME_INT_PAGES &&
 392             size <= NVME_INT_BYTES(dev)) {
 393                 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
 394
 395                 iod = &cmd->__iod;
 396                 iod_init(iod, size, rq->nr_phys_segments,
 397                                 (unsigned long) rq | NVME_INT_MASK);
 398                 return iod;
 399         }
 400
 401         return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
 402                                 (unsigned long) rq, gfp);
 403 }
 404
 405 static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
 406 {
 407         const int last_prp = dev->ctrl.page_size / 8 - 1;
 408         int i;
 409         __le64 **list = iod_list(iod);
 410         dma_addr_t prp_dma = iod->first_dma;
 411
 412         if (iod->npages == 0)
 413                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 414         for (i = 0; i < iod->npages; i++) {
 415                 __le64 *prp_list = list[i];
 416                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 417                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 418                 prp_dma = next_prp_dma;
 419         }
 420
 421         if (iod_should_kfree(iod))
 422                 kfree(iod);
 423 }
 424
 425 #ifdef CONFIG_BLK_DEV_INTEGRITY
 426 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 427 {
 428         if (be32_to_cpu(pi->ref_tag) == v)
 429                 pi->ref_tag = cpu_to_be32(p);
 430 }
 431
 432 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 433 {
 434         if (be32_to_cpu(pi->ref_tag) == p)
 435                 pi->ref_tag = cpu_to_be32(v);
 436 }
 437
 438 /**
 439  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 440  *
 441  * The virtual start sector is the one that was originally submitted by the
 442  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 443  * start sector may be different. Remap protection information to match the
 444  * physical LBA on writes, and back to the original seed on reads.
 445  *
 446  * Type 0 and 3 do not have a ref tag, so no remapping required.
 447  */
 448 static void nvme_dif_remap(struct request *req,
 449                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 450 {
 451         struct nvme_ns *ns = req->rq_disk->private_data;
 452         struct bio_integrity_payload *bip;
 453         struct t10_pi_tuple *pi;
 454         void *p, *pmap;
 455         u32 i, nlb, ts, phys, virt;
 456
 457         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 458                 return;
 459
 460         bip = bio_integrity(req->bio);
 461         if (!bip)
 462                 return;
 463
 464         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 465
 466         p = pmap;
 467         virt = bip_get_seed(bip);
 468         phys = nvme_block_nr(ns, blk_rq_pos(req));
 469         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 470         ts = ns->disk->queue->integrity.tuple_size;
 471
 472         for (i = 0; i < nlb; i++, virt++, phys++) {
 473                 pi = (struct t10_pi_tuple *)p;
 474                 dif_swap(phys, virt, pi);
 475                 p += ts;
 476         }
 477         kunmap_atomic(pmap);
 478 }
 479 #else /* CONFIG_BLK_DEV_INTEGRITY */
 480 static void nvme_dif_remap(struct request *req,
 481                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 482 {
 483 }
 484 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 485 {
 486 }
 487 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 488 {
 489 }
 490 #endif
 491
 492 static bool nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod,
 493                 int total_len)
 494 {
 495         struct dma_pool *pool;
 496         int length = total_len;
 497         struct scatterlist *sg = iod->sg;
 498         int dma_len = sg_dma_len(sg);
 499         u64 dma_addr = sg_dma_address(sg);
 500         u32 page_size = dev->ctrl.page_size;
 501         int offset = dma_addr & (page_size - 1);
 502         __le64 *prp_list;
 503         __le64 **list = iod_list(iod);
 504         dma_addr_t prp_dma;
 505         int nprps, i;
 506
 507         length -= (page_size - offset);
 508         if (length <= 0)
 509                 return true;
 510
 511         dma_len -= (page_size - offset);
 512         if (dma_len) {
 513                 dma_addr += (page_size - offset);
 514         } else {
 515                 sg = sg_next(sg);
 516                 dma_addr = sg_dma_address(sg);
 517                 dma_len = sg_dma_len(sg);
 518         }
 519
 520         if (length <= page_size) {
 521                 iod->first_dma = dma_addr;
 522                 return true;
 523         }
 524
 525         nprps = DIV_ROUND_UP(length, page_size);
 526         if (nprps <= (256 / 8)) {
 527                 pool = dev->prp_small_pool;
 528                 iod->npages = 0;
 529         } else {
 530                 pool = dev->prp_page_pool;
 531                 iod->npages = 1;
 532         }
 533
 534         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 535         if (!prp_list) {
 536                 iod->first_dma = dma_addr;
 537                 iod->npages = -1;
 538                 return false;
 539         }
 540         list[0] = prp_list;
 541         iod->first_dma = prp_dma;
 542         i = 0;
 543         for (;;) {
 544                 if (i == page_size >> 3) {
 545                         __le64 *old_prp_list = prp_list;
 546                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 547                         if (!prp_list)
 548                                 return false;
 549                         list[iod->npages++] = prp_list;
 550                         prp_list[0] = old_prp_list[i - 1];
 551                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 552                         i = 1;
 553                 }
 554                 prp_list[i++] = cpu_to_le64(dma_addr);
 555                 dma_len -= page_size;
 556                 dma_addr += page_size;
 557                 length -= page_size;
 558                 if (length <= 0)
 559                         break;
 560                 if (dma_len > 0)
 561                         continue;
 562                 BUG_ON(dma_len < 0);
 563                 sg = sg_next(sg);
 564                 dma_addr = sg_dma_address(sg);
 565                 dma_len = sg_dma_len(sg);
 566         }
 567
 568         return true;
 569 }
 570
 571 static int nvme_map_data(struct nvme_dev *dev, struct nvme_iod *iod,
 572                 struct nvme_command *cmnd)
 573 {
 574         struct request *req = iod_get_private(iod);
 575         struct request_queue *q = req->q;
 576         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 577                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 578         int ret = BLK_MQ_RQ_QUEUE_ERROR;
 579
 580         sg_init_table(iod->sg, req->nr_phys_segments);
 581         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 582         if (!iod->nents)
 583                 goto out;
 584
 585         ret = BLK_MQ_RQ_QUEUE_BUSY;
 586         if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir))
 587                 goto out;
 588
 589         if (!nvme_setup_prps(dev, iod, blk_rq_bytes(req)))
 590                 goto out_unmap;
 591
 592         ret = BLK_MQ_RQ_QUEUE_ERROR;
 593         if (blk_integrity_rq(req)) {
 594                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 595                         goto out_unmap;
 596
 597                 sg_init_table(&iod->meta_sg, 1);
 598                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 599                         goto out_unmap;
 600
 601                 if (rq_data_dir(req))
 602                         nvme_dif_remap(req, nvme_dif_prep);
 603
 604                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 605                         goto out_unmap;
 606         }
 607
 608         cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 609         cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
 610         if (blk_integrity_rq(req))
 611                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 612         return BLK_MQ_RQ_QUEUE_OK;
 613
 614 out_unmap:
 615         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 616 out:
 617         return ret;
 618 }
 619
 620 static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod)
 621 {
 622         struct request *req = iod_get_private(iod);
 623         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 624                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 625
 626         if (iod->nents) {
 627                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 628                 if (blk_integrity_rq(req)) {
 629                         if (!rq_data_dir(req))
 630                                 nvme_dif_remap(req, nvme_dif_complete);
 631                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 632                 }
 633         }
 634
 635         nvme_free_iod(dev, iod);
 636 }
 637
 638 /*
 639  * We reuse the small pool to allocate the 16-byte range here as it is not
 640  * worth having a special pool for these or additional cases to handle freeing
 641  * the iod.
 642  */
 643 static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 644                 struct nvme_iod *iod, struct nvme_command *cmnd)
 645 {
 646         struct request *req = iod_get_private(iod);
 647         struct nvme_dsm_range *range;
 648
 649         range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC,
 650                                                 &iod->first_dma);
 651         if (!range)
 652                 return BLK_MQ_RQ_QUEUE_BUSY;
 653         iod_list(iod)[0] = (__le64 *)range;
 654         iod->npages = 0;
 655
 656         range->cattr = cpu_to_le32(0);
 657         range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
 658         range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
 659
 660         memset(cmnd, 0, sizeof(*cmnd));
 661         cmnd->dsm.opcode = nvme_cmd_dsm;
 662         cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
 663         cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
 664         cmnd->dsm.nr = 0;
 665         cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
 666         return BLK_MQ_RQ_QUEUE_OK;
 667 }
 668
 669 /*
 670  * NOTE: ns is NULL when called on the admin queue.
 671  */
 672 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 673                          const struct blk_mq_queue_data *bd)
 674 {
 675         struct nvme_ns *ns = hctx->queue->queuedata;
 676         struct nvme_queue *nvmeq = hctx->driver_data;
 677         struct nvme_dev *dev = nvmeq->dev;
 678         struct request *req = bd->rq;
 679         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
 680         struct nvme_iod *iod;
 681         struct nvme_command cmnd;
 682         int ret = BLK_MQ_RQ_QUEUE_OK;
 683
 684         /*
 685          * If formated with metadata, require the block layer provide a buffer
 686          * unless this namespace is formated such that the metadata can be
 687          * stripped/generated by the controller with PRACT=1.
 688          */
 689         if (ns && ns->ms && !blk_integrity_rq(req)) {
 690                 if (!(ns->pi_type && ns->ms == 8) &&
 691                                         req->cmd_type != REQ_TYPE_DRV_PRIV) {
 692                         blk_mq_end_request(req, -EFAULT);
 693                         return BLK_MQ_RQ_QUEUE_OK;
 694                 }
 695         }
 696
 697         iod = nvme_alloc_iod(req, dev, GFP_ATOMIC);
 698         if (!iod)
 699                 return BLK_MQ_RQ_QUEUE_BUSY;
 700
 701         if (req->cmd_flags & REQ_DISCARD) {
 702                 ret = nvme_setup_discard(nvmeq, ns, iod, &cmnd);
 703         } else {
 704                 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
 705                         memcpy(&cmnd, req->cmd, sizeof(cmnd));
 706                 else if (req->cmd_flags & REQ_FLUSH)
 707                         nvme_setup_flush(ns, &cmnd);
 708                 else
 709                         nvme_setup_rw(ns, req, &cmnd);
 710
 711                 if (req->nr_phys_segments)
 712                         ret = nvme_map_data(dev, iod, &cmnd);
 713         }
 714
 715         if (ret)
 716                 goto out;
 717
 718         cmd->iod = iod;
 719         cmd->aborted = 0;
 720         cmnd.common.command_id = req->tag;
 721         blk_mq_start_request(req);
 722
 723         spin_lock_irq(&nvmeq->q_lock);
 724         __nvme_submit_cmd(nvmeq, &cmnd);
 725         nvme_process_cq(nvmeq);
 726         spin_unlock_irq(&nvmeq->q_lock);
 727         return BLK_MQ_RQ_QUEUE_OK;
 728 out:
 729         nvme_free_iod(dev, iod);
 730         return ret;
 731 }
 732
 733 static void nvme_complete_rq(struct request *req)
 734 {
 735         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
 736         struct nvme_dev *dev = cmd->nvmeq->dev;
 737         int error = 0;
 738
 739         nvme_unmap_data(dev, cmd->iod);
 740
 741         if (unlikely(req->errors)) {
 742                 if (nvme_req_needs_retry(req, req->errors)) {
 743                         nvme_requeue_req(req);
 744                         return;
 745                 }
 746
 747                 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
 748                         error = req->errors;
 749                 else
 750                         error = nvme_error_status(req->errors);
 751         }
 752
 753         if (unlikely(cmd->aborted)) {
 754                 dev_warn(dev->dev,
 755                         "completing aborted command with status: %04x\n",
 756                         req->errors);
 757         }
 758
 759         blk_mq_end_request(req, error);
 760 }
 761
 762 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
 763 {
 764         u16 head, phase;
 765
 766         head = nvmeq->cq_head;
 767         phase = nvmeq->cq_phase;
 768
 769         for (;;) {
 770                 struct nvme_completion cqe = nvmeq->cqes[head];
 771                 u16 status = le16_to_cpu(cqe.status);
 772                 struct request *req;
 773
 774                 if ((status & 1) != phase)
 775                         break;
 776                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 777                 if (++head == nvmeq->q_depth) {
 778                         head = 0;
 779                         phase = !phase;
 780                 }
 781
 782                 if (tag && *tag == cqe.command_id)
 783                         *tag = -1;
 784
 785                 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
 786                         dev_warn(nvmeq->q_dmadev,
 787                                 "invalid id %d completed on queue %d\n",
 788                                 cqe.command_id, le16_to_cpu(cqe.sq_id));
 789                         continue;
 790                 }
 791
 792                 /*
 793                  * AEN requests are special as they don't time out and can
 794                  * survive any kind of queue freeze and often don't respond to
 795                  * aborts.  We don't even bother to allocate a struct request
 796                  * for them but rather special case them here.
 797                  */
 798                 if (unlikely(nvmeq->qid == 0 &&
 799                                 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
 800                         nvme_complete_async_event(nvmeq->dev, &cqe);
 801                         continue;
 802                 }
 803
 804                 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
 805                 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
 806                         u32 result = le32_to_cpu(cqe.result);
 807                         req->special = (void *)(uintptr_t)result;
 808                 }
 809                 blk_mq_complete_request(req, status >> 1);
 810
 811         }
 812
 813         /* If the controller ignores the cq head doorbell and continuously
 814          * writes to the queue, it is theoretically possible to wrap around
 815          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 816          * requires that 0.1% of your interrupts are handled, so this isn't
 817          * a big problem.
 818          */
 819         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 820                 return;
 821
 822         if (likely(nvmeq->cq_vector >= 0))
 823                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 824         nvmeq->cq_head = head;
 825         nvmeq->cq_phase = phase;
 826
 827         nvmeq->cqe_seen = 1;
 828 }
 829
 830 static void nvme_process_cq(struct nvme_queue *nvmeq)
 831 {
 832         __nvme_process_cq(nvmeq, NULL);
 833 }
 834
 835 static irqreturn_t nvme_irq(int irq, void *data)
 836 {
 837         irqreturn_t result;
 838         struct nvme_queue *nvmeq = data;
 839         spin_lock(&nvmeq->q_lock);
 840         nvme_process_cq(nvmeq);
 841         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 842         nvmeq->cqe_seen = 0;
 843         spin_unlock(&nvmeq->q_lock);
 844         return result;
 845 }
 846
 847 static irqreturn_t nvme_irq_check(int irq, void *data)
 848 {
 849         struct nvme_queue *nvmeq = data;
 850         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 851         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 852                 return IRQ_NONE;
 853         return IRQ_WAKE_THREAD;
 854 }
 855
 856 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
 857 {
 858         struct nvme_queue *nvmeq = hctx->driver_data;
 859
 860         if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
 861             nvmeq->cq_phase) {
 862                 spin_lock_irq(&nvmeq->q_lock);
 863                 __nvme_process_cq(nvmeq, &tag);
 864                 spin_unlock_irq(&nvmeq->q_lock);
 865
 866                 if (tag == -1)
 867                         return 1;
 868         }
 869
 870         return 0;
 871 }
 872
 873 static void nvme_submit_async_event(struct nvme_dev *dev)
 874 {
 875         struct nvme_command c;
 876
 877         memset(&c, 0, sizeof(c));
 878         c.common.opcode = nvme_admin_async_event;
 879         c.common.command_id = NVME_AQ_BLKMQ_DEPTH + --dev->ctrl.event_limit;
 880
 881         __nvme_submit_cmd(dev->queues[0], &c);
 882 }
 883
 884 static void async_cmd_info_endio(struct request *req, int error)
 885 {
 886         struct async_cmd_info *cmdinfo = req->end_io_data;
 887
 888         cmdinfo->status = req->errors;
 889         queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
 890         blk_mq_free_request(req);
 891 }
 892
 893 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 894 {
 895         struct nvme_command c;
 896
 897         memset(&c, 0, sizeof(c));
 898         c.delete_queue.opcode = opcode;
 899         c.delete_queue.qid = cpu_to_le16(id);
 900
 901         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 902 }
 903
 904 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 905                                                 struct nvme_queue *nvmeq)
 906 {
 907         struct nvme_command c;
 908         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 909
 910         /*
 911          * Note: we (ab)use the fact the the prp fields survive if no data
 912          * is attached to the request.
 913          */
 914         memset(&c, 0, sizeof(c));
 915         c.create_cq.opcode = nvme_admin_create_cq;
 916         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 917         c.create_cq.cqid = cpu_to_le16(qid);
 918         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 919         c.create_cq.cq_flags = cpu_to_le16(flags);
 920         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 921
 922         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 923 }
 924
 925 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 926                                                 struct nvme_queue *nvmeq)
 927 {
 928         struct nvme_command c;
 929         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 930
 931         /*
 932          * Note: we (ab)use the fact the the prp fields survive if no data
 933          * is attached to the request.
 934          */
 935         memset(&c, 0, sizeof(c));
 936         c.create_sq.opcode = nvme_admin_create_sq;
 937         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 938         c.create_sq.sqid = cpu_to_le16(qid);
 939         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 940         c.create_sq.sq_flags = cpu_to_le16(flags);
 941         c.create_sq.cqid = cpu_to_le16(qid);
 942
 943         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 944 }
 945
 946 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 947 {
 948         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 949 }
 950
 951 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 952 {
 953         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 954 }
 955
 956 static void abort_endio(struct request *req, int error)
 957 {
 958         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
 959         struct nvme_queue *nvmeq = cmd->nvmeq;
 960         u32 result = (u32)(uintptr_t)req->special;
 961         u16 status = req->errors;
 962
 963         dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
 964         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
 965
 966         blk_mq_free_request(req);
 967 }
 968
 969 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
 970 {
 971         struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
 972         struct nvme_queue *nvmeq = cmd_rq->nvmeq;
 973         struct nvme_dev *dev = nvmeq->dev;
 974         struct request *abort_req;
 975         struct nvme_command cmd;
 976
 977         /*
 978          * Shutdown immediately if controller times out while starting. The
 979          * reset work will see the pci device disabled when it gets the forced
 980          * cancellation error. All outstanding requests are completed on
 981          * shutdown, so we return BLK_EH_HANDLED.
 982          */
 983         if (test_bit(NVME_CTRL_RESETTING, &dev->flags)) {
 984                 dev_warn(dev->dev,
 985                          "I/O %d QID %d timeout, disable controller\n",
 986                          req->tag, nvmeq->qid);
 987                 nvme_dev_shutdown(dev);
 988                 req->errors = NVME_SC_CANCELLED;
 989                 return BLK_EH_HANDLED;
 990         }
 991
 992         /*
 993          * Shutdown the controller immediately and schedule a reset if the
 994          * command was already aborted once before and still hasn't been
 995          * returned to the driver, or if this is the admin queue.
 996          */
 997         if (!nvmeq->qid || cmd_rq->aborted) {
 998                 dev_warn(dev->dev,
 999                          "I/O %d QID %d timeout, reset controller\n",
1000                          req->tag, nvmeq->qid);
1001                 nvme_dev_shutdown(dev);
1002                 queue_work(nvme_workq, &dev->reset_work);
1003
1004                 /*
1005                  * Mark the request as handled, since the inline shutdown
1006                  * forces all outstanding requests to complete.
1007                  */
1008                 req->errors = NVME_SC_CANCELLED;
1009                 return BLK_EH_HANDLED;
1010         }
1011
1012         cmd_rq->aborted = 1;
1013
1014         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1015                 atomic_inc(&dev->ctrl.abort_limit);
1016                 return BLK_EH_RESET_TIMER;
1017         }
1018
1019         memset(&cmd, 0, sizeof(cmd));
1020         cmd.abort.opcode = nvme_admin_abort_cmd;
1021         cmd.abort.cid = req->tag;
1022         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1023
1024         dev_warn(nvmeq->q_dmadev, "I/O %d QID %d timeout, aborting\n",
1025                                  req->tag, nvmeq->qid);
1026
1027         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1028                         BLK_MQ_REQ_NOWAIT);
1029         if (IS_ERR(abort_req)) {
1030                 atomic_inc(&dev->ctrl.abort_limit);
1031                 return BLK_EH_RESET_TIMER;
1032         }
1033
1034         abort_req->timeout = ADMIN_TIMEOUT;
1035         abort_req->end_io_data = NULL;
1036         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1037
1038         /*
1039          * The aborted req will be completed on receiving the abort req.
1040          * We enable the timer again. If hit twice, it'll cause a device reset,
1041          * as the device then is in a faulty state.
1042          */
1043         return BLK_EH_RESET_TIMER;
1044 }
1045
1046 static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
1047 {
1048         struct nvme_queue *nvmeq = data;
1049         int status;
1050
1051         if (!blk_mq_request_started(req))
1052                 return;
1053
1054         dev_warn(nvmeq->q_dmadev,
1055                  "Cancelling I/O %d QID %d\n", req->tag, nvmeq->qid);
1056
1057         status = NVME_SC_CANCELLED;
1058         if (blk_queue_dying(req->q))
1059                 status |= NVME_SC_DNR;
1060         blk_mq_complete_request(req, status);
1061 }
1062
1063 static void nvme_free_queue(struct nvme_queue *nvmeq)
1064 {
1065         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1066                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1067         if (nvmeq->sq_cmds)
1068                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1069                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1070         kfree(nvmeq);
1071 }
1072
1073 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1074 {
1075         int i;
1076
1077         for (i = dev->queue_count - 1; i >= lowest; i--) {
1078                 struct nvme_queue *nvmeq = dev->queues[i];
1079                 dev->queue_count--;
1080                 dev->queues[i] = NULL;
1081                 nvme_free_queue(nvmeq);
1082         }
1083 }
1084
1085 /**
1086  * nvme_suspend_queue - put queue into suspended state
1087  * @nvmeq - queue to suspend
1088  */
1089 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1090 {
1091         int vector;
1092
1093         spin_lock_irq(&nvmeq->q_lock);
1094         if (nvmeq->cq_vector == -1) {
1095                 spin_unlock_irq(&nvmeq->q_lock);
1096                 return 1;
1097         }
1098         vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1099         nvmeq->dev->online_queues--;
1100         nvmeq->cq_vector = -1;
1101         spin_unlock_irq(&nvmeq->q_lock);
1102
1103         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1104                 blk_mq_freeze_queue_start(nvmeq->dev->ctrl.admin_q);
1105
1106         irq_set_affinity_hint(vector, NULL);
1107         free_irq(vector, nvmeq);
1108
1109         return 0;
1110 }
1111
1112 static void nvme_clear_queue(struct nvme_queue *nvmeq)
1113 {
1114         spin_lock_irq(&nvmeq->q_lock);
1115         if (nvmeq->tags && *nvmeq->tags)
1116                 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
1117         spin_unlock_irq(&nvmeq->q_lock);
1118 }
1119
1120 static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1121 {
1122         struct nvme_queue *nvmeq = dev->queues[qid];
1123
1124         if (!nvmeq)
1125                 return;
1126         if (nvme_suspend_queue(nvmeq))
1127                 return;
1128
1129         /* Don't tell the adapter to delete the admin queue.
1130          * Don't tell a removed adapter to delete IO queues. */
1131         if (qid && readl(dev->bar + NVME_REG_CSTS) != -1) {
1132                 adapter_delete_sq(dev, qid);
1133                 adapter_delete_cq(dev, qid);
1134         }
1135
1136         spin_lock_irq(&nvmeq->q_lock);
1137         nvme_process_cq(nvmeq);
1138         spin_unlock_irq(&nvmeq->q_lock);
1139 }
1140
1141 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1142                                 int entry_size)
1143 {
1144         int q_depth = dev->q_depth;
1145         unsigned q_size_aligned = roundup(q_depth * entry_size,
1146                                           dev->ctrl.page_size);
1147
1148         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1149                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1150                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1151                 q_depth = div_u64(mem_per_q, entry_size);
1152
1153                 /*
1154                  * Ensure the reduced q_depth is above some threshold where it
1155                  * would be better to map queues in system memory with the
1156                  * original depth
1157                  */
1158                 if (q_depth < 64)
1159                         return -ENOMEM;
1160         }
1161
1162         return q_depth;
1163 }
1164
1165 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1166                                 int qid, int depth)
1167 {
1168         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1169                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1170                                                       dev->ctrl.page_size);
1171                 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1172                 nvmeq->sq_cmds_io = dev->cmb + offset;
1173         } else {
1174                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1175                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1176                 if (!nvmeq->sq_cmds)
1177                         return -ENOMEM;
1178         }
1179
1180         return 0;
1181 }
1182
1183 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1184                                                         int depth)
1185 {
1186         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1187         if (!nvmeq)
1188                 return NULL;
1189
1190         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1191                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1192         if (!nvmeq->cqes)
1193                 goto free_nvmeq;
1194
1195         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1196                 goto free_cqdma;
1197
1198         nvmeq->q_dmadev = dev->dev;
1199         nvmeq->dev = dev;
1200         snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1201                         dev->ctrl.instance, qid);
1202         spin_lock_init(&nvmeq->q_lock);
1203         nvmeq->cq_head = 0;
1204         nvmeq->cq_phase = 1;
1205         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1206         nvmeq->q_depth = depth;
1207         nvmeq->qid = qid;
1208         nvmeq->cq_vector = -1;
1209         dev->queues[qid] = nvmeq;
1210
1211         /* make sure queue descriptor is set before queue count, for kthread */
1212         mb();
1213         dev->queue_count++;
1214
1215         return nvmeq;
1216
1217  free_cqdma:
1218         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1219                                                         nvmeq->cq_dma_addr);
1220  free_nvmeq:
1221         kfree(nvmeq);
1222         return NULL;
1223 }
1224
1225 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1226                                                         const char *name)
1227 {
1228         if (use_threaded_interrupts)
1229                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1230                                         nvme_irq_check, nvme_irq, IRQF_SHARED,
1231                                         name, nvmeq);
1232         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1233                                 IRQF_SHARED, name, nvmeq);
1234 }
1235
1236 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1237 {
1238         struct nvme_dev *dev = nvmeq->dev;
1239
1240         spin_lock_irq(&nvmeq->q_lock);
1241         nvmeq->sq_tail = 0;
1242         nvmeq->cq_head = 0;
1243         nvmeq->cq_phase = 1;
1244         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1245         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1246         dev->online_queues++;
1247         spin_unlock_irq(&nvmeq->q_lock);
1248 }
1249
1250 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1251 {
1252         struct nvme_dev *dev = nvmeq->dev;
1253         int result;
1254
1255         nvmeq->cq_vector = qid - 1;
1256         result = adapter_alloc_cq(dev, qid, nvmeq);
1257         if (result < 0)
1258                 return result;
1259
1260         result = adapter_alloc_sq(dev, qid, nvmeq);
1261         if (result < 0)
1262                 goto release_cq;
1263
1264         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1265         if (result < 0)
1266                 goto release_sq;
1267
1268         nvme_init_queue(nvmeq, qid);
1269         return result;
1270
1271  release_sq:
1272         adapter_delete_sq(dev, qid);
1273  release_cq:
1274         adapter_delete_cq(dev, qid);
1275         return result;
1276 }
1277
1278 static struct blk_mq_ops nvme_mq_admin_ops = {
1279         .queue_rq       = nvme_queue_rq,
1280         .complete       = nvme_complete_rq,
1281         .map_queue      = blk_mq_map_queue,
1282         .init_hctx      = nvme_admin_init_hctx,
1283         .exit_hctx      = nvme_admin_exit_hctx,
1284         .init_request   = nvme_admin_init_request,
1285         .timeout        = nvme_timeout,
1286 };
1287
1288 static struct blk_mq_ops nvme_mq_ops = {
1289         .queue_rq       = nvme_queue_rq,
1290         .complete       = nvme_complete_rq,
1291         .map_queue      = blk_mq_map_queue,
1292         .init_hctx      = nvme_init_hctx,
1293         .init_request   = nvme_init_request,
1294         .timeout        = nvme_timeout,
1295         .poll           = nvme_poll,
1296 };
1297
1298 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1299 {
1300         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1301                 blk_cleanup_queue(dev->ctrl.admin_q);
1302                 blk_mq_free_tag_set(&dev->admin_tagset);
1303         }
1304 }
1305
1306 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1307 {
1308         if (!dev->ctrl.admin_q) {
1309                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1310                 dev->admin_tagset.nr_hw_queues = 1;
1311                 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH;
1312                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1313                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1314                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1315                 dev->admin_tagset.driver_data = dev;
1316
1317                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1318                         return -ENOMEM;
1319
1320                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1321                 if (IS_ERR(dev->ctrl.admin_q)) {
1322                         blk_mq_free_tag_set(&dev->admin_tagset);
1323                         return -ENOMEM;
1324                 }
1325                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1326                         nvme_dev_remove_admin(dev);
1327                         dev->ctrl.admin_q = NULL;
1328                         return -ENODEV;
1329                 }
1330         } else
1331                 blk_mq_unfreeze_queue(dev->ctrl.admin_q);
1332
1333         return 0;
1334 }
1335
1336 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1337 {
1338         int result;
1339         u32 aqa;
1340         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1341         struct nvme_queue *nvmeq;
1342
1343         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ?
1344                                                 NVME_CAP_NSSRC(cap) : 0;
1345
1346         if (dev->subsystem &&
1347             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1348                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1349
1350         result = nvme_disable_ctrl(&dev->ctrl, cap);
1351         if (result < 0)
1352                 return result;
1353
1354         nvmeq = dev->queues[0];
1355         if (!nvmeq) {
1356                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1357                 if (!nvmeq)
1358                         return -ENOMEM;
1359         }
1360
1361         aqa = nvmeq->q_depth - 1;
1362         aqa |= aqa << 16;
1363
1364         writel(aqa, dev->bar + NVME_REG_AQA);
1365         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1366         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1367
1368         result = nvme_enable_ctrl(&dev->ctrl, cap);
1369         if (result)
1370                 goto free_nvmeq;
1371
1372         nvmeq->cq_vector = 0;
1373         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1374         if (result) {
1375                 nvmeq->cq_vector = -1;
1376                 goto free_nvmeq;
1377         }
1378
1379         return result;
1380
1381  free_nvmeq:
1382         nvme_free_queues(dev, 0);
1383         return result;
1384 }
1385
1386 static int nvme_kthread(void *data)
1387 {
1388         struct nvme_dev *dev, *next;
1389
1390         while (!kthread_should_stop()) {
1391                 set_current_state(TASK_INTERRUPTIBLE);
1392                 spin_lock(&dev_list_lock);
1393                 list_for_each_entry_safe(dev, next, &dev_list, node) {
1394                         int i;
1395                         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1396
1397                         /*
1398                          * Skip controllers currently under reset.
1399                          */
1400                         if (work_pending(&dev->reset_work) || work_busy(&dev->reset_work))
1401                                 continue;
1402
1403                         if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) ||
1404                                                         csts & NVME_CSTS_CFS) {
1405                                 if (queue_work(nvme_workq, &dev->reset_work)) {
1406                                         dev_warn(dev->dev,
1407                                                 "Failed status: %x, reset controller\n",
1408                                                 readl(dev->bar + NVME_REG_CSTS));
1409                                 }
1410                                 continue;
1411                         }
1412                         for (i = 0; i < dev->queue_count; i++) {
1413                                 struct nvme_queue *nvmeq = dev->queues[i];
1414                                 if (!nvmeq)
1415                                         continue;
1416                                 spin_lock_irq(&nvmeq->q_lock);
1417                                 nvme_process_cq(nvmeq);
1418
1419                                 while (i == 0 && dev->ctrl.event_limit > 0)
1420                                         nvme_submit_async_event(dev);
1421                                 spin_unlock_irq(&nvmeq->q_lock);
1422                         }
1423                 }
1424                 spin_unlock(&dev_list_lock);
1425                 schedule_timeout(round_jiffies_relative(HZ));
1426         }
1427         return 0;
1428 }
1429
1430 static int nvme_create_io_queues(struct nvme_dev *dev)
1431 {
1432         unsigned i;
1433         int ret = 0;
1434
1435         for (i = dev->queue_count; i <= dev->max_qid; i++) {
1436                 if (!nvme_alloc_queue(dev, i, dev->q_depth)) {
1437                         ret = -ENOMEM;
1438                         break;
1439                 }
1440         }
1441
1442         for (i = dev->online_queues; i <= dev->queue_count - 1; i++) {
1443                 ret = nvme_create_queue(dev->queues[i], i);
1444                 if (ret) {
1445                         nvme_free_queues(dev, i);
1446                         break;
1447                 }
1448         }
1449
1450         /*
1451          * Ignore failing Create SQ/CQ commands, we can continue with less
1452          * than the desired aount of queues, and even a controller without
1453          * I/O queues an still be used to issue admin commands.  This might
1454          * be useful to upgrade a buggy firmware for example.
1455          */
1456         return ret >= 0 ? 0 : ret;
1457 }
1458
1459 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1460 {
1461         u64 szu, size, offset;
1462         u32 cmbloc;
1463         resource_size_t bar_size;
1464         struct pci_dev *pdev = to_pci_dev(dev->dev);
1465         void __iomem *cmb;
1466         dma_addr_t dma_addr;
1467
1468         if (!use_cmb_sqes)
1469                 return NULL;
1470
1471         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1472         if (!(NVME_CMB_SZ(dev->cmbsz)))
1473                 return NULL;
1474
1475         cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1476
1477         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1478         size = szu * NVME_CMB_SZ(dev->cmbsz);
1479         offset = szu * NVME_CMB_OFST(cmbloc);
1480         bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
1481
1482         if (offset > bar_size)
1483                 return NULL;
1484
1485         /*
1486          * Controllers may support a CMB size larger than their BAR,
1487          * for example, due to being behind a bridge. Reduce the CMB to
1488          * the reported size of the BAR
1489          */
1490         if (size > bar_size - offset)
1491                 size = bar_size - offset;
1492
1493         dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
1494         cmb = ioremap_wc(dma_addr, size);
1495         if (!cmb)
1496                 return NULL;
1497
1498         dev->cmb_dma_addr = dma_addr;
1499         dev->cmb_size = size;
1500         return cmb;
1501 }
1502
1503 static inline void nvme_release_cmb(struct nvme_dev *dev)
1504 {
1505         if (dev->cmb) {
1506                 iounmap(dev->cmb);
1507                 dev->cmb = NULL;
1508         }
1509 }
1510
1511 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1512 {
1513         return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1514 }
1515
1516 static int nvme_setup_io_queues(struct nvme_dev *dev)
1517 {
1518         struct nvme_queue *adminq = dev->queues[0];
1519         struct pci_dev *pdev = to_pci_dev(dev->dev);
1520         int result, i, vecs, nr_io_queues, size;
1521
1522         nr_io_queues = num_possible_cpus();
1523         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1524         if (result < 0)
1525                 return result;
1526
1527         /*
1528          * Degraded controllers might return an error when setting the queue
1529          * count.  We still want to be able to bring them online and offer
1530          * access to the admin queue, as that might be only way to fix them up.
1531          */
1532         if (result > 0) {
1533                 dev_err(dev->dev, "Could not set queue count (%d)\n", result);
1534                 nr_io_queues = 0;
1535                 result = 0;
1536         }
1537
1538         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1539                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1540                                 sizeof(struct nvme_command));
1541                 if (result > 0)
1542                         dev->q_depth = result;
1543                 else
1544                         nvme_release_cmb(dev);
1545         }
1546
1547         size = db_bar_size(dev, nr_io_queues);
1548         if (size > 8192) {
1549                 iounmap(dev->bar);
1550                 do {
1551                         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1552                         if (dev->bar)
1553                                 break;
1554                         if (!--nr_io_queues)
1555                                 return -ENOMEM;
1556                         size = db_bar_size(dev, nr_io_queues);
1557                 } while (1);
1558                 dev->dbs = dev->bar + 4096;
1559                 adminq->q_db = dev->dbs;
1560         }
1561
1562         /* Deregister the admin queue's interrupt */
1563         free_irq(dev->entry[0].vector, adminq);
1564
1565         /*
1566          * If we enable msix early due to not intx, disable it again before
1567          * setting up the full range we need.
1568          */
1569         if (!pdev->irq)
1570                 pci_disable_msix(pdev);
1571
1572         for (i = 0; i < nr_io_queues; i++)
1573                 dev->entry[i].entry = i;
1574         vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
1575         if (vecs < 0) {
1576                 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
1577                 if (vecs < 0) {
1578                         vecs = 1;
1579                 } else {
1580                         for (i = 0; i < vecs; i++)
1581                                 dev->entry[i].vector = i + pdev->irq;
1582                 }
1583         }
1584
1585         /*
1586          * Should investigate if there's a performance win from allocating
1587          * more queues than interrupt vectors; it might allow the submission
1588          * path to scale better, even if the receive path is limited by the
1589          * number of interrupts.
1590          */
1591         nr_io_queues = vecs;
1592         dev->max_qid = nr_io_queues;
1593
1594         result = queue_request_irq(dev, adminq, adminq->irqname);
1595         if (result) {
1596                 adminq->cq_vector = -1;
1597                 goto free_queues;
1598         }
1599
1600         /* Free previously allocated queues that are no longer usable */
1601         nvme_free_queues(dev, nr_io_queues + 1);
1602         return nvme_create_io_queues(dev);
1603
1604  free_queues:
1605         nvme_free_queues(dev, 1);
1606         return result;
1607 }
1608
1609 static void nvme_set_irq_hints(struct nvme_dev *dev)
1610 {
1611         struct nvme_queue *nvmeq;
1612         int i;
1613
1614         for (i = 0; i < dev->online_queues; i++) {
1615                 nvmeq = dev->queues[i];
1616
1617                 if (!nvmeq->tags || !(*nvmeq->tags))
1618                         continue;
1619
1620                 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
1621                                         blk_mq_tags_cpumask(*nvmeq->tags));
1622         }
1623 }
1624
1625 static void nvme_dev_scan(struct work_struct *work)
1626 {
1627         struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
1628
1629         if (!dev->tagset.tags)
1630                 return;
1631         nvme_scan_namespaces(&dev->ctrl);
1632         nvme_set_irq_hints(dev);
1633 }
1634
1635 /*
1636  * Return: error value if an error occurred setting up the queues or calling
1637  * Identify Device.  0 if these succeeded, even if adding some of the
1638  * namespaces failed.  At the moment, these failures are silent.  TBD which
1639  * failures should be reported.
1640  */
1641 static int nvme_dev_add(struct nvme_dev *dev)
1642 {
1643         if (!dev->ctrl.tagset) {
1644                 dev->tagset.ops = &nvme_mq_ops;
1645                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1646                 dev->tagset.timeout = NVME_IO_TIMEOUT;
1647                 dev->tagset.numa_node = dev_to_node(dev->dev);
1648                 dev->tagset.queue_depth =
1649                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1650                 dev->tagset.cmd_size = nvme_cmd_size(dev);
1651                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1652                 dev->tagset.driver_data = dev;
1653
1654                 if (blk_mq_alloc_tag_set(&dev->tagset))
1655                         return 0;
1656                 dev->ctrl.tagset = &dev->tagset;
1657         }
1658         queue_work(nvme_workq, &dev->scan_work);
1659         return 0;
1660 }
1661
1662 static int nvme_dev_map(struct nvme_dev *dev)
1663 {
1664         u64 cap;
1665         int bars, result = -ENOMEM;
1666         struct pci_dev *pdev = to_pci_dev(dev->dev);
1667
1668         if (pci_enable_device_mem(pdev))
1669                 return result;
1670
1671         dev->entry[0].vector = pdev->irq;
1672         pci_set_master(pdev);
1673         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1674         if (!bars)
1675                 goto disable_pci;
1676
1677         if (pci_request_selected_regions(pdev, bars, "nvme"))
1678                 goto disable_pci;
1679
1680         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1681             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1682                 goto disable;
1683
1684         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1685         if (!dev->bar)
1686                 goto disable;
1687
1688         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1689                 result = -ENODEV;
1690                 goto unmap;
1691         }
1692
1693         /*
1694          * Some devices don't advertse INTx interrupts, pre-enable a single
1695          * MSIX vec for setup. We'll adjust this later.
1696          */
1697         if (!pdev->irq) {
1698                 result = pci_enable_msix(pdev, dev->entry, 1);
1699                 if (result < 0)
1700                         goto unmap;
1701         }
1702
1703         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1704
1705         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1706         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1707         dev->dbs = dev->bar + 4096;
1708         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2))
1709                 dev->cmb = nvme_map_cmb(dev);
1710
1711         return 0;
1712
1713  unmap:
1714         iounmap(dev->bar);
1715         dev->bar = NULL;
1716  disable:
1717         pci_release_regions(pdev);
1718  disable_pci:
1719         pci_disable_device(pdev);
1720         return result;
1721 }
1722
1723 static void nvme_dev_unmap(struct nvme_dev *dev)
1724 {
1725         struct pci_dev *pdev = to_pci_dev(dev->dev);
1726
1727         if (pdev->msi_enabled)
1728                 pci_disable_msi(pdev);
1729         else if (pdev->msix_enabled)
1730                 pci_disable_msix(pdev);
1731
1732         if (dev->bar) {
1733                 iounmap(dev->bar);
1734                 dev->bar = NULL;
1735                 pci_release_regions(pdev);
1736         }
1737
1738         if (pci_is_enabled(pdev))
1739                 pci_disable_device(pdev);
1740 }
1741
1742 struct nvme_delq_ctx {
1743         struct task_struct *waiter;
1744         struct kthread_worker *worker;
1745         atomic_t refcount;
1746 };
1747
1748 static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
1749 {
1750         dq->waiter = current;
1751         mb();
1752
1753         for (;;) {
1754                 set_current_state(TASK_KILLABLE);
1755                 if (!atomic_read(&dq->refcount))
1756                         break;
1757                 if (!schedule_timeout(ADMIN_TIMEOUT) ||
1758                                         fatal_signal_pending(current)) {
1759                         /*
1760                          * Disable the controller first since we can't trust it
1761                          * at this point, but leave the admin queue enabled
1762                          * until all queue deletion requests are flushed.
1763                          * FIXME: This may take a while if there are more h/w
1764                          * queues than admin tags.
1765                          */
1766                         set_current_state(TASK_RUNNING);
1767                         nvme_disable_ctrl(&dev->ctrl,
1768                                 lo_hi_readq(dev->bar + NVME_REG_CAP));
1769                         nvme_clear_queue(dev->queues[0]);
1770                         flush_kthread_worker(dq->worker);
1771                         nvme_disable_queue(dev, 0);
1772                         return;
1773                 }
1774         }
1775         set_current_state(TASK_RUNNING);
1776 }
1777
1778 static void nvme_put_dq(struct nvme_delq_ctx *dq)
1779 {
1780         atomic_dec(&dq->refcount);
1781         if (dq->waiter)
1782                 wake_up_process(dq->waiter);
1783 }
1784
1785 static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
1786 {
1787         atomic_inc(&dq->refcount);
1788         return dq;
1789 }
1790
1791 static void nvme_del_queue_end(struct nvme_queue *nvmeq)
1792 {
1793         struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
1794         nvme_put_dq(dq);
1795
1796         spin_lock_irq(&nvmeq->q_lock);
1797         nvme_process_cq(nvmeq);
1798         spin_unlock_irq(&nvmeq->q_lock);
1799 }
1800
1801 static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
1802                                                 kthread_work_func_t fn)
1803 {
1804         struct request *req;
1805         struct nvme_command c;
1806
1807         memset(&c, 0, sizeof(c));
1808         c.delete_queue.opcode = opcode;
1809         c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1810
1811         init_kthread_work(&nvmeq->cmdinfo.work, fn);
1812
1813         req = nvme_alloc_request(nvmeq->dev->ctrl.admin_q, &c, 0);
1814         if (IS_ERR(req))
1815                 return PTR_ERR(req);
1816
1817         req->timeout = ADMIN_TIMEOUT;
1818         req->end_io_data = &nvmeq->cmdinfo;
1819         blk_execute_rq_nowait(req->q, NULL, req, 0, async_cmd_info_endio);
1820         return 0;
1821 }
1822
1823 static void nvme_del_cq_work_handler(struct kthread_work *work)
1824 {
1825         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
1826                                                         cmdinfo.work);
1827         nvme_del_queue_end(nvmeq);
1828 }
1829
1830 static int nvme_delete_cq(struct nvme_queue *nvmeq)
1831 {
1832         return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
1833                                                 nvme_del_cq_work_handler);
1834 }
1835
1836 static void nvme_del_sq_work_handler(struct kthread_work *work)
1837 {
1838         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
1839                                                         cmdinfo.work);
1840         int status = nvmeq->cmdinfo.status;
1841
1842         if (!status)
1843                 status = nvme_delete_cq(nvmeq);
1844         if (status)
1845                 nvme_del_queue_end(nvmeq);
1846 }
1847
1848 static int nvme_delete_sq(struct nvme_queue *nvmeq)
1849 {
1850         return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
1851                                                 nvme_del_sq_work_handler);
1852 }
1853
1854 static void nvme_del_queue_start(struct kthread_work *work)
1855 {
1856         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
1857                                                         cmdinfo.work);
1858         if (nvme_delete_sq(nvmeq))
1859                 nvme_del_queue_end(nvmeq);
1860 }
1861
1862 static void nvme_disable_io_queues(struct nvme_dev *dev)
1863 {
1864         int i;
1865         DEFINE_KTHREAD_WORKER_ONSTACK(worker);
1866         struct nvme_delq_ctx dq;
1867         struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
1868                                         &worker, "nvme%d", dev->ctrl.instance);
1869
1870         if (IS_ERR(kworker_task)) {
1871                 dev_err(dev->dev,
1872                         "Failed to create queue del task\n");
1873                 for (i = dev->queue_count - 1; i > 0; i--)
1874                         nvme_disable_queue(dev, i);
1875                 return;
1876         }
1877
1878         dq.waiter = NULL;
1879         atomic_set(&dq.refcount, 0);
1880         dq.worker = &worker;
1881         for (i = dev->queue_count - 1; i > 0; i--) {
1882                 struct nvme_queue *nvmeq = dev->queues[i];
1883
1884                 if (nvme_suspend_queue(nvmeq))
1885                         continue;
1886                 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
1887                 nvmeq->cmdinfo.worker = dq.worker;
1888                 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
1889                 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
1890         }
1891         nvme_wait_dq(&dq, dev);
1892         kthread_stop(kworker_task);
1893 }
1894
1895 static int nvme_dev_list_add(struct nvme_dev *dev)
1896 {
1897         bool start_thread = false;
1898
1899         spin_lock(&dev_list_lock);
1900         if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
1901                 start_thread = true;
1902                 nvme_thread = NULL;
1903         }
1904         list_add(&dev->node, &dev_list);
1905         spin_unlock(&dev_list_lock);
1906
1907         if (start_thread) {
1908                 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1909                 wake_up_all(&nvme_kthread_wait);
1910         } else
1911                 wait_event_killable(nvme_kthread_wait, nvme_thread);
1912
1913         if (IS_ERR_OR_NULL(nvme_thread))
1914                 return nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
1915
1916         return 0;
1917 }
1918
1919 /*
1920 * Remove the node from the device list and check
1921 * for whether or not we need to stop the nvme_thread.
1922 */
1923 static void nvme_dev_list_remove(struct nvme_dev *dev)
1924 {
1925         struct task_struct *tmp = NULL;
1926
1927         spin_lock(&dev_list_lock);
1928         list_del_init(&dev->node);
1929         if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
1930                 tmp = nvme_thread;
1931                 nvme_thread = NULL;
1932         }
1933         spin_unlock(&dev_list_lock);
1934
1935         if (tmp)
1936                 kthread_stop(tmp);
1937 }
1938
1939 static void nvme_freeze_queues(struct nvme_dev *dev)
1940 {
1941         struct nvme_ns *ns;
1942
1943         list_for_each_entry(ns, &dev->ctrl.namespaces, list) {
1944                 blk_mq_freeze_queue_start(ns->queue);
1945
1946                 spin_lock_irq(ns->queue->queue_lock);
1947                 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
1948                 spin_unlock_irq(ns->queue->queue_lock);
1949
1950                 blk_mq_cancel_requeue_work(ns->queue);
1951                 blk_mq_stop_hw_queues(ns->queue);
1952         }
1953 }
1954
1955 static void nvme_unfreeze_queues(struct nvme_dev *dev)
1956 {
1957         struct nvme_ns *ns;
1958
1959         list_for_each_entry(ns, &dev->ctrl.namespaces, list) {
1960                 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
1961                 blk_mq_unfreeze_queue(ns->queue);
1962                 blk_mq_start_stopped_hw_queues(ns->queue, true);
1963                 blk_mq_kick_requeue_list(ns->queue);
1964         }
1965 }
1966
1967 static void nvme_dev_shutdown(struct nvme_dev *dev)
1968 {
1969         int i;
1970         u32 csts = -1;
1971
1972         nvme_dev_list_remove(dev);
1973
1974         mutex_lock(&dev->shutdown_lock);
1975         if (dev->bar) {
1976                 nvme_freeze_queues(dev);
1977                 csts = readl(dev->bar + NVME_REG_CSTS);
1978         }
1979         if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
1980                 for (i = dev->queue_count - 1; i >= 0; i--) {
1981                         struct nvme_queue *nvmeq = dev->queues[i];
1982                         nvme_suspend_queue(nvmeq);
1983                 }
1984         } else {
1985                 nvme_disable_io_queues(dev);
1986                 nvme_shutdown_ctrl(&dev->ctrl);
1987                 nvme_disable_queue(dev, 0);
1988         }
1989         nvme_dev_unmap(dev);
1990
1991         for (i = dev->queue_count - 1; i >= 0; i--)
1992                 nvme_clear_queue(dev->queues[i]);
1993         mutex_unlock(&dev->shutdown_lock);
1994 }
1995
1996 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1997 {
1998         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1999                                                 PAGE_SIZE, PAGE_SIZE, 0);
2000         if (!dev->prp_page_pool)
2001                 return -ENOMEM;
2002
2003         /* Optimisation for I/Os between 4k and 128k */
2004         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2005                                                 256, 256, 0);
2006         if (!dev->prp_small_pool) {
2007                 dma_pool_destroy(dev->prp_page_pool);
2008                 return -ENOMEM;
2009         }
2010         return 0;
2011 }
2012
2013 static void nvme_release_prp_pools(struct nvme_dev *dev)
2014 {
2015         dma_pool_destroy(dev->prp_page_pool);
2016         dma_pool_destroy(dev->prp_small_pool);
2017 }
2018
2019 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2020 {
2021         struct nvme_dev *dev = to_nvme_dev(ctrl);
2022
2023         put_device(dev->dev);
2024         if (dev->tagset.tags)
2025                 blk_mq_free_tag_set(&dev->tagset);
2026         if (dev->ctrl.admin_q)
2027                 blk_put_queue(dev->ctrl.admin_q);
2028         kfree(dev->queues);
2029         kfree(dev->entry);
2030         kfree(dev);
2031 }
2032
2033 static void nvme_reset_work(struct work_struct *work)
2034 {
2035         struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2036         int result;
2037
2038         if (WARN_ON(test_bit(NVME_CTRL_RESETTING, &dev->flags)))
2039                 goto out;
2040
2041         /*
2042          * If we're called to reset a live controller first shut it down before
2043          * moving on.
2044          */
2045         if (dev->bar)
2046                 nvme_dev_shutdown(dev);
2047
2048         set_bit(NVME_CTRL_RESETTING, &dev->flags);
2049
2050         result = nvme_dev_map(dev);
2051         if (result)
2052                 goto out;
2053
2054         result = nvme_configure_admin_queue(dev);
2055         if (result)
2056                 goto unmap;
2057
2058         nvme_init_queue(dev->queues[0], 0);
2059         result = nvme_alloc_admin_tags(dev);
2060         if (result)
2061                 goto disable;
2062
2063         result = nvme_init_identify(&dev->ctrl);
2064         if (result)
2065                 goto free_tags;
2066
2067         result = nvme_setup_io_queues(dev);
2068         if (result)
2069                 goto free_tags;
2070
2071         dev->ctrl.event_limit = NVME_NR_AEN_COMMANDS;
2072
2073         result = nvme_dev_list_add(dev);
2074         if (result)
2075                 goto remove;
2076
2077         /*
2078          * Keep the controller around but remove all namespaces if we don't have
2079          * any working I/O queue.
2080          */
2081         if (dev->online_queues < 2) {
2082                 dev_warn(dev->dev, "IO queues not created\n");
2083                 nvme_remove_namespaces(&dev->ctrl);
2084         } else {
2085                 nvme_unfreeze_queues(dev);
2086                 nvme_dev_add(dev);
2087         }
2088
2089         clear_bit(NVME_CTRL_RESETTING, &dev->flags);
2090         return;
2091
2092  remove:
2093         nvme_dev_list_remove(dev);
2094  free_tags:
2095         nvme_dev_remove_admin(dev);
2096         blk_put_queue(dev->ctrl.admin_q);
2097         dev->ctrl.admin_q = NULL;
2098         dev->queues[0]->tags = NULL;
2099  disable:
2100         nvme_disable_queue(dev, 0);
2101  unmap:
2102         nvme_dev_unmap(dev);
2103  out:
2104         nvme_remove_dead_ctrl(dev);
2105 }
2106
2107 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2108 {
2109         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2110         struct pci_dev *pdev = to_pci_dev(dev->dev);
2111
2112         if (pci_get_drvdata(pdev))
2113                 pci_stop_and_remove_bus_device_locked(pdev);
2114         nvme_put_ctrl(&dev->ctrl);
2115 }
2116
2117 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2118 {
2119         dev_warn(dev->dev, "Removing after probe failure\n");
2120         kref_get(&dev->ctrl.kref);
2121         if (!schedule_work(&dev->remove_work))
2122                 nvme_put_ctrl(&dev->ctrl);
2123 }
2124
2125 static int nvme_reset(struct nvme_dev *dev)
2126 {
2127         if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
2128                 return -ENODEV;
2129
2130         if (!queue_work(nvme_workq, &dev->reset_work))
2131                 return -EBUSY;
2132
2133         flush_work(&dev->reset_work);
2134         return 0;
2135 }
2136
2137 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2138 {
2139         *val = readl(to_nvme_dev(ctrl)->bar + off);
2140         return 0;
2141 }
2142
2143 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2144 {
2145         writel(val, to_nvme_dev(ctrl)->bar + off);
2146         return 0;
2147 }
2148
2149 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2150 {
2151         *val = readq(to_nvme_dev(ctrl)->bar + off);
2152         return 0;
2153 }
2154
2155 static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl)
2156 {
2157         struct nvme_dev *dev = to_nvme_dev(ctrl);
2158
2159         return !dev->bar || dev->online_queues < 2;
2160 }
2161
2162 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
2163 {
2164         return nvme_reset(to_nvme_dev(ctrl));
2165 }
2166
2167 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2168         .reg_read32             = nvme_pci_reg_read32,
2169         .reg_write32            = nvme_pci_reg_write32,
2170         .reg_read64             = nvme_pci_reg_read64,
2171         .io_incapable           = nvme_pci_io_incapable,
2172         .reset_ctrl             = nvme_pci_reset_ctrl,
2173         .free_ctrl              = nvme_pci_free_ctrl,
2174 };
2175
2176 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2177 {
2178         int node, result = -ENOMEM;
2179         struct nvme_dev *dev;
2180
2181         node = dev_to_node(&pdev->dev);
2182         if (node == NUMA_NO_NODE)
2183                 set_dev_node(&pdev->dev, 0);
2184
2185         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2186         if (!dev)
2187                 return -ENOMEM;
2188         dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2189                                                         GFP_KERNEL, node);
2190         if (!dev->entry)
2191                 goto free;
2192         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2193                                                         GFP_KERNEL, node);
2194         if (!dev->queues)
2195                 goto free;
2196
2197         dev->dev = get_device(&pdev->dev);
2198         pci_set_drvdata(pdev, dev);
2199
2200         INIT_LIST_HEAD(&dev->node);
2201         INIT_WORK(&dev->scan_work, nvme_dev_scan);
2202         INIT_WORK(&dev->reset_work, nvme_reset_work);
2203         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2204         mutex_init(&dev->shutdown_lock);
2205
2206         result = nvme_setup_prp_pools(dev);
2207         if (result)
2208                 goto put_pci;
2209
2210         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2211                         id->driver_data);
2212         if (result)
2213                 goto release_pools;
2214
2215         queue_work(nvme_workq, &dev->reset_work);
2216         return 0;
2217
2218  release_pools:
2219         nvme_release_prp_pools(dev);
2220  put_pci:
2221         put_device(dev->dev);
2222  free:
2223         kfree(dev->queues);
2224         kfree(dev->entry);
2225         kfree(dev);
2226         return result;
2227 }
2228
2229 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2230 {
2231         struct nvme_dev *dev = pci_get_drvdata(pdev);
2232
2233         if (prepare)
2234                 nvme_dev_shutdown(dev);
2235         else
2236                 queue_work(nvme_workq, &dev->reset_work);
2237 }
2238
2239 static void nvme_shutdown(struct pci_dev *pdev)
2240 {
2241         struct nvme_dev *dev = pci_get_drvdata(pdev);
2242         nvme_dev_shutdown(dev);
2243 }
2244
2245 static void nvme_remove(struct pci_dev *pdev)
2246 {
2247         struct nvme_dev *dev = pci_get_drvdata(pdev);
2248
2249         spin_lock(&dev_list_lock);
2250         list_del_init(&dev->node);
2251         spin_unlock(&dev_list_lock);
2252
2253         pci_set_drvdata(pdev, NULL);
2254         flush_work(&dev->reset_work);
2255         flush_work(&dev->scan_work);
2256         nvme_remove_namespaces(&dev->ctrl);
2257         nvme_uninit_ctrl(&dev->ctrl);
2258         nvme_dev_shutdown(dev);
2259         nvme_dev_remove_admin(dev);
2260         nvme_free_queues(dev, 0);
2261         nvme_release_cmb(dev);
2262         nvme_release_prp_pools(dev);
2263         nvme_put_ctrl(&dev->ctrl);
2264 }
2265
2266 /* These functions are yet to be implemented */
2267 #define nvme_error_detected NULL
2268 #define nvme_dump_registers NULL
2269 #define nvme_link_reset NULL
2270 #define nvme_slot_reset NULL
2271 #define nvme_error_resume NULL
2272
2273 #ifdef CONFIG_PM_SLEEP
2274 static int nvme_suspend(struct device *dev)
2275 {
2276         struct pci_dev *pdev = to_pci_dev(dev);
2277         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2278
2279         nvme_dev_shutdown(ndev);
2280         return 0;
2281 }
2282
2283 static int nvme_resume(struct device *dev)
2284 {
2285         struct pci_dev *pdev = to_pci_dev(dev);
2286         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2287
2288         queue_work(nvme_workq, &ndev->reset_work);
2289         return 0;
2290 }
2291 #endif
2292
2293 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2294
2295 static const struct pci_error_handlers nvme_err_handler = {
2296         .error_detected = nvme_error_detected,
2297         .mmio_enabled   = nvme_dump_registers,
2298         .link_reset     = nvme_link_reset,
2299         .slot_reset     = nvme_slot_reset,
2300         .resume         = nvme_error_resume,
2301         .reset_notify   = nvme_reset_notify,
2302 };
2303
2304 /* Move to pci_ids.h later */
2305 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
2306
2307 static const struct pci_device_id nvme_id_table[] = {
2308         { PCI_VDEVICE(INTEL, 0x0953),
2309                 .driver_data = NVME_QUIRK_STRIPE_SIZE, },
2310         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2311                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2312         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2313         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2314         { 0, }
2315 };
2316 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2317
2318 static struct pci_driver nvme_driver = {
2319         .name           = "nvme",
2320         .id_table       = nvme_id_table,
2321         .probe          = nvme_probe,
2322         .remove         = nvme_remove,
2323         .shutdown       = nvme_shutdown,
2324         .driver         = {
2325                 .pm     = &nvme_dev_pm_ops,
2326         },
2327         .err_handler    = &nvme_err_handler,
2328 };
2329
2330 static int __init nvme_init(void)
2331 {
2332         int result;
2333
2334         init_waitqueue_head(&nvme_kthread_wait);
2335
2336         nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2337         if (!nvme_workq)
2338                 return -ENOMEM;
2339
2340         result = nvme_core_init();
2341         if (result < 0)
2342                 goto kill_workq;
2343
2344         result = pci_register_driver(&nvme_driver);
2345         if (result)
2346                 goto core_exit;
2347         return 0;
2348
2349  core_exit:
2350         nvme_core_exit();
2351  kill_workq:
2352         destroy_workqueue(nvme_workq);
2353         return result;
2354 }
2355
2356 static void __exit nvme_exit(void)
2357 {
2358         pci_unregister_driver(&nvme_driver);
2359         nvme_core_exit();
2360         destroy_workqueue(nvme_workq);
2361         BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
2362         _nvme_check_size();
2363 }
2364
2365 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2366 MODULE_LICENSE("GPL");
2367 MODULE_VERSION("1.0");
2368 module_init(nvme_init);
2369 module_exit(nvme_exit);