drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/aer.h>
  16 #include <linux/blkdev.h>
  17 #include <linux/blk-mq.h>
  18 #include <linux/blk-mq-pci.h>
  19 #include <linux/dmi.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/mm.h>
  24 #include <linux/module.h>
  25 #include <linux/mutex.h>
  26 #include <linux/once.h>
  27 #include <linux/pci.h>
  28 #include <linux/t10-pi.h>
  29 #include <linux/types.h>
  30 #include <linux/io-64-nonatomic-lo-hi.h>
  31 #include <linux/sed-opal.h>
  32
  33 #include "nvme.h"
  34
  35 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  36 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  37
  38 #define SGES_PER_PAGE   (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
  39
  40 static int use_threaded_interrupts;
  41 module_param(use_threaded_interrupts, int, 0);
  42
  43 static bool use_cmb_sqes = true;
  44 module_param(use_cmb_sqes, bool, 0644);
  45 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  46
  47 static unsigned int max_host_mem_size_mb = 128;
  48 module_param(max_host_mem_size_mb, uint, 0444);
  49 MODULE_PARM_DESC(max_host_mem_size_mb,
  50         "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
  51
  52 static unsigned int sgl_threshold = SZ_32K;
  53 module_param(sgl_threshold, uint, 0644);
  54 MODULE_PARM_DESC(sgl_threshold,
  55                 "Use SGLs when average request segment size is larger or equal to "
  56                 "this size. Use 0 to disable SGLs.");
  57
  58 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
  59 static const struct kernel_param_ops io_queue_depth_ops = {
  60         .set = io_queue_depth_set,
  61         .get = param_get_int,
  62 };
  63
  64 static int io_queue_depth = 1024;
  65 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
  66 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
  67
  68 struct nvme_dev;
  69 struct nvme_queue;
  70
  71 static void nvme_process_cq(struct nvme_queue *nvmeq);
  72 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  73
  74 /*
  75  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  76  */
  77 struct nvme_dev {
  78         struct nvme_queue **queues;
  79         struct blk_mq_tag_set tagset;
  80         struct blk_mq_tag_set admin_tagset;
  81         u32 __iomem *dbs;
  82         struct device *dev;
  83         struct dma_pool *prp_page_pool;
  84         struct dma_pool *prp_small_pool;
  85         unsigned online_queues;
  86         unsigned max_qid;
  87         int q_depth;
  88         u32 db_stride;
  89         void __iomem *bar;
  90         unsigned long bar_mapped_size;
  91         struct work_struct remove_work;
  92         struct mutex shutdown_lock;
  93         bool subsystem;
  94         void __iomem *cmb;
  95         pci_bus_addr_t cmb_bus_addr;
  96         u64 cmb_size;
  97         u32 cmbsz;
  98         u32 cmbloc;
  99         struct nvme_ctrl ctrl;
 100         struct completion ioq_wait;
 101
 102         /* shadow doorbell buffer support: */
 103         u32 *dbbuf_dbs;
 104         dma_addr_t dbbuf_dbs_dma_addr;
 105         u32 *dbbuf_eis;
 106         dma_addr_t dbbuf_eis_dma_addr;
 107
 108         /* host memory buffer support: */
 109         u64 host_mem_size;
 110         u32 nr_host_mem_descs;
 111         dma_addr_t host_mem_descs_dma;
 112         struct nvme_host_mem_buf_desc *host_mem_descs;
 113         void **host_mem_desc_bufs;
 114 };
 115
 116 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
 117 {
 118         int n = 0, ret;
 119
 120         ret = kstrtoint(val, 10, &n);
 121         if (ret != 0 || n < 2)
 122                 return -EINVAL;
 123
 124         return param_set_int(val, kp);
 125 }
 126
 127 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
 128 {
 129         return qid * 2 * stride;
 130 }
 131
 132 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
 133 {
 134         return (qid * 2 + 1) * stride;
 135 }
 136
 137 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 138 {
 139         return container_of(ctrl, struct nvme_dev, ctrl);
 140 }
 141
 142 /*
 143  * An NVM Express queue.  Each device has at least two (one for admin
 144  * commands and one for I/O commands).
 145  */
 146 struct nvme_queue {
 147         struct device *q_dmadev;
 148         struct nvme_dev *dev;
 149         spinlock_t q_lock;
 150         struct nvme_command *sq_cmds;
 151         struct nvme_command __iomem *sq_cmds_io;
 152         volatile struct nvme_completion *cqes;
 153         struct blk_mq_tags **tags;
 154         dma_addr_t sq_dma_addr;
 155         dma_addr_t cq_dma_addr;
 156         u32 __iomem *q_db;
 157         u16 q_depth;
 158         s16 cq_vector;
 159         u16 sq_tail;
 160         u16 cq_head;
 161         u16 qid;
 162         u8 cq_phase;
 163         u8 cqe_seen;
 164         u32 *dbbuf_sq_db;
 165         u32 *dbbuf_cq_db;
 166         u32 *dbbuf_sq_ei;
 167         u32 *dbbuf_cq_ei;
 168 };
 169
 170 /*
 171  * The nvme_iod describes the data in an I/O, including the list of PRP
 172  * entries.  You can't see it in this data structure because C doesn't let
 173  * me express that.  Use nvme_init_iod to ensure there's enough space
 174  * allocated to store the PRP list.
 175  */
 176 struct nvme_iod {
 177         struct nvme_request req;
 178         struct nvme_queue *nvmeq;
 179         bool use_sgl;
 180         int aborted;
 181         int npages;             /* In the PRP list. 0 means small pool in use */
 182         int nents;              /* Used in scatterlist */
 183         int length;             /* Of data, in bytes */
 184         dma_addr_t first_dma;
 185         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 186         struct scatterlist *sg;
 187         struct scatterlist inline_sg[0];
 188 };
 189
 190 /*
 191  * Check we didin't inadvertently grow the command struct
 192  */
 193 static inline void _nvme_check_size(void)
 194 {
 195         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 196         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 197         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 198         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 199         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 200         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 201         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 202         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 203         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
 204         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
 205         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 206         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 207         BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
 208 }
 209
 210 static inline unsigned int nvme_dbbuf_size(u32 stride)
 211 {
 212         return ((num_possible_cpus() + 1) * 8 * stride);
 213 }
 214
 215 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
 216 {
 217         unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
 218
 219         if (dev->dbbuf_dbs)
 220                 return 0;
 221
 222         dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
 223                                             &dev->dbbuf_dbs_dma_addr,
 224                                             GFP_KERNEL);
 225         if (!dev->dbbuf_dbs)
 226                 return -ENOMEM;
 227         dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
 228                                             &dev->dbbuf_eis_dma_addr,
 229                                             GFP_KERNEL);
 230         if (!dev->dbbuf_eis) {
 231                 dma_free_coherent(dev->dev, mem_size,
 232                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 233                 dev->dbbuf_dbs = NULL;
 234                 return -ENOMEM;
 235         }
 236
 237         return 0;
 238 }
 239
 240 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
 241 {
 242         unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
 243
 244         if (dev->dbbuf_dbs) {
 245                 dma_free_coherent(dev->dev, mem_size,
 246                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 247                 dev->dbbuf_dbs = NULL;
 248         }
 249         if (dev->dbbuf_eis) {
 250                 dma_free_coherent(dev->dev, mem_size,
 251                                   dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
 252                 dev->dbbuf_eis = NULL;
 253         }
 254 }
 255
 256 static void nvme_dbbuf_init(struct nvme_dev *dev,
 257                             struct nvme_queue *nvmeq, int qid)
 258 {
 259         if (!dev->dbbuf_dbs || !qid)
 260                 return;
 261
 262         nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
 263         nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
 264         nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
 265         nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
 266 }
 267
 268 static void nvme_dbbuf_set(struct nvme_dev *dev)
 269 {
 270         struct nvme_command c;
 271
 272         if (!dev->dbbuf_dbs)
 273                 return;
 274
 275         memset(&c, 0, sizeof(c));
 276         c.dbbuf.opcode = nvme_admin_dbbuf;
 277         c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
 278         c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
 279
 280         if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
 281                 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
 282                 /* Free memory and continue on */
 283                 nvme_dbbuf_dma_free(dev);
 284         }
 285 }
 286
 287 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
 288 {
 289         return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
 290 }
 291
 292 /* Update dbbuf and return true if an MMIO is required */
 293 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
 294                                               volatile u32 *dbbuf_ei)
 295 {
 296         if (dbbuf_db) {
 297                 u16 old_value;
 298
 299                 /*
 300                  * Ensure that the queue is written before updating
 301                  * the doorbell in memory
 302                  */
 303                 wmb();
 304
 305                 old_value = *dbbuf_db;
 306                 *dbbuf_db = value;
 307
 308                 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
 309                         return false;
 310         }
 311
 312         return true;
 313 }
 314
 315 /*
 316  * Max size of iod being embedded in the request payload
 317  */
 318 #define NVME_INT_PAGES          2
 319 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 320
 321 /*
 322  * Will slightly overestimate the number of pages needed.  This is OK
 323  * as it only leads to a small amount of wasted memory for the lifetime of
 324  * the I/O.
 325  */
 326 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 327 {
 328         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 329                                       dev->ctrl.page_size);
 330         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 331 }
 332
 333 /*
 334  * Calculates the number of pages needed for the SGL segments. For example a 4k
 335  * page can accommodate 256 SGL descriptors.
 336  */
 337 static int nvme_pci_npages_sgl(unsigned int num_seg)
 338 {
 339         return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
 340 }
 341
 342 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
 343                 unsigned int size, unsigned int nseg, bool use_sgl)
 344 {
 345         size_t alloc_size;
 346
 347         if (use_sgl)
 348                 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
 349         else
 350                 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
 351
 352         return alloc_size + sizeof(struct scatterlist) * nseg;
 353 }
 354
 355 static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
 356 {
 357         unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
 358                                     NVME_INT_BYTES(dev), NVME_INT_PAGES,
 359                                     use_sgl);
 360
 361         return sizeof(struct nvme_iod) + alloc_size;
 362 }
 363
 364 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 365                                 unsigned int hctx_idx)
 366 {
 367         struct nvme_dev *dev = data;
 368         struct nvme_queue *nvmeq = dev->queues[0];
 369
 370         WARN_ON(hctx_idx != 0);
 371         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 372         WARN_ON(nvmeq->tags);
 373
 374         hctx->driver_data = nvmeq;
 375         nvmeq->tags = &dev->admin_tagset.tags[0];
 376         return 0;
 377 }
 378
 379 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 380 {
 381         struct nvme_queue *nvmeq = hctx->driver_data;
 382
 383         nvmeq->tags = NULL;
 384 }
 385
 386 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 387                           unsigned int hctx_idx)
 388 {
 389         struct nvme_dev *dev = data;
 390         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 391
 392         if (!nvmeq->tags)
 393                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 394
 395         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 396         hctx->driver_data = nvmeq;
 397         return 0;
 398 }
 399
 400 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
 401                 unsigned int hctx_idx, unsigned int numa_node)
 402 {
 403         struct nvme_dev *dev = set->driver_data;
 404         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 405         int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
 406         struct nvme_queue *nvmeq = dev->queues[queue_idx];
 407
 408         BUG_ON(!nvmeq);
 409         iod->nvmeq = nvmeq;
 410         return 0;
 411 }
 412
 413 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 414 {
 415         struct nvme_dev *dev = set->driver_data;
 416
 417         return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
 418 }
 419
 420 /**
 421  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 422  * @nvmeq: The queue to use
 423  * @cmd: The command to send
 424  *
 425  * Safe to use from interrupt context
 426  */
 427 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 428                                                 struct nvme_command *cmd)
 429 {
 430         u16 tail = nvmeq->sq_tail;
 431
 432         if (nvmeq->sq_cmds_io)
 433                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 434         else
 435                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 436
 437         if (++tail == nvmeq->q_depth)
 438                 tail = 0;
 439         if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db,
 440                                               nvmeq->dbbuf_sq_ei))
 441                 writel(tail, nvmeq->q_db);
 442         nvmeq->sq_tail = tail;
 443 }
 444
 445 static void **nvme_pci_iod_list(struct request *req)
 446 {
 447         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 448         return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
 449 }
 450
 451 static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
 452 {
 453         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
 454         int nseg = blk_rq_nr_phys_segments(rq);
 455         unsigned int size = blk_rq_payload_bytes(rq);
 456
 457         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
 458                 size_t alloc_size = nvme_pci_iod_alloc_size(dev, size, nseg,
 459                                 iod->use_sgl);
 460
 461                 iod->sg = kmalloc(alloc_size, GFP_ATOMIC);
 462                 if (!iod->sg)
 463                         return BLK_STS_RESOURCE;
 464         } else {
 465                 iod->sg = iod->inline_sg;
 466         }
 467
 468         iod->aborted = 0;
 469         iod->npages = -1;
 470         iod->nents = 0;
 471         iod->length = size;
 472
 473         return BLK_STS_OK;
 474 }
 475
 476 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
 477 {
 478         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 479         const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
 480         dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
 481
 482         int i;
 483
 484         if (iod->npages == 0)
 485                 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
 486                         dma_addr);
 487
 488         for (i = 0; i < iod->npages; i++) {
 489                 void *addr = nvme_pci_iod_list(req)[i];
 490
 491                 if (iod->use_sgl) {
 492                         struct nvme_sgl_desc *sg_list = addr;
 493
 494                         next_dma_addr =
 495                             le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
 496                 } else {
 497                         __le64 *prp_list = addr;
 498
 499                         next_dma_addr = le64_to_cpu(prp_list[last_prp]);
 500                 }
 501
 502                 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
 503                 dma_addr = next_dma_addr;
 504         }
 505
 506         if (iod->sg != iod->inline_sg)
 507                 kfree(iod->sg);
 508 }
 509
 510 #ifdef CONFIG_BLK_DEV_INTEGRITY
 511 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 512 {
 513         if (be32_to_cpu(pi->ref_tag) == v)
 514                 pi->ref_tag = cpu_to_be32(p);
 515 }
 516
 517 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 518 {
 519         if (be32_to_cpu(pi->ref_tag) == p)
 520                 pi->ref_tag = cpu_to_be32(v);
 521 }
 522
 523 /**
 524  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 525  *
 526  * The virtual start sector is the one that was originally submitted by the
 527  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 528  * start sector may be different. Remap protection information to match the
 529  * physical LBA on writes, and back to the original seed on reads.
 530  *
 531  * Type 0 and 3 do not have a ref tag, so no remapping required.
 532  */
 533 static void nvme_dif_remap(struct request *req,
 534                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 535 {
 536         struct nvme_ns *ns = req->rq_disk->private_data;
 537         struct bio_integrity_payload *bip;
 538         struct t10_pi_tuple *pi;
 539         void *p, *pmap;
 540         u32 i, nlb, ts, phys, virt;
 541
 542         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 543                 return;
 544
 545         bip = bio_integrity(req->bio);
 546         if (!bip)
 547                 return;
 548
 549         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 550
 551         p = pmap;
 552         virt = bip_get_seed(bip);
 553         phys = nvme_block_nr(ns, blk_rq_pos(req));
 554         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 555         ts = ns->disk->queue->integrity.tuple_size;
 556
 557         for (i = 0; i < nlb; i++, virt++, phys++) {
 558                 pi = (struct t10_pi_tuple *)p;
 559                 dif_swap(phys, virt, pi);
 560                 p += ts;
 561         }
 562         kunmap_atomic(pmap);
 563 }
 564 #else /* CONFIG_BLK_DEV_INTEGRITY */
 565 static void nvme_dif_remap(struct request *req,
 566                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 567 {
 568 }
 569 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 570 {
 571 }
 572 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 573 {
 574 }
 575 #endif
 576
 577 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
 578 {
 579         int i;
 580         struct scatterlist *sg;
 581
 582         for_each_sg(sgl, sg, nents, i) {
 583                 dma_addr_t phys = sg_phys(sg);
 584                 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
 585                         "dma_address:%pad dma_length:%d\n",
 586                         i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
 587                         sg_dma_len(sg));
 588         }
 589 }
 590
 591 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
 592                 struct request *req, struct nvme_rw_command *cmnd)
 593 {
 594         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 595         struct dma_pool *pool;
 596         int length = blk_rq_payload_bytes(req);
 597         struct scatterlist *sg = iod->sg;
 598         int dma_len = sg_dma_len(sg);
 599         u64 dma_addr = sg_dma_address(sg);
 600         u32 page_size = dev->ctrl.page_size;
 601         int offset = dma_addr & (page_size - 1);
 602         __le64 *prp_list;
 603         void **list = nvme_pci_iod_list(req);
 604         dma_addr_t prp_dma;
 605         int nprps, i;
 606
 607         iod->use_sgl = false;
 608
 609         length -= (page_size - offset);
 610         if (length <= 0) {
 611                 iod->first_dma = 0;
 612                 goto done;
 613         }
 614
 615         dma_len -= (page_size - offset);
 616         if (dma_len) {
 617                 dma_addr += (page_size - offset);
 618         } else {
 619                 sg = sg_next(sg);
 620                 dma_addr = sg_dma_address(sg);
 621                 dma_len = sg_dma_len(sg);
 622         }
 623
 624         if (length <= page_size) {
 625                 iod->first_dma = dma_addr;
 626                 goto done;
 627         }
 628
 629         nprps = DIV_ROUND_UP(length, page_size);
 630         if (nprps <= (256 / 8)) {
 631                 pool = dev->prp_small_pool;
 632                 iod->npages = 0;
 633         } else {
 634                 pool = dev->prp_page_pool;
 635                 iod->npages = 1;
 636         }
 637
 638         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 639         if (!prp_list) {
 640                 iod->first_dma = dma_addr;
 641                 iod->npages = -1;
 642                 return BLK_STS_RESOURCE;
 643         }
 644         list[0] = prp_list;
 645         iod->first_dma = prp_dma;
 646         i = 0;
 647         for (;;) {
 648                 if (i == page_size >> 3) {
 649                         __le64 *old_prp_list = prp_list;
 650                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 651                         if (!prp_list)
 652                                 return BLK_STS_RESOURCE;
 653                         list[iod->npages++] = prp_list;
 654                         prp_list[0] = old_prp_list[i - 1];
 655                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 656                         i = 1;
 657                 }
 658                 prp_list[i++] = cpu_to_le64(dma_addr);
 659                 dma_len -= page_size;
 660                 dma_addr += page_size;
 661                 length -= page_size;
 662                 if (length <= 0)
 663                         break;
 664                 if (dma_len > 0)
 665                         continue;
 666                 if (unlikely(dma_len < 0))
 667                         goto bad_sgl;
 668                 sg = sg_next(sg);
 669                 dma_addr = sg_dma_address(sg);
 670                 dma_len = sg_dma_len(sg);
 671         }
 672
 673 done:
 674         cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 675         cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
 676
 677         return BLK_STS_OK;
 678
 679  bad_sgl:
 680         WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
 681                         "Invalid SGL for payload:%d nents:%d\n",
 682                         blk_rq_payload_bytes(req), iod->nents);
 683         return BLK_STS_IOERR;
 684 }
 685
 686 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
 687                 struct scatterlist *sg)
 688 {
 689         sge->addr = cpu_to_le64(sg_dma_address(sg));
 690         sge->length = cpu_to_le32(sg_dma_len(sg));
 691         sge->type = NVME_SGL_FMT_DATA_DESC << 4;
 692 }
 693
 694 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
 695                 dma_addr_t dma_addr, int entries)
 696 {
 697         sge->addr = cpu_to_le64(dma_addr);
 698         if (entries < SGES_PER_PAGE) {
 699                 sge->length = cpu_to_le32(entries * sizeof(*sge));
 700                 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
 701         } else {
 702                 sge->length = cpu_to_le32(PAGE_SIZE);
 703                 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
 704         }
 705 }
 706
 707 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
 708                 struct request *req, struct nvme_rw_command *cmd)
 709 {
 710         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 711         int length = blk_rq_payload_bytes(req);
 712         struct dma_pool *pool;
 713         struct nvme_sgl_desc *sg_list;
 714         struct scatterlist *sg = iod->sg;
 715         int entries = iod->nents, i = 0;
 716         dma_addr_t sgl_dma;
 717
 718         iod->use_sgl = true;
 719
 720         /* setting the transfer type as SGL */
 721         cmd->flags = NVME_CMD_SGL_METABUF;
 722
 723         if (length == sg_dma_len(sg)) {
 724                 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
 725                 return BLK_STS_OK;
 726         }
 727
 728         if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
 729                 pool = dev->prp_small_pool;
 730                 iod->npages = 0;
 731         } else {
 732                 pool = dev->prp_page_pool;
 733                 iod->npages = 1;
 734         }
 735
 736         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 737         if (!sg_list) {
 738                 iod->npages = -1;
 739                 return BLK_STS_RESOURCE;
 740         }
 741
 742         nvme_pci_iod_list(req)[0] = sg_list;
 743         iod->first_dma = sgl_dma;
 744
 745         nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
 746
 747         do {
 748                 if (i == SGES_PER_PAGE) {
 749                         struct nvme_sgl_desc *old_sg_desc = sg_list;
 750                         struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
 751
 752                         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 753                         if (!sg_list)
 754                                 return BLK_STS_RESOURCE;
 755
 756                         i = 0;
 757                         nvme_pci_iod_list(req)[iod->npages++] = sg_list;
 758                         sg_list[i++] = *link;
 759                         nvme_pci_sgl_set_seg(link, sgl_dma, entries);
 760                 }
 761
 762                 nvme_pci_sgl_set_data(&sg_list[i++], sg);
 763
 764                 length -= sg_dma_len(sg);
 765                 sg = sg_next(sg);
 766                 entries--;
 767         } while (length > 0);
 768
 769         WARN_ON(entries > 0);
 770         return BLK_STS_OK;
 771 }
 772
 773 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
 774 {
 775         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 776         unsigned int avg_seg_size;
 777
 778         avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req),
 779                         blk_rq_nr_phys_segments(req));
 780
 781         if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
 782                 return false;
 783         if (!iod->nvmeq->qid)
 784                 return false;
 785         if (!sgl_threshold || avg_seg_size < sgl_threshold)
 786                 return false;
 787         return true;
 788 }
 789
 790 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
 791                 struct nvme_command *cmnd)
 792 {
 793         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 794         struct request_queue *q = req->q;
 795         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 796                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 797         blk_status_t ret = BLK_STS_IOERR;
 798
 799         sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
 800         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 801         if (!iod->nents)
 802                 goto out;
 803
 804         ret = BLK_STS_RESOURCE;
 805         if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
 806                                 DMA_ATTR_NO_WARN))
 807                 goto out;
 808
 809         if (nvme_pci_use_sgls(dev, req))
 810                 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
 811         else
 812                 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
 813
 814         if (ret != BLK_STS_OK)
 815                 goto out_unmap;
 816
 817         ret = BLK_STS_IOERR;
 818         if (blk_integrity_rq(req)) {
 819                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 820                         goto out_unmap;
 821
 822                 sg_init_table(&iod->meta_sg, 1);
 823                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 824                         goto out_unmap;
 825
 826                 if (req_op(req) == REQ_OP_WRITE)
 827                         nvme_dif_remap(req, nvme_dif_prep);
 828
 829                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 830                         goto out_unmap;
 831         }
 832
 833         if (blk_integrity_rq(req))
 834                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 835         return BLK_STS_OK;
 836
 837 out_unmap:
 838         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 839 out:
 840         return ret;
 841 }
 842
 843 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 844 {
 845         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 846         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 847                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 848
 849         if (iod->nents) {
 850                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 851                 if (blk_integrity_rq(req)) {
 852                         if (req_op(req) == REQ_OP_READ)
 853                                 nvme_dif_remap(req, nvme_dif_complete);
 854                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 855                 }
 856         }
 857
 858         nvme_cleanup_cmd(req);
 859         nvme_free_iod(dev, req);
 860 }
 861
 862 /*
 863  * NOTE: ns is NULL when called on the admin queue.
 864  */
 865 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 866                          const struct blk_mq_queue_data *bd)
 867 {
 868         struct nvme_ns *ns = hctx->queue->queuedata;
 869         struct nvme_queue *nvmeq = hctx->driver_data;
 870         struct nvme_dev *dev = nvmeq->dev;
 871         struct request *req = bd->rq;
 872         struct nvme_command cmnd;
 873         blk_status_t ret;
 874
 875         ret = nvme_setup_cmd(ns, req, &cmnd);
 876         if (ret)
 877                 return ret;
 878
 879         ret = nvme_init_iod(req, dev);
 880         if (ret)
 881                 goto out_free_cmd;
 882
 883         if (blk_rq_nr_phys_segments(req)) {
 884                 ret = nvme_map_data(dev, req, &cmnd);
 885                 if (ret)
 886                         goto out_cleanup_iod;
 887         }
 888
 889         blk_mq_start_request(req);
 890
 891         spin_lock_irq(&nvmeq->q_lock);
 892         if (unlikely(nvmeq->cq_vector < 0)) {
 893                 ret = BLK_STS_IOERR;
 894                 spin_unlock_irq(&nvmeq->q_lock);
 895                 goto out_cleanup_iod;
 896         }
 897         __nvme_submit_cmd(nvmeq, &cmnd);
 898         nvme_process_cq(nvmeq);
 899         spin_unlock_irq(&nvmeq->q_lock);
 900         return BLK_STS_OK;
 901 out_cleanup_iod:
 902         nvme_free_iod(dev, req);
 903 out_free_cmd:
 904         nvme_cleanup_cmd(req);
 905         return ret;
 906 }
 907
 908 static void nvme_pci_complete_rq(struct request *req)
 909 {
 910         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 911
 912         nvme_unmap_data(iod->nvmeq->dev, req);
 913         nvme_complete_rq(req);
 914 }
 915
 916 /* We read the CQE phase first to check if the rest of the entry is valid */
 917 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
 918                 u16 phase)
 919 {
 920         return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
 921 }
 922
 923 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
 924 {
 925         u16 head = nvmeq->cq_head;
 926
 927         if (likely(nvmeq->cq_vector >= 0)) {
 928                 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
 929                                                       nvmeq->dbbuf_cq_ei))
 930                         writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 931         }
 932 }
 933
 934 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
 935                 struct nvme_completion *cqe)
 936 {
 937         struct request *req;
 938
 939         if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
 940                 dev_warn(nvmeq->dev->ctrl.device,
 941                         "invalid id %d completed on queue %d\n",
 942                         cqe->command_id, le16_to_cpu(cqe->sq_id));
 943                 return;
 944         }
 945
 946         /*
 947          * AEN requests are special as they don't time out and can
 948          * survive any kind of queue freeze and often don't respond to
 949          * aborts.  We don't even bother to allocate a struct request
 950          * for them but rather special case them here.
 951          */
 952         if (unlikely(nvmeq->qid == 0 &&
 953                         cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
 954                 nvme_complete_async_event(&nvmeq->dev->ctrl,
 955                                 cqe->status, &cqe->result);
 956                 return;
 957         }
 958
 959         nvmeq->cqe_seen = 1;
 960         req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
 961         nvme_end_request(req, cqe->status, cqe->result);
 962 }
 963
 964 static inline bool nvme_read_cqe(struct nvme_queue *nvmeq,
 965                 struct nvme_completion *cqe)
 966 {
 967         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
 968                 *cqe = nvmeq->cqes[nvmeq->cq_head];
 969
 970                 if (++nvmeq->cq_head == nvmeq->q_depth) {
 971                         nvmeq->cq_head = 0;
 972                         nvmeq->cq_phase = !nvmeq->cq_phase;
 973                 }
 974                 return true;
 975         }
 976         return false;
 977 }
 978
 979 static void nvme_process_cq(struct nvme_queue *nvmeq)
 980 {
 981         struct nvme_completion cqe;
 982         int consumed = 0;
 983
 984         while (nvme_read_cqe(nvmeq, &cqe)) {
 985                 nvme_handle_cqe(nvmeq, &cqe);
 986                 consumed++;
 987         }
 988
 989         if (consumed)
 990                 nvme_ring_cq_doorbell(nvmeq);
 991 }
 992
 993 static irqreturn_t nvme_irq(int irq, void *data)
 994 {
 995         irqreturn_t result;
 996         struct nvme_queue *nvmeq = data;
 997         spin_lock(&nvmeq->q_lock);
 998         nvme_process_cq(nvmeq);
 999         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
1000         nvmeq->cqe_seen = 0;
1001         spin_unlock(&nvmeq->q_lock);
1002         return result;
1003 }
1004
1005 static irqreturn_t nvme_irq_check(int irq, void *data)
1006 {
1007         struct nvme_queue *nvmeq = data;
1008         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
1009                 return IRQ_WAKE_THREAD;
1010         return IRQ_NONE;
1011 }
1012
1013 static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
1014 {
1015         struct nvme_completion cqe;
1016         int found = 0, consumed = 0;
1017
1018         if (!nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
1019                 return 0;
1020
1021         spin_lock_irq(&nvmeq->q_lock);
1022         while (nvme_read_cqe(nvmeq, &cqe)) {
1023                 nvme_handle_cqe(nvmeq, &cqe);
1024                 consumed++;
1025
1026                 if (tag == cqe.command_id) {
1027                         found = 1;
1028                         break;
1029                 }
1030        }
1031
1032         if (consumed)
1033                 nvme_ring_cq_doorbell(nvmeq);
1034         spin_unlock_irq(&nvmeq->q_lock);
1035
1036         return found;
1037 }
1038
1039 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
1040 {
1041         struct nvme_queue *nvmeq = hctx->driver_data;
1042
1043         return __nvme_poll(nvmeq, tag);
1044 }
1045
1046 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1047 {
1048         struct nvme_dev *dev = to_nvme_dev(ctrl);
1049         struct nvme_queue *nvmeq = dev->queues[0];
1050         struct nvme_command c;
1051
1052         memset(&c, 0, sizeof(c));
1053         c.common.opcode = nvme_admin_async_event;
1054         c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1055
1056         spin_lock_irq(&nvmeq->q_lock);
1057         __nvme_submit_cmd(nvmeq, &c);
1058         spin_unlock_irq(&nvmeq->q_lock);
1059 }
1060
1061 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1062 {
1063         struct nvme_command c;
1064
1065         memset(&c, 0, sizeof(c));
1066         c.delete_queue.opcode = opcode;
1067         c.delete_queue.qid = cpu_to_le16(id);
1068
1069         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1070 }
1071
1072 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1073                                                 struct nvme_queue *nvmeq)
1074 {
1075         struct nvme_command c;
1076         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1077
1078         /*
1079          * Note: we (ab)use the fact that the prp fields survive if no data
1080          * is attached to the request.
1081          */
1082         memset(&c, 0, sizeof(c));
1083         c.create_cq.opcode = nvme_admin_create_cq;
1084         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1085         c.create_cq.cqid = cpu_to_le16(qid);
1086         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1087         c.create_cq.cq_flags = cpu_to_le16(flags);
1088         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1089
1090         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1091 }
1092
1093 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1094                                                 struct nvme_queue *nvmeq)
1095 {
1096         struct nvme_command c;
1097         int flags = NVME_QUEUE_PHYS_CONTIG;
1098
1099         /*
1100          * Note: we (ab)use the fact that the prp fields survive if no data
1101          * is attached to the request.
1102          */
1103         memset(&c, 0, sizeof(c));
1104         c.create_sq.opcode = nvme_admin_create_sq;
1105         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1106         c.create_sq.sqid = cpu_to_le16(qid);
1107         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1108         c.create_sq.sq_flags = cpu_to_le16(flags);
1109         c.create_sq.cqid = cpu_to_le16(qid);
1110
1111         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1112 }
1113
1114 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1115 {
1116         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1117 }
1118
1119 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1120 {
1121         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1122 }
1123
1124 static void abort_endio(struct request *req, blk_status_t error)
1125 {
1126         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1127         struct nvme_queue *nvmeq = iod->nvmeq;
1128
1129         dev_warn(nvmeq->dev->ctrl.device,
1130                  "Abort status: 0x%x", nvme_req(req)->status);
1131         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1132         blk_mq_free_request(req);
1133 }
1134
1135 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1136 {
1137
1138         /* If true, indicates loss of adapter communication, possibly by a
1139          * NVMe Subsystem reset.
1140          */
1141         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1142
1143         /* If there is a reset ongoing, we shouldn't reset again. */
1144         if (dev->ctrl.state == NVME_CTRL_RESETTING)
1145                 return false;
1146
1147         /* We shouldn't reset unless the controller is on fatal error state
1148          * _or_ if we lost the communication with it.
1149          */
1150         if (!(csts & NVME_CSTS_CFS) && !nssro)
1151                 return false;
1152
1153         /* If PCI error recovery process is happening, we cannot reset or
1154          * the recovery mechanism will surely fail.
1155          */
1156         if (pci_channel_offline(to_pci_dev(dev->dev)))
1157                 return false;
1158
1159         return true;
1160 }
1161
1162 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1163 {
1164         /* Read a config register to help see what died. */
1165         u16 pci_status;
1166         int result;
1167
1168         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1169                                       &pci_status);
1170         if (result == PCIBIOS_SUCCESSFUL)
1171                 dev_warn(dev->ctrl.device,
1172                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1173                          csts, pci_status);
1174         else
1175                 dev_warn(dev->ctrl.device,
1176                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1177                          csts, result);
1178 }
1179
1180 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1181 {
1182         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1183         struct nvme_queue *nvmeq = iod->nvmeq;
1184         struct nvme_dev *dev = nvmeq->dev;
1185         struct request *abort_req;
1186         struct nvme_command cmd;
1187         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1188
1189         /*
1190          * Reset immediately if the controller is failed
1191          */
1192         if (nvme_should_reset(dev, csts)) {
1193                 nvme_warn_reset(dev, csts);
1194                 nvme_dev_disable(dev, false);
1195                 nvme_reset_ctrl(&dev->ctrl);
1196                 return BLK_EH_HANDLED;
1197         }
1198
1199         /*
1200          * Did we miss an interrupt?
1201          */
1202         if (__nvme_poll(nvmeq, req->tag)) {
1203                 dev_warn(dev->ctrl.device,
1204                          "I/O %d QID %d timeout, completion polled\n",
1205                          req->tag, nvmeq->qid);
1206                 return BLK_EH_HANDLED;
1207         }
1208
1209         /*
1210          * Shutdown immediately if controller times out while starting. The
1211          * reset work will see the pci device disabled when it gets the forced
1212          * cancellation error. All outstanding requests are completed on
1213          * shutdown, so we return BLK_EH_HANDLED.
1214          */
1215         if (dev->ctrl.state == NVME_CTRL_RESETTING) {
1216                 dev_warn(dev->ctrl.device,
1217                          "I/O %d QID %d timeout, disable controller\n",
1218                          req->tag, nvmeq->qid);
1219                 nvme_dev_disable(dev, false);
1220                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1221                 return BLK_EH_HANDLED;
1222         }
1223
1224         /*
1225          * Shutdown the controller immediately and schedule a reset if the
1226          * command was already aborted once before and still hasn't been
1227          * returned to the driver, or if this is the admin queue.
1228          */
1229         if (!nvmeq->qid || iod->aborted) {
1230                 dev_warn(dev->ctrl.device,
1231                          "I/O %d QID %d timeout, reset controller\n",
1232                          req->tag, nvmeq->qid);
1233                 nvme_dev_disable(dev, false);
1234                 nvme_reset_ctrl(&dev->ctrl);
1235
1236                 /*
1237                  * Mark the request as handled, since the inline shutdown
1238                  * forces all outstanding requests to complete.
1239                  */
1240                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1241                 return BLK_EH_HANDLED;
1242         }
1243
1244         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1245                 atomic_inc(&dev->ctrl.abort_limit);
1246                 return BLK_EH_RESET_TIMER;
1247         }
1248         iod->aborted = 1;
1249
1250         memset(&cmd, 0, sizeof(cmd));
1251         cmd.abort.opcode = nvme_admin_abort_cmd;
1252         cmd.abort.cid = req->tag;
1253         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1254
1255         dev_warn(nvmeq->dev->ctrl.device,
1256                 "I/O %d QID %d timeout, aborting\n",
1257                  req->tag, nvmeq->qid);
1258
1259         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1260                         BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1261         if (IS_ERR(abort_req)) {
1262                 atomic_inc(&dev->ctrl.abort_limit);
1263                 return BLK_EH_RESET_TIMER;
1264         }
1265
1266         abort_req->timeout = ADMIN_TIMEOUT;
1267         abort_req->end_io_data = NULL;
1268         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1269
1270         /*
1271          * The aborted req will be completed on receiving the abort req.
1272          * We enable the timer again. If hit twice, it'll cause a device reset,
1273          * as the device then is in a faulty state.
1274          */
1275         return BLK_EH_RESET_TIMER;
1276 }
1277
1278 static void nvme_free_queue(struct nvme_queue *nvmeq)
1279 {
1280         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1281                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1282         if (nvmeq->sq_cmds)
1283                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1284                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1285         kfree(nvmeq);
1286 }
1287
1288 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1289 {
1290         int i;
1291
1292         for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1293                 struct nvme_queue *nvmeq = dev->queues[i];
1294                 dev->ctrl.queue_count--;
1295                 dev->queues[i] = NULL;
1296                 nvme_free_queue(nvmeq);
1297         }
1298 }
1299
1300 /**
1301  * nvme_suspend_queue - put queue into suspended state
1302  * @nvmeq - queue to suspend
1303  */
1304 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1305 {
1306         int vector;
1307
1308         spin_lock_irq(&nvmeq->q_lock);
1309         if (nvmeq->cq_vector == -1) {
1310                 spin_unlock_irq(&nvmeq->q_lock);
1311                 return 1;
1312         }
1313         vector = nvmeq->cq_vector;
1314         nvmeq->dev->online_queues--;
1315         nvmeq->cq_vector = -1;
1316         spin_unlock_irq(&nvmeq->q_lock);
1317
1318         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1319                 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1320
1321         pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
1322
1323         return 0;
1324 }
1325
1326 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1327 {
1328         struct nvme_queue *nvmeq = dev->queues[0];
1329
1330         if (!nvmeq)
1331                 return;
1332         if (nvme_suspend_queue(nvmeq))
1333                 return;
1334
1335         if (shutdown)
1336                 nvme_shutdown_ctrl(&dev->ctrl);
1337         else
1338                 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1339
1340         spin_lock_irq(&nvmeq->q_lock);
1341         nvme_process_cq(nvmeq);
1342         spin_unlock_irq(&nvmeq->q_lock);
1343 }
1344
1345 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1346                                 int entry_size)
1347 {
1348         int q_depth = dev->q_depth;
1349         unsigned q_size_aligned = roundup(q_depth * entry_size,
1350                                           dev->ctrl.page_size);
1351
1352         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1353                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1354                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1355                 q_depth = div_u64(mem_per_q, entry_size);
1356
1357                 /*
1358                  * Ensure the reduced q_depth is above some threshold where it
1359                  * would be better to map queues in system memory with the
1360                  * original depth
1361                  */
1362                 if (q_depth < 64)
1363                         return -ENOMEM;
1364         }
1365
1366         return q_depth;
1367 }
1368
1369 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1370                                 int qid, int depth)
1371 {
1372         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1373                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1374                                                       dev->ctrl.page_size);
1375                 nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
1376                 nvmeq->sq_cmds_io = dev->cmb + offset;
1377         } else {
1378                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1379                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1380                 if (!nvmeq->sq_cmds)
1381                         return -ENOMEM;
1382         }
1383
1384         return 0;
1385 }
1386
1387 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1388                                                         int depth, int node)
1389 {
1390         struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL,
1391                                                         node);
1392         if (!nvmeq)
1393                 return NULL;
1394
1395         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1396                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1397         if (!nvmeq->cqes)
1398                 goto free_nvmeq;
1399
1400         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1401                 goto free_cqdma;
1402
1403         nvmeq->q_dmadev = dev->dev;
1404         nvmeq->dev = dev;
1405         spin_lock_init(&nvmeq->q_lock);
1406         nvmeq->cq_head = 0;
1407         nvmeq->cq_phase = 1;
1408         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1409         nvmeq->q_depth = depth;
1410         nvmeq->qid = qid;
1411         nvmeq->cq_vector = -1;
1412         dev->queues[qid] = nvmeq;
1413         dev->ctrl.queue_count++;
1414
1415         return nvmeq;
1416
1417  free_cqdma:
1418         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1419                                                         nvmeq->cq_dma_addr);
1420  free_nvmeq:
1421         kfree(nvmeq);
1422         return NULL;
1423 }
1424
1425 static int queue_request_irq(struct nvme_queue *nvmeq)
1426 {
1427         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1428         int nr = nvmeq->dev->ctrl.instance;
1429
1430         if (use_threaded_interrupts) {
1431                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1432                                 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1433         } else {
1434                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1435                                 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1436         }
1437 }
1438
1439 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1440 {
1441         struct nvme_dev *dev = nvmeq->dev;
1442
1443         spin_lock_irq(&nvmeq->q_lock);
1444         nvmeq->sq_tail = 0;
1445         nvmeq->cq_head = 0;
1446         nvmeq->cq_phase = 1;
1447         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1448         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1449         nvme_dbbuf_init(dev, nvmeq, qid);
1450         dev->online_queues++;
1451         spin_unlock_irq(&nvmeq->q_lock);
1452 }
1453
1454 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1455 {
1456         struct nvme_dev *dev = nvmeq->dev;
1457         int result;
1458
1459         nvmeq->cq_vector = qid - 1;
1460         result = adapter_alloc_cq(dev, qid, nvmeq);
1461         if (result < 0)
1462                 return result;
1463
1464         result = adapter_alloc_sq(dev, qid, nvmeq);
1465         if (result < 0)
1466                 goto release_cq;
1467
1468         nvme_init_queue(nvmeq, qid);
1469         result = queue_request_irq(nvmeq);
1470         if (result < 0)
1471                 goto release_sq;
1472
1473         return result;
1474
1475  release_sq:
1476         adapter_delete_sq(dev, qid);
1477  release_cq:
1478         adapter_delete_cq(dev, qid);
1479         return result;
1480 }
1481
1482 static const struct blk_mq_ops nvme_mq_admin_ops = {
1483         .queue_rq       = nvme_queue_rq,
1484         .complete       = nvme_pci_complete_rq,
1485         .init_hctx      = nvme_admin_init_hctx,
1486         .exit_hctx      = nvme_admin_exit_hctx,
1487         .init_request   = nvme_init_request,
1488         .timeout        = nvme_timeout,
1489 };
1490
1491 static const struct blk_mq_ops nvme_mq_ops = {
1492         .queue_rq       = nvme_queue_rq,
1493         .complete       = nvme_pci_complete_rq,
1494         .init_hctx      = nvme_init_hctx,
1495         .init_request   = nvme_init_request,
1496         .map_queues     = nvme_pci_map_queues,
1497         .timeout        = nvme_timeout,
1498         .poll           = nvme_poll,
1499 };
1500
1501 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1502 {
1503         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1504                 /*
1505                  * If the controller was reset during removal, it's possible
1506                  * user requests may be waiting on a stopped queue. Start the
1507                  * queue to flush these to completion.
1508                  */
1509                 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1510                 blk_cleanup_queue(dev->ctrl.admin_q);
1511                 blk_mq_free_tag_set(&dev->admin_tagset);
1512         }
1513 }
1514
1515 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1516 {
1517         if (!dev->ctrl.admin_q) {
1518                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1519                 dev->admin_tagset.nr_hw_queues = 1;
1520
1521                 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1522                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1523                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1524                 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
1525                 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1526                 dev->admin_tagset.driver_data = dev;
1527
1528                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1529                         return -ENOMEM;
1530                 dev->ctrl.admin_tagset = &dev->admin_tagset;
1531
1532                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1533                 if (IS_ERR(dev->ctrl.admin_q)) {
1534                         blk_mq_free_tag_set(&dev->admin_tagset);
1535                         return -ENOMEM;
1536                 }
1537                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1538                         nvme_dev_remove_admin(dev);
1539                         dev->ctrl.admin_q = NULL;
1540                         return -ENODEV;
1541                 }
1542         } else
1543                 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1544
1545         return 0;
1546 }
1547
1548 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1549 {
1550         return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1551 }
1552
1553 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1554 {
1555         struct pci_dev *pdev = to_pci_dev(dev->dev);
1556
1557         if (size <= dev->bar_mapped_size)
1558                 return 0;
1559         if (size > pci_resource_len(pdev, 0))
1560                 return -ENOMEM;
1561         if (dev->bar)
1562                 iounmap(dev->bar);
1563         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1564         if (!dev->bar) {
1565                 dev->bar_mapped_size = 0;
1566                 return -ENOMEM;
1567         }
1568         dev->bar_mapped_size = size;
1569         dev->dbs = dev->bar + NVME_REG_DBS;
1570
1571         return 0;
1572 }
1573
1574 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1575 {
1576         int result;
1577         u32 aqa;
1578         struct nvme_queue *nvmeq;
1579
1580         result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1581         if (result < 0)
1582                 return result;
1583
1584         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1585                                 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1586
1587         if (dev->subsystem &&
1588             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1589                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1590
1591         result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1592         if (result < 0)
1593                 return result;
1594
1595         nvmeq = dev->queues[0];
1596         if (!nvmeq) {
1597                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH,
1598                                         dev_to_node(dev->dev));
1599                 if (!nvmeq)
1600                         return -ENOMEM;
1601         }
1602
1603         aqa = nvmeq->q_depth - 1;
1604         aqa |= aqa << 16;
1605
1606         writel(aqa, dev->bar + NVME_REG_AQA);
1607         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1608         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1609
1610         result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
1611         if (result)
1612                 return result;
1613
1614         nvmeq->cq_vector = 0;
1615         nvme_init_queue(nvmeq, 0);
1616         result = queue_request_irq(nvmeq);
1617         if (result) {
1618                 nvmeq->cq_vector = -1;
1619                 return result;
1620         }
1621
1622         return result;
1623 }
1624
1625 static int nvme_create_io_queues(struct nvme_dev *dev)
1626 {
1627         unsigned i, max;
1628         int ret = 0;
1629
1630         for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1631                 /* vector == qid - 1, match nvme_create_queue */
1632                 if (!nvme_alloc_queue(dev, i, dev->q_depth,
1633                      pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) {
1634                         ret = -ENOMEM;
1635                         break;
1636                 }
1637         }
1638
1639         max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1640         for (i = dev->online_queues; i <= max; i++) {
1641                 ret = nvme_create_queue(dev->queues[i], i);
1642                 if (ret)
1643                         break;
1644         }
1645
1646         /*
1647          * Ignore failing Create SQ/CQ commands, we can continue with less
1648          * than the desired aount of queues, and even a controller without
1649          * I/O queues an still be used to issue admin commands.  This might
1650          * be useful to upgrade a buggy firmware for example.
1651          */
1652         return ret >= 0 ? 0 : ret;
1653 }
1654
1655 static ssize_t nvme_cmb_show(struct device *dev,
1656                              struct device_attribute *attr,
1657                              char *buf)
1658 {
1659         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1660
1661         return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1662                        ndev->cmbloc, ndev->cmbsz);
1663 }
1664 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1665
1666 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1667 {
1668         u64 szu, size, offset;
1669         resource_size_t bar_size;
1670         struct pci_dev *pdev = to_pci_dev(dev->dev);
1671         void __iomem *cmb;
1672         int bar;
1673
1674         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1675         if (!(NVME_CMB_SZ(dev->cmbsz)))
1676                 return NULL;
1677         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1678
1679         if (!use_cmb_sqes)
1680                 return NULL;
1681
1682         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1683         size = szu * NVME_CMB_SZ(dev->cmbsz);
1684         offset = szu * NVME_CMB_OFST(dev->cmbloc);
1685         bar = NVME_CMB_BIR(dev->cmbloc);
1686         bar_size = pci_resource_len(pdev, bar);
1687
1688         if (offset > bar_size)
1689                 return NULL;
1690
1691         /*
1692          * Controllers may support a CMB size larger than their BAR,
1693          * for example, due to being behind a bridge. Reduce the CMB to
1694          * the reported size of the BAR
1695          */
1696         if (size > bar_size - offset)
1697                 size = bar_size - offset;
1698
1699         cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size);
1700         if (!cmb)
1701                 return NULL;
1702
1703         dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset;
1704         dev->cmb_size = size;
1705         return cmb;
1706 }
1707
1708 static inline void nvme_release_cmb(struct nvme_dev *dev)
1709 {
1710         if (dev->cmb) {
1711                 iounmap(dev->cmb);
1712                 dev->cmb = NULL;
1713                 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1714                                              &dev_attr_cmb.attr, NULL);
1715                 dev->cmbsz = 0;
1716         }
1717 }
1718
1719 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1720 {
1721         u64 dma_addr = dev->host_mem_descs_dma;
1722         struct nvme_command c;
1723         int ret;
1724
1725         memset(&c, 0, sizeof(c));
1726         c.features.opcode       = nvme_admin_set_features;
1727         c.features.fid          = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1728         c.features.dword11      = cpu_to_le32(bits);
1729         c.features.dword12      = cpu_to_le32(dev->host_mem_size >>
1730                                               ilog2(dev->ctrl.page_size));
1731         c.features.dword13      = cpu_to_le32(lower_32_bits(dma_addr));
1732         c.features.dword14      = cpu_to_le32(upper_32_bits(dma_addr));
1733         c.features.dword15      = cpu_to_le32(dev->nr_host_mem_descs);
1734
1735         ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1736         if (ret) {
1737                 dev_warn(dev->ctrl.device,
1738                          "failed to set host mem (err %d, flags %#x).\n",
1739                          ret, bits);
1740         }
1741         return ret;
1742 }
1743
1744 static void nvme_free_host_mem(struct nvme_dev *dev)
1745 {
1746         int i;
1747
1748         for (i = 0; i < dev->nr_host_mem_descs; i++) {
1749                 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1750                 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1751
1752                 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1753                                 le64_to_cpu(desc->addr));
1754         }
1755
1756         kfree(dev->host_mem_desc_bufs);
1757         dev->host_mem_desc_bufs = NULL;
1758         dma_free_coherent(dev->dev,
1759                         dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1760                         dev->host_mem_descs, dev->host_mem_descs_dma);
1761         dev->host_mem_descs = NULL;
1762 }
1763
1764 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1765                 u32 chunk_size)
1766 {
1767         struct nvme_host_mem_buf_desc *descs;
1768         u32 max_entries, len;
1769         dma_addr_t descs_dma;
1770         int i = 0;
1771         void **bufs;
1772         u64 size = 0, tmp;
1773
1774         tmp = (preferred + chunk_size - 1);
1775         do_div(tmp, chunk_size);
1776         max_entries = tmp;
1777
1778         if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1779                 max_entries = dev->ctrl.hmmaxd;
1780
1781         descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1782                         &descs_dma, GFP_KERNEL);
1783         if (!descs)
1784                 goto out;
1785
1786         bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1787         if (!bufs)
1788                 goto out_free_descs;
1789
1790         for (size = 0; size < preferred; size += len) {
1791                 dma_addr_t dma_addr;
1792
1793                 len = min_t(u64, chunk_size, preferred - size);
1794                 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1795                                 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1796                 if (!bufs[i])
1797                         break;
1798
1799                 descs[i].addr = cpu_to_le64(dma_addr);
1800                 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1801                 i++;
1802         }
1803
1804         if (!size)
1805                 goto out_free_bufs;
1806
1807         dev->nr_host_mem_descs = i;
1808         dev->host_mem_size = size;
1809         dev->host_mem_descs = descs;
1810         dev->host_mem_descs_dma = descs_dma;
1811         dev->host_mem_desc_bufs = bufs;
1812         return 0;
1813
1814 out_free_bufs:
1815         while (--i >= 0) {
1816                 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1817
1818                 dma_free_coherent(dev->dev, size, bufs[i],
1819                                 le64_to_cpu(descs[i].addr));
1820         }
1821
1822         kfree(bufs);
1823 out_free_descs:
1824         dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1825                         descs_dma);
1826 out:
1827         dev->host_mem_descs = NULL;
1828         return -ENOMEM;
1829 }
1830
1831 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1832 {
1833         u32 chunk_size;
1834
1835         /* start big and work our way down */
1836         for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1837              chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1838              chunk_size /= 2) {
1839                 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1840                         if (!min || dev->host_mem_size >= min)
1841                                 return 0;
1842                         nvme_free_host_mem(dev);
1843                 }
1844         }
1845
1846         return -ENOMEM;
1847 }
1848
1849 static int nvme_setup_host_mem(struct nvme_dev *dev)
1850 {
1851         u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1852         u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1853         u64 min = (u64)dev->ctrl.hmmin * 4096;
1854         u32 enable_bits = NVME_HOST_MEM_ENABLE;
1855         int ret = 0;
1856
1857         preferred = min(preferred, max);
1858         if (min > max) {
1859                 dev_warn(dev->ctrl.device,
1860                         "min host memory (%lld MiB) above limit (%d MiB).\n",
1861                         min >> ilog2(SZ_1M), max_host_mem_size_mb);
1862                 nvme_free_host_mem(dev);
1863                 return 0;
1864         }
1865
1866         /*
1867          * If we already have a buffer allocated check if we can reuse it.
1868          */
1869         if (dev->host_mem_descs) {
1870                 if (dev->host_mem_size >= min)
1871                         enable_bits |= NVME_HOST_MEM_RETURN;
1872                 else
1873                         nvme_free_host_mem(dev);
1874         }
1875
1876         if (!dev->host_mem_descs) {
1877                 if (nvme_alloc_host_mem(dev, min, preferred)) {
1878                         dev_warn(dev->ctrl.device,
1879                                 "failed to allocate host memory buffer.\n");
1880                         return 0; /* controller must work without HMB */
1881                 }
1882
1883                 dev_info(dev->ctrl.device,
1884                         "allocated %lld MiB host memory buffer.\n",
1885                         dev->host_mem_size >> ilog2(SZ_1M));
1886         }
1887
1888         ret = nvme_set_host_mem(dev, enable_bits);
1889         if (ret)
1890                 nvme_free_host_mem(dev);
1891         return ret;
1892 }
1893
1894 static int nvme_setup_io_queues(struct nvme_dev *dev)
1895 {
1896         struct nvme_queue *adminq = dev->queues[0];
1897         struct pci_dev *pdev = to_pci_dev(dev->dev);
1898         int result, nr_io_queues;
1899         unsigned long size;
1900
1901         nr_io_queues = num_present_cpus();
1902         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1903         if (result < 0)
1904                 return result;
1905
1906         if (nr_io_queues == 0)
1907                 return 0;
1908
1909         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1910                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1911                                 sizeof(struct nvme_command));
1912                 if (result > 0)
1913                         dev->q_depth = result;
1914                 else
1915                         nvme_release_cmb(dev);
1916         }
1917
1918         do {
1919                 size = db_bar_size(dev, nr_io_queues);
1920                 result = nvme_remap_bar(dev, size);
1921                 if (!result)
1922                         break;
1923                 if (!--nr_io_queues)
1924                         return -ENOMEM;
1925         } while (1);
1926         adminq->q_db = dev->dbs;
1927
1928         /* Deregister the admin queue's interrupt */
1929         pci_free_irq(pdev, 0, adminq);
1930
1931         /*
1932          * If we enable msix early due to not intx, disable it again before
1933          * setting up the full range we need.
1934          */
1935         pci_free_irq_vectors(pdev);
1936         nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1937                         PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1938         if (nr_io_queues <= 0)
1939                 return -EIO;
1940         dev->max_qid = nr_io_queues;
1941
1942         /*
1943          * Should investigate if there's a performance win from allocating
1944          * more queues than interrupt vectors; it might allow the submission
1945          * path to scale better, even if the receive path is limited by the
1946          * number of interrupts.
1947          */
1948
1949         result = queue_request_irq(adminq);
1950         if (result) {
1951                 adminq->cq_vector = -1;
1952                 return result;
1953         }
1954         return nvme_create_io_queues(dev);
1955 }
1956
1957 static void nvme_del_queue_end(struct request *req, blk_status_t error)
1958 {
1959         struct nvme_queue *nvmeq = req->end_io_data;
1960
1961         blk_mq_free_request(req);
1962         complete(&nvmeq->dev->ioq_wait);
1963 }
1964
1965 static void nvme_del_cq_end(struct request *req, blk_status_t error)
1966 {
1967         struct nvme_queue *nvmeq = req->end_io_data;
1968
1969         if (!error) {
1970                 unsigned long flags;
1971
1972                 /*
1973                  * We might be called with the AQ q_lock held
1974                  * and the I/O queue q_lock should always
1975                  * nest inside the AQ one.
1976                  */
1977                 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1978                                         SINGLE_DEPTH_NESTING);
1979                 nvme_process_cq(nvmeq);
1980                 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1981         }
1982
1983         nvme_del_queue_end(req, error);
1984 }
1985
1986 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1987 {
1988         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1989         struct request *req;
1990         struct nvme_command cmd;
1991
1992         memset(&cmd, 0, sizeof(cmd));
1993         cmd.delete_queue.opcode = opcode;
1994         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1995
1996         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1997         if (IS_ERR(req))
1998                 return PTR_ERR(req);
1999
2000         req->timeout = ADMIN_TIMEOUT;
2001         req->end_io_data = nvmeq;
2002
2003         blk_execute_rq_nowait(q, NULL, req, false,
2004                         opcode == nvme_admin_delete_cq ?
2005                                 nvme_del_cq_end : nvme_del_queue_end);
2006         return 0;
2007 }
2008
2009 static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
2010 {
2011         int pass;
2012         unsigned long timeout;
2013         u8 opcode = nvme_admin_delete_sq;
2014
2015         for (pass = 0; pass < 2; pass++) {
2016                 int sent = 0, i = queues;
2017
2018                 reinit_completion(&dev->ioq_wait);
2019  retry:
2020                 timeout = ADMIN_TIMEOUT;
2021                 for (; i > 0; i--, sent++)
2022                         if (nvme_delete_queue(dev->queues[i], opcode))
2023                                 break;
2024
2025                 while (sent--) {
2026                         timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
2027                         if (timeout == 0)
2028                                 return;
2029                         if (i)
2030                                 goto retry;
2031                 }
2032                 opcode = nvme_admin_delete_cq;
2033         }
2034 }
2035
2036 /*
2037  * Return: error value if an error occurred setting up the queues or calling
2038  * Identify Device.  0 if these succeeded, even if adding some of the
2039  * namespaces failed.  At the moment, these failures are silent.  TBD which
2040  * failures should be reported.
2041  */
2042 static int nvme_dev_add(struct nvme_dev *dev)
2043 {
2044         if (!dev->ctrl.tagset) {
2045                 dev->tagset.ops = &nvme_mq_ops;
2046                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2047                 dev->tagset.timeout = NVME_IO_TIMEOUT;
2048                 dev->tagset.numa_node = dev_to_node(dev->dev);
2049                 dev->tagset.queue_depth =
2050                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2051                 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2052                 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2053                         dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2054                                         nvme_pci_cmd_size(dev, true));
2055                 }
2056                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2057                 dev->tagset.driver_data = dev;
2058
2059                 if (blk_mq_alloc_tag_set(&dev->tagset))
2060                         return 0;
2061                 dev->ctrl.tagset = &dev->tagset;
2062
2063                 nvme_dbbuf_set(dev);
2064         } else {
2065                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2066
2067                 /* Free previously allocated queues that are no longer usable */
2068                 nvme_free_queues(dev, dev->online_queues);
2069         }
2070
2071         return 0;
2072 }
2073
2074 static int nvme_pci_enable(struct nvme_dev *dev)
2075 {
2076         int result = -ENOMEM;
2077         struct pci_dev *pdev = to_pci_dev(dev->dev);
2078
2079         if (pci_enable_device_mem(pdev))
2080                 return result;
2081
2082         pci_set_master(pdev);
2083
2084         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2085             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
2086                 goto disable;
2087
2088         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2089                 result = -ENODEV;
2090                 goto disable;
2091         }
2092
2093         /*
2094          * Some devices and/or platforms don't advertise or work with INTx
2095          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2096          * adjust this later.
2097          */
2098         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2099         if (result < 0)
2100                 return result;
2101
2102         dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2103
2104         dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2105                                 io_queue_depth);
2106         dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2107         dev->dbs = dev->bar + 4096;
2108
2109         /*
2110          * Temporary fix for the Apple controller found in the MacBook8,1 and
2111          * some MacBook7,1 to avoid controller resets and data loss.
2112          */
2113         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2114                 dev->q_depth = 2;
2115                 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2116                         "set queue depth=%u to work around controller resets\n",
2117                         dev->q_depth);
2118         } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2119                    (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2120                    NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2121                 dev->q_depth = 64;
2122                 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2123                         "set queue depth=%u\n", dev->q_depth);
2124         }
2125
2126         /*
2127          * CMBs can currently only exist on >=1.2 PCIe devices. We only
2128          * populate sysfs if a CMB is implemented. Since nvme_dev_attrs_group
2129          * has no name we can pass NULL as final argument to
2130          * sysfs_add_file_to_group.
2131          */
2132
2133         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
2134                 dev->cmb = nvme_map_cmb(dev);
2135                 if (dev->cmb) {
2136                         if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
2137                                                     &dev_attr_cmb.attr, NULL))
2138                                 dev_warn(dev->ctrl.device,
2139                                          "failed to add sysfs attribute for CMB\n");
2140                 }
2141         }
2142
2143         pci_enable_pcie_error_reporting(pdev);
2144         pci_save_state(pdev);
2145         return 0;
2146
2147  disable:
2148         pci_disable_device(pdev);
2149         return result;
2150 }
2151
2152 static void nvme_dev_unmap(struct nvme_dev *dev)
2153 {
2154         if (dev->bar)
2155                 iounmap(dev->bar);
2156         pci_release_mem_regions(to_pci_dev(dev->dev));
2157 }
2158
2159 static void nvme_pci_disable(struct nvme_dev *dev)
2160 {
2161         struct pci_dev *pdev = to_pci_dev(dev->dev);
2162
2163         nvme_release_cmb(dev);
2164         pci_free_irq_vectors(pdev);
2165
2166         if (pci_is_enabled(pdev)) {
2167                 pci_disable_pcie_error_reporting(pdev);
2168                 pci_disable_device(pdev);
2169         }
2170 }
2171
2172 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2173 {
2174         int i, queues;
2175         bool dead = true;
2176         struct pci_dev *pdev = to_pci_dev(dev->dev);
2177
2178         mutex_lock(&dev->shutdown_lock);
2179         if (pci_is_enabled(pdev)) {
2180                 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2181
2182                 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2183                     dev->ctrl.state == NVME_CTRL_RESETTING)
2184                         nvme_start_freeze(&dev->ctrl);
2185                 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2186                         pdev->error_state  != pci_channel_io_normal);
2187         }
2188
2189         /*
2190          * Give the controller a chance to complete all entered requests if
2191          * doing a safe shutdown.
2192          */
2193         if (!dead) {
2194                 if (shutdown)
2195                         nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2196
2197                 /*
2198                  * If the controller is still alive tell it to stop using the
2199                  * host memory buffer.  In theory the shutdown / reset should
2200                  * make sure that it doesn't access the host memoery anymore,
2201                  * but I'd rather be safe than sorry..
2202                  */
2203                 if (dev->host_mem_descs)
2204                         nvme_set_host_mem(dev, 0);
2205
2206         }
2207         nvme_stop_queues(&dev->ctrl);
2208
2209         queues = dev->online_queues - 1;
2210         for (i = dev->ctrl.queue_count - 1; i > 0; i--)
2211                 nvme_suspend_queue(dev->queues[i]);
2212
2213         if (dead) {
2214                 /* A device might become IO incapable very soon during
2215                  * probe, before the admin queue is configured. Thus,
2216                  * queue_count can be 0 here.
2217                  */
2218                 if (dev->ctrl.queue_count)
2219                         nvme_suspend_queue(dev->queues[0]);
2220         } else {
2221                 nvme_disable_io_queues(dev, queues);
2222                 nvme_disable_admin_queue(dev, shutdown);
2223         }
2224         nvme_pci_disable(dev);
2225
2226         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2227         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2228
2229         /*
2230          * The driver will not be starting up queues again if shutting down so
2231          * must flush all entered requests to their failed completion to avoid
2232          * deadlocking blk-mq hot-cpu notifier.
2233          */
2234         if (shutdown)
2235                 nvme_start_queues(&dev->ctrl);
2236         mutex_unlock(&dev->shutdown_lock);
2237 }
2238
2239 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2240 {
2241         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2242                                                 PAGE_SIZE, PAGE_SIZE, 0);
2243         if (!dev->prp_page_pool)
2244                 return -ENOMEM;
2245
2246         /* Optimisation for I/Os between 4k and 128k */
2247         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2248                                                 256, 256, 0);
2249         if (!dev->prp_small_pool) {
2250                 dma_pool_destroy(dev->prp_page_pool);
2251                 return -ENOMEM;
2252         }
2253         return 0;
2254 }
2255
2256 static void nvme_release_prp_pools(struct nvme_dev *dev)
2257 {
2258         dma_pool_destroy(dev->prp_page_pool);
2259         dma_pool_destroy(dev->prp_small_pool);
2260 }
2261
2262 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2263 {
2264         struct nvme_dev *dev = to_nvme_dev(ctrl);
2265
2266         nvme_dbbuf_dma_free(dev);
2267         put_device(dev->dev);
2268         if (dev->tagset.tags)
2269                 blk_mq_free_tag_set(&dev->tagset);
2270         if (dev->ctrl.admin_q)
2271                 blk_put_queue(dev->ctrl.admin_q);
2272         kfree(dev->queues);
2273         free_opal_dev(dev->ctrl.opal_dev);
2274         kfree(dev);
2275 }
2276
2277 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2278 {
2279         dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
2280
2281         nvme_get_ctrl(&dev->ctrl);
2282         nvme_dev_disable(dev, false);
2283         if (!queue_work(nvme_wq, &dev->remove_work))
2284                 nvme_put_ctrl(&dev->ctrl);
2285 }
2286
2287 static void nvme_reset_work(struct work_struct *work)
2288 {
2289         struct nvme_dev *dev =
2290                 container_of(work, struct nvme_dev, ctrl.reset_work);
2291         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2292         int result = -ENODEV;
2293
2294         if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
2295                 goto out;
2296
2297         /*
2298          * If we're called to reset a live controller first shut it down before
2299          * moving on.
2300          */
2301         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2302                 nvme_dev_disable(dev, false);
2303
2304         result = nvme_pci_enable(dev);
2305         if (result)
2306                 goto out;
2307
2308         result = nvme_pci_configure_admin_queue(dev);
2309         if (result)
2310                 goto out;
2311
2312         result = nvme_alloc_admin_tags(dev);
2313         if (result)
2314                 goto out;
2315
2316         result = nvme_init_identify(&dev->ctrl);
2317         if (result)
2318                 goto out;
2319
2320         if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2321                 if (!dev->ctrl.opal_dev)
2322                         dev->ctrl.opal_dev =
2323                                 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2324                 else if (was_suspend)
2325                         opal_unlock_from_suspend(dev->ctrl.opal_dev);
2326         } else {
2327                 free_opal_dev(dev->ctrl.opal_dev);
2328                 dev->ctrl.opal_dev = NULL;
2329         }
2330
2331         if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2332                 result = nvme_dbbuf_dma_alloc(dev);
2333                 if (result)
2334                         dev_warn(dev->dev,
2335                                  "unable to allocate dma for dbbuf\n");
2336         }
2337
2338         if (dev->ctrl.hmpre) {
2339                 result = nvme_setup_host_mem(dev);
2340                 if (result < 0)
2341                         goto out;
2342         }
2343
2344         result = nvme_setup_io_queues(dev);
2345         if (result)
2346                 goto out;
2347
2348         /*
2349          * Keep the controller around but remove all namespaces if we don't have
2350          * any working I/O queue.
2351          */
2352         if (dev->online_queues < 2) {
2353                 dev_warn(dev->ctrl.device, "IO queues not created\n");
2354                 nvme_kill_queues(&dev->ctrl);
2355                 nvme_remove_namespaces(&dev->ctrl);
2356         } else {
2357                 nvme_start_queues(&dev->ctrl);
2358                 nvme_wait_freeze(&dev->ctrl);
2359                 nvme_dev_add(dev);
2360                 nvme_unfreeze(&dev->ctrl);
2361         }
2362
2363         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2364                 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
2365                 goto out;
2366         }
2367
2368         nvme_start_ctrl(&dev->ctrl);
2369         return;
2370
2371  out:
2372         nvme_remove_dead_ctrl(dev, result);
2373 }
2374
2375 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2376 {
2377         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2378         struct pci_dev *pdev = to_pci_dev(dev->dev);
2379
2380         nvme_kill_queues(&dev->ctrl);
2381         if (pci_get_drvdata(pdev))
2382                 device_release_driver(&pdev->dev);
2383         nvme_put_ctrl(&dev->ctrl);
2384 }
2385
2386 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2387 {
2388         *val = readl(to_nvme_dev(ctrl)->bar + off);
2389         return 0;
2390 }
2391
2392 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2393 {
2394         writel(val, to_nvme_dev(ctrl)->bar + off);
2395         return 0;
2396 }
2397
2398 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2399 {
2400         *val = readq(to_nvme_dev(ctrl)->bar + off);
2401         return 0;
2402 }
2403
2404 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2405         .name                   = "pcie",
2406         .module                 = THIS_MODULE,
2407         .flags                  = NVME_F_METADATA_SUPPORTED,
2408         .reg_read32             = nvme_pci_reg_read32,
2409         .reg_write32            = nvme_pci_reg_write32,
2410         .reg_read64             = nvme_pci_reg_read64,
2411         .free_ctrl              = nvme_pci_free_ctrl,
2412         .submit_async_event     = nvme_pci_submit_async_event,
2413 };
2414
2415 static int nvme_dev_map(struct nvme_dev *dev)
2416 {
2417         struct pci_dev *pdev = to_pci_dev(dev->dev);
2418
2419         if (pci_request_mem_regions(pdev, "nvme"))
2420                 return -ENODEV;
2421
2422         if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2423                 goto release;
2424
2425         return 0;
2426   release:
2427         pci_release_mem_regions(pdev);
2428         return -ENODEV;
2429 }
2430
2431 static unsigned long check_dell_samsung_bug(struct pci_dev *pdev)
2432 {
2433         if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2434                 /*
2435                  * Several Samsung devices seem to drop off the PCIe bus
2436                  * randomly when APST is on and uses the deepest sleep state.
2437                  * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2438                  * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2439                  * 950 PRO 256GB", but it seems to be restricted to two Dell
2440                  * laptops.
2441                  */
2442                 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2443                     (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2444                      dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2445                         return NVME_QUIRK_NO_DEEPEST_PS;
2446         }
2447
2448         return 0;
2449 }
2450
2451 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2452 {
2453         int node, result = -ENOMEM;
2454         struct nvme_dev *dev;
2455         unsigned long quirks = id->driver_data;
2456
2457         node = dev_to_node(&pdev->dev);
2458         if (node == NUMA_NO_NODE)
2459                 set_dev_node(&pdev->dev, first_memory_node);
2460
2461         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2462         if (!dev)
2463                 return -ENOMEM;
2464         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2465                                                         GFP_KERNEL, node);
2466         if (!dev->queues)
2467                 goto free;
2468
2469         dev->dev = get_device(&pdev->dev);
2470         pci_set_drvdata(pdev, dev);
2471
2472         result = nvme_dev_map(dev);
2473         if (result)
2474                 goto put_pci;
2475
2476         INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2477         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2478         mutex_init(&dev->shutdown_lock);
2479         init_completion(&dev->ioq_wait);
2480
2481         result = nvme_setup_prp_pools(dev);
2482         if (result)
2483                 goto unmap;
2484
2485         quirks |= check_dell_samsung_bug(pdev);
2486
2487         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2488                         quirks);
2489         if (result)
2490                 goto release_pools;
2491
2492         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING);
2493         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2494
2495         queue_work(nvme_wq, &dev->ctrl.reset_work);
2496         return 0;
2497
2498  release_pools:
2499         nvme_release_prp_pools(dev);
2500  unmap:
2501         nvme_dev_unmap(dev);
2502  put_pci:
2503         put_device(dev->dev);
2504  free:
2505         kfree(dev->queues);
2506         kfree(dev);
2507         return result;
2508 }
2509
2510 static void nvme_reset_prepare(struct pci_dev *pdev)
2511 {
2512         struct nvme_dev *dev = pci_get_drvdata(pdev);
2513         nvme_dev_disable(dev, false);
2514 }
2515
2516 static void nvme_reset_done(struct pci_dev *pdev)
2517 {
2518         struct nvme_dev *dev = pci_get_drvdata(pdev);
2519         nvme_reset_ctrl(&dev->ctrl);
2520 }
2521
2522 static void nvme_shutdown(struct pci_dev *pdev)
2523 {
2524         struct nvme_dev *dev = pci_get_drvdata(pdev);
2525         nvme_dev_disable(dev, true);
2526 }
2527
2528 /*
2529  * The driver's remove may be called on a device in a partially initialized
2530  * state. This function must not have any dependencies on the device state in
2531  * order to proceed.
2532  */
2533 static void nvme_remove(struct pci_dev *pdev)
2534 {
2535         struct nvme_dev *dev = pci_get_drvdata(pdev);
2536
2537         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2538
2539         cancel_work_sync(&dev->ctrl.reset_work);
2540         pci_set_drvdata(pdev, NULL);
2541
2542         if (!pci_device_is_present(pdev)) {
2543                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2544                 nvme_dev_disable(dev, false);
2545         }
2546
2547         flush_work(&dev->ctrl.reset_work);
2548         nvme_stop_ctrl(&dev->ctrl);
2549         nvme_remove_namespaces(&dev->ctrl);
2550         nvme_dev_disable(dev, true);
2551         nvme_free_host_mem(dev);
2552         nvme_dev_remove_admin(dev);
2553         nvme_free_queues(dev, 0);
2554         nvme_uninit_ctrl(&dev->ctrl);
2555         nvme_release_prp_pools(dev);
2556         nvme_dev_unmap(dev);
2557         nvme_put_ctrl(&dev->ctrl);
2558 }
2559
2560 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2561 {
2562         int ret = 0;
2563
2564         if (numvfs == 0) {
2565                 if (pci_vfs_assigned(pdev)) {
2566                         dev_warn(&pdev->dev,
2567                                 "Cannot disable SR-IOV VFs while assigned\n");
2568                         return -EPERM;
2569                 }
2570                 pci_disable_sriov(pdev);
2571                 return 0;
2572         }
2573
2574         ret = pci_enable_sriov(pdev, numvfs);
2575         return ret ? ret : numvfs;
2576 }
2577
2578 #ifdef CONFIG_PM_SLEEP
2579 static int nvme_suspend(struct device *dev)
2580 {
2581         struct pci_dev *pdev = to_pci_dev(dev);
2582         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2583
2584         nvme_dev_disable(ndev, true);
2585         return 0;
2586 }
2587
2588 static int nvme_resume(struct device *dev)
2589 {
2590         struct pci_dev *pdev = to_pci_dev(dev);
2591         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2592
2593         nvme_reset_ctrl(&ndev->ctrl);
2594         return 0;
2595 }
2596 #endif
2597
2598 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2599
2600 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2601                                                 pci_channel_state_t state)
2602 {
2603         struct nvme_dev *dev = pci_get_drvdata(pdev);
2604
2605         /*
2606          * A frozen channel requires a reset. When detected, this method will
2607          * shutdown the controller to quiesce. The controller will be restarted
2608          * after the slot reset through driver's slot_reset callback.
2609          */
2610         switch (state) {
2611         case pci_channel_io_normal:
2612                 return PCI_ERS_RESULT_CAN_RECOVER;
2613         case pci_channel_io_frozen:
2614                 dev_warn(dev->ctrl.device,
2615                         "frozen state error detected, reset controller\n");
2616                 nvme_dev_disable(dev, false);
2617                 return PCI_ERS_RESULT_NEED_RESET;
2618         case pci_channel_io_perm_failure:
2619                 dev_warn(dev->ctrl.device,
2620                         "failure state error detected, request disconnect\n");
2621                 return PCI_ERS_RESULT_DISCONNECT;
2622         }
2623         return PCI_ERS_RESULT_NEED_RESET;
2624 }
2625
2626 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2627 {
2628         struct nvme_dev *dev = pci_get_drvdata(pdev);
2629
2630         dev_info(dev->ctrl.device, "restart after slot reset\n");
2631         pci_restore_state(pdev);
2632         nvme_reset_ctrl(&dev->ctrl);
2633         return PCI_ERS_RESULT_RECOVERED;
2634 }
2635
2636 static void nvme_error_resume(struct pci_dev *pdev)
2637 {
2638         pci_cleanup_aer_uncorrect_error_status(pdev);
2639 }
2640
2641 static const struct pci_error_handlers nvme_err_handler = {
2642         .error_detected = nvme_error_detected,
2643         .slot_reset     = nvme_slot_reset,
2644         .resume         = nvme_error_resume,
2645         .reset_prepare  = nvme_reset_prepare,
2646         .reset_done     = nvme_reset_done,
2647 };
2648
2649 static const struct pci_device_id nvme_id_table[] = {
2650         { PCI_VDEVICE(INTEL, 0x0953),
2651                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2652                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2653         { PCI_VDEVICE(INTEL, 0x0a53),
2654                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2655                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2656         { PCI_VDEVICE(INTEL, 0x0a54),
2657                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2658                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2659         { PCI_VDEVICE(INTEL, 0x0a55),
2660                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2661                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2662         { PCI_VDEVICE(INTEL, 0xf1a5),   /* Intel 600P/P3100 */
2663                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS },
2664         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2665                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2666         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
2667                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2668         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
2669                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2670         { PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */
2671                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2672         { PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */
2673                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2674         { PCI_DEVICE(0x1d1d, 0x1f1f),   /* LighNVM qemu device */
2675                 .driver_data = NVME_QUIRK_LIGHTNVM, },
2676         { PCI_DEVICE(0x1d1d, 0x2807),   /* CNEX WL */
2677                 .driver_data = NVME_QUIRK_LIGHTNVM, },
2678         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2679         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2680         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2681         { 0, }
2682 };
2683 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2684
2685 static struct pci_driver nvme_driver = {
2686         .name           = "nvme",
2687         .id_table       = nvme_id_table,
2688         .probe          = nvme_probe,
2689         .remove         = nvme_remove,
2690         .shutdown       = nvme_shutdown,
2691         .driver         = {
2692                 .pm     = &nvme_dev_pm_ops,
2693         },
2694         .sriov_configure = nvme_pci_sriov_configure,
2695         .err_handler    = &nvme_err_handler,
2696 };
2697
2698 static int __init nvme_init(void)
2699 {
2700         return pci_register_driver(&nvme_driver);
2701 }
2702
2703 static void __exit nvme_exit(void)
2704 {
2705         pci_unregister_driver(&nvme_driver);
2706         flush_workqueue(nvme_wq);
2707         _nvme_check_size();
2708 }
2709
2710 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2711 MODULE_LICENSE("GPL");
2712 MODULE_VERSION("1.0");
2713 module_init(nvme_init);
2714 module_exit(nvme_exit);