drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/bitops.h>
  16 #include <linux/blkdev.h>
  17 #include <linux/blk-mq.h>
  18 #include <linux/cpu.h>
  19 #include <linux/delay.h>
  20 #include <linux/errno.h>
  21 #include <linux/fs.h>
  22 #include <linux/genhd.h>
  23 #include <linux/hdreg.h>
  24 #include <linux/idr.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kdev_t.h>
  29 #include <linux/kthread.h>
  30 #include <linux/kernel.h>
  31 #include <linux/mm.h>
  32 #include <linux/module.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/mutex.h>
  35 #include <linux/pci.h>
  36 #include <linux/poison.h>
  37 #include <linux/ptrace.h>
  38 #include <linux/sched.h>
  39 #include <linux/slab.h>
  40 #include <linux/t10-pi.h>
  41 #include <linux/types.h>
  42 #include <linux/io-64-nonatomic-lo-hi.h>
  43 #include <asm/unaligned.h>
  44
  45 #include "nvme.h"
  46
  47 #define NVME_Q_DEPTH            1024
  48 #define NVME_AQ_DEPTH           256
  49 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  50 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  51
  52 unsigned char admin_timeout = 60;
  53 module_param(admin_timeout, byte, 0644);
  54 MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
  55
  56 unsigned char nvme_io_timeout = 30;
  57 module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
  58 MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
  59
  60 unsigned char shutdown_timeout = 5;
  61 module_param(shutdown_timeout, byte, 0644);
  62 MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
  63
  64 static int use_threaded_interrupts;
  65 module_param(use_threaded_interrupts, int, 0);
  66
  67 static bool use_cmb_sqes = true;
  68 module_param(use_cmb_sqes, bool, 0644);
  69 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  70
  71 static LIST_HEAD(dev_list);
  72 static struct task_struct *nvme_thread;
  73 static struct workqueue_struct *nvme_workq;
  74 static wait_queue_head_t nvme_kthread_wait;
  75
  76 struct nvme_dev;
  77 struct nvme_queue;
  78 struct nvme_iod;
  79
  80 static int nvme_reset(struct nvme_dev *dev);
  81 static void nvme_process_cq(struct nvme_queue *nvmeq);
  82 static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod);
  83 static void nvme_dead_ctrl(struct nvme_dev *dev);
  84
  85 struct async_cmd_info {
  86         struct kthread_work work;
  87         struct kthread_worker *worker;
  88         struct request *req;
  89         u32 result;
  90         int status;
  91         void *ctx;
  92 };
  93
  94 /*
  95  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  96  */
  97 struct nvme_dev {
  98         struct list_head node;
  99         struct nvme_queue **queues;
 100         struct blk_mq_tag_set tagset;
 101         struct blk_mq_tag_set admin_tagset;
 102         u32 __iomem *dbs;
 103         struct device *dev;
 104         struct dma_pool *prp_page_pool;
 105         struct dma_pool *prp_small_pool;
 106         unsigned queue_count;
 107         unsigned online_queues;
 108         unsigned max_qid;
 109         int q_depth;
 110         u32 db_stride;
 111         struct msix_entry *entry;
 112         void __iomem *bar;
 113         struct work_struct reset_work;
 114         struct work_struct probe_work;
 115         struct work_struct scan_work;
 116         struct mutex shutdown_lock;
 117         bool subsystem;
 118         void __iomem *cmb;
 119         dma_addr_t cmb_dma_addr;
 120         u64 cmb_size;
 121         u32 cmbsz;
 122
 123         struct nvme_ctrl ctrl;
 124 };
 125
 126 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 127 {
 128         return container_of(ctrl, struct nvme_dev, ctrl);
 129 }
 130
 131 /*
 132  * An NVM Express queue.  Each device has at least two (one for admin
 133  * commands and one for I/O commands).
 134  */
 135 struct nvme_queue {
 136         struct device *q_dmadev;
 137         struct nvme_dev *dev;
 138         char irqname[24];       /* nvme4294967295-65535\0 */
 139         spinlock_t q_lock;
 140         struct nvme_command *sq_cmds;
 141         struct nvme_command __iomem *sq_cmds_io;
 142         volatile struct nvme_completion *cqes;
 143         struct blk_mq_tags **tags;
 144         dma_addr_t sq_dma_addr;
 145         dma_addr_t cq_dma_addr;
 146         u32 __iomem *q_db;
 147         u16 q_depth;
 148         s16 cq_vector;
 149         u16 sq_head;
 150         u16 sq_tail;
 151         u16 cq_head;
 152         u16 qid;
 153         u8 cq_phase;
 154         u8 cqe_seen;
 155         struct async_cmd_info cmdinfo;
 156 };
 157
 158 /*
 159  * The nvme_iod describes the data in an I/O, including the list of PRP
 160  * entries.  You can't see it in this data structure because C doesn't let
 161  * me express that.  Use nvme_alloc_iod to ensure there's enough space
 162  * allocated to store the PRP list.
 163  */
 164 struct nvme_iod {
 165         unsigned long private;  /* For the use of the submitter of the I/O */
 166         int npages;             /* In the PRP list. 0 means small pool in use */
 167         int offset;             /* Of PRP list */
 168         int nents;              /* Used in scatterlist */
 169         int length;             /* Of data, in bytes */
 170         dma_addr_t first_dma;
 171         struct scatterlist meta_sg[1]; /* metadata requires single contiguous buffer */
 172         struct scatterlist sg[0];
 173 };
 174
 175 /*
 176  * Check we didin't inadvertently grow the command struct
 177  */
 178 static inline void _nvme_check_size(void)
 179 {
 180         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 181         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 182         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 183         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 184         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 185         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 186         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 187         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 188         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 189         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 190         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 191         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 192 }
 193
 194 typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
 195                                                 struct nvme_completion *);
 196
 197 struct nvme_cmd_info {
 198         nvme_completion_fn fn;
 199         void *ctx;
 200         int aborted;
 201         struct nvme_queue *nvmeq;
 202         struct nvme_iod iod[0];
 203 };
 204
 205 /*
 206  * Max size of iod being embedded in the request payload
 207  */
 208 #define NVME_INT_PAGES          2
 209 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 210 #define NVME_INT_MASK           0x01
 211
 212 /*
 213  * Will slightly overestimate the number of pages needed.  This is OK
 214  * as it only leads to a small amount of wasted memory for the lifetime of
 215  * the I/O.
 216  */
 217 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 218 {
 219         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 220                                       dev->ctrl.page_size);
 221         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 222 }
 223
 224 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 225 {
 226         unsigned int ret = sizeof(struct nvme_cmd_info);
 227
 228         ret += sizeof(struct nvme_iod);
 229         ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
 230         ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
 231
 232         return ret;
 233 }
 234
 235 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 236                                 unsigned int hctx_idx)
 237 {
 238         struct nvme_dev *dev = data;
 239         struct nvme_queue *nvmeq = dev->queues[0];
 240
 241         WARN_ON(hctx_idx != 0);
 242         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 243         WARN_ON(nvmeq->tags);
 244
 245         hctx->driver_data = nvmeq;
 246         nvmeq->tags = &dev->admin_tagset.tags[0];
 247         return 0;
 248 }
 249
 250 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 251 {
 252         struct nvme_queue *nvmeq = hctx->driver_data;
 253
 254         nvmeq->tags = NULL;
 255 }
 256
 257 static int nvme_admin_init_request(void *data, struct request *req,
 258                                 unsigned int hctx_idx, unsigned int rq_idx,
 259                                 unsigned int numa_node)
 260 {
 261         struct nvme_dev *dev = data;
 262         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
 263         struct nvme_queue *nvmeq = dev->queues[0];
 264
 265         BUG_ON(!nvmeq);
 266         cmd->nvmeq = nvmeq;
 267         return 0;
 268 }
 269
 270 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 271                           unsigned int hctx_idx)
 272 {
 273         struct nvme_dev *dev = data;
 274         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 275
 276         if (!nvmeq->tags)
 277                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 278
 279         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 280         hctx->driver_data = nvmeq;
 281         return 0;
 282 }
 283
 284 static int nvme_init_request(void *data, struct request *req,
 285                                 unsigned int hctx_idx, unsigned int rq_idx,
 286                                 unsigned int numa_node)
 287 {
 288         struct nvme_dev *dev = data;
 289         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
 290         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 291
 292         BUG_ON(!nvmeq);
 293         cmd->nvmeq = nvmeq;
 294         return 0;
 295 }
 296
 297 static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
 298                                 nvme_completion_fn handler)
 299 {
 300         cmd->fn = handler;
 301         cmd->ctx = ctx;
 302         cmd->aborted = 0;
 303         blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
 304 }
 305
 306 static void *iod_get_private(struct nvme_iod *iod)
 307 {
 308         return (void *) (iod->private & ~0x1UL);
 309 }
 310
 311 /*
 312  * If bit 0 is set, the iod is embedded in the request payload.
 313  */
 314 static bool iod_should_kfree(struct nvme_iod *iod)
 315 {
 316         return (iod->private & NVME_INT_MASK) == 0;
 317 }
 318
 319 /* Special values must be less than 0x1000 */
 320 #define CMD_CTX_BASE            ((void *)POISON_POINTER_DELTA)
 321 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
 322 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
 323 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
 324
 325 static void special_completion(struct nvme_queue *nvmeq, void *ctx,
 326                                                 struct nvme_completion *cqe)
 327 {
 328         if (ctx == CMD_CTX_CANCELLED)
 329                 return;
 330         if (ctx == CMD_CTX_COMPLETED) {
 331                 dev_warn(nvmeq->q_dmadev,
 332                                 "completed id %d twice on queue %d\n",
 333                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 334                 return;
 335         }
 336         if (ctx == CMD_CTX_INVALID) {
 337                 dev_warn(nvmeq->q_dmadev,
 338                                 "invalid id %d completed on queue %d\n",
 339                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 340                 return;
 341         }
 342         dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
 343 }
 344
 345 static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
 346 {
 347         void *ctx;
 348
 349         if (fn)
 350                 *fn = cmd->fn;
 351         ctx = cmd->ctx;
 352         cmd->fn = special_completion;
 353         cmd->ctx = CMD_CTX_CANCELLED;
 354         return ctx;
 355 }
 356
 357 static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
 358                                                 struct nvme_completion *cqe)
 359 {
 360         u32 result = le32_to_cpup(&cqe->result);
 361         u16 status = le16_to_cpup(&cqe->status) >> 1;
 362
 363         if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
 364                 ++nvmeq->dev->ctrl.event_limit;
 365         if (status != NVME_SC_SUCCESS)
 366                 return;
 367
 368         switch (result & 0xff07) {
 369         case NVME_AER_NOTICE_NS_CHANGED:
 370                 dev_info(nvmeq->q_dmadev, "rescanning\n");
 371                 schedule_work(&nvmeq->dev->scan_work);
 372         default:
 373                 dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result);
 374         }
 375 }
 376
 377 static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
 378                                                 struct nvme_completion *cqe)
 379 {
 380         struct request *req = ctx;
 381
 382         u16 status = le16_to_cpup(&cqe->status) >> 1;
 383         u32 result = le32_to_cpup(&cqe->result);
 384
 385         blk_mq_free_request(req);
 386
 387         dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
 388         ++nvmeq->dev->ctrl.abort_limit;
 389 }
 390
 391 static void async_completion(struct nvme_queue *nvmeq, void *ctx,
 392                                                 struct nvme_completion *cqe)
 393 {
 394         struct async_cmd_info *cmdinfo = ctx;
 395         cmdinfo->result = le32_to_cpup(&cqe->result);
 396         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 397         queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
 398         blk_mq_free_request(cmdinfo->req);
 399 }
 400
 401 static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
 402                                   unsigned int tag)
 403 {
 404         struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag);
 405
 406         return blk_mq_rq_to_pdu(req);
 407 }
 408
 409 /*
 410  * Called with local interrupts disabled and the q_lock held.  May not sleep.
 411  */
 412 static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
 413                                                 nvme_completion_fn *fn)
 414 {
 415         struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
 416         void *ctx;
 417         if (tag >= nvmeq->q_depth) {
 418                 *fn = special_completion;
 419                 return CMD_CTX_INVALID;
 420         }
 421         if (fn)
 422                 *fn = cmd->fn;
 423         ctx = cmd->ctx;
 424         cmd->fn = special_completion;
 425         cmd->ctx = CMD_CTX_COMPLETED;
 426         return ctx;
 427 }
 428
 429 /**
 430  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 431  * @nvmeq: The queue to use
 432  * @cmd: The command to send
 433  *
 434  * Safe to use from interrupt context
 435  */
 436 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 437                                                 struct nvme_command *cmd)
 438 {
 439         u16 tail = nvmeq->sq_tail;
 440
 441         if (nvmeq->sq_cmds_io)
 442                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 443         else
 444                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 445
 446         if (++tail == nvmeq->q_depth)
 447                 tail = 0;
 448         writel(tail, nvmeq->q_db);
 449         nvmeq->sq_tail = tail;
 450 }
 451
 452 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 453 {
 454         unsigned long flags;
 455         spin_lock_irqsave(&nvmeq->q_lock, flags);
 456         __nvme_submit_cmd(nvmeq, cmd);
 457         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 458 }
 459
 460 static __le64 **iod_list(struct nvme_iod *iod)
 461 {
 462         return ((void *)iod) + iod->offset;
 463 }
 464
 465 static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
 466                             unsigned nseg, unsigned long private)
 467 {
 468         iod->private = private;
 469         iod->offset = offsetof(struct nvme_iod, sg[nseg]);
 470         iod->npages = -1;
 471         iod->length = nbytes;
 472         iod->nents = 0;
 473 }
 474
 475 static struct nvme_iod *
 476 __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
 477                  unsigned long priv, gfp_t gfp)
 478 {
 479         struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
 480                                 sizeof(__le64 *) * nvme_npages(bytes, dev) +
 481                                 sizeof(struct scatterlist) * nseg, gfp);
 482
 483         if (iod)
 484                 iod_init(iod, bytes, nseg, priv);
 485
 486         return iod;
 487 }
 488
 489 static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
 490                                        gfp_t gfp)
 491 {
 492         unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
 493                                                 sizeof(struct nvme_dsm_range);
 494         struct nvme_iod *iod;
 495
 496         if (rq->nr_phys_segments <= NVME_INT_PAGES &&
 497             size <= NVME_INT_BYTES(dev)) {
 498                 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
 499
 500                 iod = cmd->iod;
 501                 iod_init(iod, size, rq->nr_phys_segments,
 502                                 (unsigned long) rq | NVME_INT_MASK);
 503                 return iod;
 504         }
 505
 506         return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
 507                                 (unsigned long) rq, gfp);
 508 }
 509
 510 static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
 511 {
 512         const int last_prp = dev->ctrl.page_size / 8 - 1;
 513         int i;
 514         __le64 **list = iod_list(iod);
 515         dma_addr_t prp_dma = iod->first_dma;
 516
 517         if (iod->npages == 0)
 518                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 519         for (i = 0; i < iod->npages; i++) {
 520                 __le64 *prp_list = list[i];
 521                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 522                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 523                 prp_dma = next_prp_dma;
 524         }
 525
 526         if (iod_should_kfree(iod))
 527                 kfree(iod);
 528 }
 529
 530 #ifdef CONFIG_BLK_DEV_INTEGRITY
 531 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 532 {
 533         if (be32_to_cpu(pi->ref_tag) == v)
 534                 pi->ref_tag = cpu_to_be32(p);
 535 }
 536
 537 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 538 {
 539         if (be32_to_cpu(pi->ref_tag) == p)
 540                 pi->ref_tag = cpu_to_be32(v);
 541 }
 542
 543 /**
 544  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 545  *
 546  * The virtual start sector is the one that was originally submitted by the
 547  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 548  * start sector may be different. Remap protection information to match the
 549  * physical LBA on writes, and back to the original seed on reads.
 550  *
 551  * Type 0 and 3 do not have a ref tag, so no remapping required.
 552  */
 553 static void nvme_dif_remap(struct request *req,
 554                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 555 {
 556         struct nvme_ns *ns = req->rq_disk->private_data;
 557         struct bio_integrity_payload *bip;
 558         struct t10_pi_tuple *pi;
 559         void *p, *pmap;
 560         u32 i, nlb, ts, phys, virt;
 561
 562         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 563                 return;
 564
 565         bip = bio_integrity(req->bio);
 566         if (!bip)
 567                 return;
 568
 569         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 570
 571         p = pmap;
 572         virt = bip_get_seed(bip);
 573         phys = nvme_block_nr(ns, blk_rq_pos(req));
 574         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 575         ts = ns->disk->queue->integrity.tuple_size;
 576
 577         for (i = 0; i < nlb; i++, virt++, phys++) {
 578                 pi = (struct t10_pi_tuple *)p;
 579                 dif_swap(phys, virt, pi);
 580                 p += ts;
 581         }
 582         kunmap_atomic(pmap);
 583 }
 584 #else /* CONFIG_BLK_DEV_INTEGRITY */
 585 static void nvme_dif_remap(struct request *req,
 586                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 587 {
 588 }
 589 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 590 {
 591 }
 592 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 593 {
 594 }
 595 #endif
 596
 597 static void req_completion(struct nvme_queue *nvmeq, void *ctx,
 598                                                 struct nvme_completion *cqe)
 599 {
 600         struct nvme_iod *iod = ctx;
 601         struct request *req = iod_get_private(iod);
 602         struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
 603         u16 status = le16_to_cpup(&cqe->status) >> 1;
 604         int error = 0;
 605
 606         if (unlikely(status)) {
 607                 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
 608                     && (jiffies - req->start_time) < req->timeout) {
 609                         unsigned long flags;
 610
 611                         nvme_unmap_data(nvmeq->dev, iod);
 612
 613                         blk_mq_requeue_request(req);
 614                         spin_lock_irqsave(req->q->queue_lock, flags);
 615                         if (!blk_queue_stopped(req->q))
 616                                 blk_mq_kick_requeue_list(req->q);
 617                         spin_unlock_irqrestore(req->q->queue_lock, flags);
 618                         return;
 619                 }
 620
 621                 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
 622                         if (cmd_rq->ctx == CMD_CTX_CANCELLED)
 623                                 error = NVME_SC_CANCELLED;
 624                         else
 625                                 error = status;
 626                 } else {
 627                         error = nvme_error_status(status);
 628                 }
 629         }
 630
 631         if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
 632                 u32 result = le32_to_cpup(&cqe->result);
 633                 req->special = (void *)(uintptr_t)result;
 634         }
 635
 636         if (cmd_rq->aborted)
 637                 dev_warn(nvmeq->dev->dev,
 638                         "completing aborted command with status:%04x\n",
 639                         error);
 640
 641         nvme_unmap_data(nvmeq->dev, iod);
 642         blk_mq_complete_request(req, error);
 643 }
 644
 645 static bool nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod,
 646                 int total_len)
 647 {
 648         struct dma_pool *pool;
 649         int length = total_len;
 650         struct scatterlist *sg = iod->sg;
 651         int dma_len = sg_dma_len(sg);
 652         u64 dma_addr = sg_dma_address(sg);
 653         u32 page_size = dev->ctrl.page_size;
 654         int offset = dma_addr & (page_size - 1);
 655         __le64 *prp_list;
 656         __le64 **list = iod_list(iod);
 657         dma_addr_t prp_dma;
 658         int nprps, i;
 659
 660         length -= (page_size - offset);
 661         if (length <= 0)
 662                 return true;
 663
 664         dma_len -= (page_size - offset);
 665         if (dma_len) {
 666                 dma_addr += (page_size - offset);
 667         } else {
 668                 sg = sg_next(sg);
 669                 dma_addr = sg_dma_address(sg);
 670                 dma_len = sg_dma_len(sg);
 671         }
 672
 673         if (length <= page_size) {
 674                 iod->first_dma = dma_addr;
 675                 return true;
 676         }
 677
 678         nprps = DIV_ROUND_UP(length, page_size);
 679         if (nprps <= (256 / 8)) {
 680                 pool = dev->prp_small_pool;
 681                 iod->npages = 0;
 682         } else {
 683                 pool = dev->prp_page_pool;
 684                 iod->npages = 1;
 685         }
 686
 687         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 688         if (!prp_list) {
 689                 iod->first_dma = dma_addr;
 690                 iod->npages = -1;
 691                 return false;
 692         }
 693         list[0] = prp_list;
 694         iod->first_dma = prp_dma;
 695         i = 0;
 696         for (;;) {
 697                 if (i == page_size >> 3) {
 698                         __le64 *old_prp_list = prp_list;
 699                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 700                         if (!prp_list)
 701                                 return false;
 702                         list[iod->npages++] = prp_list;
 703                         prp_list[0] = old_prp_list[i - 1];
 704                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 705                         i = 1;
 706                 }
 707                 prp_list[i++] = cpu_to_le64(dma_addr);
 708                 dma_len -= page_size;
 709                 dma_addr += page_size;
 710                 length -= page_size;
 711                 if (length <= 0)
 712                         break;
 713                 if (dma_len > 0)
 714                         continue;
 715                 BUG_ON(dma_len < 0);
 716                 sg = sg_next(sg);
 717                 dma_addr = sg_dma_address(sg);
 718                 dma_len = sg_dma_len(sg);
 719         }
 720
 721         return true;
 722 }
 723
 724 static int nvme_map_data(struct nvme_dev *dev, struct nvme_iod *iod,
 725                 struct nvme_command *cmnd)
 726 {
 727         struct request *req = iod_get_private(iod);
 728         struct request_queue *q = req->q;
 729         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 730                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 731         int ret = BLK_MQ_RQ_QUEUE_ERROR;
 732
 733         sg_init_table(iod->sg, req->nr_phys_segments);
 734         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 735         if (!iod->nents)
 736                 goto out;
 737
 738         ret = BLK_MQ_RQ_QUEUE_BUSY;
 739         if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir))
 740                 goto out;
 741
 742         if (!nvme_setup_prps(dev, iod, blk_rq_bytes(req)))
 743                 goto out_unmap;
 744
 745         ret = BLK_MQ_RQ_QUEUE_ERROR;
 746         if (blk_integrity_rq(req)) {
 747                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 748                         goto out_unmap;
 749
 750                 sg_init_table(iod->meta_sg, 1);
 751                 if (blk_rq_map_integrity_sg(q, req->bio, iod->meta_sg) != 1)
 752                         goto out_unmap;
 753
 754                 if (rq_data_dir(req))
 755                         nvme_dif_remap(req, nvme_dif_prep);
 756
 757                 if (!dma_map_sg(dev->dev, iod->meta_sg, 1, dma_dir))
 758                         goto out_unmap;
 759         }
 760
 761         cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 762         cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
 763         if (blk_integrity_rq(req))
 764                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg));
 765         return BLK_MQ_RQ_QUEUE_OK;
 766
 767 out_unmap:
 768         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 769 out:
 770         return ret;
 771 }
 772
 773 static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod)
 774 {
 775         struct request *req = iod_get_private(iod);
 776         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 777                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 778
 779         if (iod->nents) {
 780                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 781                 if (blk_integrity_rq(req)) {
 782                         if (!rq_data_dir(req))
 783                                 nvme_dif_remap(req, nvme_dif_complete);
 784                         dma_unmap_sg(dev->dev, iod->meta_sg, 1, dma_dir);
 785                 }
 786         }
 787
 788         nvme_free_iod(dev, iod);
 789 }
 790
 791 /*
 792  * We reuse the small pool to allocate the 16-byte range here as it is not
 793  * worth having a special pool for these or additional cases to handle freeing
 794  * the iod.
 795  */
 796 static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 797                 struct nvme_iod *iod, struct nvme_command *cmnd)
 798 {
 799         struct request *req = iod_get_private(iod);
 800         struct nvme_dsm_range *range;
 801
 802         range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC,
 803                                                 &iod->first_dma);
 804         if (!range)
 805                 return BLK_MQ_RQ_QUEUE_BUSY;
 806         iod_list(iod)[0] = (__le64 *)range;
 807         iod->npages = 0;
 808
 809         range->cattr = cpu_to_le32(0);
 810         range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
 811         range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
 812
 813         memset(cmnd, 0, sizeof(*cmnd));
 814         cmnd->dsm.opcode = nvme_cmd_dsm;
 815         cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
 816         cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
 817         cmnd->dsm.nr = 0;
 818         cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
 819         return BLK_MQ_RQ_QUEUE_OK;
 820 }
 821
 822 /*
 823  * NOTE: ns is NULL when called on the admin queue.
 824  */
 825 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 826                          const struct blk_mq_queue_data *bd)
 827 {
 828         struct nvme_ns *ns = hctx->queue->queuedata;
 829         struct nvme_queue *nvmeq = hctx->driver_data;
 830         struct nvme_dev *dev = nvmeq->dev;
 831         struct request *req = bd->rq;
 832         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
 833         struct nvme_iod *iod;
 834         struct nvme_command cmnd;
 835         int ret = BLK_MQ_RQ_QUEUE_OK;
 836
 837         /*
 838          * If formated with metadata, require the block layer provide a buffer
 839          * unless this namespace is formated such that the metadata can be
 840          * stripped/generated by the controller with PRACT=1.
 841          */
 842         if (ns && ns->ms && !blk_integrity_rq(req)) {
 843                 if (!(ns->pi_type && ns->ms == 8) &&
 844                                         req->cmd_type != REQ_TYPE_DRV_PRIV) {
 845                         blk_mq_complete_request(req, -EFAULT);
 846                         return BLK_MQ_RQ_QUEUE_OK;
 847                 }
 848         }
 849
 850         iod = nvme_alloc_iod(req, dev, GFP_ATOMIC);
 851         if (!iod)
 852                 return BLK_MQ_RQ_QUEUE_BUSY;
 853
 854         if (req->cmd_flags & REQ_DISCARD) {
 855                 ret = nvme_setup_discard(nvmeq, ns, iod, &cmnd);
 856         } else {
 857                 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
 858                         memcpy(&cmnd, req->cmd, sizeof(cmnd));
 859                 else if (req->cmd_flags & REQ_FLUSH)
 860                         nvme_setup_flush(ns, &cmnd);
 861                 else
 862                         nvme_setup_rw(ns, req, &cmnd);
 863
 864                 if (req->nr_phys_segments)
 865                         ret = nvme_map_data(dev, iod, &cmnd);
 866         }
 867
 868         if (ret)
 869                 goto out;
 870
 871         cmnd.common.command_id = req->tag;
 872         nvme_set_info(cmd, iod, req_completion);
 873
 874         spin_lock_irq(&nvmeq->q_lock);
 875         __nvme_submit_cmd(nvmeq, &cmnd);
 876         nvme_process_cq(nvmeq);
 877         spin_unlock_irq(&nvmeq->q_lock);
 878         return BLK_MQ_RQ_QUEUE_OK;
 879 out:
 880         nvme_free_iod(dev, iod);
 881         return ret;
 882 }
 883
 884 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
 885 {
 886         u16 head, phase;
 887
 888         head = nvmeq->cq_head;
 889         phase = nvmeq->cq_phase;
 890
 891         for (;;) {
 892                 void *ctx;
 893                 nvme_completion_fn fn;
 894                 struct nvme_completion cqe = nvmeq->cqes[head];
 895                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 896                         break;
 897                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 898                 if (++head == nvmeq->q_depth) {
 899                         head = 0;
 900                         phase = !phase;
 901                 }
 902                 if (tag && *tag == cqe.command_id)
 903                         *tag = -1;
 904                 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
 905                 fn(nvmeq, ctx, &cqe);
 906         }
 907
 908         /* If the controller ignores the cq head doorbell and continuously
 909          * writes to the queue, it is theoretically possible to wrap around
 910          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 911          * requires that 0.1% of your interrupts are handled, so this isn't
 912          * a big problem.
 913          */
 914         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 915                 return;
 916
 917         if (likely(nvmeq->cq_vector >= 0))
 918                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 919         nvmeq->cq_head = head;
 920         nvmeq->cq_phase = phase;
 921
 922         nvmeq->cqe_seen = 1;
 923 }
 924
 925 static void nvme_process_cq(struct nvme_queue *nvmeq)
 926 {
 927         __nvme_process_cq(nvmeq, NULL);
 928 }
 929
 930 static irqreturn_t nvme_irq(int irq, void *data)
 931 {
 932         irqreturn_t result;
 933         struct nvme_queue *nvmeq = data;
 934         spin_lock(&nvmeq->q_lock);
 935         nvme_process_cq(nvmeq);
 936         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 937         nvmeq->cqe_seen = 0;
 938         spin_unlock(&nvmeq->q_lock);
 939         return result;
 940 }
 941
 942 static irqreturn_t nvme_irq_check(int irq, void *data)
 943 {
 944         struct nvme_queue *nvmeq = data;
 945         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 946         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 947                 return IRQ_NONE;
 948         return IRQ_WAKE_THREAD;
 949 }
 950
 951 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
 952 {
 953         struct nvme_queue *nvmeq = hctx->driver_data;
 954
 955         if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
 956             nvmeq->cq_phase) {
 957                 spin_lock_irq(&nvmeq->q_lock);
 958                 __nvme_process_cq(nvmeq, &tag);
 959                 spin_unlock_irq(&nvmeq->q_lock);
 960
 961                 if (tag == -1)
 962                         return 1;
 963         }
 964
 965         return 0;
 966 }
 967
 968 static int nvme_submit_async_admin_req(struct nvme_dev *dev)
 969 {
 970         struct nvme_queue *nvmeq = dev->queues[0];
 971         struct nvme_command c;
 972         struct nvme_cmd_info *cmd_info;
 973         struct request *req;
 974
 975         req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE,
 976                         BLK_MQ_REQ_NOWAIT | BLK_MQ_REQ_RESERVED);
 977         if (IS_ERR(req))
 978                 return PTR_ERR(req);
 979
 980         req->cmd_flags |= REQ_NO_TIMEOUT;
 981         cmd_info = blk_mq_rq_to_pdu(req);
 982         nvme_set_info(cmd_info, NULL, async_req_completion);
 983
 984         memset(&c, 0, sizeof(c));
 985         c.common.opcode = nvme_admin_async_event;
 986         c.common.command_id = req->tag;
 987
 988         blk_mq_free_request(req);
 989         __nvme_submit_cmd(nvmeq, &c);
 990         return 0;
 991 }
 992
 993 static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
 994                         struct nvme_command *cmd,
 995                         struct async_cmd_info *cmdinfo, unsigned timeout)
 996 {
 997         struct nvme_queue *nvmeq = dev->queues[0];
 998         struct request *req;
 999         struct nvme_cmd_info *cmd_rq;
1000
1001         req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, 0);
1002         if (IS_ERR(req))
1003                 return PTR_ERR(req);
1004
1005         req->timeout = timeout;
1006         cmd_rq = blk_mq_rq_to_pdu(req);
1007         cmdinfo->req = req;
1008         nvme_set_info(cmd_rq, cmdinfo, async_completion);
1009         cmdinfo->status = -EINTR;
1010
1011         cmd->common.command_id = req->tag;
1012
1013         nvme_submit_cmd(nvmeq, cmd);
1014         return 0;
1015 }
1016
1017 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1018 {
1019         struct nvme_command c;
1020
1021         memset(&c, 0, sizeof(c));
1022         c.delete_queue.opcode = opcode;
1023         c.delete_queue.qid = cpu_to_le16(id);
1024
1025         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1026 }
1027
1028 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1029                                                 struct nvme_queue *nvmeq)
1030 {
1031         struct nvme_command c;
1032         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1033
1034         /*
1035          * Note: we (ab)use the fact the the prp fields survive if no data
1036          * is attached to the request.
1037          */
1038         memset(&c, 0, sizeof(c));
1039         c.create_cq.opcode = nvme_admin_create_cq;
1040         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1041         c.create_cq.cqid = cpu_to_le16(qid);
1042         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1043         c.create_cq.cq_flags = cpu_to_le16(flags);
1044         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1045
1046         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1047 }
1048
1049 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1050                                                 struct nvme_queue *nvmeq)
1051 {
1052         struct nvme_command c;
1053         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1054
1055         /*
1056          * Note: we (ab)use the fact the the prp fields survive if no data
1057          * is attached to the request.
1058          */
1059         memset(&c, 0, sizeof(c));
1060         c.create_sq.opcode = nvme_admin_create_sq;
1061         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1062         c.create_sq.sqid = cpu_to_le16(qid);
1063         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1064         c.create_sq.sq_flags = cpu_to_le16(flags);
1065         c.create_sq.cqid = cpu_to_le16(qid);
1066
1067         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1068 }
1069
1070 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1071 {
1072         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1073 }
1074
1075 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1076 {
1077         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1078 }
1079
1080 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1081 {
1082         struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1083         struct nvme_queue *nvmeq = cmd_rq->nvmeq;
1084         struct nvme_dev *dev = nvmeq->dev;
1085         struct request *abort_req;
1086         struct nvme_cmd_info *abort_cmd;
1087         struct nvme_command cmd;
1088
1089         /*
1090          * Schedule controller reset if the command was already aborted once
1091          * before and still hasn't been returned to the driver, or if this is
1092          * the admin queue.
1093          */
1094         if (!nvmeq->qid || cmd_rq->aborted) {
1095                 if (queue_work(nvme_workq, &dev->reset_work)) {
1096                         dev_warn(dev->dev,
1097                                  "I/O %d QID %d timeout, reset controller\n",
1098                                  req->tag, nvmeq->qid);
1099                 }
1100                 return BLK_EH_RESET_TIMER;
1101         }
1102
1103         if (!dev->ctrl.abort_limit)
1104                 return BLK_EH_RESET_TIMER;
1105
1106         abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE,
1107                         BLK_MQ_REQ_NOWAIT);
1108         if (IS_ERR(abort_req))
1109                 return BLK_EH_RESET_TIMER;
1110
1111         abort_cmd = blk_mq_rq_to_pdu(abort_req);
1112         nvme_set_info(abort_cmd, abort_req, abort_completion);
1113
1114         memset(&cmd, 0, sizeof(cmd));
1115         cmd.abort.opcode = nvme_admin_abort_cmd;
1116         cmd.abort.cid = req->tag;
1117         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1118         cmd.abort.command_id = abort_req->tag;
1119
1120         --dev->ctrl.abort_limit;
1121         cmd_rq->aborted = 1;
1122
1123         dev_warn(nvmeq->q_dmadev, "I/O %d QID %d timeout, aborting\n",
1124                                  req->tag, nvmeq->qid);
1125         nvme_submit_cmd(dev->queues[0], &cmd);
1126
1127         /*
1128          * The aborted req will be completed on receiving the abort req.
1129          * We enable the timer again. If hit twice, it'll cause a device reset,
1130          * as the device then is in a faulty state.
1131          */
1132         return BLK_EH_RESET_TIMER;
1133 }
1134
1135 static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
1136 {
1137         struct nvme_queue *nvmeq = data;
1138         void *ctx;
1139         nvme_completion_fn fn;
1140         struct nvme_cmd_info *cmd;
1141         struct nvme_completion cqe;
1142
1143         if (!blk_mq_request_started(req))
1144                 return;
1145
1146         cmd = blk_mq_rq_to_pdu(req);
1147
1148         if (cmd->ctx == CMD_CTX_CANCELLED)
1149                 return;
1150
1151         if (blk_queue_dying(req->q))
1152                 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1153         else
1154                 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1155
1156
1157         dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1158                                                 req->tag, nvmeq->qid);
1159         ctx = cancel_cmd_info(cmd, &fn);
1160         fn(nvmeq, ctx, &cqe);
1161 }
1162
1163 static void nvme_free_queue(struct nvme_queue *nvmeq)
1164 {
1165         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1166                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1167         if (nvmeq->sq_cmds)
1168                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1169                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1170         kfree(nvmeq);
1171 }
1172
1173 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1174 {
1175         int i;
1176
1177         for (i = dev->queue_count - 1; i >= lowest; i--) {
1178                 struct nvme_queue *nvmeq = dev->queues[i];
1179                 dev->queue_count--;
1180                 dev->queues[i] = NULL;
1181                 nvme_free_queue(nvmeq);
1182         }
1183 }
1184
1185 /**
1186  * nvme_suspend_queue - put queue into suspended state
1187  * @nvmeq - queue to suspend
1188  */
1189 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1190 {
1191         int vector;
1192
1193         spin_lock_irq(&nvmeq->q_lock);
1194         if (nvmeq->cq_vector == -1) {
1195                 spin_unlock_irq(&nvmeq->q_lock);
1196                 return 1;
1197         }
1198         vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1199         nvmeq->dev->online_queues--;
1200         nvmeq->cq_vector = -1;
1201         spin_unlock_irq(&nvmeq->q_lock);
1202
1203         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1204                 blk_mq_freeze_queue_start(nvmeq->dev->ctrl.admin_q);
1205
1206         irq_set_affinity_hint(vector, NULL);
1207         free_irq(vector, nvmeq);
1208
1209         return 0;
1210 }
1211
1212 static void nvme_clear_queue(struct nvme_queue *nvmeq)
1213 {
1214         spin_lock_irq(&nvmeq->q_lock);
1215         if (nvmeq->tags && *nvmeq->tags)
1216                 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
1217         spin_unlock_irq(&nvmeq->q_lock);
1218 }
1219
1220 static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1221 {
1222         struct nvme_queue *nvmeq = dev->queues[qid];
1223
1224         if (!nvmeq)
1225                 return;
1226         if (nvme_suspend_queue(nvmeq))
1227                 return;
1228
1229         /* Don't tell the adapter to delete the admin queue.
1230          * Don't tell a removed adapter to delete IO queues. */
1231         if (qid && readl(dev->bar + NVME_REG_CSTS) != -1) {
1232                 adapter_delete_sq(dev, qid);
1233                 adapter_delete_cq(dev, qid);
1234         }
1235
1236         spin_lock_irq(&nvmeq->q_lock);
1237         nvme_process_cq(nvmeq);
1238         spin_unlock_irq(&nvmeq->q_lock);
1239 }
1240
1241 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1242                                 int entry_size)
1243 {
1244         int q_depth = dev->q_depth;
1245         unsigned q_size_aligned = roundup(q_depth * entry_size,
1246                                           dev->ctrl.page_size);
1247
1248         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1249                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1250                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1251                 q_depth = div_u64(mem_per_q, entry_size);
1252
1253                 /*
1254                  * Ensure the reduced q_depth is above some threshold where it
1255                  * would be better to map queues in system memory with the
1256                  * original depth
1257                  */
1258                 if (q_depth < 64)
1259                         return -ENOMEM;
1260         }
1261
1262         return q_depth;
1263 }
1264
1265 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1266                                 int qid, int depth)
1267 {
1268         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1269                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1270                                                       dev->ctrl.page_size);
1271                 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1272                 nvmeq->sq_cmds_io = dev->cmb + offset;
1273         } else {
1274                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1275                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1276                 if (!nvmeq->sq_cmds)
1277                         return -ENOMEM;
1278         }
1279
1280         return 0;
1281 }
1282
1283 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1284                                                         int depth)
1285 {
1286         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1287         if (!nvmeq)
1288                 return NULL;
1289
1290         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1291                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1292         if (!nvmeq->cqes)
1293                 goto free_nvmeq;
1294
1295         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1296                 goto free_cqdma;
1297
1298         nvmeq->q_dmadev = dev->dev;
1299         nvmeq->dev = dev;
1300         snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1301                         dev->ctrl.instance, qid);
1302         spin_lock_init(&nvmeq->q_lock);
1303         nvmeq->cq_head = 0;
1304         nvmeq->cq_phase = 1;
1305         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1306         nvmeq->q_depth = depth;
1307         nvmeq->qid = qid;
1308         nvmeq->cq_vector = -1;
1309         dev->queues[qid] = nvmeq;
1310
1311         /* make sure queue descriptor is set before queue count, for kthread */
1312         mb();
1313         dev->queue_count++;
1314
1315         return nvmeq;
1316
1317  free_cqdma:
1318         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1319                                                         nvmeq->cq_dma_addr);
1320  free_nvmeq:
1321         kfree(nvmeq);
1322         return NULL;
1323 }
1324
1325 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1326                                                         const char *name)
1327 {
1328         if (use_threaded_interrupts)
1329                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1330                                         nvme_irq_check, nvme_irq, IRQF_SHARED,
1331                                         name, nvmeq);
1332         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1333                                 IRQF_SHARED, name, nvmeq);
1334 }
1335
1336 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1337 {
1338         struct nvme_dev *dev = nvmeq->dev;
1339
1340         spin_lock_irq(&nvmeq->q_lock);
1341         nvmeq->sq_tail = 0;
1342         nvmeq->cq_head = 0;
1343         nvmeq->cq_phase = 1;
1344         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1345         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1346         dev->online_queues++;
1347         spin_unlock_irq(&nvmeq->q_lock);
1348 }
1349
1350 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1351 {
1352         struct nvme_dev *dev = nvmeq->dev;
1353         int result;
1354
1355         nvmeq->cq_vector = qid - 1;
1356         result = adapter_alloc_cq(dev, qid, nvmeq);
1357         if (result < 0)
1358                 return result;
1359
1360         result = adapter_alloc_sq(dev, qid, nvmeq);
1361         if (result < 0)
1362                 goto release_cq;
1363
1364         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1365         if (result < 0)
1366                 goto release_sq;
1367
1368         nvme_init_queue(nvmeq, qid);
1369         return result;
1370
1371  release_sq:
1372         adapter_delete_sq(dev, qid);
1373  release_cq:
1374         adapter_delete_cq(dev, qid);
1375         return result;
1376 }
1377
1378 static struct blk_mq_ops nvme_mq_admin_ops = {
1379         .queue_rq       = nvme_queue_rq,
1380         .map_queue      = blk_mq_map_queue,
1381         .init_hctx      = nvme_admin_init_hctx,
1382         .exit_hctx      = nvme_admin_exit_hctx,
1383         .init_request   = nvme_admin_init_request,
1384         .timeout        = nvme_timeout,
1385 };
1386
1387 static struct blk_mq_ops nvme_mq_ops = {
1388         .queue_rq       = nvme_queue_rq,
1389         .map_queue      = blk_mq_map_queue,
1390         .init_hctx      = nvme_init_hctx,
1391         .init_request   = nvme_init_request,
1392         .timeout        = nvme_timeout,
1393         .poll           = nvme_poll,
1394 };
1395
1396 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1397 {
1398         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1399                 blk_cleanup_queue(dev->ctrl.admin_q);
1400                 blk_mq_free_tag_set(&dev->admin_tagset);
1401         }
1402 }
1403
1404 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1405 {
1406         if (!dev->ctrl.admin_q) {
1407                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1408                 dev->admin_tagset.nr_hw_queues = 1;
1409                 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1410                 dev->admin_tagset.reserved_tags = 1;
1411                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1412                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1413                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1414                 dev->admin_tagset.driver_data = dev;
1415
1416                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1417                         return -ENOMEM;
1418
1419                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1420                 if (IS_ERR(dev->ctrl.admin_q)) {
1421                         blk_mq_free_tag_set(&dev->admin_tagset);
1422                         return -ENOMEM;
1423                 }
1424                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1425                         nvme_dev_remove_admin(dev);
1426                         dev->ctrl.admin_q = NULL;
1427                         return -ENODEV;
1428                 }
1429         } else
1430                 blk_mq_unfreeze_queue(dev->ctrl.admin_q);
1431
1432         return 0;
1433 }
1434
1435 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1436 {
1437         int result;
1438         u32 aqa;
1439         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1440         struct nvme_queue *nvmeq;
1441
1442         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ?
1443                                                 NVME_CAP_NSSRC(cap) : 0;
1444
1445         if (dev->subsystem &&
1446             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1447                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1448
1449         result = nvme_disable_ctrl(&dev->ctrl, cap);
1450         if (result < 0)
1451                 return result;
1452
1453         nvmeq = dev->queues[0];
1454         if (!nvmeq) {
1455                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1456                 if (!nvmeq)
1457                         return -ENOMEM;
1458         }
1459
1460         aqa = nvmeq->q_depth - 1;
1461         aqa |= aqa << 16;
1462
1463         writel(aqa, dev->bar + NVME_REG_AQA);
1464         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1465         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1466
1467         result = nvme_enable_ctrl(&dev->ctrl, cap);
1468         if (result)
1469                 goto free_nvmeq;
1470
1471         nvmeq->cq_vector = 0;
1472         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1473         if (result) {
1474                 nvmeq->cq_vector = -1;
1475                 goto free_nvmeq;
1476         }
1477
1478         return result;
1479
1480  free_nvmeq:
1481         nvme_free_queues(dev, 0);
1482         return result;
1483 }
1484
1485 static int nvme_kthread(void *data)
1486 {
1487         struct nvme_dev *dev, *next;
1488
1489         while (!kthread_should_stop()) {
1490                 set_current_state(TASK_INTERRUPTIBLE);
1491                 spin_lock(&dev_list_lock);
1492                 list_for_each_entry_safe(dev, next, &dev_list, node) {
1493                         int i;
1494                         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1495
1496                         /*
1497                          * Skip controllers currently under reset.
1498                          */
1499                         if (work_pending(&dev->reset_work) || work_busy(&dev->reset_work))
1500                                 continue;
1501
1502                         if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) ||
1503                                                         csts & NVME_CSTS_CFS) {
1504                                 if (queue_work(nvme_workq, &dev->reset_work)) {
1505                                         dev_warn(dev->dev,
1506                                                 "Failed status: %x, reset controller\n",
1507                                                 readl(dev->bar + NVME_REG_CSTS));
1508                                 }
1509                                 continue;
1510                         }
1511                         for (i = 0; i < dev->queue_count; i++) {
1512                                 struct nvme_queue *nvmeq = dev->queues[i];
1513                                 if (!nvmeq)
1514                                         continue;
1515                                 spin_lock_irq(&nvmeq->q_lock);
1516                                 nvme_process_cq(nvmeq);
1517
1518                                 while (i == 0 && dev->ctrl.event_limit > 0) {
1519                                         if (nvme_submit_async_admin_req(dev))
1520                                                 break;
1521                                         dev->ctrl.event_limit--;
1522                                 }
1523                                 spin_unlock_irq(&nvmeq->q_lock);
1524                         }
1525                 }
1526                 spin_unlock(&dev_list_lock);
1527                 schedule_timeout(round_jiffies_relative(HZ));
1528         }
1529         return 0;
1530 }
1531
1532 static int nvme_create_io_queues(struct nvme_dev *dev)
1533 {
1534         unsigned i;
1535         int ret = 0;
1536
1537         for (i = dev->queue_count; i <= dev->max_qid; i++) {
1538                 if (!nvme_alloc_queue(dev, i, dev->q_depth)) {
1539                         ret = -ENOMEM;
1540                         break;
1541                 }
1542         }
1543
1544         for (i = dev->online_queues; i <= dev->queue_count - 1; i++) {
1545                 ret = nvme_create_queue(dev->queues[i], i);
1546                 if (ret) {
1547                         nvme_free_queues(dev, i);
1548                         break;
1549                 }
1550         }
1551
1552         /*
1553          * Ignore failing Create SQ/CQ commands, we can continue with less
1554          * than the desired aount of queues, and even a controller without
1555          * I/O queues an still be used to issue admin commands.  This might
1556          * be useful to upgrade a buggy firmware for example.
1557          */
1558         return ret >= 0 ? 0 : ret;
1559 }
1560
1561 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1562 {
1563         u64 szu, size, offset;
1564         u32 cmbloc;
1565         resource_size_t bar_size;
1566         struct pci_dev *pdev = to_pci_dev(dev->dev);
1567         void __iomem *cmb;
1568         dma_addr_t dma_addr;
1569
1570         if (!use_cmb_sqes)
1571                 return NULL;
1572
1573         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1574         if (!(NVME_CMB_SZ(dev->cmbsz)))
1575                 return NULL;
1576
1577         cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1578
1579         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1580         size = szu * NVME_CMB_SZ(dev->cmbsz);
1581         offset = szu * NVME_CMB_OFST(cmbloc);
1582         bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
1583
1584         if (offset > bar_size)
1585                 return NULL;
1586
1587         /*
1588          * Controllers may support a CMB size larger than their BAR,
1589          * for example, due to being behind a bridge. Reduce the CMB to
1590          * the reported size of the BAR
1591          */
1592         if (size > bar_size - offset)
1593                 size = bar_size - offset;
1594
1595         dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
1596         cmb = ioremap_wc(dma_addr, size);
1597         if (!cmb)
1598                 return NULL;
1599
1600         dev->cmb_dma_addr = dma_addr;
1601         dev->cmb_size = size;
1602         return cmb;
1603 }
1604
1605 static inline void nvme_release_cmb(struct nvme_dev *dev)
1606 {
1607         if (dev->cmb) {
1608                 iounmap(dev->cmb);
1609                 dev->cmb = NULL;
1610         }
1611 }
1612
1613 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1614 {
1615         return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1616 }
1617
1618 static int nvme_setup_io_queues(struct nvme_dev *dev)
1619 {
1620         struct nvme_queue *adminq = dev->queues[0];
1621         struct pci_dev *pdev = to_pci_dev(dev->dev);
1622         int result, i, vecs, nr_io_queues, size;
1623
1624         nr_io_queues = num_possible_cpus();
1625         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1626         if (result < 0)
1627                 return result;
1628
1629         /*
1630          * Degraded controllers might return an error when setting the queue
1631          * count.  We still want to be able to bring them online and offer
1632          * access to the admin queue, as that might be only way to fix them up.
1633          */
1634         if (result > 0) {
1635                 dev_err(dev->dev, "Could not set queue count (%d)\n", result);
1636                 nr_io_queues = 0;
1637                 result = 0;
1638         }
1639
1640         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1641                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1642                                 sizeof(struct nvme_command));
1643                 if (result > 0)
1644                         dev->q_depth = result;
1645                 else
1646                         nvme_release_cmb(dev);
1647         }
1648
1649         size = db_bar_size(dev, nr_io_queues);
1650         if (size > 8192) {
1651                 iounmap(dev->bar);
1652                 do {
1653                         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1654                         if (dev->bar)
1655                                 break;
1656                         if (!--nr_io_queues)
1657                                 return -ENOMEM;
1658                         size = db_bar_size(dev, nr_io_queues);
1659                 } while (1);
1660                 dev->dbs = dev->bar + 4096;
1661                 adminq->q_db = dev->dbs;
1662         }
1663
1664         /* Deregister the admin queue's interrupt */
1665         free_irq(dev->entry[0].vector, adminq);
1666
1667         /*
1668          * If we enable msix early due to not intx, disable it again before
1669          * setting up the full range we need.
1670          */
1671         if (!pdev->irq)
1672                 pci_disable_msix(pdev);
1673
1674         for (i = 0; i < nr_io_queues; i++)
1675                 dev->entry[i].entry = i;
1676         vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
1677         if (vecs < 0) {
1678                 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
1679                 if (vecs < 0) {
1680                         vecs = 1;
1681                 } else {
1682                         for (i = 0; i < vecs; i++)
1683                                 dev->entry[i].vector = i + pdev->irq;
1684                 }
1685         }
1686
1687         /*
1688          * Should investigate if there's a performance win from allocating
1689          * more queues than interrupt vectors; it might allow the submission
1690          * path to scale better, even if the receive path is limited by the
1691          * number of interrupts.
1692          */
1693         nr_io_queues = vecs;
1694         dev->max_qid = nr_io_queues;
1695
1696         result = queue_request_irq(dev, adminq, adminq->irqname);
1697         if (result) {
1698                 adminq->cq_vector = -1;
1699                 goto free_queues;
1700         }
1701
1702         /* Free previously allocated queues that are no longer usable */
1703         nvme_free_queues(dev, nr_io_queues + 1);
1704         return nvme_create_io_queues(dev);
1705
1706  free_queues:
1707         nvme_free_queues(dev, 1);
1708         return result;
1709 }
1710
1711 static void nvme_set_irq_hints(struct nvme_dev *dev)
1712 {
1713         struct nvme_queue *nvmeq;
1714         int i;
1715
1716         for (i = 0; i < dev->online_queues; i++) {
1717                 nvmeq = dev->queues[i];
1718
1719                 if (!nvmeq->tags || !(*nvmeq->tags))
1720                         continue;
1721
1722                 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
1723                                         blk_mq_tags_cpumask(*nvmeq->tags));
1724         }
1725 }
1726
1727 static void nvme_dev_scan(struct work_struct *work)
1728 {
1729         struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
1730
1731         if (!dev->tagset.tags)
1732                 return;
1733         nvme_scan_namespaces(&dev->ctrl);
1734         nvme_set_irq_hints(dev);
1735 }
1736
1737 /*
1738  * Return: error value if an error occurred setting up the queues or calling
1739  * Identify Device.  0 if these succeeded, even if adding some of the
1740  * namespaces failed.  At the moment, these failures are silent.  TBD which
1741  * failures should be reported.
1742  */
1743 static int nvme_dev_add(struct nvme_dev *dev)
1744 {
1745         if (!dev->ctrl.tagset) {
1746                 dev->tagset.ops = &nvme_mq_ops;
1747                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1748                 dev->tagset.timeout = NVME_IO_TIMEOUT;
1749                 dev->tagset.numa_node = dev_to_node(dev->dev);
1750                 dev->tagset.queue_depth =
1751                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1752                 dev->tagset.cmd_size = nvme_cmd_size(dev);
1753                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1754                 dev->tagset.driver_data = dev;
1755
1756                 if (blk_mq_alloc_tag_set(&dev->tagset))
1757                         return 0;
1758                 dev->ctrl.tagset = &dev->tagset;
1759         }
1760         schedule_work(&dev->scan_work);
1761         return 0;
1762 }
1763
1764 static int nvme_dev_map(struct nvme_dev *dev)
1765 {
1766         u64 cap;
1767         int bars, result = -ENOMEM;
1768         struct pci_dev *pdev = to_pci_dev(dev->dev);
1769
1770         if (pci_enable_device_mem(pdev))
1771                 return result;
1772
1773         dev->entry[0].vector = pdev->irq;
1774         pci_set_master(pdev);
1775         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1776         if (!bars)
1777                 goto disable_pci;
1778
1779         if (pci_request_selected_regions(pdev, bars, "nvme"))
1780                 goto disable_pci;
1781
1782         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1783             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1784                 goto disable;
1785
1786         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1787         if (!dev->bar)
1788                 goto disable;
1789
1790         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1791                 result = -ENODEV;
1792                 goto unmap;
1793         }
1794
1795         /*
1796          * Some devices don't advertse INTx interrupts, pre-enable a single
1797          * MSIX vec for setup. We'll adjust this later.
1798          */
1799         if (!pdev->irq) {
1800                 result = pci_enable_msix(pdev, dev->entry, 1);
1801                 if (result < 0)
1802                         goto unmap;
1803         }
1804
1805         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1806
1807         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1808         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1809         dev->dbs = dev->bar + 4096;
1810         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2))
1811                 dev->cmb = nvme_map_cmb(dev);
1812
1813         return 0;
1814
1815  unmap:
1816         iounmap(dev->bar);
1817         dev->bar = NULL;
1818  disable:
1819         pci_release_regions(pdev);
1820  disable_pci:
1821         pci_disable_device(pdev);
1822         return result;
1823 }
1824
1825 static void nvme_dev_unmap(struct nvme_dev *dev)
1826 {
1827         struct pci_dev *pdev = to_pci_dev(dev->dev);
1828
1829         if (pdev->msi_enabled)
1830                 pci_disable_msi(pdev);
1831         else if (pdev->msix_enabled)
1832                 pci_disable_msix(pdev);
1833
1834         if (dev->bar) {
1835                 iounmap(dev->bar);
1836                 dev->bar = NULL;
1837                 pci_release_regions(pdev);
1838         }
1839
1840         if (pci_is_enabled(pdev))
1841                 pci_disable_device(pdev);
1842 }
1843
1844 struct nvme_delq_ctx {
1845         struct task_struct *waiter;
1846         struct kthread_worker *worker;
1847         atomic_t refcount;
1848 };
1849
1850 static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
1851 {
1852         dq->waiter = current;
1853         mb();
1854
1855         for (;;) {
1856                 set_current_state(TASK_KILLABLE);
1857                 if (!atomic_read(&dq->refcount))
1858                         break;
1859                 if (!schedule_timeout(ADMIN_TIMEOUT) ||
1860                                         fatal_signal_pending(current)) {
1861                         /*
1862                          * Disable the controller first since we can't trust it
1863                          * at this point, but leave the admin queue enabled
1864                          * until all queue deletion requests are flushed.
1865                          * FIXME: This may take a while if there are more h/w
1866                          * queues than admin tags.
1867                          */
1868                         set_current_state(TASK_RUNNING);
1869                         nvme_disable_ctrl(&dev->ctrl,
1870                                 lo_hi_readq(dev->bar + NVME_REG_CAP));
1871                         nvme_clear_queue(dev->queues[0]);
1872                         flush_kthread_worker(dq->worker);
1873                         nvme_disable_queue(dev, 0);
1874                         return;
1875                 }
1876         }
1877         set_current_state(TASK_RUNNING);
1878 }
1879
1880 static void nvme_put_dq(struct nvme_delq_ctx *dq)
1881 {
1882         atomic_dec(&dq->refcount);
1883         if (dq->waiter)
1884                 wake_up_process(dq->waiter);
1885 }
1886
1887 static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
1888 {
1889         atomic_inc(&dq->refcount);
1890         return dq;
1891 }
1892
1893 static void nvme_del_queue_end(struct nvme_queue *nvmeq)
1894 {
1895         struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
1896         nvme_put_dq(dq);
1897
1898         spin_lock_irq(&nvmeq->q_lock);
1899         nvme_process_cq(nvmeq);
1900         spin_unlock_irq(&nvmeq->q_lock);
1901 }
1902
1903 static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
1904                                                 kthread_work_func_t fn)
1905 {
1906         struct nvme_command c;
1907
1908         memset(&c, 0, sizeof(c));
1909         c.delete_queue.opcode = opcode;
1910         c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1911
1912         init_kthread_work(&nvmeq->cmdinfo.work, fn);
1913         return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
1914                                                                 ADMIN_TIMEOUT);
1915 }
1916
1917 static void nvme_del_cq_work_handler(struct kthread_work *work)
1918 {
1919         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
1920                                                         cmdinfo.work);
1921         nvme_del_queue_end(nvmeq);
1922 }
1923
1924 static int nvme_delete_cq(struct nvme_queue *nvmeq)
1925 {
1926         return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
1927                                                 nvme_del_cq_work_handler);
1928 }
1929
1930 static void nvme_del_sq_work_handler(struct kthread_work *work)
1931 {
1932         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
1933                                                         cmdinfo.work);
1934         int status = nvmeq->cmdinfo.status;
1935
1936         if (!status)
1937                 status = nvme_delete_cq(nvmeq);
1938         if (status)
1939                 nvme_del_queue_end(nvmeq);
1940 }
1941
1942 static int nvme_delete_sq(struct nvme_queue *nvmeq)
1943 {
1944         return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
1945                                                 nvme_del_sq_work_handler);
1946 }
1947
1948 static void nvme_del_queue_start(struct kthread_work *work)
1949 {
1950         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
1951                                                         cmdinfo.work);
1952         if (nvme_delete_sq(nvmeq))
1953                 nvme_del_queue_end(nvmeq);
1954 }
1955
1956 static void nvme_disable_io_queues(struct nvme_dev *dev)
1957 {
1958         int i;
1959         DEFINE_KTHREAD_WORKER_ONSTACK(worker);
1960         struct nvme_delq_ctx dq;
1961         struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
1962                                         &worker, "nvme%d", dev->ctrl.instance);
1963
1964         if (IS_ERR(kworker_task)) {
1965                 dev_err(dev->dev,
1966                         "Failed to create queue del task\n");
1967                 for (i = dev->queue_count - 1; i > 0; i--)
1968                         nvme_disable_queue(dev, i);
1969                 return;
1970         }
1971
1972         dq.waiter = NULL;
1973         atomic_set(&dq.refcount, 0);
1974         dq.worker = &worker;
1975         for (i = dev->queue_count - 1; i > 0; i--) {
1976                 struct nvme_queue *nvmeq = dev->queues[i];
1977
1978                 if (nvme_suspend_queue(nvmeq))
1979                         continue;
1980                 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
1981                 nvmeq->cmdinfo.worker = dq.worker;
1982                 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
1983                 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
1984         }
1985         nvme_wait_dq(&dq, dev);
1986         kthread_stop(kworker_task);
1987 }
1988
1989 static int nvme_dev_list_add(struct nvme_dev *dev)
1990 {
1991         bool start_thread = false;
1992
1993         spin_lock(&dev_list_lock);
1994         if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
1995                 start_thread = true;
1996                 nvme_thread = NULL;
1997         }
1998         list_add(&dev->node, &dev_list);
1999         spin_unlock(&dev_list_lock);
2000
2001         if (start_thread) {
2002                 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2003                 wake_up_all(&nvme_kthread_wait);
2004         } else
2005                 wait_event_killable(nvme_kthread_wait, nvme_thread);
2006
2007         if (IS_ERR_OR_NULL(nvme_thread))
2008                 return nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2009
2010         return 0;
2011 }
2012
2013 /*
2014 * Remove the node from the device list and check
2015 * for whether or not we need to stop the nvme_thread.
2016 */
2017 static void nvme_dev_list_remove(struct nvme_dev *dev)
2018 {
2019         struct task_struct *tmp = NULL;
2020
2021         spin_lock(&dev_list_lock);
2022         list_del_init(&dev->node);
2023         if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2024                 tmp = nvme_thread;
2025                 nvme_thread = NULL;
2026         }
2027         spin_unlock(&dev_list_lock);
2028
2029         if (tmp)
2030                 kthread_stop(tmp);
2031 }
2032
2033 static void nvme_freeze_queues(struct nvme_dev *dev)
2034 {
2035         struct nvme_ns *ns;
2036
2037         list_for_each_entry(ns, &dev->ctrl.namespaces, list) {
2038                 blk_mq_freeze_queue_start(ns->queue);
2039
2040                 spin_lock_irq(ns->queue->queue_lock);
2041                 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
2042                 spin_unlock_irq(ns->queue->queue_lock);
2043
2044                 blk_mq_cancel_requeue_work(ns->queue);
2045                 blk_mq_stop_hw_queues(ns->queue);
2046         }
2047 }
2048
2049 static void nvme_unfreeze_queues(struct nvme_dev *dev)
2050 {
2051         struct nvme_ns *ns;
2052
2053         list_for_each_entry(ns, &dev->ctrl.namespaces, list) {
2054                 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2055                 blk_mq_unfreeze_queue(ns->queue);
2056                 blk_mq_start_stopped_hw_queues(ns->queue, true);
2057                 blk_mq_kick_requeue_list(ns->queue);
2058         }
2059 }
2060
2061 static void nvme_dev_shutdown(struct nvme_dev *dev)
2062 {
2063         int i;
2064         u32 csts = -1;
2065
2066         nvme_dev_list_remove(dev);
2067
2068         mutex_lock(&dev->shutdown_lock);
2069         if (dev->bar) {
2070                 nvme_freeze_queues(dev);
2071                 csts = readl(dev->bar + NVME_REG_CSTS);
2072         }
2073         if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
2074                 for (i = dev->queue_count - 1; i >= 0; i--) {
2075                         struct nvme_queue *nvmeq = dev->queues[i];
2076                         nvme_suspend_queue(nvmeq);
2077                 }
2078         } else {
2079                 nvme_disable_io_queues(dev);
2080                 nvme_shutdown_ctrl(&dev->ctrl);
2081                 nvme_disable_queue(dev, 0);
2082         }
2083         nvme_dev_unmap(dev);
2084
2085         for (i = dev->queue_count - 1; i >= 0; i--)
2086                 nvme_clear_queue(dev->queues[i]);
2087         mutex_unlock(&dev->shutdown_lock);
2088 }
2089
2090 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2091 {
2092         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2093                                                 PAGE_SIZE, PAGE_SIZE, 0);
2094         if (!dev->prp_page_pool)
2095                 return -ENOMEM;
2096
2097         /* Optimisation for I/Os between 4k and 128k */
2098         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2099                                                 256, 256, 0);
2100         if (!dev->prp_small_pool) {
2101                 dma_pool_destroy(dev->prp_page_pool);
2102                 return -ENOMEM;
2103         }
2104         return 0;
2105 }
2106
2107 static void nvme_release_prp_pools(struct nvme_dev *dev)
2108 {
2109         dma_pool_destroy(dev->prp_page_pool);
2110         dma_pool_destroy(dev->prp_small_pool);
2111 }
2112
2113 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2114 {
2115         struct nvme_dev *dev = to_nvme_dev(ctrl);
2116
2117         put_device(dev->dev);
2118         if (dev->tagset.tags)
2119                 blk_mq_free_tag_set(&dev->tagset);
2120         if (dev->ctrl.admin_q)
2121                 blk_put_queue(dev->ctrl.admin_q);
2122         kfree(dev->queues);
2123         kfree(dev->entry);
2124         kfree(dev);
2125 }
2126
2127 static void nvme_probe_work(struct work_struct *work)
2128 {
2129         struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
2130         int result;
2131
2132         result = nvme_dev_map(dev);
2133         if (result)
2134                 goto out;
2135
2136         result = nvme_configure_admin_queue(dev);
2137         if (result)
2138                 goto unmap;
2139
2140         nvme_init_queue(dev->queues[0], 0);
2141         result = nvme_alloc_admin_tags(dev);
2142         if (result)
2143                 goto disable;
2144
2145         result = nvme_init_identify(&dev->ctrl);
2146         if (result)
2147                 goto free_tags;
2148
2149         result = nvme_setup_io_queues(dev);
2150         if (result)
2151                 goto free_tags;
2152
2153         dev->ctrl.event_limit = 1;
2154
2155         result = nvme_dev_list_add(dev);
2156         if (result)
2157                 goto remove;
2158
2159         /*
2160          * Keep the controller around but remove all namespaces if we don't have
2161          * any working I/O queue.
2162          */
2163         if (dev->online_queues < 2) {
2164                 dev_warn(dev->dev, "IO queues not created\n");
2165                 nvme_remove_namespaces(&dev->ctrl);
2166         } else {
2167                 nvme_unfreeze_queues(dev);
2168                 nvme_dev_add(dev);
2169         }
2170
2171         return;
2172
2173  remove:
2174         nvme_dev_list_remove(dev);
2175  free_tags:
2176         nvme_dev_remove_admin(dev);
2177         blk_put_queue(dev->ctrl.admin_q);
2178         dev->ctrl.admin_q = NULL;
2179         dev->queues[0]->tags = NULL;
2180  disable:
2181         nvme_disable_queue(dev, 0);
2182  unmap:
2183         nvme_dev_unmap(dev);
2184  out:
2185         if (!work_busy(&dev->reset_work))
2186                 nvme_dead_ctrl(dev);
2187 }
2188
2189 static int nvme_remove_dead_ctrl(void *arg)
2190 {
2191         struct nvme_dev *dev = (struct nvme_dev *)arg;
2192         struct pci_dev *pdev = to_pci_dev(dev->dev);
2193
2194         if (pci_get_drvdata(pdev))
2195                 pci_stop_and_remove_bus_device_locked(pdev);
2196         nvme_put_ctrl(&dev->ctrl);
2197         return 0;
2198 }
2199
2200 static void nvme_dead_ctrl(struct nvme_dev *dev)
2201 {
2202         dev_warn(dev->dev, "Device failed to resume\n");
2203         kref_get(&dev->ctrl.kref);
2204         if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2205                                                 dev->ctrl.instance))) {
2206                 dev_err(dev->dev,
2207                         "Failed to start controller remove task\n");
2208                 nvme_put_ctrl(&dev->ctrl);
2209         }
2210 }
2211
2212 static void nvme_reset_work(struct work_struct *ws)
2213 {
2214         struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2215         bool in_probe = work_busy(&dev->probe_work);
2216
2217         nvme_dev_shutdown(dev);
2218
2219         /* Synchronize with device probe so that work will see failure status
2220          * and exit gracefully without trying to schedule another reset */
2221         flush_work(&dev->probe_work);
2222
2223         /* Fail this device if reset occured during probe to avoid
2224          * infinite initialization loops. */
2225         if (in_probe) {
2226                 nvme_dead_ctrl(dev);
2227                 return;
2228         }
2229         /* Schedule device resume asynchronously so the reset work is available
2230          * to cleanup errors that may occur during reinitialization */
2231         schedule_work(&dev->probe_work);
2232 }
2233
2234 static int nvme_reset(struct nvme_dev *dev)
2235 {
2236         if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
2237                 return -ENODEV;
2238
2239         if (!queue_work(nvme_workq, &dev->reset_work))
2240                 return -EBUSY;
2241
2242         flush_work(&dev->reset_work);
2243         flush_work(&dev->probe_work);
2244         return 0;
2245 }
2246
2247 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2248 {
2249         *val = readl(to_nvme_dev(ctrl)->bar + off);
2250         return 0;
2251 }
2252
2253 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2254 {
2255         writel(val, to_nvme_dev(ctrl)->bar + off);
2256         return 0;
2257 }
2258
2259 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2260 {
2261         *val = readq(to_nvme_dev(ctrl)->bar + off);
2262         return 0;
2263 }
2264
2265 static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl)
2266 {
2267         struct nvme_dev *dev = to_nvme_dev(ctrl);
2268
2269         return !dev->bar || dev->online_queues < 2;
2270 }
2271
2272 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
2273 {
2274         return nvme_reset(to_nvme_dev(ctrl));
2275 }
2276
2277 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2278         .reg_read32             = nvme_pci_reg_read32,
2279         .reg_write32            = nvme_pci_reg_write32,
2280         .reg_read64             = nvme_pci_reg_read64,
2281         .io_incapable           = nvme_pci_io_incapable,
2282         .reset_ctrl             = nvme_pci_reset_ctrl,
2283         .free_ctrl              = nvme_pci_free_ctrl,
2284 };
2285
2286 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2287 {
2288         int node, result = -ENOMEM;
2289         struct nvme_dev *dev;
2290
2291         node = dev_to_node(&pdev->dev);
2292         if (node == NUMA_NO_NODE)
2293                 set_dev_node(&pdev->dev, 0);
2294
2295         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2296         if (!dev)
2297                 return -ENOMEM;
2298         dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2299                                                         GFP_KERNEL, node);
2300         if (!dev->entry)
2301                 goto free;
2302         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2303                                                         GFP_KERNEL, node);
2304         if (!dev->queues)
2305                 goto free;
2306
2307         dev->dev = get_device(&pdev->dev);
2308         pci_set_drvdata(pdev, dev);
2309
2310         INIT_LIST_HEAD(&dev->node);
2311         INIT_WORK(&dev->scan_work, nvme_dev_scan);
2312         INIT_WORK(&dev->probe_work, nvme_probe_work);
2313         INIT_WORK(&dev->reset_work, nvme_reset_work);
2314         mutex_init(&dev->shutdown_lock);
2315
2316         result = nvme_setup_prp_pools(dev);
2317         if (result)
2318                 goto put_pci;
2319
2320         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2321                         id->driver_data);
2322         if (result)
2323                 goto release_pools;
2324
2325         schedule_work(&dev->probe_work);
2326         return 0;
2327
2328  release_pools:
2329         nvme_release_prp_pools(dev);
2330  put_pci:
2331         put_device(dev->dev);
2332  free:
2333         kfree(dev->queues);
2334         kfree(dev->entry);
2335         kfree(dev);
2336         return result;
2337 }
2338
2339 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2340 {
2341         struct nvme_dev *dev = pci_get_drvdata(pdev);
2342
2343         if (prepare)
2344                 nvme_dev_shutdown(dev);
2345         else
2346                 schedule_work(&dev->probe_work);
2347 }
2348
2349 static void nvme_shutdown(struct pci_dev *pdev)
2350 {
2351         struct nvme_dev *dev = pci_get_drvdata(pdev);
2352         nvme_dev_shutdown(dev);
2353 }
2354
2355 static void nvme_remove(struct pci_dev *pdev)
2356 {
2357         struct nvme_dev *dev = pci_get_drvdata(pdev);
2358
2359         spin_lock(&dev_list_lock);
2360         list_del_init(&dev->node);
2361         spin_unlock(&dev_list_lock);
2362
2363         pci_set_drvdata(pdev, NULL);
2364         flush_work(&dev->probe_work);
2365         flush_work(&dev->reset_work);
2366         flush_work(&dev->scan_work);
2367         nvme_remove_namespaces(&dev->ctrl);
2368         nvme_dev_shutdown(dev);
2369         nvme_dev_remove_admin(dev);
2370         nvme_free_queues(dev, 0);
2371         nvme_release_cmb(dev);
2372         nvme_release_prp_pools(dev);
2373         nvme_put_ctrl(&dev->ctrl);
2374 }
2375
2376 /* These functions are yet to be implemented */
2377 #define nvme_error_detected NULL
2378 #define nvme_dump_registers NULL
2379 #define nvme_link_reset NULL
2380 #define nvme_slot_reset NULL
2381 #define nvme_error_resume NULL
2382
2383 #ifdef CONFIG_PM_SLEEP
2384 static int nvme_suspend(struct device *dev)
2385 {
2386         struct pci_dev *pdev = to_pci_dev(dev);
2387         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2388
2389         nvme_dev_shutdown(ndev);
2390         return 0;
2391 }
2392
2393 static int nvme_resume(struct device *dev)
2394 {
2395         struct pci_dev *pdev = to_pci_dev(dev);
2396         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2397
2398         schedule_work(&ndev->probe_work);
2399         return 0;
2400 }
2401 #endif
2402
2403 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2404
2405 static const struct pci_error_handlers nvme_err_handler = {
2406         .error_detected = nvme_error_detected,
2407         .mmio_enabled   = nvme_dump_registers,
2408         .link_reset     = nvme_link_reset,
2409         .slot_reset     = nvme_slot_reset,
2410         .resume         = nvme_error_resume,
2411         .reset_notify   = nvme_reset_notify,
2412 };
2413
2414 /* Move to pci_ids.h later */
2415 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
2416
2417 static const struct pci_device_id nvme_id_table[] = {
2418         { PCI_VDEVICE(INTEL, 0x0953),
2419                 .driver_data = NVME_QUIRK_STRIPE_SIZE, },
2420         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2421         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2422         { 0, }
2423 };
2424 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2425
2426 static struct pci_driver nvme_driver = {
2427         .name           = "nvme",
2428         .id_table       = nvme_id_table,
2429         .probe          = nvme_probe,
2430         .remove         = nvme_remove,
2431         .shutdown       = nvme_shutdown,
2432         .driver         = {
2433                 .pm     = &nvme_dev_pm_ops,
2434         },
2435         .err_handler    = &nvme_err_handler,
2436 };
2437
2438 static int __init nvme_init(void)
2439 {
2440         int result;
2441
2442         init_waitqueue_head(&nvme_kthread_wait);
2443
2444         nvme_workq = create_singlethread_workqueue("nvme");
2445         if (!nvme_workq)
2446                 return -ENOMEM;
2447
2448         result = nvme_core_init();
2449         if (result < 0)
2450                 goto kill_workq;
2451
2452         result = pci_register_driver(&nvme_driver);
2453         if (result)
2454                 goto core_exit;
2455         return 0;
2456
2457  core_exit:
2458         nvme_core_exit();
2459  kill_workq:
2460         destroy_workqueue(nvme_workq);
2461         return result;
2462 }
2463
2464 static void __exit nvme_exit(void)
2465 {
2466         pci_unregister_driver(&nvme_driver);
2467         nvme_core_exit();
2468         destroy_workqueue(nvme_workq);
2469         BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
2470         _nvme_check_size();
2471 }
2472
2473 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2474 MODULE_LICENSE("GPL");
2475 MODULE_VERSION("1.0");
2476 module_init(nvme_init);
2477 module_exit(nvme_exit);