drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/aer.h>
  16 #include <linux/bitops.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/blk-mq.h>
  19 #include <linux/cpu.h>
  20 #include <linux/delay.h>
  21 #include <linux/errno.h>
  22 #include <linux/fs.h>
  23 #include <linux/genhd.h>
  24 #include <linux/hdreg.h>
  25 #include <linux/idr.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/kdev_t.h>
  30 #include <linux/kernel.h>
  31 #include <linux/mm.h>
  32 #include <linux/module.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/mutex.h>
  35 #include <linux/pci.h>
  36 #include <linux/poison.h>
  37 #include <linux/ptrace.h>
  38 #include <linux/sched.h>
  39 #include <linux/slab.h>
  40 #include <linux/t10-pi.h>
  41 #include <linux/timer.h>
  42 #include <linux/types.h>
  43 #include <linux/io-64-nonatomic-lo-hi.h>
  44 #include <asm/unaligned.h>
  45
  46 #include "nvme.h"
  47
  48 #define NVME_Q_DEPTH            1024
  49 #define NVME_AQ_DEPTH           256
  50 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  51 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  52
  53 /*
  54  * We handle AEN commands ourselves and don't even let the
  55  * block layer know about them.
  56  */
  57 #define NVME_NR_AEN_COMMANDS    1
  58 #define NVME_AQ_BLKMQ_DEPTH     (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
  59
  60 static int use_threaded_interrupts;
  61 module_param(use_threaded_interrupts, int, 0);
  62
  63 static bool use_cmb_sqes = true;
  64 module_param(use_cmb_sqes, bool, 0644);
  65 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  66
  67 static struct workqueue_struct *nvme_workq;
  68
  69 struct nvme_dev;
  70 struct nvme_queue;
  71
  72 static int nvme_reset(struct nvme_dev *dev);
  73 static void nvme_process_cq(struct nvme_queue *nvmeq);
  74 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  75
  76 /*
  77  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  78  */
  79 struct nvme_dev {
  80         struct nvme_queue **queues;
  81         struct blk_mq_tag_set tagset;
  82         struct blk_mq_tag_set admin_tagset;
  83         u32 __iomem *dbs;
  84         struct device *dev;
  85         struct dma_pool *prp_page_pool;
  86         struct dma_pool *prp_small_pool;
  87         unsigned queue_count;
  88         unsigned online_queues;
  89         unsigned max_qid;
  90         int q_depth;
  91         u32 db_stride;
  92         struct msix_entry *entry;
  93         void __iomem *bar;
  94         struct work_struct reset_work;
  95         struct work_struct scan_work;
  96         struct work_struct remove_work;
  97         struct work_struct async_work;
  98         struct timer_list watchdog_timer;
  99         struct mutex shutdown_lock;
 100         bool subsystem;
 101         void __iomem *cmb;
 102         dma_addr_t cmb_dma_addr;
 103         u64 cmb_size;
 104         u32 cmbsz;
 105         unsigned long flags;
 106
 107 #define NVME_CTRL_RESETTING    0
 108 #define NVME_CTRL_REMOVING     1
 109
 110         struct nvme_ctrl ctrl;
 111         struct completion ioq_wait;
 112 };
 113
 114 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 115 {
 116         return container_of(ctrl, struct nvme_dev, ctrl);
 117 }
 118
 119 /*
 120  * An NVM Express queue.  Each device has at least two (one for admin
 121  * commands and one for I/O commands).
 122  */
 123 struct nvme_queue {
 124         struct device *q_dmadev;
 125         struct nvme_dev *dev;
 126         char irqname[24];       /* nvme4294967295-65535\0 */
 127         spinlock_t q_lock;
 128         struct nvme_command *sq_cmds;
 129         struct nvme_command __iomem *sq_cmds_io;
 130         volatile struct nvme_completion *cqes;
 131         struct blk_mq_tags **tags;
 132         dma_addr_t sq_dma_addr;
 133         dma_addr_t cq_dma_addr;
 134         u32 __iomem *q_db;
 135         u16 q_depth;
 136         s16 cq_vector;
 137         u16 sq_tail;
 138         u16 cq_head;
 139         u16 qid;
 140         u8 cq_phase;
 141         u8 cqe_seen;
 142 };
 143
 144 /*
 145  * The nvme_iod describes the data in an I/O, including the list of PRP
 146  * entries.  You can't see it in this data structure because C doesn't let
 147  * me express that.  Use nvme_init_iod to ensure there's enough space
 148  * allocated to store the PRP list.
 149  */
 150 struct nvme_iod {
 151         struct nvme_queue *nvmeq;
 152         int aborted;
 153         int npages;             /* In the PRP list. 0 means small pool in use */
 154         int nents;              /* Used in scatterlist */
 155         int length;             /* Of data, in bytes */
 156         dma_addr_t first_dma;
 157         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 158         struct scatterlist *sg;
 159         struct scatterlist inline_sg[0];
 160 };
 161
 162 /*
 163  * Check we didin't inadvertently grow the command struct
 164  */
 165 static inline void _nvme_check_size(void)
 166 {
 167         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 168         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 169         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 170         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 171         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 172         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 173         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 174         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 175         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 176         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 177         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 178         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 179 }
 180
 181 /*
 182  * Max size of iod being embedded in the request payload
 183  */
 184 #define NVME_INT_PAGES          2
 185 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 186
 187 /*
 188  * Will slightly overestimate the number of pages needed.  This is OK
 189  * as it only leads to a small amount of wasted memory for the lifetime of
 190  * the I/O.
 191  */
 192 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 193 {
 194         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 195                                       dev->ctrl.page_size);
 196         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 197 }
 198
 199 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
 200                 unsigned int size, unsigned int nseg)
 201 {
 202         return sizeof(__le64 *) * nvme_npages(size, dev) +
 203                         sizeof(struct scatterlist) * nseg;
 204 }
 205
 206 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 207 {
 208         return sizeof(struct nvme_iod) +
 209                 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
 210 }
 211
 212 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 213                                 unsigned int hctx_idx)
 214 {
 215         struct nvme_dev *dev = data;
 216         struct nvme_queue *nvmeq = dev->queues[0];
 217
 218         WARN_ON(hctx_idx != 0);
 219         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 220         WARN_ON(nvmeq->tags);
 221
 222         hctx->driver_data = nvmeq;
 223         nvmeq->tags = &dev->admin_tagset.tags[0];
 224         return 0;
 225 }
 226
 227 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 228 {
 229         struct nvme_queue *nvmeq = hctx->driver_data;
 230
 231         nvmeq->tags = NULL;
 232 }
 233
 234 static int nvme_admin_init_request(void *data, struct request *req,
 235                                 unsigned int hctx_idx, unsigned int rq_idx,
 236                                 unsigned int numa_node)
 237 {
 238         struct nvme_dev *dev = data;
 239         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 240         struct nvme_queue *nvmeq = dev->queues[0];
 241
 242         BUG_ON(!nvmeq);
 243         iod->nvmeq = nvmeq;
 244         return 0;
 245 }
 246
 247 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 248                           unsigned int hctx_idx)
 249 {
 250         struct nvme_dev *dev = data;
 251         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 252
 253         if (!nvmeq->tags)
 254                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 255
 256         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 257         hctx->driver_data = nvmeq;
 258         return 0;
 259 }
 260
 261 static int nvme_init_request(void *data, struct request *req,
 262                                 unsigned int hctx_idx, unsigned int rq_idx,
 263                                 unsigned int numa_node)
 264 {
 265         struct nvme_dev *dev = data;
 266         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 267         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 268
 269         BUG_ON(!nvmeq);
 270         iod->nvmeq = nvmeq;
 271         return 0;
 272 }
 273
 274 static void nvme_queue_scan(struct nvme_dev *dev)
 275 {
 276         /*
 277          * Do not queue new scan work when a controller is reset during
 278          * removal.
 279          */
 280         if (test_bit(NVME_CTRL_REMOVING, &dev->flags))
 281                 return;
 282         queue_work(nvme_workq, &dev->scan_work);
 283 }
 284
 285 static void nvme_complete_async_event(struct nvme_dev *dev,
 286                 struct nvme_completion *cqe)
 287 {
 288         u16 status = le16_to_cpu(cqe->status) >> 1;
 289         u32 result = le32_to_cpu(cqe->result);
 290
 291         if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) {
 292                 ++dev->ctrl.event_limit;
 293                 queue_work(nvme_workq, &dev->async_work);
 294         }
 295
 296         if (status != NVME_SC_SUCCESS)
 297                 return;
 298
 299         switch (result & 0xff07) {
 300         case NVME_AER_NOTICE_NS_CHANGED:
 301                 dev_info(dev->ctrl.device, "rescanning\n");
 302                 nvme_queue_scan(dev);
 303         default:
 304                 dev_warn(dev->ctrl.device, "async event result %08x\n", result);
 305         }
 306 }
 307
 308 /**
 309  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 310  * @nvmeq: The queue to use
 311  * @cmd: The command to send
 312  *
 313  * Safe to use from interrupt context
 314  */
 315 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 316                                                 struct nvme_command *cmd)
 317 {
 318         u16 tail = nvmeq->sq_tail;
 319
 320         if (nvmeq->sq_cmds_io)
 321                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 322         else
 323                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 324
 325         if (++tail == nvmeq->q_depth)
 326                 tail = 0;
 327         writel(tail, nvmeq->q_db);
 328         nvmeq->sq_tail = tail;
 329 }
 330
 331 static __le64 **iod_list(struct request *req)
 332 {
 333         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 334         return (__le64 **)(iod->sg + req->nr_phys_segments);
 335 }
 336
 337 static int nvme_init_iod(struct request *rq, unsigned size,
 338                 struct nvme_dev *dev)
 339 {
 340         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
 341         int nseg = rq->nr_phys_segments;
 342
 343         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
 344                 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
 345                 if (!iod->sg)
 346                         return BLK_MQ_RQ_QUEUE_BUSY;
 347         } else {
 348                 iod->sg = iod->inline_sg;
 349         }
 350
 351         iod->aborted = 0;
 352         iod->npages = -1;
 353         iod->nents = 0;
 354         iod->length = size;
 355         return 0;
 356 }
 357
 358 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
 359 {
 360         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 361         const int last_prp = dev->ctrl.page_size / 8 - 1;
 362         int i;
 363         __le64 **list = iod_list(req);
 364         dma_addr_t prp_dma = iod->first_dma;
 365
 366         if (req->cmd_flags & REQ_DISCARD)
 367                 kfree(req->completion_data);
 368
 369         if (iod->npages == 0)
 370                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 371         for (i = 0; i < iod->npages; i++) {
 372                 __le64 *prp_list = list[i];
 373                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 374                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 375                 prp_dma = next_prp_dma;
 376         }
 377
 378         if (iod->sg != iod->inline_sg)
 379                 kfree(iod->sg);
 380 }
 381
 382 #ifdef CONFIG_BLK_DEV_INTEGRITY
 383 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 384 {
 385         if (be32_to_cpu(pi->ref_tag) == v)
 386                 pi->ref_tag = cpu_to_be32(p);
 387 }
 388
 389 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 390 {
 391         if (be32_to_cpu(pi->ref_tag) == p)
 392                 pi->ref_tag = cpu_to_be32(v);
 393 }
 394
 395 /**
 396  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 397  *
 398  * The virtual start sector is the one that was originally submitted by the
 399  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 400  * start sector may be different. Remap protection information to match the
 401  * physical LBA on writes, and back to the original seed on reads.
 402  *
 403  * Type 0 and 3 do not have a ref tag, so no remapping required.
 404  */
 405 static void nvme_dif_remap(struct request *req,
 406                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 407 {
 408         struct nvme_ns *ns = req->rq_disk->private_data;
 409         struct bio_integrity_payload *bip;
 410         struct t10_pi_tuple *pi;
 411         void *p, *pmap;
 412         u32 i, nlb, ts, phys, virt;
 413
 414         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 415                 return;
 416
 417         bip = bio_integrity(req->bio);
 418         if (!bip)
 419                 return;
 420
 421         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 422
 423         p = pmap;
 424         virt = bip_get_seed(bip);
 425         phys = nvme_block_nr(ns, blk_rq_pos(req));
 426         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 427         ts = ns->disk->queue->integrity.tuple_size;
 428
 429         for (i = 0; i < nlb; i++, virt++, phys++) {
 430                 pi = (struct t10_pi_tuple *)p;
 431                 dif_swap(phys, virt, pi);
 432                 p += ts;
 433         }
 434         kunmap_atomic(pmap);
 435 }
 436 #else /* CONFIG_BLK_DEV_INTEGRITY */
 437 static void nvme_dif_remap(struct request *req,
 438                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 439 {
 440 }
 441 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 442 {
 443 }
 444 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 445 {
 446 }
 447 #endif
 448
 449 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req,
 450                 int total_len)
 451 {
 452         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 453         struct dma_pool *pool;
 454         int length = total_len;
 455         struct scatterlist *sg = iod->sg;
 456         int dma_len = sg_dma_len(sg);
 457         u64 dma_addr = sg_dma_address(sg);
 458         u32 page_size = dev->ctrl.page_size;
 459         int offset = dma_addr & (page_size - 1);
 460         __le64 *prp_list;
 461         __le64 **list = iod_list(req);
 462         dma_addr_t prp_dma;
 463         int nprps, i;
 464
 465         length -= (page_size - offset);
 466         if (length <= 0)
 467                 return true;
 468
 469         dma_len -= (page_size - offset);
 470         if (dma_len) {
 471                 dma_addr += (page_size - offset);
 472         } else {
 473                 sg = sg_next(sg);
 474                 dma_addr = sg_dma_address(sg);
 475                 dma_len = sg_dma_len(sg);
 476         }
 477
 478         if (length <= page_size) {
 479                 iod->first_dma = dma_addr;
 480                 return true;
 481         }
 482
 483         nprps = DIV_ROUND_UP(length, page_size);
 484         if (nprps <= (256 / 8)) {
 485                 pool = dev->prp_small_pool;
 486                 iod->npages = 0;
 487         } else {
 488                 pool = dev->prp_page_pool;
 489                 iod->npages = 1;
 490         }
 491
 492         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 493         if (!prp_list) {
 494                 iod->first_dma = dma_addr;
 495                 iod->npages = -1;
 496                 return false;
 497         }
 498         list[0] = prp_list;
 499         iod->first_dma = prp_dma;
 500         i = 0;
 501         for (;;) {
 502                 if (i == page_size >> 3) {
 503                         __le64 *old_prp_list = prp_list;
 504                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 505                         if (!prp_list)
 506                                 return false;
 507                         list[iod->npages++] = prp_list;
 508                         prp_list[0] = old_prp_list[i - 1];
 509                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 510                         i = 1;
 511                 }
 512                 prp_list[i++] = cpu_to_le64(dma_addr);
 513                 dma_len -= page_size;
 514                 dma_addr += page_size;
 515                 length -= page_size;
 516                 if (length <= 0)
 517                         break;
 518                 if (dma_len > 0)
 519                         continue;
 520                 BUG_ON(dma_len < 0);
 521                 sg = sg_next(sg);
 522                 dma_addr = sg_dma_address(sg);
 523                 dma_len = sg_dma_len(sg);
 524         }
 525
 526         return true;
 527 }
 528
 529 static int nvme_map_data(struct nvme_dev *dev, struct request *req,
 530                 unsigned size, struct nvme_command *cmnd)
 531 {
 532         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 533         struct request_queue *q = req->q;
 534         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 535                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 536         int ret = BLK_MQ_RQ_QUEUE_ERROR;
 537
 538         sg_init_table(iod->sg, req->nr_phys_segments);
 539         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 540         if (!iod->nents)
 541                 goto out;
 542
 543         ret = BLK_MQ_RQ_QUEUE_BUSY;
 544         if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir))
 545                 goto out;
 546
 547         if (!nvme_setup_prps(dev, req, size))
 548                 goto out_unmap;
 549
 550         ret = BLK_MQ_RQ_QUEUE_ERROR;
 551         if (blk_integrity_rq(req)) {
 552                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 553                         goto out_unmap;
 554
 555                 sg_init_table(&iod->meta_sg, 1);
 556                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 557                         goto out_unmap;
 558
 559                 if (rq_data_dir(req))
 560                         nvme_dif_remap(req, nvme_dif_prep);
 561
 562                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 563                         goto out_unmap;
 564         }
 565
 566         cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 567         cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
 568         if (blk_integrity_rq(req))
 569                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 570         return BLK_MQ_RQ_QUEUE_OK;
 571
 572 out_unmap:
 573         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 574 out:
 575         return ret;
 576 }
 577
 578 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 579 {
 580         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 581         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 582                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 583
 584         if (iod->nents) {
 585                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 586                 if (blk_integrity_rq(req)) {
 587                         if (!rq_data_dir(req))
 588                                 nvme_dif_remap(req, nvme_dif_complete);
 589                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 590                 }
 591         }
 592
 593         nvme_free_iod(dev, req);
 594 }
 595
 596 /*
 597  * NOTE: ns is NULL when called on the admin queue.
 598  */
 599 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 600                          const struct blk_mq_queue_data *bd)
 601 {
 602         struct nvme_ns *ns = hctx->queue->queuedata;
 603         struct nvme_queue *nvmeq = hctx->driver_data;
 604         struct nvme_dev *dev = nvmeq->dev;
 605         struct request *req = bd->rq;
 606         struct nvme_command cmnd;
 607         unsigned map_len;
 608         int ret = BLK_MQ_RQ_QUEUE_OK;
 609
 610         /*
 611          * If formated with metadata, require the block layer provide a buffer
 612          * unless this namespace is formated such that the metadata can be
 613          * stripped/generated by the controller with PRACT=1.
 614          */
 615         if (ns && ns->ms && !blk_integrity_rq(req)) {
 616                 if (!(ns->pi_type && ns->ms == 8) &&
 617                                         req->cmd_type != REQ_TYPE_DRV_PRIV) {
 618                         blk_mq_end_request(req, -EFAULT);
 619                         return BLK_MQ_RQ_QUEUE_OK;
 620                 }
 621         }
 622
 623         map_len = nvme_map_len(req);
 624         ret = nvme_init_iod(req, map_len, dev);
 625         if (ret)
 626                 return ret;
 627
 628         ret = nvme_setup_cmd(ns, req, &cmnd);
 629         if (ret)
 630                 goto out;
 631
 632         if (req->nr_phys_segments)
 633                 ret = nvme_map_data(dev, req, map_len, &cmnd);
 634
 635         if (ret)
 636                 goto out;
 637
 638         cmnd.common.command_id = req->tag;
 639         blk_mq_start_request(req);
 640
 641         spin_lock_irq(&nvmeq->q_lock);
 642         if (unlikely(nvmeq->cq_vector < 0)) {
 643                 if (ns && !test_bit(NVME_NS_DEAD, &ns->flags))
 644                         ret = BLK_MQ_RQ_QUEUE_BUSY;
 645                 else
 646                         ret = BLK_MQ_RQ_QUEUE_ERROR;
 647                 spin_unlock_irq(&nvmeq->q_lock);
 648                 goto out;
 649         }
 650         __nvme_submit_cmd(nvmeq, &cmnd);
 651         nvme_process_cq(nvmeq);
 652         spin_unlock_irq(&nvmeq->q_lock);
 653         return BLK_MQ_RQ_QUEUE_OK;
 654 out:
 655         nvme_free_iod(dev, req);
 656         return ret;
 657 }
 658
 659 static void nvme_complete_rq(struct request *req)
 660 {
 661         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 662         struct nvme_dev *dev = iod->nvmeq->dev;
 663         int error = 0;
 664
 665         nvme_unmap_data(dev, req);
 666
 667         if (unlikely(req->errors)) {
 668                 if (nvme_req_needs_retry(req, req->errors)) {
 669                         nvme_requeue_req(req);
 670                         return;
 671                 }
 672
 673                 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
 674                         error = req->errors;
 675                 else
 676                         error = nvme_error_status(req->errors);
 677         }
 678
 679         if (unlikely(iod->aborted)) {
 680                 dev_warn(dev->ctrl.device,
 681                         "completing aborted command with status: %04x\n",
 682                         req->errors);
 683         }
 684
 685         blk_mq_end_request(req, error);
 686 }
 687
 688 /* We read the CQE phase first to check if the rest of the entry is valid */
 689 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
 690                 u16 phase)
 691 {
 692         return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
 693 }
 694
 695 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
 696 {
 697         u16 head, phase;
 698
 699         head = nvmeq->cq_head;
 700         phase = nvmeq->cq_phase;
 701
 702         while (nvme_cqe_valid(nvmeq, head, phase)) {
 703                 struct nvme_completion cqe = nvmeq->cqes[head];
 704                 struct request *req;
 705
 706                 if (++head == nvmeq->q_depth) {
 707                         head = 0;
 708                         phase = !phase;
 709                 }
 710
 711                 if (tag && *tag == cqe.command_id)
 712                         *tag = -1;
 713
 714                 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
 715                         dev_warn(nvmeq->dev->ctrl.device,
 716                                 "invalid id %d completed on queue %d\n",
 717                                 cqe.command_id, le16_to_cpu(cqe.sq_id));
 718                         continue;
 719                 }
 720
 721                 /*
 722                  * AEN requests are special as they don't time out and can
 723                  * survive any kind of queue freeze and often don't respond to
 724                  * aborts.  We don't even bother to allocate a struct request
 725                  * for them but rather special case them here.
 726                  */
 727                 if (unlikely(nvmeq->qid == 0 &&
 728                                 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
 729                         nvme_complete_async_event(nvmeq->dev, &cqe);
 730                         continue;
 731                 }
 732
 733                 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
 734                 if (req->cmd_type == REQ_TYPE_DRV_PRIV && req->special)
 735                         memcpy(req->special, &cqe, sizeof(cqe));
 736                 blk_mq_complete_request(req, le16_to_cpu(cqe.status) >> 1);
 737
 738         }
 739
 740         /* If the controller ignores the cq head doorbell and continuously
 741          * writes to the queue, it is theoretically possible to wrap around
 742          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 743          * requires that 0.1% of your interrupts are handled, so this isn't
 744          * a big problem.
 745          */
 746         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 747                 return;
 748
 749         if (likely(nvmeq->cq_vector >= 0))
 750                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 751         nvmeq->cq_head = head;
 752         nvmeq->cq_phase = phase;
 753
 754         nvmeq->cqe_seen = 1;
 755 }
 756
 757 static void nvme_process_cq(struct nvme_queue *nvmeq)
 758 {
 759         __nvme_process_cq(nvmeq, NULL);
 760 }
 761
 762 static irqreturn_t nvme_irq(int irq, void *data)
 763 {
 764         irqreturn_t result;
 765         struct nvme_queue *nvmeq = data;
 766         spin_lock(&nvmeq->q_lock);
 767         nvme_process_cq(nvmeq);
 768         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 769         nvmeq->cqe_seen = 0;
 770         spin_unlock(&nvmeq->q_lock);
 771         return result;
 772 }
 773
 774 static irqreturn_t nvme_irq_check(int irq, void *data)
 775 {
 776         struct nvme_queue *nvmeq = data;
 777         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
 778                 return IRQ_WAKE_THREAD;
 779         return IRQ_NONE;
 780 }
 781
 782 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
 783 {
 784         struct nvme_queue *nvmeq = hctx->driver_data;
 785
 786         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
 787                 spin_lock_irq(&nvmeq->q_lock);
 788                 __nvme_process_cq(nvmeq, &tag);
 789                 spin_unlock_irq(&nvmeq->q_lock);
 790
 791                 if (tag == -1)
 792                         return 1;
 793         }
 794
 795         return 0;
 796 }
 797
 798 static void nvme_async_event_work(struct work_struct *work)
 799 {
 800         struct nvme_dev *dev = container_of(work, struct nvme_dev, async_work);
 801         struct nvme_queue *nvmeq = dev->queues[0];
 802         struct nvme_command c;
 803
 804         memset(&c, 0, sizeof(c));
 805         c.common.opcode = nvme_admin_async_event;
 806
 807         spin_lock_irq(&nvmeq->q_lock);
 808         while (dev->ctrl.event_limit > 0) {
 809                 c.common.command_id = NVME_AQ_BLKMQ_DEPTH +
 810                         --dev->ctrl.event_limit;
 811                 __nvme_submit_cmd(nvmeq, &c);
 812         }
 813         spin_unlock_irq(&nvmeq->q_lock);
 814 }
 815
 816 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 817 {
 818         struct nvme_command c;
 819
 820         memset(&c, 0, sizeof(c));
 821         c.delete_queue.opcode = opcode;
 822         c.delete_queue.qid = cpu_to_le16(id);
 823
 824         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 825 }
 826
 827 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 828                                                 struct nvme_queue *nvmeq)
 829 {
 830         struct nvme_command c;
 831         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 832
 833         /*
 834          * Note: we (ab)use the fact the the prp fields survive if no data
 835          * is attached to the request.
 836          */
 837         memset(&c, 0, sizeof(c));
 838         c.create_cq.opcode = nvme_admin_create_cq;
 839         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 840         c.create_cq.cqid = cpu_to_le16(qid);
 841         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 842         c.create_cq.cq_flags = cpu_to_le16(flags);
 843         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 844
 845         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 846 }
 847
 848 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 849                                                 struct nvme_queue *nvmeq)
 850 {
 851         struct nvme_command c;
 852         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 853
 854         /*
 855          * Note: we (ab)use the fact the the prp fields survive if no data
 856          * is attached to the request.
 857          */
 858         memset(&c, 0, sizeof(c));
 859         c.create_sq.opcode = nvme_admin_create_sq;
 860         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 861         c.create_sq.sqid = cpu_to_le16(qid);
 862         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 863         c.create_sq.sq_flags = cpu_to_le16(flags);
 864         c.create_sq.cqid = cpu_to_le16(qid);
 865
 866         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 867 }
 868
 869 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 870 {
 871         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 872 }
 873
 874 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 875 {
 876         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 877 }
 878
 879 static void abort_endio(struct request *req, int error)
 880 {
 881         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 882         struct nvme_queue *nvmeq = iod->nvmeq;
 883         u16 status = req->errors;
 884
 885         dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status);
 886         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
 887         blk_mq_free_request(req);
 888 }
 889
 890 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
 891 {
 892         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 893         struct nvme_queue *nvmeq = iod->nvmeq;
 894         struct nvme_dev *dev = nvmeq->dev;
 895         struct request *abort_req;
 896         struct nvme_command cmd;
 897
 898         /*
 899          * Shutdown immediately if controller times out while starting. The
 900          * reset work will see the pci device disabled when it gets the forced
 901          * cancellation error. All outstanding requests are completed on
 902          * shutdown, so we return BLK_EH_HANDLED.
 903          */
 904         if (test_bit(NVME_CTRL_RESETTING, &dev->flags)) {
 905                 dev_warn(dev->ctrl.device,
 906                          "I/O %d QID %d timeout, disable controller\n",
 907                          req->tag, nvmeq->qid);
 908                 nvme_dev_disable(dev, false);
 909                 req->errors = NVME_SC_CANCELLED;
 910                 return BLK_EH_HANDLED;
 911         }
 912
 913         /*
 914          * Shutdown the controller immediately and schedule a reset if the
 915          * command was already aborted once before and still hasn't been
 916          * returned to the driver, or if this is the admin queue.
 917          */
 918         if (!nvmeq->qid || iod->aborted) {
 919                 dev_warn(dev->ctrl.device,
 920                          "I/O %d QID %d timeout, reset controller\n",
 921                          req->tag, nvmeq->qid);
 922                 nvme_dev_disable(dev, false);
 923                 queue_work(nvme_workq, &dev->reset_work);
 924
 925                 /*
 926                  * Mark the request as handled, since the inline shutdown
 927                  * forces all outstanding requests to complete.
 928                  */
 929                 req->errors = NVME_SC_CANCELLED;
 930                 return BLK_EH_HANDLED;
 931         }
 932
 933         iod->aborted = 1;
 934
 935         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
 936                 atomic_inc(&dev->ctrl.abort_limit);
 937                 return BLK_EH_RESET_TIMER;
 938         }
 939
 940         memset(&cmd, 0, sizeof(cmd));
 941         cmd.abort.opcode = nvme_admin_abort_cmd;
 942         cmd.abort.cid = req->tag;
 943         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
 944
 945         dev_warn(nvmeq->dev->ctrl.device,
 946                 "I/O %d QID %d timeout, aborting\n",
 947                  req->tag, nvmeq->qid);
 948
 949         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
 950                         BLK_MQ_REQ_NOWAIT);
 951         if (IS_ERR(abort_req)) {
 952                 atomic_inc(&dev->ctrl.abort_limit);
 953                 return BLK_EH_RESET_TIMER;
 954         }
 955
 956         abort_req->timeout = ADMIN_TIMEOUT;
 957         abort_req->end_io_data = NULL;
 958         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
 959
 960         /*
 961          * The aborted req will be completed on receiving the abort req.
 962          * We enable the timer again. If hit twice, it'll cause a device reset,
 963          * as the device then is in a faulty state.
 964          */
 965         return BLK_EH_RESET_TIMER;
 966 }
 967
 968 static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
 969 {
 970         struct nvme_queue *nvmeq = data;
 971         int status;
 972
 973         if (!blk_mq_request_started(req))
 974                 return;
 975
 976         dev_dbg_ratelimited(nvmeq->dev->ctrl.device,
 977                  "Cancelling I/O %d QID %d\n", req->tag, nvmeq->qid);
 978
 979         status = NVME_SC_ABORT_REQ;
 980         if (blk_queue_dying(req->q))
 981                 status |= NVME_SC_DNR;
 982         blk_mq_complete_request(req, status);
 983 }
 984
 985 static void nvme_free_queue(struct nvme_queue *nvmeq)
 986 {
 987         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 988                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 989         if (nvmeq->sq_cmds)
 990                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 991                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 992         kfree(nvmeq);
 993 }
 994
 995 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
 996 {
 997         int i;
 998
 999         for (i = dev->queue_count - 1; i >= lowest; i--) {
1000                 struct nvme_queue *nvmeq = dev->queues[i];
1001                 dev->queue_count--;
1002                 dev->queues[i] = NULL;
1003                 nvme_free_queue(nvmeq);
1004         }
1005 }
1006
1007 /**
1008  * nvme_suspend_queue - put queue into suspended state
1009  * @nvmeq - queue to suspend
1010  */
1011 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1012 {
1013         int vector;
1014
1015         spin_lock_irq(&nvmeq->q_lock);
1016         if (nvmeq->cq_vector == -1) {
1017                 spin_unlock_irq(&nvmeq->q_lock);
1018                 return 1;
1019         }
1020         vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1021         nvmeq->dev->online_queues--;
1022         nvmeq->cq_vector = -1;
1023         spin_unlock_irq(&nvmeq->q_lock);
1024
1025         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1026                 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
1027
1028         irq_set_affinity_hint(vector, NULL);
1029         free_irq(vector, nvmeq);
1030
1031         return 0;
1032 }
1033
1034 static void nvme_clear_queue(struct nvme_queue *nvmeq)
1035 {
1036         spin_lock_irq(&nvmeq->q_lock);
1037         if (nvmeq->tags && *nvmeq->tags)
1038                 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
1039         spin_unlock_irq(&nvmeq->q_lock);
1040 }
1041
1042 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1043 {
1044         struct nvme_queue *nvmeq = dev->queues[0];
1045
1046         if (!nvmeq)
1047                 return;
1048         if (nvme_suspend_queue(nvmeq))
1049                 return;
1050
1051         if (shutdown)
1052                 nvme_shutdown_ctrl(&dev->ctrl);
1053         else
1054                 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
1055                                                 dev->bar + NVME_REG_CAP));
1056
1057         spin_lock_irq(&nvmeq->q_lock);
1058         nvme_process_cq(nvmeq);
1059         spin_unlock_irq(&nvmeq->q_lock);
1060 }
1061
1062 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1063                                 int entry_size)
1064 {
1065         int q_depth = dev->q_depth;
1066         unsigned q_size_aligned = roundup(q_depth * entry_size,
1067                                           dev->ctrl.page_size);
1068
1069         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1070                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1071                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1072                 q_depth = div_u64(mem_per_q, entry_size);
1073
1074                 /*
1075                  * Ensure the reduced q_depth is above some threshold where it
1076                  * would be better to map queues in system memory with the
1077                  * original depth
1078                  */
1079                 if (q_depth < 64)
1080                         return -ENOMEM;
1081         }
1082
1083         return q_depth;
1084 }
1085
1086 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1087                                 int qid, int depth)
1088 {
1089         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1090                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1091                                                       dev->ctrl.page_size);
1092                 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1093                 nvmeq->sq_cmds_io = dev->cmb + offset;
1094         } else {
1095                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1096                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1097                 if (!nvmeq->sq_cmds)
1098                         return -ENOMEM;
1099         }
1100
1101         return 0;
1102 }
1103
1104 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1105                                                         int depth)
1106 {
1107         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1108         if (!nvmeq)
1109                 return NULL;
1110
1111         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1112                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1113         if (!nvmeq->cqes)
1114                 goto free_nvmeq;
1115
1116         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1117                 goto free_cqdma;
1118
1119         nvmeq->q_dmadev = dev->dev;
1120         nvmeq->dev = dev;
1121         snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1122                         dev->ctrl.instance, qid);
1123         spin_lock_init(&nvmeq->q_lock);
1124         nvmeq->cq_head = 0;
1125         nvmeq->cq_phase = 1;
1126         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1127         nvmeq->q_depth = depth;
1128         nvmeq->qid = qid;
1129         nvmeq->cq_vector = -1;
1130         dev->queues[qid] = nvmeq;
1131         dev->queue_count++;
1132
1133         return nvmeq;
1134
1135  free_cqdma:
1136         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1137                                                         nvmeq->cq_dma_addr);
1138  free_nvmeq:
1139         kfree(nvmeq);
1140         return NULL;
1141 }
1142
1143 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1144                                                         const char *name)
1145 {
1146         if (use_threaded_interrupts)
1147                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1148                                         nvme_irq_check, nvme_irq, IRQF_SHARED,
1149                                         name, nvmeq);
1150         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1151                                 IRQF_SHARED, name, nvmeq);
1152 }
1153
1154 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1155 {
1156         struct nvme_dev *dev = nvmeq->dev;
1157
1158         spin_lock_irq(&nvmeq->q_lock);
1159         nvmeq->sq_tail = 0;
1160         nvmeq->cq_head = 0;
1161         nvmeq->cq_phase = 1;
1162         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1163         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1164         dev->online_queues++;
1165         spin_unlock_irq(&nvmeq->q_lock);
1166 }
1167
1168 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1169 {
1170         struct nvme_dev *dev = nvmeq->dev;
1171         int result;
1172
1173         nvmeq->cq_vector = qid - 1;
1174         result = adapter_alloc_cq(dev, qid, nvmeq);
1175         if (result < 0)
1176                 return result;
1177
1178         result = adapter_alloc_sq(dev, qid, nvmeq);
1179         if (result < 0)
1180                 goto release_cq;
1181
1182         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1183         if (result < 0)
1184                 goto release_sq;
1185
1186         nvme_init_queue(nvmeq, qid);
1187         return result;
1188
1189  release_sq:
1190         adapter_delete_sq(dev, qid);
1191  release_cq:
1192         adapter_delete_cq(dev, qid);
1193         return result;
1194 }
1195
1196 static struct blk_mq_ops nvme_mq_admin_ops = {
1197         .queue_rq       = nvme_queue_rq,
1198         .complete       = nvme_complete_rq,
1199         .map_queue      = blk_mq_map_queue,
1200         .init_hctx      = nvme_admin_init_hctx,
1201         .exit_hctx      = nvme_admin_exit_hctx,
1202         .init_request   = nvme_admin_init_request,
1203         .timeout        = nvme_timeout,
1204 };
1205
1206 static struct blk_mq_ops nvme_mq_ops = {
1207         .queue_rq       = nvme_queue_rq,
1208         .complete       = nvme_complete_rq,
1209         .map_queue      = blk_mq_map_queue,
1210         .init_hctx      = nvme_init_hctx,
1211         .init_request   = nvme_init_request,
1212         .timeout        = nvme_timeout,
1213         .poll           = nvme_poll,
1214 };
1215
1216 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1217 {
1218         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1219                 /*
1220                  * If the controller was reset during removal, it's possible
1221                  * user requests may be waiting on a stopped queue. Start the
1222                  * queue to flush these to completion.
1223                  */
1224                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1225                 blk_cleanup_queue(dev->ctrl.admin_q);
1226                 blk_mq_free_tag_set(&dev->admin_tagset);
1227         }
1228 }
1229
1230 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1231 {
1232         if (!dev->ctrl.admin_q) {
1233                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1234                 dev->admin_tagset.nr_hw_queues = 1;
1235
1236                 /*
1237                  * Subtract one to leave an empty queue entry for 'Full Queue'
1238                  * condition. See NVM-Express 1.2 specification, section 4.1.2.
1239                  */
1240                 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1241                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1242                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1243                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1244                 dev->admin_tagset.driver_data = dev;
1245
1246                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1247                         return -ENOMEM;
1248
1249                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1250                 if (IS_ERR(dev->ctrl.admin_q)) {
1251                         blk_mq_free_tag_set(&dev->admin_tagset);
1252                         return -ENOMEM;
1253                 }
1254                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1255                         nvme_dev_remove_admin(dev);
1256                         dev->ctrl.admin_q = NULL;
1257                         return -ENODEV;
1258                 }
1259         } else
1260                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1261
1262         return 0;
1263 }
1264
1265 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1266 {
1267         int result;
1268         u32 aqa;
1269         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1270         struct nvme_queue *nvmeq;
1271
1272         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ?
1273                                                 NVME_CAP_NSSRC(cap) : 0;
1274
1275         if (dev->subsystem &&
1276             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1277                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1278
1279         result = nvme_disable_ctrl(&dev->ctrl, cap);
1280         if (result < 0)
1281                 return result;
1282
1283         nvmeq = dev->queues[0];
1284         if (!nvmeq) {
1285                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1286                 if (!nvmeq)
1287                         return -ENOMEM;
1288         }
1289
1290         aqa = nvmeq->q_depth - 1;
1291         aqa |= aqa << 16;
1292
1293         writel(aqa, dev->bar + NVME_REG_AQA);
1294         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1295         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1296
1297         result = nvme_enable_ctrl(&dev->ctrl, cap);
1298         if (result)
1299                 goto free_nvmeq;
1300
1301         nvmeq->cq_vector = 0;
1302         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1303         if (result) {
1304                 nvmeq->cq_vector = -1;
1305                 goto free_nvmeq;
1306         }
1307
1308         return result;
1309
1310  free_nvmeq:
1311         nvme_free_queues(dev, 0);
1312         return result;
1313 }
1314
1315 static void nvme_watchdog_timer(unsigned long data)
1316 {
1317         struct nvme_dev *dev = (struct nvme_dev *)data;
1318         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1319
1320         /*
1321          * Skip controllers currently under reset.
1322          */
1323         if (!work_pending(&dev->reset_work) && !work_busy(&dev->reset_work) &&
1324             ((csts & NVME_CSTS_CFS) ||
1325              (dev->subsystem && (csts & NVME_CSTS_NSSRO)))) {
1326                 if (queue_work(nvme_workq, &dev->reset_work)) {
1327                         dev_warn(dev->dev,
1328                                 "Failed status: 0x%x, reset controller.\n",
1329                                 csts);
1330                 }
1331                 return;
1332         }
1333
1334         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1335 }
1336
1337 static int nvme_create_io_queues(struct nvme_dev *dev)
1338 {
1339         unsigned i, max;
1340         int ret = 0;
1341
1342         for (i = dev->queue_count; i <= dev->max_qid; i++) {
1343                 if (!nvme_alloc_queue(dev, i, dev->q_depth)) {
1344                         ret = -ENOMEM;
1345                         break;
1346                 }
1347         }
1348
1349         max = min(dev->max_qid, dev->queue_count - 1);
1350         for (i = dev->online_queues; i <= max; i++) {
1351                 ret = nvme_create_queue(dev->queues[i], i);
1352                 if (ret) {
1353                         nvme_free_queues(dev, i);
1354                         break;
1355                 }
1356         }
1357
1358         /*
1359          * Ignore failing Create SQ/CQ commands, we can continue with less
1360          * than the desired aount of queues, and even a controller without
1361          * I/O queues an still be used to issue admin commands.  This might
1362          * be useful to upgrade a buggy firmware for example.
1363          */
1364         return ret >= 0 ? 0 : ret;
1365 }
1366
1367 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1368 {
1369         u64 szu, size, offset;
1370         u32 cmbloc;
1371         resource_size_t bar_size;
1372         struct pci_dev *pdev = to_pci_dev(dev->dev);
1373         void __iomem *cmb;
1374         dma_addr_t dma_addr;
1375
1376         if (!use_cmb_sqes)
1377                 return NULL;
1378
1379         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1380         if (!(NVME_CMB_SZ(dev->cmbsz)))
1381                 return NULL;
1382
1383         cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1384
1385         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1386         size = szu * NVME_CMB_SZ(dev->cmbsz);
1387         offset = szu * NVME_CMB_OFST(cmbloc);
1388         bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
1389
1390         if (offset > bar_size)
1391                 return NULL;
1392
1393         /*
1394          * Controllers may support a CMB size larger than their BAR,
1395          * for example, due to being behind a bridge. Reduce the CMB to
1396          * the reported size of the BAR
1397          */
1398         if (size > bar_size - offset)
1399                 size = bar_size - offset;
1400
1401         dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
1402         cmb = ioremap_wc(dma_addr, size);
1403         if (!cmb)
1404                 return NULL;
1405
1406         dev->cmb_dma_addr = dma_addr;
1407         dev->cmb_size = size;
1408         return cmb;
1409 }
1410
1411 static inline void nvme_release_cmb(struct nvme_dev *dev)
1412 {
1413         if (dev->cmb) {
1414                 iounmap(dev->cmb);
1415                 dev->cmb = NULL;
1416         }
1417 }
1418
1419 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1420 {
1421         return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1422 }
1423
1424 static int nvme_setup_io_queues(struct nvme_dev *dev)
1425 {
1426         struct nvme_queue *adminq = dev->queues[0];
1427         struct pci_dev *pdev = to_pci_dev(dev->dev);
1428         int result, i, vecs, nr_io_queues, size;
1429
1430         nr_io_queues = num_possible_cpus();
1431         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1432         if (result < 0)
1433                 return result;
1434
1435         /*
1436          * Degraded controllers might return an error when setting the queue
1437          * count.  We still want to be able to bring them online and offer
1438          * access to the admin queue, as that might be only way to fix them up.
1439          */
1440         if (result > 0) {
1441                 dev_err(dev->ctrl.device,
1442                         "Could not set queue count (%d)\n", result);
1443                 return 0;
1444         }
1445
1446         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1447                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1448                                 sizeof(struct nvme_command));
1449                 if (result > 0)
1450                         dev->q_depth = result;
1451                 else
1452                         nvme_release_cmb(dev);
1453         }
1454
1455         size = db_bar_size(dev, nr_io_queues);
1456         if (size > 8192) {
1457                 iounmap(dev->bar);
1458                 do {
1459                         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1460                         if (dev->bar)
1461                                 break;
1462                         if (!--nr_io_queues)
1463                                 return -ENOMEM;
1464                         size = db_bar_size(dev, nr_io_queues);
1465                 } while (1);
1466                 dev->dbs = dev->bar + 4096;
1467                 adminq->q_db = dev->dbs;
1468         }
1469
1470         /* Deregister the admin queue's interrupt */
1471         free_irq(dev->entry[0].vector, adminq);
1472
1473         /*
1474          * If we enable msix early due to not intx, disable it again before
1475          * setting up the full range we need.
1476          */
1477         if (pdev->msi_enabled)
1478                 pci_disable_msi(pdev);
1479         else if (pdev->msix_enabled)
1480                 pci_disable_msix(pdev);
1481
1482         for (i = 0; i < nr_io_queues; i++)
1483                 dev->entry[i].entry = i;
1484         vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
1485         if (vecs < 0) {
1486                 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
1487                 if (vecs < 0) {
1488                         vecs = 1;
1489                 } else {
1490                         for (i = 0; i < vecs; i++)
1491                                 dev->entry[i].vector = i + pdev->irq;
1492                 }
1493         }
1494
1495         /*
1496          * Should investigate if there's a performance win from allocating
1497          * more queues than interrupt vectors; it might allow the submission
1498          * path to scale better, even if the receive path is limited by the
1499          * number of interrupts.
1500          */
1501         nr_io_queues = vecs;
1502         dev->max_qid = nr_io_queues;
1503
1504         result = queue_request_irq(dev, adminq, adminq->irqname);
1505         if (result) {
1506                 adminq->cq_vector = -1;
1507                 goto free_queues;
1508         }
1509         return nvme_create_io_queues(dev);
1510
1511  free_queues:
1512         nvme_free_queues(dev, 1);
1513         return result;
1514 }
1515
1516 static void nvme_set_irq_hints(struct nvme_dev *dev)
1517 {
1518         struct nvme_queue *nvmeq;
1519         int i;
1520
1521         for (i = 0; i < dev->online_queues; i++) {
1522                 nvmeq = dev->queues[i];
1523
1524                 if (!nvmeq->tags || !(*nvmeq->tags))
1525                         continue;
1526
1527                 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
1528                                         blk_mq_tags_cpumask(*nvmeq->tags));
1529         }
1530 }
1531
1532 static void nvme_dev_scan(struct work_struct *work)
1533 {
1534         struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
1535
1536         if (!dev->tagset.tags)
1537                 return;
1538         nvme_scan_namespaces(&dev->ctrl);
1539         nvme_set_irq_hints(dev);
1540 }
1541
1542 static void nvme_del_queue_end(struct request *req, int error)
1543 {
1544         struct nvme_queue *nvmeq = req->end_io_data;
1545
1546         blk_mq_free_request(req);
1547         complete(&nvmeq->dev->ioq_wait);
1548 }
1549
1550 static void nvme_del_cq_end(struct request *req, int error)
1551 {
1552         struct nvme_queue *nvmeq = req->end_io_data;
1553
1554         if (!error) {
1555                 unsigned long flags;
1556
1557                 /*
1558                  * We might be called with the AQ q_lock held
1559                  * and the I/O queue q_lock should always
1560                  * nest inside the AQ one.
1561                  */
1562                 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1563                                         SINGLE_DEPTH_NESTING);
1564                 nvme_process_cq(nvmeq);
1565                 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1566         }
1567
1568         nvme_del_queue_end(req, error);
1569 }
1570
1571 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1572 {
1573         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1574         struct request *req;
1575         struct nvme_command cmd;
1576
1577         memset(&cmd, 0, sizeof(cmd));
1578         cmd.delete_queue.opcode = opcode;
1579         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1580
1581         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
1582         if (IS_ERR(req))
1583                 return PTR_ERR(req);
1584
1585         req->timeout = ADMIN_TIMEOUT;
1586         req->end_io_data = nvmeq;
1587
1588         blk_execute_rq_nowait(q, NULL, req, false,
1589                         opcode == nvme_admin_delete_cq ?
1590                                 nvme_del_cq_end : nvme_del_queue_end);
1591         return 0;
1592 }
1593
1594 static void nvme_disable_io_queues(struct nvme_dev *dev)
1595 {
1596         int pass;
1597         unsigned long timeout;
1598         u8 opcode = nvme_admin_delete_sq;
1599
1600         for (pass = 0; pass < 2; pass++) {
1601                 int sent = 0, i = dev->queue_count - 1;
1602
1603                 reinit_completion(&dev->ioq_wait);
1604  retry:
1605                 timeout = ADMIN_TIMEOUT;
1606                 for (; i > 0; i--) {
1607                         struct nvme_queue *nvmeq = dev->queues[i];
1608
1609                         if (!pass)
1610                                 nvme_suspend_queue(nvmeq);
1611                         if (nvme_delete_queue(nvmeq, opcode))
1612                                 break;
1613                         ++sent;
1614                 }
1615                 while (sent--) {
1616                         timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1617                         if (timeout == 0)
1618                                 return;
1619                         if (i)
1620                                 goto retry;
1621                 }
1622                 opcode = nvme_admin_delete_cq;
1623         }
1624 }
1625
1626 /*
1627  * Return: error value if an error occurred setting up the queues or calling
1628  * Identify Device.  0 if these succeeded, even if adding some of the
1629  * namespaces failed.  At the moment, these failures are silent.  TBD which
1630  * failures should be reported.
1631  */
1632 static int nvme_dev_add(struct nvme_dev *dev)
1633 {
1634         if (!dev->ctrl.tagset) {
1635                 dev->tagset.ops = &nvme_mq_ops;
1636                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1637                 dev->tagset.timeout = NVME_IO_TIMEOUT;
1638                 dev->tagset.numa_node = dev_to_node(dev->dev);
1639                 dev->tagset.queue_depth =
1640                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1641                 dev->tagset.cmd_size = nvme_cmd_size(dev);
1642                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1643                 dev->tagset.driver_data = dev;
1644
1645                 if (blk_mq_alloc_tag_set(&dev->tagset))
1646                         return 0;
1647                 dev->ctrl.tagset = &dev->tagset;
1648         } else {
1649                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1650
1651                 /* Free previously allocated queues that are no longer usable */
1652                 nvme_free_queues(dev, dev->online_queues);
1653         }
1654
1655         nvme_queue_scan(dev);
1656         return 0;
1657 }
1658
1659 static int nvme_pci_enable(struct nvme_dev *dev)
1660 {
1661         u64 cap;
1662         int result = -ENOMEM;
1663         struct pci_dev *pdev = to_pci_dev(dev->dev);
1664
1665         if (pci_enable_device_mem(pdev))
1666                 return result;
1667
1668         pci_set_master(pdev);
1669
1670         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1671             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1672                 goto disable;
1673
1674         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1675                 result = -ENODEV;
1676                 goto disable;
1677         }
1678
1679         /*
1680          * Some devices and/or platforms don't advertise or work with INTx
1681          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1682          * adjust this later.
1683          */
1684         if (pci_enable_msix(pdev, dev->entry, 1)) {
1685                 pci_enable_msi(pdev);
1686                 dev->entry[0].vector = pdev->irq;
1687         }
1688
1689         if (!dev->entry[0].vector) {
1690                 result = -ENODEV;
1691                 goto disable;
1692         }
1693
1694         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1695
1696         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1697         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1698         dev->dbs = dev->bar + 4096;
1699
1700         /*
1701          * Temporary fix for the Apple controller found in the MacBook8,1 and
1702          * some MacBook7,1 to avoid controller resets and data loss.
1703          */
1704         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1705                 dev->q_depth = 2;
1706                 dev_warn(dev->dev, "detected Apple NVMe controller, set "
1707                         "queue depth=%u to work around controller resets\n",
1708                         dev->q_depth);
1709         }
1710
1711         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2))
1712                 dev->cmb = nvme_map_cmb(dev);
1713
1714         pci_enable_pcie_error_reporting(pdev);
1715         pci_save_state(pdev);
1716         return 0;
1717
1718  disable:
1719         pci_disable_device(pdev);
1720         return result;
1721 }
1722
1723 static void nvme_dev_unmap(struct nvme_dev *dev)
1724 {
1725         if (dev->bar)
1726                 iounmap(dev->bar);
1727         pci_release_regions(to_pci_dev(dev->dev));
1728 }
1729
1730 static void nvme_pci_disable(struct nvme_dev *dev)
1731 {
1732         struct pci_dev *pdev = to_pci_dev(dev->dev);
1733
1734         if (pdev->msi_enabled)
1735                 pci_disable_msi(pdev);
1736         else if (pdev->msix_enabled)
1737                 pci_disable_msix(pdev);
1738
1739         if (pci_is_enabled(pdev)) {
1740                 pci_disable_pcie_error_reporting(pdev);
1741                 pci_disable_device(pdev);
1742         }
1743 }
1744
1745 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1746 {
1747         int i;
1748         u32 csts = -1;
1749
1750         del_timer_sync(&dev->watchdog_timer);
1751
1752         mutex_lock(&dev->shutdown_lock);
1753         if (pci_is_enabled(to_pci_dev(dev->dev))) {
1754                 nvme_stop_queues(&dev->ctrl);
1755                 csts = readl(dev->bar + NVME_REG_CSTS);
1756         }
1757         if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
1758                 for (i = dev->queue_count - 1; i >= 0; i--) {
1759                         struct nvme_queue *nvmeq = dev->queues[i];
1760                         nvme_suspend_queue(nvmeq);
1761                 }
1762         } else {
1763                 nvme_disable_io_queues(dev);
1764                 nvme_disable_admin_queue(dev, shutdown);
1765         }
1766         nvme_pci_disable(dev);
1767
1768         for (i = dev->queue_count - 1; i >= 0; i--)
1769                 nvme_clear_queue(dev->queues[i]);
1770         mutex_unlock(&dev->shutdown_lock);
1771 }
1772
1773 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1774 {
1775         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1776                                                 PAGE_SIZE, PAGE_SIZE, 0);
1777         if (!dev->prp_page_pool)
1778                 return -ENOMEM;
1779
1780         /* Optimisation for I/Os between 4k and 128k */
1781         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
1782                                                 256, 256, 0);
1783         if (!dev->prp_small_pool) {
1784                 dma_pool_destroy(dev->prp_page_pool);
1785                 return -ENOMEM;
1786         }
1787         return 0;
1788 }
1789
1790 static void nvme_release_prp_pools(struct nvme_dev *dev)
1791 {
1792         dma_pool_destroy(dev->prp_page_pool);
1793         dma_pool_destroy(dev->prp_small_pool);
1794 }
1795
1796 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
1797 {
1798         struct nvme_dev *dev = to_nvme_dev(ctrl);
1799
1800         put_device(dev->dev);
1801         if (dev->tagset.tags)
1802                 blk_mq_free_tag_set(&dev->tagset);
1803         if (dev->ctrl.admin_q)
1804                 blk_put_queue(dev->ctrl.admin_q);
1805         kfree(dev->queues);
1806         kfree(dev->entry);
1807         kfree(dev);
1808 }
1809
1810 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
1811 {
1812         dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
1813
1814         kref_get(&dev->ctrl.kref);
1815         nvme_dev_disable(dev, false);
1816         if (!schedule_work(&dev->remove_work))
1817                 nvme_put_ctrl(&dev->ctrl);
1818 }
1819
1820 static void nvme_reset_work(struct work_struct *work)
1821 {
1822         struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
1823         int result = -ENODEV;
1824
1825         if (WARN_ON(test_bit(NVME_CTRL_RESETTING, &dev->flags)))
1826                 goto out;
1827
1828         /*
1829          * If we're called to reset a live controller first shut it down before
1830          * moving on.
1831          */
1832         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
1833                 nvme_dev_disable(dev, false);
1834
1835         set_bit(NVME_CTRL_RESETTING, &dev->flags);
1836
1837         result = nvme_pci_enable(dev);
1838         if (result)
1839                 goto out;
1840
1841         result = nvme_configure_admin_queue(dev);
1842         if (result)
1843                 goto out;
1844
1845         nvme_init_queue(dev->queues[0], 0);
1846         result = nvme_alloc_admin_tags(dev);
1847         if (result)
1848                 goto out;
1849
1850         result = nvme_init_identify(&dev->ctrl);
1851         if (result)
1852                 goto out;
1853
1854         result = nvme_setup_io_queues(dev);
1855         if (result)
1856                 goto out;
1857
1858         dev->ctrl.event_limit = NVME_NR_AEN_COMMANDS;
1859         queue_work(nvme_workq, &dev->async_work);
1860
1861         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1862
1863         /*
1864          * Keep the controller around but remove all namespaces if we don't have
1865          * any working I/O queue.
1866          */
1867         if (dev->online_queues < 2) {
1868                 dev_warn(dev->ctrl.device, "IO queues not created\n");
1869                 nvme_remove_namespaces(&dev->ctrl);
1870         } else {
1871                 nvme_start_queues(&dev->ctrl);
1872                 nvme_dev_add(dev);
1873         }
1874
1875         clear_bit(NVME_CTRL_RESETTING, &dev->flags);
1876         return;
1877
1878  out:
1879         nvme_remove_dead_ctrl(dev, result);
1880 }
1881
1882 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
1883 {
1884         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
1885         struct pci_dev *pdev = to_pci_dev(dev->dev);
1886
1887         nvme_kill_queues(&dev->ctrl);
1888         if (pci_get_drvdata(pdev))
1889                 pci_stop_and_remove_bus_device_locked(pdev);
1890         nvme_put_ctrl(&dev->ctrl);
1891 }
1892
1893 static int nvme_reset(struct nvme_dev *dev)
1894 {
1895         if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
1896                 return -ENODEV;
1897
1898         if (!queue_work(nvme_workq, &dev->reset_work))
1899                 return -EBUSY;
1900
1901         flush_work(&dev->reset_work);
1902         return 0;
1903 }
1904
1905 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
1906 {
1907         *val = readl(to_nvme_dev(ctrl)->bar + off);
1908         return 0;
1909 }
1910
1911 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
1912 {
1913         writel(val, to_nvme_dev(ctrl)->bar + off);
1914         return 0;
1915 }
1916
1917 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
1918 {
1919         *val = readq(to_nvme_dev(ctrl)->bar + off);
1920         return 0;
1921 }
1922
1923 static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl)
1924 {
1925         struct nvme_dev *dev = to_nvme_dev(ctrl);
1926
1927         return !dev->bar || dev->online_queues < 2;
1928 }
1929
1930 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
1931 {
1932         return nvme_reset(to_nvme_dev(ctrl));
1933 }
1934
1935 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1936         .module                 = THIS_MODULE,
1937         .reg_read32             = nvme_pci_reg_read32,
1938         .reg_write32            = nvme_pci_reg_write32,
1939         .reg_read64             = nvme_pci_reg_read64,
1940         .io_incapable           = nvme_pci_io_incapable,
1941         .reset_ctrl             = nvme_pci_reset_ctrl,
1942         .free_ctrl              = nvme_pci_free_ctrl,
1943 };
1944
1945 static int nvme_dev_map(struct nvme_dev *dev)
1946 {
1947         int bars;
1948         struct pci_dev *pdev = to_pci_dev(dev->dev);
1949
1950         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1951         if (!bars)
1952                 return -ENODEV;
1953         if (pci_request_selected_regions(pdev, bars, "nvme"))
1954                 return -ENODEV;
1955
1956         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1957         if (!dev->bar)
1958                 goto release;
1959
1960        return 0;
1961   release:
1962        pci_release_regions(pdev);
1963        return -ENODEV;
1964 }
1965
1966 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1967 {
1968         int node, result = -ENOMEM;
1969         struct nvme_dev *dev;
1970
1971         node = dev_to_node(&pdev->dev);
1972         if (node == NUMA_NO_NODE)
1973                 set_dev_node(&pdev->dev, 0);
1974
1975         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
1976         if (!dev)
1977                 return -ENOMEM;
1978         dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
1979                                                         GFP_KERNEL, node);
1980         if (!dev->entry)
1981                 goto free;
1982         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
1983                                                         GFP_KERNEL, node);
1984         if (!dev->queues)
1985                 goto free;
1986
1987         dev->dev = get_device(&pdev->dev);
1988         pci_set_drvdata(pdev, dev);
1989
1990         result = nvme_dev_map(dev);
1991         if (result)
1992                 goto free;
1993
1994         INIT_WORK(&dev->scan_work, nvme_dev_scan);
1995         INIT_WORK(&dev->reset_work, nvme_reset_work);
1996         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
1997         INIT_WORK(&dev->async_work, nvme_async_event_work);
1998         setup_timer(&dev->watchdog_timer, nvme_watchdog_timer,
1999                 (unsigned long)dev);
2000         mutex_init(&dev->shutdown_lock);
2001         init_completion(&dev->ioq_wait);
2002
2003         result = nvme_setup_prp_pools(dev);
2004         if (result)
2005                 goto put_pci;
2006
2007         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2008                         id->driver_data);
2009         if (result)
2010                 goto release_pools;
2011
2012         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2013
2014         queue_work(nvme_workq, &dev->reset_work);
2015         return 0;
2016
2017  release_pools:
2018         nvme_release_prp_pools(dev);
2019  put_pci:
2020         put_device(dev->dev);
2021         nvme_dev_unmap(dev);
2022  free:
2023         kfree(dev->queues);
2024         kfree(dev->entry);
2025         kfree(dev);
2026         return result;
2027 }
2028
2029 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2030 {
2031         struct nvme_dev *dev = pci_get_drvdata(pdev);
2032
2033         if (prepare)
2034                 nvme_dev_disable(dev, false);
2035         else
2036                 queue_work(nvme_workq, &dev->reset_work);
2037 }
2038
2039 static void nvme_shutdown(struct pci_dev *pdev)
2040 {
2041         struct nvme_dev *dev = pci_get_drvdata(pdev);
2042         nvme_dev_disable(dev, true);
2043 }
2044
2045 /*
2046  * The driver's remove may be called on a device in a partially initialized
2047  * state. This function must not have any dependencies on the device state in
2048  * order to proceed.
2049  */
2050 static void nvme_remove(struct pci_dev *pdev)
2051 {
2052         struct nvme_dev *dev = pci_get_drvdata(pdev);
2053
2054         del_timer_sync(&dev->watchdog_timer);
2055
2056         set_bit(NVME_CTRL_REMOVING, &dev->flags);
2057         pci_set_drvdata(pdev, NULL);
2058         flush_work(&dev->async_work);
2059         flush_work(&dev->scan_work);
2060         nvme_remove_namespaces(&dev->ctrl);
2061         nvme_uninit_ctrl(&dev->ctrl);
2062         nvme_dev_disable(dev, true);
2063         flush_work(&dev->reset_work);
2064         nvme_dev_remove_admin(dev);
2065         nvme_free_queues(dev, 0);
2066         nvme_release_cmb(dev);
2067         nvme_release_prp_pools(dev);
2068         nvme_dev_unmap(dev);
2069         nvme_put_ctrl(&dev->ctrl);
2070 }
2071
2072 #ifdef CONFIG_PM_SLEEP
2073 static int nvme_suspend(struct device *dev)
2074 {
2075         struct pci_dev *pdev = to_pci_dev(dev);
2076         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2077
2078         nvme_dev_disable(ndev, true);
2079         return 0;
2080 }
2081
2082 static int nvme_resume(struct device *dev)
2083 {
2084         struct pci_dev *pdev = to_pci_dev(dev);
2085         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2086
2087         queue_work(nvme_workq, &ndev->reset_work);
2088         return 0;
2089 }
2090 #endif
2091
2092 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2093
2094 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2095                                                 pci_channel_state_t state)
2096 {
2097         struct nvme_dev *dev = pci_get_drvdata(pdev);
2098
2099         /*
2100          * A frozen channel requires a reset. When detected, this method will
2101          * shutdown the controller to quiesce. The controller will be restarted
2102          * after the slot reset through driver's slot_reset callback.
2103          */
2104         dev_warn(dev->ctrl.device, "error detected: state:%d\n", state);
2105         switch (state) {
2106         case pci_channel_io_normal:
2107                 return PCI_ERS_RESULT_CAN_RECOVER;
2108         case pci_channel_io_frozen:
2109                 nvme_dev_disable(dev, false);
2110                 return PCI_ERS_RESULT_NEED_RESET;
2111         case pci_channel_io_perm_failure:
2112                 return PCI_ERS_RESULT_DISCONNECT;
2113         }
2114         return PCI_ERS_RESULT_NEED_RESET;
2115 }
2116
2117 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2118 {
2119         struct nvme_dev *dev = pci_get_drvdata(pdev);
2120
2121         dev_info(dev->ctrl.device, "restart after slot reset\n");
2122         pci_restore_state(pdev);
2123         queue_work(nvme_workq, &dev->reset_work);
2124         return PCI_ERS_RESULT_RECOVERED;
2125 }
2126
2127 static void nvme_error_resume(struct pci_dev *pdev)
2128 {
2129         pci_cleanup_aer_uncorrect_error_status(pdev);
2130 }
2131
2132 static const struct pci_error_handlers nvme_err_handler = {
2133         .error_detected = nvme_error_detected,
2134         .slot_reset     = nvme_slot_reset,
2135         .resume         = nvme_error_resume,
2136         .reset_notify   = nvme_reset_notify,
2137 };
2138
2139 /* Move to pci_ids.h later */
2140 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
2141
2142 static const struct pci_device_id nvme_id_table[] = {
2143         { PCI_VDEVICE(INTEL, 0x0953),
2144                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2145                                 NVME_QUIRK_DISCARD_ZEROES, },
2146         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2147                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2148         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2149         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2150         { 0, }
2151 };
2152 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2153
2154 static struct pci_driver nvme_driver = {
2155         .name           = "nvme",
2156         .id_table       = nvme_id_table,
2157         .probe          = nvme_probe,
2158         .remove         = nvme_remove,
2159         .shutdown       = nvme_shutdown,
2160         .driver         = {
2161                 .pm     = &nvme_dev_pm_ops,
2162         },
2163         .err_handler    = &nvme_err_handler,
2164 };
2165
2166 static int __init nvme_init(void)
2167 {
2168         int result;
2169
2170         nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2171         if (!nvme_workq)
2172                 return -ENOMEM;
2173
2174         result = pci_register_driver(&nvme_driver);
2175         if (result)
2176                 destroy_workqueue(nvme_workq);
2177         return result;
2178 }
2179
2180 static void __exit nvme_exit(void)
2181 {
2182         pci_unregister_driver(&nvme_driver);
2183         destroy_workqueue(nvme_workq);
2184         _nvme_check_size();
2185 }
2186
2187 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2188 MODULE_LICENSE("GPL");
2189 MODULE_VERSION("1.0");
2190 module_init(nvme_init);
2191 module_exit(nvme_exit);