2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/blk-mq-pci.h>
20 #include <linux/dmi.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
25 #include <linux/module.h>
26 #include <linux/mutex.h>
27 #include <linux/pci.h>
28 #include <linux/poison.h>
29 #include <linux/t10-pi.h>
30 #include <linux/timer.h>
31 #include <linux/types.h>
32 #include <linux/io-64-nonatomic-lo-hi.h>
33 #include <asm/unaligned.h>
34 #include <linux/sed-opal.h>
38 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
39 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
42 * We handle AEN commands ourselves and don't even let the
43 * block layer know about them.
45 #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS)
47 static int use_threaded_interrupts;
48 module_param(use_threaded_interrupts, int, 0);
50 static bool use_cmb_sqes = true;
51 module_param(use_cmb_sqes, bool, 0644);
52 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
54 static unsigned int max_host_mem_size_mb = 128;
55 module_param(max_host_mem_size_mb, uint, 0444);
56 MODULE_PARM_DESC(max_host_mem_size_mb,
57 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
59 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
60 static const struct kernel_param_ops io_queue_depth_ops = {
61 .set = io_queue_depth_set,
65 static int io_queue_depth = 1024;
66 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
67 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
72 static void nvme_process_cq(struct nvme_queue *nvmeq);
73 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
76 * Represents an NVM Express device. Each nvme_dev is a PCI function.
79 struct nvme_queue **queues;
80 struct blk_mq_tag_set tagset;
81 struct blk_mq_tag_set admin_tagset;
84 struct dma_pool *prp_page_pool;
85 struct dma_pool *prp_small_pool;
86 unsigned online_queues;
91 unsigned long bar_mapped_size;
92 struct work_struct remove_work;
93 struct mutex shutdown_lock;
96 dma_addr_t cmb_dma_addr;
100 struct nvme_ctrl ctrl;
101 struct completion ioq_wait;
103 /* shadow doorbell buffer support: */
105 dma_addr_t dbbuf_dbs_dma_addr;
107 dma_addr_t dbbuf_eis_dma_addr;
109 /* host memory buffer support: */
111 u32 nr_host_mem_descs;
112 dma_addr_t host_mem_descs_dma;
113 struct nvme_host_mem_buf_desc *host_mem_descs;
114 void **host_mem_desc_bufs;
117 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
121 ret = kstrtoint(val, 10, &n);
122 if (ret != 0 || n < 2)
125 return param_set_int(val, kp);
128 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
130 return qid * 2 * stride;
133 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
135 return (qid * 2 + 1) * stride;
138 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
140 return container_of(ctrl, struct nvme_dev, ctrl);
144 * An NVM Express queue. Each device has at least two (one for admin
145 * commands and one for I/O commands).
148 struct device *q_dmadev;
149 struct nvme_dev *dev;
151 struct nvme_command *sq_cmds;
152 struct nvme_command __iomem *sq_cmds_io;
153 volatile struct nvme_completion *cqes;
154 struct blk_mq_tags **tags;
155 dma_addr_t sq_dma_addr;
156 dma_addr_t cq_dma_addr;
172 * The nvme_iod describes the data in an I/O, including the list of PRP
173 * entries. You can't see it in this data structure because C doesn't let
174 * me express that. Use nvme_init_iod to ensure there's enough space
175 * allocated to store the PRP list.
178 struct nvme_request req;
179 struct nvme_queue *nvmeq;
181 int npages; /* In the PRP list. 0 means small pool in use */
182 int nents; /* Used in scatterlist */
183 int length; /* Of data, in bytes */
184 dma_addr_t first_dma;
185 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
186 struct scatterlist *sg;
187 struct scatterlist inline_sg[0];
191 * Check we didin't inadvertently grow the command struct
193 static inline void _nvme_check_size(void)
195 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
196 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
197 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
198 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
199 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
200 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
201 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
202 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
203 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
204 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
205 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
206 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
207 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
210 static inline unsigned int nvme_dbbuf_size(u32 stride)
212 return ((num_possible_cpus() + 1) * 8 * stride);
215 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
217 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
222 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
223 &dev->dbbuf_dbs_dma_addr,
227 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
228 &dev->dbbuf_eis_dma_addr,
230 if (!dev->dbbuf_eis) {
231 dma_free_coherent(dev->dev, mem_size,
232 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
233 dev->dbbuf_dbs = NULL;
240 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
242 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
244 if (dev->dbbuf_dbs) {
245 dma_free_coherent(dev->dev, mem_size,
246 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
247 dev->dbbuf_dbs = NULL;
249 if (dev->dbbuf_eis) {
250 dma_free_coherent(dev->dev, mem_size,
251 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
252 dev->dbbuf_eis = NULL;
256 static void nvme_dbbuf_init(struct nvme_dev *dev,
257 struct nvme_queue *nvmeq, int qid)
259 if (!dev->dbbuf_dbs || !qid)
262 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
263 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
264 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
265 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
268 static void nvme_dbbuf_set(struct nvme_dev *dev)
270 struct nvme_command c;
275 memset(&c, 0, sizeof(c));
276 c.dbbuf.opcode = nvme_admin_dbbuf;
277 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
278 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
280 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
281 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
282 /* Free memory and continue on */
283 nvme_dbbuf_dma_free(dev);
287 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
289 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
292 /* Update dbbuf and return true if an MMIO is required */
293 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
294 volatile u32 *dbbuf_ei)
300 * Ensure that the queue is written before updating
301 * the doorbell in memory
305 old_value = *dbbuf_db;
308 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
316 * Max size of iod being embedded in the request payload
318 #define NVME_INT_PAGES 2
319 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
322 * Will slightly overestimate the number of pages needed. This is OK
323 * as it only leads to a small amount of wasted memory for the lifetime of
326 static int nvme_npages(unsigned size, struct nvme_dev *dev)
328 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
329 dev->ctrl.page_size);
330 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
333 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
334 unsigned int size, unsigned int nseg)
336 return sizeof(__le64 *) * nvme_npages(size, dev) +
337 sizeof(struct scatterlist) * nseg;
340 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
342 return sizeof(struct nvme_iod) +
343 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
346 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
347 unsigned int hctx_idx)
349 struct nvme_dev *dev = data;
350 struct nvme_queue *nvmeq = dev->queues[0];
352 WARN_ON(hctx_idx != 0);
353 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
354 WARN_ON(nvmeq->tags);
356 hctx->driver_data = nvmeq;
357 nvmeq->tags = &dev->admin_tagset.tags[0];
361 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
363 struct nvme_queue *nvmeq = hctx->driver_data;
368 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
369 unsigned int hctx_idx)
371 struct nvme_dev *dev = data;
372 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
375 nvmeq->tags = &dev->tagset.tags[hctx_idx];
377 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
378 hctx->driver_data = nvmeq;
382 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
383 unsigned int hctx_idx, unsigned int numa_node)
385 struct nvme_dev *dev = set->driver_data;
386 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
387 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
388 struct nvme_queue *nvmeq = dev->queues[queue_idx];
395 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
397 struct nvme_dev *dev = set->driver_data;
399 return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
403 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
404 * @nvmeq: The queue to use
405 * @cmd: The command to send
407 * Safe to use from interrupt context
409 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
410 struct nvme_command *cmd)
412 u16 tail = nvmeq->sq_tail;
414 if (nvmeq->sq_cmds_io)
415 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
417 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
419 if (++tail == nvmeq->q_depth)
421 if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db,
423 writel(tail, nvmeq->q_db);
424 nvmeq->sq_tail = tail;
427 static __le64 **iod_list(struct request *req)
429 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
430 return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req));
433 static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
435 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
436 int nseg = blk_rq_nr_phys_segments(rq);
437 unsigned int size = blk_rq_payload_bytes(rq);
439 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
440 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
442 return BLK_STS_RESOURCE;
444 iod->sg = iod->inline_sg;
455 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
457 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
458 const int last_prp = dev->ctrl.page_size / 8 - 1;
460 __le64 **list = iod_list(req);
461 dma_addr_t prp_dma = iod->first_dma;
463 if (iod->npages == 0)
464 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
465 for (i = 0; i < iod->npages; i++) {
466 __le64 *prp_list = list[i];
467 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
468 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
469 prp_dma = next_prp_dma;
472 if (iod->sg != iod->inline_sg)
476 #ifdef CONFIG_BLK_DEV_INTEGRITY
477 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
479 if (be32_to_cpu(pi->ref_tag) == v)
480 pi->ref_tag = cpu_to_be32(p);
483 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
485 if (be32_to_cpu(pi->ref_tag) == p)
486 pi->ref_tag = cpu_to_be32(v);
490 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
492 * The virtual start sector is the one that was originally submitted by the
493 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
494 * start sector may be different. Remap protection information to match the
495 * physical LBA on writes, and back to the original seed on reads.
497 * Type 0 and 3 do not have a ref tag, so no remapping required.
499 static void nvme_dif_remap(struct request *req,
500 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
502 struct nvme_ns *ns = req->rq_disk->private_data;
503 struct bio_integrity_payload *bip;
504 struct t10_pi_tuple *pi;
506 u32 i, nlb, ts, phys, virt;
508 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
511 bip = bio_integrity(req->bio);
515 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
518 virt = bip_get_seed(bip);
519 phys = nvme_block_nr(ns, blk_rq_pos(req));
520 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
521 ts = ns->disk->queue->integrity.tuple_size;
523 for (i = 0; i < nlb; i++, virt++, phys++) {
524 pi = (struct t10_pi_tuple *)p;
525 dif_swap(phys, virt, pi);
530 #else /* CONFIG_BLK_DEV_INTEGRITY */
531 static void nvme_dif_remap(struct request *req,
532 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
535 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
538 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
543 static blk_status_t nvme_setup_prps(struct nvme_dev *dev, struct request *req)
545 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
546 struct dma_pool *pool;
547 int length = blk_rq_payload_bytes(req);
548 struct scatterlist *sg = iod->sg;
549 int dma_len = sg_dma_len(sg);
550 u64 dma_addr = sg_dma_address(sg);
551 u32 page_size = dev->ctrl.page_size;
552 int offset = dma_addr & (page_size - 1);
554 __le64 **list = iod_list(req);
558 length -= (page_size - offset);
562 dma_len -= (page_size - offset);
564 dma_addr += (page_size - offset);
567 dma_addr = sg_dma_address(sg);
568 dma_len = sg_dma_len(sg);
571 if (length <= page_size) {
572 iod->first_dma = dma_addr;
576 nprps = DIV_ROUND_UP(length, page_size);
577 if (nprps <= (256 / 8)) {
578 pool = dev->prp_small_pool;
581 pool = dev->prp_page_pool;
585 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
587 iod->first_dma = dma_addr;
589 return BLK_STS_RESOURCE;
592 iod->first_dma = prp_dma;
595 if (i == page_size >> 3) {
596 __le64 *old_prp_list = prp_list;
597 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
599 return BLK_STS_RESOURCE;
600 list[iod->npages++] = prp_list;
601 prp_list[0] = old_prp_list[i - 1];
602 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
605 prp_list[i++] = cpu_to_le64(dma_addr);
606 dma_len -= page_size;
607 dma_addr += page_size;
613 if (unlikely(dma_len < 0))
616 dma_addr = sg_dma_address(sg);
617 dma_len = sg_dma_len(sg);
623 if (WARN_ONCE(1, "Invalid SGL for payload:%d nents:%d\n",
624 blk_rq_payload_bytes(req), iod->nents)) {
625 for_each_sg(iod->sg, sg, iod->nents, i) {
626 dma_addr_t phys = sg_phys(sg);
627 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
628 "dma_address:%pad dma_length:%d\n", i, &phys,
629 sg->offset, sg->length,
634 return BLK_STS_IOERR;
638 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
639 struct nvme_command *cmnd)
641 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
642 struct request_queue *q = req->q;
643 enum dma_data_direction dma_dir = rq_data_dir(req) ?
644 DMA_TO_DEVICE : DMA_FROM_DEVICE;
645 blk_status_t ret = BLK_STS_IOERR;
647 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
648 iod->nents = blk_rq_map_sg(q, req, iod->sg);
652 ret = BLK_STS_RESOURCE;
653 if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
657 ret = nvme_setup_prps(dev, req);
658 if (ret != BLK_STS_OK)
662 if (blk_integrity_rq(req)) {
663 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
666 sg_init_table(&iod->meta_sg, 1);
667 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
670 if (rq_data_dir(req))
671 nvme_dif_remap(req, nvme_dif_prep);
673 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
677 cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
678 cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma);
679 if (blk_integrity_rq(req))
680 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
684 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
689 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
691 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
692 enum dma_data_direction dma_dir = rq_data_dir(req) ?
693 DMA_TO_DEVICE : DMA_FROM_DEVICE;
696 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
697 if (blk_integrity_rq(req)) {
698 if (!rq_data_dir(req))
699 nvme_dif_remap(req, nvme_dif_complete);
700 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
704 nvme_cleanup_cmd(req);
705 nvme_free_iod(dev, req);
709 * NOTE: ns is NULL when called on the admin queue.
711 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
712 const struct blk_mq_queue_data *bd)
714 struct nvme_ns *ns = hctx->queue->queuedata;
715 struct nvme_queue *nvmeq = hctx->driver_data;
716 struct nvme_dev *dev = nvmeq->dev;
717 struct request *req = bd->rq;
718 struct nvme_command cmnd;
721 ret = nvme_setup_cmd(ns, req, &cmnd);
725 ret = nvme_init_iod(req, dev);
729 if (blk_rq_nr_phys_segments(req)) {
730 ret = nvme_map_data(dev, req, &cmnd);
732 goto out_cleanup_iod;
735 blk_mq_start_request(req);
737 spin_lock_irq(&nvmeq->q_lock);
738 if (unlikely(nvmeq->cq_vector < 0)) {
740 spin_unlock_irq(&nvmeq->q_lock);
741 goto out_cleanup_iod;
743 __nvme_submit_cmd(nvmeq, &cmnd);
744 nvme_process_cq(nvmeq);
745 spin_unlock_irq(&nvmeq->q_lock);
748 nvme_free_iod(dev, req);
750 nvme_cleanup_cmd(req);
754 static void nvme_pci_complete_rq(struct request *req)
756 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
758 nvme_unmap_data(iod->nvmeq->dev, req);
759 nvme_complete_rq(req);
762 /* We read the CQE phase first to check if the rest of the entry is valid */
763 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
766 return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
769 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
771 u16 head = nvmeq->cq_head;
773 if (likely(nvmeq->cq_vector >= 0)) {
774 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
776 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
780 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
781 struct nvme_completion *cqe)
785 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
786 dev_warn(nvmeq->dev->ctrl.device,
787 "invalid id %d completed on queue %d\n",
788 cqe->command_id, le16_to_cpu(cqe->sq_id));
793 * AEN requests are special as they don't time out and can
794 * survive any kind of queue freeze and often don't respond to
795 * aborts. We don't even bother to allocate a struct request
796 * for them but rather special case them here.
798 if (unlikely(nvmeq->qid == 0 &&
799 cqe->command_id >= NVME_AQ_BLKMQ_DEPTH)) {
800 nvme_complete_async_event(&nvmeq->dev->ctrl,
801 cqe->status, &cqe->result);
806 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
807 nvme_end_request(req, cqe->status, cqe->result);
810 static inline bool nvme_read_cqe(struct nvme_queue *nvmeq,
811 struct nvme_completion *cqe)
813 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
814 *cqe = nvmeq->cqes[nvmeq->cq_head];
816 if (++nvmeq->cq_head == nvmeq->q_depth) {
818 nvmeq->cq_phase = !nvmeq->cq_phase;
825 static void nvme_process_cq(struct nvme_queue *nvmeq)
827 struct nvme_completion cqe;
830 while (nvme_read_cqe(nvmeq, &cqe)) {
831 nvme_handle_cqe(nvmeq, &cqe);
836 nvme_ring_cq_doorbell(nvmeq);
839 static irqreturn_t nvme_irq(int irq, void *data)
842 struct nvme_queue *nvmeq = data;
843 spin_lock(&nvmeq->q_lock);
844 nvme_process_cq(nvmeq);
845 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
847 spin_unlock(&nvmeq->q_lock);
851 static irqreturn_t nvme_irq_check(int irq, void *data)
853 struct nvme_queue *nvmeq = data;
854 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
855 return IRQ_WAKE_THREAD;
859 static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
861 struct nvme_completion cqe;
862 int found = 0, consumed = 0;
864 if (!nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
867 spin_lock_irq(&nvmeq->q_lock);
868 while (nvme_read_cqe(nvmeq, &cqe)) {
869 nvme_handle_cqe(nvmeq, &cqe);
872 if (tag == cqe.command_id) {
879 nvme_ring_cq_doorbell(nvmeq);
880 spin_unlock_irq(&nvmeq->q_lock);
885 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
887 struct nvme_queue *nvmeq = hctx->driver_data;
889 return __nvme_poll(nvmeq, tag);
892 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx)
894 struct nvme_dev *dev = to_nvme_dev(ctrl);
895 struct nvme_queue *nvmeq = dev->queues[0];
896 struct nvme_command c;
898 memset(&c, 0, sizeof(c));
899 c.common.opcode = nvme_admin_async_event;
900 c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx;
902 spin_lock_irq(&nvmeq->q_lock);
903 __nvme_submit_cmd(nvmeq, &c);
904 spin_unlock_irq(&nvmeq->q_lock);
907 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
909 struct nvme_command c;
911 memset(&c, 0, sizeof(c));
912 c.delete_queue.opcode = opcode;
913 c.delete_queue.qid = cpu_to_le16(id);
915 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
918 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
919 struct nvme_queue *nvmeq)
921 struct nvme_command c;
922 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
925 * Note: we (ab)use the fact the the prp fields survive if no data
926 * is attached to the request.
928 memset(&c, 0, sizeof(c));
929 c.create_cq.opcode = nvme_admin_create_cq;
930 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
931 c.create_cq.cqid = cpu_to_le16(qid);
932 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
933 c.create_cq.cq_flags = cpu_to_le16(flags);
934 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
936 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
939 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
940 struct nvme_queue *nvmeq)
942 struct nvme_command c;
943 int flags = NVME_QUEUE_PHYS_CONTIG;
946 * Note: we (ab)use the fact the the prp fields survive if no data
947 * is attached to the request.
949 memset(&c, 0, sizeof(c));
950 c.create_sq.opcode = nvme_admin_create_sq;
951 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
952 c.create_sq.sqid = cpu_to_le16(qid);
953 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
954 c.create_sq.sq_flags = cpu_to_le16(flags);
955 c.create_sq.cqid = cpu_to_le16(qid);
957 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
960 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
962 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
965 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
967 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
970 static void abort_endio(struct request *req, blk_status_t error)
972 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
973 struct nvme_queue *nvmeq = iod->nvmeq;
975 dev_warn(nvmeq->dev->ctrl.device,
976 "Abort status: 0x%x", nvme_req(req)->status);
977 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
978 blk_mq_free_request(req);
981 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
984 /* If true, indicates loss of adapter communication, possibly by a
985 * NVMe Subsystem reset.
987 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
989 /* If there is a reset ongoing, we shouldn't reset again. */
990 if (dev->ctrl.state == NVME_CTRL_RESETTING)
993 /* We shouldn't reset unless the controller is on fatal error state
994 * _or_ if we lost the communication with it.
996 if (!(csts & NVME_CSTS_CFS) && !nssro)
999 /* If PCI error recovery process is happening, we cannot reset or
1000 * the recovery mechanism will surely fail.
1002 if (pci_channel_offline(to_pci_dev(dev->dev)))
1008 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1010 /* Read a config register to help see what died. */
1014 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1016 if (result == PCIBIOS_SUCCESSFUL)
1017 dev_warn(dev->ctrl.device,
1018 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1021 dev_warn(dev->ctrl.device,
1022 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1026 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1028 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1029 struct nvme_queue *nvmeq = iod->nvmeq;
1030 struct nvme_dev *dev = nvmeq->dev;
1031 struct request *abort_req;
1032 struct nvme_command cmd;
1033 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1036 * Reset immediately if the controller is failed
1038 if (nvme_should_reset(dev, csts)) {
1039 nvme_warn_reset(dev, csts);
1040 nvme_dev_disable(dev, false);
1041 nvme_reset_ctrl(&dev->ctrl);
1042 return BLK_EH_HANDLED;
1046 * Did we miss an interrupt?
1048 if (__nvme_poll(nvmeq, req->tag)) {
1049 dev_warn(dev->ctrl.device,
1050 "I/O %d QID %d timeout, completion polled\n",
1051 req->tag, nvmeq->qid);
1052 return BLK_EH_HANDLED;
1056 * Shutdown immediately if controller times out while starting. The
1057 * reset work will see the pci device disabled when it gets the forced
1058 * cancellation error. All outstanding requests are completed on
1059 * shutdown, so we return BLK_EH_HANDLED.
1061 if (dev->ctrl.state == NVME_CTRL_RESETTING) {
1062 dev_warn(dev->ctrl.device,
1063 "I/O %d QID %d timeout, disable controller\n",
1064 req->tag, nvmeq->qid);
1065 nvme_dev_disable(dev, false);
1066 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1067 return BLK_EH_HANDLED;
1071 * Shutdown the controller immediately and schedule a reset if the
1072 * command was already aborted once before and still hasn't been
1073 * returned to the driver, or if this is the admin queue.
1075 if (!nvmeq->qid || iod->aborted) {
1076 dev_warn(dev->ctrl.device,
1077 "I/O %d QID %d timeout, reset controller\n",
1078 req->tag, nvmeq->qid);
1079 nvme_dev_disable(dev, false);
1080 nvme_reset_ctrl(&dev->ctrl);
1083 * Mark the request as handled, since the inline shutdown
1084 * forces all outstanding requests to complete.
1086 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1087 return BLK_EH_HANDLED;
1090 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1091 atomic_inc(&dev->ctrl.abort_limit);
1092 return BLK_EH_RESET_TIMER;
1096 memset(&cmd, 0, sizeof(cmd));
1097 cmd.abort.opcode = nvme_admin_abort_cmd;
1098 cmd.abort.cid = req->tag;
1099 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1101 dev_warn(nvmeq->dev->ctrl.device,
1102 "I/O %d QID %d timeout, aborting\n",
1103 req->tag, nvmeq->qid);
1105 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1106 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1107 if (IS_ERR(abort_req)) {
1108 atomic_inc(&dev->ctrl.abort_limit);
1109 return BLK_EH_RESET_TIMER;
1112 abort_req->timeout = ADMIN_TIMEOUT;
1113 abort_req->end_io_data = NULL;
1114 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1117 * The aborted req will be completed on receiving the abort req.
1118 * We enable the timer again. If hit twice, it'll cause a device reset,
1119 * as the device then is in a faulty state.
1121 return BLK_EH_RESET_TIMER;
1124 static void nvme_free_queue(struct nvme_queue *nvmeq)
1126 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1127 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1129 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1130 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1134 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1138 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1139 struct nvme_queue *nvmeq = dev->queues[i];
1140 dev->ctrl.queue_count--;
1141 dev->queues[i] = NULL;
1142 nvme_free_queue(nvmeq);
1147 * nvme_suspend_queue - put queue into suspended state
1148 * @nvmeq - queue to suspend
1150 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1154 spin_lock_irq(&nvmeq->q_lock);
1155 if (nvmeq->cq_vector == -1) {
1156 spin_unlock_irq(&nvmeq->q_lock);
1159 vector = nvmeq->cq_vector;
1160 nvmeq->dev->online_queues--;
1161 nvmeq->cq_vector = -1;
1162 spin_unlock_irq(&nvmeq->q_lock);
1164 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1165 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1167 pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
1172 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1174 struct nvme_queue *nvmeq = dev->queues[0];
1178 if (nvme_suspend_queue(nvmeq))
1182 nvme_shutdown_ctrl(&dev->ctrl);
1184 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1186 spin_lock_irq(&nvmeq->q_lock);
1187 nvme_process_cq(nvmeq);
1188 spin_unlock_irq(&nvmeq->q_lock);
1191 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1194 int q_depth = dev->q_depth;
1195 unsigned q_size_aligned = roundup(q_depth * entry_size,
1196 dev->ctrl.page_size);
1198 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1199 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1200 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1201 q_depth = div_u64(mem_per_q, entry_size);
1204 * Ensure the reduced q_depth is above some threshold where it
1205 * would be better to map queues in system memory with the
1215 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1218 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1219 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1220 dev->ctrl.page_size);
1221 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1222 nvmeq->sq_cmds_io = dev->cmb + offset;
1224 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1225 &nvmeq->sq_dma_addr, GFP_KERNEL);
1226 if (!nvmeq->sq_cmds)
1233 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1234 int depth, int node)
1236 struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL,
1241 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1242 &nvmeq->cq_dma_addr, GFP_KERNEL);
1246 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1249 nvmeq->q_dmadev = dev->dev;
1251 spin_lock_init(&nvmeq->q_lock);
1253 nvmeq->cq_phase = 1;
1254 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1255 nvmeq->q_depth = depth;
1257 nvmeq->cq_vector = -1;
1258 dev->queues[qid] = nvmeq;
1259 dev->ctrl.queue_count++;
1264 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1265 nvmeq->cq_dma_addr);
1271 static int queue_request_irq(struct nvme_queue *nvmeq)
1273 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1274 int nr = nvmeq->dev->ctrl.instance;
1276 if (use_threaded_interrupts) {
1277 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1278 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1280 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1281 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1285 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1287 struct nvme_dev *dev = nvmeq->dev;
1289 spin_lock_irq(&nvmeq->q_lock);
1292 nvmeq->cq_phase = 1;
1293 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1294 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1295 nvme_dbbuf_init(dev, nvmeq, qid);
1296 dev->online_queues++;
1297 spin_unlock_irq(&nvmeq->q_lock);
1300 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1302 struct nvme_dev *dev = nvmeq->dev;
1305 nvmeq->cq_vector = qid - 1;
1306 result = adapter_alloc_cq(dev, qid, nvmeq);
1310 result = adapter_alloc_sq(dev, qid, nvmeq);
1314 result = queue_request_irq(nvmeq);
1318 nvme_init_queue(nvmeq, qid);
1322 adapter_delete_sq(dev, qid);
1324 adapter_delete_cq(dev, qid);
1328 static const struct blk_mq_ops nvme_mq_admin_ops = {
1329 .queue_rq = nvme_queue_rq,
1330 .complete = nvme_pci_complete_rq,
1331 .init_hctx = nvme_admin_init_hctx,
1332 .exit_hctx = nvme_admin_exit_hctx,
1333 .init_request = nvme_init_request,
1334 .timeout = nvme_timeout,
1337 static const struct blk_mq_ops nvme_mq_ops = {
1338 .queue_rq = nvme_queue_rq,
1339 .complete = nvme_pci_complete_rq,
1340 .init_hctx = nvme_init_hctx,
1341 .init_request = nvme_init_request,
1342 .map_queues = nvme_pci_map_queues,
1343 .timeout = nvme_timeout,
1347 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1349 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1351 * If the controller was reset during removal, it's possible
1352 * user requests may be waiting on a stopped queue. Start the
1353 * queue to flush these to completion.
1355 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1356 blk_cleanup_queue(dev->ctrl.admin_q);
1357 blk_mq_free_tag_set(&dev->admin_tagset);
1361 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1363 if (!dev->ctrl.admin_q) {
1364 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1365 dev->admin_tagset.nr_hw_queues = 1;
1368 * Subtract one to leave an empty queue entry for 'Full Queue'
1369 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1371 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1372 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1373 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1374 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1375 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1376 dev->admin_tagset.driver_data = dev;
1378 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1381 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1382 if (IS_ERR(dev->ctrl.admin_q)) {
1383 blk_mq_free_tag_set(&dev->admin_tagset);
1386 if (!blk_get_queue(dev->ctrl.admin_q)) {
1387 nvme_dev_remove_admin(dev);
1388 dev->ctrl.admin_q = NULL;
1392 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1397 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1399 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1402 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1404 struct pci_dev *pdev = to_pci_dev(dev->dev);
1406 if (size <= dev->bar_mapped_size)
1408 if (size > pci_resource_len(pdev, 0))
1412 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1414 dev->bar_mapped_size = 0;
1417 dev->bar_mapped_size = size;
1418 dev->dbs = dev->bar + NVME_REG_DBS;
1423 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1427 struct nvme_queue *nvmeq;
1429 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1433 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1434 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1436 if (dev->subsystem &&
1437 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1438 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1440 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1444 nvmeq = dev->queues[0];
1446 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH,
1447 dev_to_node(dev->dev));
1452 aqa = nvmeq->q_depth - 1;
1455 writel(aqa, dev->bar + NVME_REG_AQA);
1456 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1457 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1459 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
1463 nvmeq->cq_vector = 0;
1464 result = queue_request_irq(nvmeq);
1466 nvmeq->cq_vector = -1;
1473 static int nvme_create_io_queues(struct nvme_dev *dev)
1478 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1479 /* vector == qid - 1, match nvme_create_queue */
1480 if (!nvme_alloc_queue(dev, i, dev->q_depth,
1481 pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) {
1487 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1488 for (i = dev->online_queues; i <= max; i++) {
1489 ret = nvme_create_queue(dev->queues[i], i);
1495 * Ignore failing Create SQ/CQ commands, we can continue with less
1496 * than the desired aount of queues, and even a controller without
1497 * I/O queues an still be used to issue admin commands. This might
1498 * be useful to upgrade a buggy firmware for example.
1500 return ret >= 0 ? 0 : ret;
1503 static ssize_t nvme_cmb_show(struct device *dev,
1504 struct device_attribute *attr,
1507 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1509 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1510 ndev->cmbloc, ndev->cmbsz);
1512 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1514 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1516 u64 szu, size, offset;
1517 resource_size_t bar_size;
1518 struct pci_dev *pdev = to_pci_dev(dev->dev);
1520 dma_addr_t dma_addr;
1522 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1523 if (!(NVME_CMB_SZ(dev->cmbsz)))
1525 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1530 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1531 size = szu * NVME_CMB_SZ(dev->cmbsz);
1532 offset = szu * NVME_CMB_OFST(dev->cmbloc);
1533 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc));
1535 if (offset > bar_size)
1539 * Controllers may support a CMB size larger than their BAR,
1540 * for example, due to being behind a bridge. Reduce the CMB to
1541 * the reported size of the BAR
1543 if (size > bar_size - offset)
1544 size = bar_size - offset;
1546 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset;
1547 cmb = ioremap_wc(dma_addr, size);
1551 dev->cmb_dma_addr = dma_addr;
1552 dev->cmb_size = size;
1556 static inline void nvme_release_cmb(struct nvme_dev *dev)
1561 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1562 &dev_attr_cmb.attr, NULL);
1567 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1569 u64 dma_addr = dev->host_mem_descs_dma;
1570 struct nvme_command c;
1573 memset(&c, 0, sizeof(c));
1574 c.features.opcode = nvme_admin_set_features;
1575 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1576 c.features.dword11 = cpu_to_le32(bits);
1577 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1578 ilog2(dev->ctrl.page_size));
1579 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1580 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1581 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1583 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1585 dev_warn(dev->ctrl.device,
1586 "failed to set host mem (err %d, flags %#x).\n",
1592 static void nvme_free_host_mem(struct nvme_dev *dev)
1596 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1597 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1598 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1600 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1601 le64_to_cpu(desc->addr));
1604 kfree(dev->host_mem_desc_bufs);
1605 dev->host_mem_desc_bufs = NULL;
1606 dma_free_coherent(dev->dev,
1607 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1608 dev->host_mem_descs, dev->host_mem_descs_dma);
1609 dev->host_mem_descs = NULL;
1612 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1614 struct nvme_host_mem_buf_desc *descs;
1615 u32 chunk_size, max_entries, len;
1616 dma_addr_t descs_dma;
1621 /* start big and work our way down */
1622 chunk_size = min(preferred, (u64)PAGE_SIZE << MAX_ORDER);
1624 tmp = (preferred + chunk_size - 1);
1625 do_div(tmp, chunk_size);
1627 descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1628 &descs_dma, GFP_KERNEL);
1632 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1634 goto out_free_descs;
1636 for (size = 0; size < preferred; size += len) {
1637 dma_addr_t dma_addr;
1639 len = min_t(u64, chunk_size, preferred - size);
1640 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1641 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1645 descs[i].addr = cpu_to_le64(dma_addr);
1646 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1650 if (!size || (min && size < min)) {
1651 dev_warn(dev->ctrl.device,
1652 "failed to allocate host memory buffer.\n");
1656 dev_info(dev->ctrl.device,
1657 "allocated %lld MiB host memory buffer.\n",
1658 size >> ilog2(SZ_1M));
1659 dev->nr_host_mem_descs = i;
1660 dev->host_mem_size = size;
1661 dev->host_mem_descs = descs;
1662 dev->host_mem_descs_dma = descs_dma;
1663 dev->host_mem_desc_bufs = bufs;
1668 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1670 dma_free_coherent(dev->dev, size, bufs[i],
1671 le64_to_cpu(descs[i].addr));
1676 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1679 /* try a smaller chunk size if we failed early */
1680 if (chunk_size >= PAGE_SIZE * 2 && (i == 0 || size < min)) {
1684 dev->host_mem_descs = NULL;
1688 static void nvme_setup_host_mem(struct nvme_dev *dev)
1690 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1691 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1692 u64 min = (u64)dev->ctrl.hmmin * 4096;
1693 u32 enable_bits = NVME_HOST_MEM_ENABLE;
1695 preferred = min(preferred, max);
1697 dev_warn(dev->ctrl.device,
1698 "min host memory (%lld MiB) above limit (%d MiB).\n",
1699 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1700 nvme_free_host_mem(dev);
1705 * If we already have a buffer allocated check if we can reuse it.
1707 if (dev->host_mem_descs) {
1708 if (dev->host_mem_size >= min)
1709 enable_bits |= NVME_HOST_MEM_RETURN;
1711 nvme_free_host_mem(dev);
1714 if (!dev->host_mem_descs) {
1715 if (nvme_alloc_host_mem(dev, min, preferred))
1719 if (nvme_set_host_mem(dev, enable_bits))
1720 nvme_free_host_mem(dev);
1723 static int nvme_setup_io_queues(struct nvme_dev *dev)
1725 struct nvme_queue *adminq = dev->queues[0];
1726 struct pci_dev *pdev = to_pci_dev(dev->dev);
1727 int result, nr_io_queues;
1730 nr_io_queues = num_present_cpus();
1731 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1735 if (nr_io_queues == 0)
1738 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1739 result = nvme_cmb_qdepth(dev, nr_io_queues,
1740 sizeof(struct nvme_command));
1742 dev->q_depth = result;
1744 nvme_release_cmb(dev);
1748 size = db_bar_size(dev, nr_io_queues);
1749 result = nvme_remap_bar(dev, size);
1752 if (!--nr_io_queues)
1755 adminq->q_db = dev->dbs;
1757 /* Deregister the admin queue's interrupt */
1758 pci_free_irq(pdev, 0, adminq);
1761 * If we enable msix early due to not intx, disable it again before
1762 * setting up the full range we need.
1764 pci_free_irq_vectors(pdev);
1765 nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1766 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1767 if (nr_io_queues <= 0)
1769 dev->max_qid = nr_io_queues;
1772 * Should investigate if there's a performance win from allocating
1773 * more queues than interrupt vectors; it might allow the submission
1774 * path to scale better, even if the receive path is limited by the
1775 * number of interrupts.
1778 result = queue_request_irq(adminq);
1780 adminq->cq_vector = -1;
1783 return nvme_create_io_queues(dev);
1786 static void nvme_del_queue_end(struct request *req, blk_status_t error)
1788 struct nvme_queue *nvmeq = req->end_io_data;
1790 blk_mq_free_request(req);
1791 complete(&nvmeq->dev->ioq_wait);
1794 static void nvme_del_cq_end(struct request *req, blk_status_t error)
1796 struct nvme_queue *nvmeq = req->end_io_data;
1799 unsigned long flags;
1802 * We might be called with the AQ q_lock held
1803 * and the I/O queue q_lock should always
1804 * nest inside the AQ one.
1806 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1807 SINGLE_DEPTH_NESTING);
1808 nvme_process_cq(nvmeq);
1809 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1812 nvme_del_queue_end(req, error);
1815 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1817 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1818 struct request *req;
1819 struct nvme_command cmd;
1821 memset(&cmd, 0, sizeof(cmd));
1822 cmd.delete_queue.opcode = opcode;
1823 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1825 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1827 return PTR_ERR(req);
1829 req->timeout = ADMIN_TIMEOUT;
1830 req->end_io_data = nvmeq;
1832 blk_execute_rq_nowait(q, NULL, req, false,
1833 opcode == nvme_admin_delete_cq ?
1834 nvme_del_cq_end : nvme_del_queue_end);
1838 static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
1841 unsigned long timeout;
1842 u8 opcode = nvme_admin_delete_sq;
1844 for (pass = 0; pass < 2; pass++) {
1845 int sent = 0, i = queues;
1847 reinit_completion(&dev->ioq_wait);
1849 timeout = ADMIN_TIMEOUT;
1850 for (; i > 0; i--, sent++)
1851 if (nvme_delete_queue(dev->queues[i], opcode))
1855 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1861 opcode = nvme_admin_delete_cq;
1866 * Return: error value if an error occurred setting up the queues or calling
1867 * Identify Device. 0 if these succeeded, even if adding some of the
1868 * namespaces failed. At the moment, these failures are silent. TBD which
1869 * failures should be reported.
1871 static int nvme_dev_add(struct nvme_dev *dev)
1873 if (!dev->ctrl.tagset) {
1874 dev->tagset.ops = &nvme_mq_ops;
1875 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1876 dev->tagset.timeout = NVME_IO_TIMEOUT;
1877 dev->tagset.numa_node = dev_to_node(dev->dev);
1878 dev->tagset.queue_depth =
1879 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1880 dev->tagset.cmd_size = nvme_cmd_size(dev);
1881 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1882 dev->tagset.driver_data = dev;
1884 if (blk_mq_alloc_tag_set(&dev->tagset))
1886 dev->ctrl.tagset = &dev->tagset;
1888 nvme_dbbuf_set(dev);
1890 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1892 /* Free previously allocated queues that are no longer usable */
1893 nvme_free_queues(dev, dev->online_queues);
1899 static int nvme_pci_enable(struct nvme_dev *dev)
1901 int result = -ENOMEM;
1902 struct pci_dev *pdev = to_pci_dev(dev->dev);
1904 if (pci_enable_device_mem(pdev))
1907 pci_set_master(pdev);
1909 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1910 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1913 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1919 * Some devices and/or platforms don't advertise or work with INTx
1920 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1921 * adjust this later.
1923 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1927 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1929 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
1931 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
1932 dev->dbs = dev->bar + 4096;
1935 * Temporary fix for the Apple controller found in the MacBook8,1 and
1936 * some MacBook7,1 to avoid controller resets and data loss.
1938 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1940 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
1941 "set queue depth=%u to work around controller resets\n",
1943 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
1944 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
1945 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
1947 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
1948 "set queue depth=%u\n", dev->q_depth);
1952 * CMBs can currently only exist on >=1.2 PCIe devices. We only
1953 * populate sysfs if a CMB is implemented. Since nvme_dev_attrs_group
1954 * has no name we can pass NULL as final argument to
1955 * sysfs_add_file_to_group.
1958 if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
1959 dev->cmb = nvme_map_cmb(dev);
1961 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1962 &dev_attr_cmb.attr, NULL))
1963 dev_warn(dev->ctrl.device,
1964 "failed to add sysfs attribute for CMB\n");
1968 pci_enable_pcie_error_reporting(pdev);
1969 pci_save_state(pdev);
1973 pci_disable_device(pdev);
1977 static void nvme_dev_unmap(struct nvme_dev *dev)
1981 pci_release_mem_regions(to_pci_dev(dev->dev));
1984 static void nvme_pci_disable(struct nvme_dev *dev)
1986 struct pci_dev *pdev = to_pci_dev(dev->dev);
1988 nvme_release_cmb(dev);
1989 pci_free_irq_vectors(pdev);
1991 if (pci_is_enabled(pdev)) {
1992 pci_disable_pcie_error_reporting(pdev);
1993 pci_disable_device(pdev);
1997 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2001 struct pci_dev *pdev = to_pci_dev(dev->dev);
2003 mutex_lock(&dev->shutdown_lock);
2004 if (pci_is_enabled(pdev)) {
2005 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2007 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2008 dev->ctrl.state == NVME_CTRL_RESETTING)
2009 nvme_start_freeze(&dev->ctrl);
2010 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2011 pdev->error_state != pci_channel_io_normal);
2015 * Give the controller a chance to complete all entered requests if
2016 * doing a safe shutdown.
2020 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2023 * If the controller is still alive tell it to stop using the
2024 * host memory buffer. In theory the shutdown / reset should
2025 * make sure that it doesn't access the host memoery anymore,
2026 * but I'd rather be safe than sorry..
2028 if (dev->host_mem_descs)
2029 nvme_set_host_mem(dev, 0);
2032 nvme_stop_queues(&dev->ctrl);
2034 queues = dev->online_queues - 1;
2035 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
2036 nvme_suspend_queue(dev->queues[i]);
2039 /* A device might become IO incapable very soon during
2040 * probe, before the admin queue is configured. Thus,
2041 * queue_count can be 0 here.
2043 if (dev->ctrl.queue_count)
2044 nvme_suspend_queue(dev->queues[0]);
2046 nvme_disable_io_queues(dev, queues);
2047 nvme_disable_admin_queue(dev, shutdown);
2049 nvme_pci_disable(dev);
2051 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2052 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2055 * The driver will not be starting up queues again if shutting down so
2056 * must flush all entered requests to their failed completion to avoid
2057 * deadlocking blk-mq hot-cpu notifier.
2060 nvme_start_queues(&dev->ctrl);
2061 mutex_unlock(&dev->shutdown_lock);
2064 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2066 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2067 PAGE_SIZE, PAGE_SIZE, 0);
2068 if (!dev->prp_page_pool)
2071 /* Optimisation for I/Os between 4k and 128k */
2072 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2074 if (!dev->prp_small_pool) {
2075 dma_pool_destroy(dev->prp_page_pool);
2081 static void nvme_release_prp_pools(struct nvme_dev *dev)
2083 dma_pool_destroy(dev->prp_page_pool);
2084 dma_pool_destroy(dev->prp_small_pool);
2087 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2089 struct nvme_dev *dev = to_nvme_dev(ctrl);
2091 nvme_dbbuf_dma_free(dev);
2092 put_device(dev->dev);
2093 if (dev->tagset.tags)
2094 blk_mq_free_tag_set(&dev->tagset);
2095 if (dev->ctrl.admin_q)
2096 blk_put_queue(dev->ctrl.admin_q);
2098 free_opal_dev(dev->ctrl.opal_dev);
2102 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2104 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
2106 kref_get(&dev->ctrl.kref);
2107 nvme_dev_disable(dev, false);
2108 if (!schedule_work(&dev->remove_work))
2109 nvme_put_ctrl(&dev->ctrl);
2112 static void nvme_reset_work(struct work_struct *work)
2114 struct nvme_dev *dev =
2115 container_of(work, struct nvme_dev, ctrl.reset_work);
2116 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2117 int result = -ENODEV;
2119 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
2123 * If we're called to reset a live controller first shut it down before
2126 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2127 nvme_dev_disable(dev, false);
2129 result = nvme_pci_enable(dev);
2133 result = nvme_pci_configure_admin_queue(dev);
2137 nvme_init_queue(dev->queues[0], 0);
2138 result = nvme_alloc_admin_tags(dev);
2142 result = nvme_init_identify(&dev->ctrl);
2146 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2147 if (!dev->ctrl.opal_dev)
2148 dev->ctrl.opal_dev =
2149 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2150 else if (was_suspend)
2151 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2153 free_opal_dev(dev->ctrl.opal_dev);
2154 dev->ctrl.opal_dev = NULL;
2157 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2158 result = nvme_dbbuf_dma_alloc(dev);
2161 "unable to allocate dma for dbbuf\n");
2164 if (dev->ctrl.hmpre)
2165 nvme_setup_host_mem(dev);
2167 result = nvme_setup_io_queues(dev);
2172 * Keep the controller around but remove all namespaces if we don't have
2173 * any working I/O queue.
2175 if (dev->online_queues < 2) {
2176 dev_warn(dev->ctrl.device, "IO queues not created\n");
2177 nvme_kill_queues(&dev->ctrl);
2178 nvme_remove_namespaces(&dev->ctrl);
2180 nvme_start_queues(&dev->ctrl);
2181 nvme_wait_freeze(&dev->ctrl);
2183 nvme_unfreeze(&dev->ctrl);
2186 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2187 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
2191 nvme_start_ctrl(&dev->ctrl);
2195 nvme_remove_dead_ctrl(dev, result);
2198 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2200 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2201 struct pci_dev *pdev = to_pci_dev(dev->dev);
2203 nvme_kill_queues(&dev->ctrl);
2204 if (pci_get_drvdata(pdev))
2205 device_release_driver(&pdev->dev);
2206 nvme_put_ctrl(&dev->ctrl);
2209 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2211 *val = readl(to_nvme_dev(ctrl)->bar + off);
2215 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2217 writel(val, to_nvme_dev(ctrl)->bar + off);
2221 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2223 *val = readq(to_nvme_dev(ctrl)->bar + off);
2227 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2229 .module = THIS_MODULE,
2230 .flags = NVME_F_METADATA_SUPPORTED,
2231 .reg_read32 = nvme_pci_reg_read32,
2232 .reg_write32 = nvme_pci_reg_write32,
2233 .reg_read64 = nvme_pci_reg_read64,
2234 .free_ctrl = nvme_pci_free_ctrl,
2235 .submit_async_event = nvme_pci_submit_async_event,
2238 static int nvme_dev_map(struct nvme_dev *dev)
2240 struct pci_dev *pdev = to_pci_dev(dev->dev);
2242 if (pci_request_mem_regions(pdev, "nvme"))
2245 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2250 pci_release_mem_regions(pdev);
2254 static unsigned long check_dell_samsung_bug(struct pci_dev *pdev)
2256 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2258 * Several Samsung devices seem to drop off the PCIe bus
2259 * randomly when APST is on and uses the deepest sleep state.
2260 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2261 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2262 * 950 PRO 256GB", but it seems to be restricted to two Dell
2265 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2266 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2267 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2268 return NVME_QUIRK_NO_DEEPEST_PS;
2274 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2276 int node, result = -ENOMEM;
2277 struct nvme_dev *dev;
2278 unsigned long quirks = id->driver_data;
2280 node = dev_to_node(&pdev->dev);
2281 if (node == NUMA_NO_NODE)
2282 set_dev_node(&pdev->dev, first_memory_node);
2284 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2287 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2292 dev->dev = get_device(&pdev->dev);
2293 pci_set_drvdata(pdev, dev);
2295 result = nvme_dev_map(dev);
2299 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2300 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2301 mutex_init(&dev->shutdown_lock);
2302 init_completion(&dev->ioq_wait);
2304 result = nvme_setup_prp_pools(dev);
2308 quirks |= check_dell_samsung_bug(pdev);
2310 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2315 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING);
2316 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2318 queue_work(nvme_wq, &dev->ctrl.reset_work);
2322 nvme_release_prp_pools(dev);
2324 nvme_dev_unmap(dev);
2326 put_device(dev->dev);
2333 static void nvme_reset_prepare(struct pci_dev *pdev)
2335 struct nvme_dev *dev = pci_get_drvdata(pdev);
2336 nvme_dev_disable(dev, false);
2339 static void nvme_reset_done(struct pci_dev *pdev)
2341 struct nvme_dev *dev = pci_get_drvdata(pdev);
2342 nvme_reset_ctrl(&dev->ctrl);
2345 static void nvme_shutdown(struct pci_dev *pdev)
2347 struct nvme_dev *dev = pci_get_drvdata(pdev);
2348 nvme_dev_disable(dev, true);
2352 * The driver's remove may be called on a device in a partially initialized
2353 * state. This function must not have any dependencies on the device state in
2356 static void nvme_remove(struct pci_dev *pdev)
2358 struct nvme_dev *dev = pci_get_drvdata(pdev);
2360 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2362 cancel_work_sync(&dev->ctrl.reset_work);
2363 pci_set_drvdata(pdev, NULL);
2365 if (!pci_device_is_present(pdev)) {
2366 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2367 nvme_dev_disable(dev, false);
2370 flush_work(&dev->ctrl.reset_work);
2371 nvme_stop_ctrl(&dev->ctrl);
2372 nvme_remove_namespaces(&dev->ctrl);
2373 nvme_dev_disable(dev, true);
2374 nvme_free_host_mem(dev);
2375 nvme_dev_remove_admin(dev);
2376 nvme_free_queues(dev, 0);
2377 nvme_uninit_ctrl(&dev->ctrl);
2378 nvme_release_prp_pools(dev);
2379 nvme_dev_unmap(dev);
2380 nvme_put_ctrl(&dev->ctrl);
2383 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2388 if (pci_vfs_assigned(pdev)) {
2389 dev_warn(&pdev->dev,
2390 "Cannot disable SR-IOV VFs while assigned\n");
2393 pci_disable_sriov(pdev);
2397 ret = pci_enable_sriov(pdev, numvfs);
2398 return ret ? ret : numvfs;
2401 #ifdef CONFIG_PM_SLEEP
2402 static int nvme_suspend(struct device *dev)
2404 struct pci_dev *pdev = to_pci_dev(dev);
2405 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2407 nvme_dev_disable(ndev, true);
2411 static int nvme_resume(struct device *dev)
2413 struct pci_dev *pdev = to_pci_dev(dev);
2414 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2416 nvme_reset_ctrl(&ndev->ctrl);
2421 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2423 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2424 pci_channel_state_t state)
2426 struct nvme_dev *dev = pci_get_drvdata(pdev);
2429 * A frozen channel requires a reset. When detected, this method will
2430 * shutdown the controller to quiesce. The controller will be restarted
2431 * after the slot reset through driver's slot_reset callback.
2434 case pci_channel_io_normal:
2435 return PCI_ERS_RESULT_CAN_RECOVER;
2436 case pci_channel_io_frozen:
2437 dev_warn(dev->ctrl.device,
2438 "frozen state error detected, reset controller\n");
2439 nvme_dev_disable(dev, false);
2440 return PCI_ERS_RESULT_NEED_RESET;
2441 case pci_channel_io_perm_failure:
2442 dev_warn(dev->ctrl.device,
2443 "failure state error detected, request disconnect\n");
2444 return PCI_ERS_RESULT_DISCONNECT;
2446 return PCI_ERS_RESULT_NEED_RESET;
2449 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2451 struct nvme_dev *dev = pci_get_drvdata(pdev);
2453 dev_info(dev->ctrl.device, "restart after slot reset\n");
2454 pci_restore_state(pdev);
2455 nvme_reset_ctrl(&dev->ctrl);
2456 return PCI_ERS_RESULT_RECOVERED;
2459 static void nvme_error_resume(struct pci_dev *pdev)
2461 pci_cleanup_aer_uncorrect_error_status(pdev);
2464 static const struct pci_error_handlers nvme_err_handler = {
2465 .error_detected = nvme_error_detected,
2466 .slot_reset = nvme_slot_reset,
2467 .resume = nvme_error_resume,
2468 .reset_prepare = nvme_reset_prepare,
2469 .reset_done = nvme_reset_done,
2472 static const struct pci_device_id nvme_id_table[] = {
2473 { PCI_VDEVICE(INTEL, 0x0953),
2474 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2475 NVME_QUIRK_DEALLOCATE_ZEROES, },
2476 { PCI_VDEVICE(INTEL, 0x0a53),
2477 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2478 NVME_QUIRK_DEALLOCATE_ZEROES, },
2479 { PCI_VDEVICE(INTEL, 0x0a54),
2480 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2481 NVME_QUIRK_DEALLOCATE_ZEROES, },
2482 { PCI_VDEVICE(INTEL, 0x0a55),
2483 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2484 NVME_QUIRK_DEALLOCATE_ZEROES, },
2485 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
2486 .driver_data = NVME_QUIRK_NO_DEEPEST_PS },
2487 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2488 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2489 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2490 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2491 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2492 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2493 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2494 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2495 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2496 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2497 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2498 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2499 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2502 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2504 static struct pci_driver nvme_driver = {
2506 .id_table = nvme_id_table,
2507 .probe = nvme_probe,
2508 .remove = nvme_remove,
2509 .shutdown = nvme_shutdown,
2511 .pm = &nvme_dev_pm_ops,
2513 .sriov_configure = nvme_pci_sriov_configure,
2514 .err_handler = &nvme_err_handler,
2517 static int __init nvme_init(void)
2519 return pci_register_driver(&nvme_driver);
2522 static void __exit nvme_exit(void)
2524 pci_unregister_driver(&nvme_driver);
2528 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2529 MODULE_LICENSE("GPL");
2530 MODULE_VERSION("1.0");
2531 module_init(nvme_init);
2532 module_exit(nvme_exit);