2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/bitops.h>
16 #include <linux/blkdev.h>
17 #include <linux/blk-mq.h>
18 #include <linux/cpu.h>
19 #include <linux/delay.h>
20 #include <linux/errno.h>
22 #include <linux/genhd.h>
23 #include <linux/hdreg.h>
24 #include <linux/idr.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
28 #include <linux/kdev_t.h>
29 #include <linux/kthread.h>
30 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/mutex.h>
35 #include <linux/pci.h>
36 #include <linux/poison.h>
37 #include <linux/ptrace.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/t10-pi.h>
41 #include <linux/types.h>
42 #include <linux/io-64-nonatomic-lo-hi.h>
43 #include <asm/unaligned.h>
47 #define NVME_Q_DEPTH 1024
48 #define NVME_AQ_DEPTH 256
49 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
50 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
52 unsigned char admin_timeout = 60;
53 module_param(admin_timeout, byte, 0644);
54 MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
56 unsigned char nvme_io_timeout = 30;
57 module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
58 MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
60 unsigned char shutdown_timeout = 5;
61 module_param(shutdown_timeout, byte, 0644);
62 MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
64 static int use_threaded_interrupts;
65 module_param(use_threaded_interrupts, int, 0);
67 static bool use_cmb_sqes = true;
68 module_param(use_cmb_sqes, bool, 0644);
69 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
71 static LIST_HEAD(dev_list);
72 static struct task_struct *nvme_thread;
73 static struct workqueue_struct *nvme_workq;
74 static wait_queue_head_t nvme_kthread_wait;
80 static int nvme_reset(struct nvme_dev *dev);
81 static void nvme_process_cq(struct nvme_queue *nvmeq);
82 static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod);
83 static void nvme_remove_dead_ctrl(struct nvme_dev *dev);
84 static void nvme_dev_shutdown(struct nvme_dev *dev);
86 struct async_cmd_info {
87 struct kthread_work work;
88 struct kthread_worker *worker;
96 * Represents an NVM Express device. Each nvme_dev is a PCI function.
99 struct list_head node;
100 struct nvme_queue **queues;
101 struct blk_mq_tag_set tagset;
102 struct blk_mq_tag_set admin_tagset;
105 struct dma_pool *prp_page_pool;
106 struct dma_pool *prp_small_pool;
107 unsigned queue_count;
108 unsigned online_queues;
112 struct msix_entry *entry;
114 struct work_struct reset_work;
115 struct work_struct scan_work;
116 struct work_struct remove_work;
117 struct mutex shutdown_lock;
120 dma_addr_t cmb_dma_addr;
124 #define NVME_CTRL_RESETTING 0
126 struct nvme_ctrl ctrl;
129 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
131 return container_of(ctrl, struct nvme_dev, ctrl);
135 * An NVM Express queue. Each device has at least two (one for admin
136 * commands and one for I/O commands).
139 struct device *q_dmadev;
140 struct nvme_dev *dev;
141 char irqname[24]; /* nvme4294967295-65535\0 */
143 struct nvme_command *sq_cmds;
144 struct nvme_command __iomem *sq_cmds_io;
145 volatile struct nvme_completion *cqes;
146 struct blk_mq_tags **tags;
147 dma_addr_t sq_dma_addr;
148 dma_addr_t cq_dma_addr;
158 struct async_cmd_info cmdinfo;
162 * The nvme_iod describes the data in an I/O, including the list of PRP
163 * entries. You can't see it in this data structure because C doesn't let
164 * me express that. Use nvme_alloc_iod to ensure there's enough space
165 * allocated to store the PRP list.
168 unsigned long private; /* For the use of the submitter of the I/O */
169 int npages; /* In the PRP list. 0 means small pool in use */
170 int offset; /* Of PRP list */
171 int nents; /* Used in scatterlist */
172 int length; /* Of data, in bytes */
173 dma_addr_t first_dma;
174 struct scatterlist meta_sg[1]; /* metadata requires single contiguous buffer */
175 struct scatterlist sg[0];
179 * Check we didin't inadvertently grow the command struct
181 static inline void _nvme_check_size(void)
183 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
184 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
185 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
186 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
187 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
188 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
189 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
190 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
191 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
192 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
193 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
194 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
197 typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
198 struct nvme_completion *);
200 struct nvme_cmd_info {
201 nvme_completion_fn fn;
204 struct nvme_queue *nvmeq;
205 struct nvme_iod iod[0];
209 * Max size of iod being embedded in the request payload
211 #define NVME_INT_PAGES 2
212 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
213 #define NVME_INT_MASK 0x01
216 * Will slightly overestimate the number of pages needed. This is OK
217 * as it only leads to a small amount of wasted memory for the lifetime of
220 static int nvme_npages(unsigned size, struct nvme_dev *dev)
222 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
223 dev->ctrl.page_size);
224 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
227 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
229 unsigned int ret = sizeof(struct nvme_cmd_info);
231 ret += sizeof(struct nvme_iod);
232 ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
233 ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
238 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
239 unsigned int hctx_idx)
241 struct nvme_dev *dev = data;
242 struct nvme_queue *nvmeq = dev->queues[0];
244 WARN_ON(hctx_idx != 0);
245 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
246 WARN_ON(nvmeq->tags);
248 hctx->driver_data = nvmeq;
249 nvmeq->tags = &dev->admin_tagset.tags[0];
253 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
255 struct nvme_queue *nvmeq = hctx->driver_data;
260 static int nvme_admin_init_request(void *data, struct request *req,
261 unsigned int hctx_idx, unsigned int rq_idx,
262 unsigned int numa_node)
264 struct nvme_dev *dev = data;
265 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
266 struct nvme_queue *nvmeq = dev->queues[0];
273 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
274 unsigned int hctx_idx)
276 struct nvme_dev *dev = data;
277 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
280 nvmeq->tags = &dev->tagset.tags[hctx_idx];
282 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
283 hctx->driver_data = nvmeq;
287 static int nvme_init_request(void *data, struct request *req,
288 unsigned int hctx_idx, unsigned int rq_idx,
289 unsigned int numa_node)
291 struct nvme_dev *dev = data;
292 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
293 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
300 static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
301 nvme_completion_fn handler)
306 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
309 static void *iod_get_private(struct nvme_iod *iod)
311 return (void *) (iod->private & ~0x1UL);
315 * If bit 0 is set, the iod is embedded in the request payload.
317 static bool iod_should_kfree(struct nvme_iod *iod)
319 return (iod->private & NVME_INT_MASK) == 0;
322 /* Special values must be less than 0x1000 */
323 #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
324 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
325 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
326 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
328 static void special_completion(struct nvme_queue *nvmeq, void *ctx,
329 struct nvme_completion *cqe)
331 if (ctx == CMD_CTX_CANCELLED)
333 if (ctx == CMD_CTX_COMPLETED) {
334 dev_warn(nvmeq->q_dmadev,
335 "completed id %d twice on queue %d\n",
336 cqe->command_id, le16_to_cpup(&cqe->sq_id));
339 if (ctx == CMD_CTX_INVALID) {
340 dev_warn(nvmeq->q_dmadev,
341 "invalid id %d completed on queue %d\n",
342 cqe->command_id, le16_to_cpup(&cqe->sq_id));
345 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
348 static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
355 cmd->fn = special_completion;
356 cmd->ctx = CMD_CTX_CANCELLED;
360 static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
361 struct nvme_completion *cqe)
363 u32 result = le32_to_cpup(&cqe->result);
364 u16 status = le16_to_cpup(&cqe->status) >> 1;
366 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
367 ++nvmeq->dev->ctrl.event_limit;
368 if (status != NVME_SC_SUCCESS)
371 switch (result & 0xff07) {
372 case NVME_AER_NOTICE_NS_CHANGED:
373 dev_info(nvmeq->q_dmadev, "rescanning\n");
374 queue_work(nvme_workq, &nvmeq->dev->scan_work);
376 dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result);
380 static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
381 struct nvme_completion *cqe)
383 struct request *req = ctx;
385 u16 status = le16_to_cpup(&cqe->status) >> 1;
386 u32 result = le32_to_cpup(&cqe->result);
388 blk_mq_free_request(req);
390 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
391 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
394 static void async_completion(struct nvme_queue *nvmeq, void *ctx,
395 struct nvme_completion *cqe)
397 struct async_cmd_info *cmdinfo = ctx;
398 cmdinfo->result = le32_to_cpup(&cqe->result);
399 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
400 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
401 blk_mq_free_request(cmdinfo->req);
404 static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
407 struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag);
409 return blk_mq_rq_to_pdu(req);
413 * Called with local interrupts disabled and the q_lock held. May not sleep.
415 static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
416 nvme_completion_fn *fn)
418 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
420 if (tag >= nvmeq->q_depth) {
421 *fn = special_completion;
422 return CMD_CTX_INVALID;
427 cmd->fn = special_completion;
428 cmd->ctx = CMD_CTX_COMPLETED;
433 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
434 * @nvmeq: The queue to use
435 * @cmd: The command to send
437 * Safe to use from interrupt context
439 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
440 struct nvme_command *cmd)
442 u16 tail = nvmeq->sq_tail;
444 if (nvmeq->sq_cmds_io)
445 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
447 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
449 if (++tail == nvmeq->q_depth)
451 writel(tail, nvmeq->q_db);
452 nvmeq->sq_tail = tail;
455 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
458 spin_lock_irqsave(&nvmeq->q_lock, flags);
459 __nvme_submit_cmd(nvmeq, cmd);
460 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
463 static __le64 **iod_list(struct nvme_iod *iod)
465 return ((void *)iod) + iod->offset;
468 static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
469 unsigned nseg, unsigned long private)
471 iod->private = private;
472 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
474 iod->length = nbytes;
478 static struct nvme_iod *
479 __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
480 unsigned long priv, gfp_t gfp)
482 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
483 sizeof(__le64 *) * nvme_npages(bytes, dev) +
484 sizeof(struct scatterlist) * nseg, gfp);
487 iod_init(iod, bytes, nseg, priv);
492 static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
495 unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
496 sizeof(struct nvme_dsm_range);
497 struct nvme_iod *iod;
499 if (rq->nr_phys_segments <= NVME_INT_PAGES &&
500 size <= NVME_INT_BYTES(dev)) {
501 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
504 iod_init(iod, size, rq->nr_phys_segments,
505 (unsigned long) rq | NVME_INT_MASK);
509 return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
510 (unsigned long) rq, gfp);
513 static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
515 const int last_prp = dev->ctrl.page_size / 8 - 1;
517 __le64 **list = iod_list(iod);
518 dma_addr_t prp_dma = iod->first_dma;
520 if (iod->npages == 0)
521 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
522 for (i = 0; i < iod->npages; i++) {
523 __le64 *prp_list = list[i];
524 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
525 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
526 prp_dma = next_prp_dma;
529 if (iod_should_kfree(iod))
533 #ifdef CONFIG_BLK_DEV_INTEGRITY
534 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
536 if (be32_to_cpu(pi->ref_tag) == v)
537 pi->ref_tag = cpu_to_be32(p);
540 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
542 if (be32_to_cpu(pi->ref_tag) == p)
543 pi->ref_tag = cpu_to_be32(v);
547 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
549 * The virtual start sector is the one that was originally submitted by the
550 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
551 * start sector may be different. Remap protection information to match the
552 * physical LBA on writes, and back to the original seed on reads.
554 * Type 0 and 3 do not have a ref tag, so no remapping required.
556 static void nvme_dif_remap(struct request *req,
557 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
559 struct nvme_ns *ns = req->rq_disk->private_data;
560 struct bio_integrity_payload *bip;
561 struct t10_pi_tuple *pi;
563 u32 i, nlb, ts, phys, virt;
565 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
568 bip = bio_integrity(req->bio);
572 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
575 virt = bip_get_seed(bip);
576 phys = nvme_block_nr(ns, blk_rq_pos(req));
577 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
578 ts = ns->disk->queue->integrity.tuple_size;
580 for (i = 0; i < nlb; i++, virt++, phys++) {
581 pi = (struct t10_pi_tuple *)p;
582 dif_swap(phys, virt, pi);
587 #else /* CONFIG_BLK_DEV_INTEGRITY */
588 static void nvme_dif_remap(struct request *req,
589 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
592 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
595 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
600 static void req_completion(struct nvme_queue *nvmeq, void *ctx,
601 struct nvme_completion *cqe)
603 struct nvme_iod *iod = ctx;
604 struct request *req = iod_get_private(iod);
605 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
606 u16 status = le16_to_cpup(&cqe->status) >> 1;
609 if (unlikely(status)) {
610 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
611 && (jiffies - req->start_time) < req->timeout) {
614 nvme_unmap_data(nvmeq->dev, iod);
616 blk_mq_requeue_request(req);
617 spin_lock_irqsave(req->q->queue_lock, flags);
618 if (!blk_queue_stopped(req->q))
619 blk_mq_kick_requeue_list(req->q);
620 spin_unlock_irqrestore(req->q->queue_lock, flags);
624 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
625 if (cmd_rq->ctx == CMD_CTX_CANCELLED)
626 error = NVME_SC_CANCELLED;
630 error = nvme_error_status(status);
634 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
635 u32 result = le32_to_cpup(&cqe->result);
636 req->special = (void *)(uintptr_t)result;
640 dev_warn(nvmeq->dev->dev,
641 "completing aborted command with status:%04x\n",
644 nvme_unmap_data(nvmeq->dev, iod);
645 blk_mq_complete_request(req, error);
648 static bool nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod,
651 struct dma_pool *pool;
652 int length = total_len;
653 struct scatterlist *sg = iod->sg;
654 int dma_len = sg_dma_len(sg);
655 u64 dma_addr = sg_dma_address(sg);
656 u32 page_size = dev->ctrl.page_size;
657 int offset = dma_addr & (page_size - 1);
659 __le64 **list = iod_list(iod);
663 length -= (page_size - offset);
667 dma_len -= (page_size - offset);
669 dma_addr += (page_size - offset);
672 dma_addr = sg_dma_address(sg);
673 dma_len = sg_dma_len(sg);
676 if (length <= page_size) {
677 iod->first_dma = dma_addr;
681 nprps = DIV_ROUND_UP(length, page_size);
682 if (nprps <= (256 / 8)) {
683 pool = dev->prp_small_pool;
686 pool = dev->prp_page_pool;
690 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
692 iod->first_dma = dma_addr;
697 iod->first_dma = prp_dma;
700 if (i == page_size >> 3) {
701 __le64 *old_prp_list = prp_list;
702 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
705 list[iod->npages++] = prp_list;
706 prp_list[0] = old_prp_list[i - 1];
707 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
710 prp_list[i++] = cpu_to_le64(dma_addr);
711 dma_len -= page_size;
712 dma_addr += page_size;
720 dma_addr = sg_dma_address(sg);
721 dma_len = sg_dma_len(sg);
727 static int nvme_map_data(struct nvme_dev *dev, struct nvme_iod *iod,
728 struct nvme_command *cmnd)
730 struct request *req = iod_get_private(iod);
731 struct request_queue *q = req->q;
732 enum dma_data_direction dma_dir = rq_data_dir(req) ?
733 DMA_TO_DEVICE : DMA_FROM_DEVICE;
734 int ret = BLK_MQ_RQ_QUEUE_ERROR;
736 sg_init_table(iod->sg, req->nr_phys_segments);
737 iod->nents = blk_rq_map_sg(q, req, iod->sg);
741 ret = BLK_MQ_RQ_QUEUE_BUSY;
742 if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir))
745 if (!nvme_setup_prps(dev, iod, blk_rq_bytes(req)))
748 ret = BLK_MQ_RQ_QUEUE_ERROR;
749 if (blk_integrity_rq(req)) {
750 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
753 sg_init_table(iod->meta_sg, 1);
754 if (blk_rq_map_integrity_sg(q, req->bio, iod->meta_sg) != 1)
757 if (rq_data_dir(req))
758 nvme_dif_remap(req, nvme_dif_prep);
760 if (!dma_map_sg(dev->dev, iod->meta_sg, 1, dma_dir))
764 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
765 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
766 if (blk_integrity_rq(req))
767 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg));
768 return BLK_MQ_RQ_QUEUE_OK;
771 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
776 static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod)
778 struct request *req = iod_get_private(iod);
779 enum dma_data_direction dma_dir = rq_data_dir(req) ?
780 DMA_TO_DEVICE : DMA_FROM_DEVICE;
783 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
784 if (blk_integrity_rq(req)) {
785 if (!rq_data_dir(req))
786 nvme_dif_remap(req, nvme_dif_complete);
787 dma_unmap_sg(dev->dev, iod->meta_sg, 1, dma_dir);
791 nvme_free_iod(dev, iod);
795 * We reuse the small pool to allocate the 16-byte range here as it is not
796 * worth having a special pool for these or additional cases to handle freeing
799 static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
800 struct nvme_iod *iod, struct nvme_command *cmnd)
802 struct request *req = iod_get_private(iod);
803 struct nvme_dsm_range *range;
805 range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC,
808 return BLK_MQ_RQ_QUEUE_BUSY;
809 iod_list(iod)[0] = (__le64 *)range;
812 range->cattr = cpu_to_le32(0);
813 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
814 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
816 memset(cmnd, 0, sizeof(*cmnd));
817 cmnd->dsm.opcode = nvme_cmd_dsm;
818 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
819 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
821 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
822 return BLK_MQ_RQ_QUEUE_OK;
826 * NOTE: ns is NULL when called on the admin queue.
828 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
829 const struct blk_mq_queue_data *bd)
831 struct nvme_ns *ns = hctx->queue->queuedata;
832 struct nvme_queue *nvmeq = hctx->driver_data;
833 struct nvme_dev *dev = nvmeq->dev;
834 struct request *req = bd->rq;
835 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
836 struct nvme_iod *iod;
837 struct nvme_command cmnd;
838 int ret = BLK_MQ_RQ_QUEUE_OK;
841 * If formated with metadata, require the block layer provide a buffer
842 * unless this namespace is formated such that the metadata can be
843 * stripped/generated by the controller with PRACT=1.
845 if (ns && ns->ms && !blk_integrity_rq(req)) {
846 if (!(ns->pi_type && ns->ms == 8) &&
847 req->cmd_type != REQ_TYPE_DRV_PRIV) {
848 blk_mq_complete_request(req, -EFAULT);
849 return BLK_MQ_RQ_QUEUE_OK;
853 iod = nvme_alloc_iod(req, dev, GFP_ATOMIC);
855 return BLK_MQ_RQ_QUEUE_BUSY;
857 if (req->cmd_flags & REQ_DISCARD) {
858 ret = nvme_setup_discard(nvmeq, ns, iod, &cmnd);
860 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
861 memcpy(&cmnd, req->cmd, sizeof(cmnd));
862 else if (req->cmd_flags & REQ_FLUSH)
863 nvme_setup_flush(ns, &cmnd);
865 nvme_setup_rw(ns, req, &cmnd);
867 if (req->nr_phys_segments)
868 ret = nvme_map_data(dev, iod, &cmnd);
874 cmnd.common.command_id = req->tag;
875 nvme_set_info(cmd, iod, req_completion);
877 spin_lock_irq(&nvmeq->q_lock);
878 __nvme_submit_cmd(nvmeq, &cmnd);
879 nvme_process_cq(nvmeq);
880 spin_unlock_irq(&nvmeq->q_lock);
881 return BLK_MQ_RQ_QUEUE_OK;
883 nvme_free_iod(dev, iod);
887 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
891 head = nvmeq->cq_head;
892 phase = nvmeq->cq_phase;
896 nvme_completion_fn fn;
897 struct nvme_completion cqe = nvmeq->cqes[head];
898 if ((le16_to_cpu(cqe.status) & 1) != phase)
900 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
901 if (++head == nvmeq->q_depth) {
905 if (tag && *tag == cqe.command_id)
907 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
908 fn(nvmeq, ctx, &cqe);
911 /* If the controller ignores the cq head doorbell and continuously
912 * writes to the queue, it is theoretically possible to wrap around
913 * the queue twice and mistakenly return IRQ_NONE. Linux only
914 * requires that 0.1% of your interrupts are handled, so this isn't
917 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
920 if (likely(nvmeq->cq_vector >= 0))
921 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
922 nvmeq->cq_head = head;
923 nvmeq->cq_phase = phase;
928 static void nvme_process_cq(struct nvme_queue *nvmeq)
930 __nvme_process_cq(nvmeq, NULL);
933 static irqreturn_t nvme_irq(int irq, void *data)
936 struct nvme_queue *nvmeq = data;
937 spin_lock(&nvmeq->q_lock);
938 nvme_process_cq(nvmeq);
939 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
941 spin_unlock(&nvmeq->q_lock);
945 static irqreturn_t nvme_irq_check(int irq, void *data)
947 struct nvme_queue *nvmeq = data;
948 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
949 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
951 return IRQ_WAKE_THREAD;
954 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
956 struct nvme_queue *nvmeq = hctx->driver_data;
958 if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
960 spin_lock_irq(&nvmeq->q_lock);
961 __nvme_process_cq(nvmeq, &tag);
962 spin_unlock_irq(&nvmeq->q_lock);
971 static int nvme_submit_async_admin_req(struct nvme_dev *dev)
973 struct nvme_queue *nvmeq = dev->queues[0];
974 struct nvme_command c;
975 struct nvme_cmd_info *cmd_info;
978 req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE,
979 BLK_MQ_REQ_NOWAIT | BLK_MQ_REQ_RESERVED);
983 req->cmd_flags |= REQ_NO_TIMEOUT;
984 cmd_info = blk_mq_rq_to_pdu(req);
985 nvme_set_info(cmd_info, NULL, async_req_completion);
987 memset(&c, 0, sizeof(c));
988 c.common.opcode = nvme_admin_async_event;
989 c.common.command_id = req->tag;
991 blk_mq_free_request(req);
992 __nvme_submit_cmd(nvmeq, &c);
996 static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
997 struct nvme_command *cmd,
998 struct async_cmd_info *cmdinfo, unsigned timeout)
1000 struct nvme_queue *nvmeq = dev->queues[0];
1001 struct request *req;
1002 struct nvme_cmd_info *cmd_rq;
1004 req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, 0);
1006 return PTR_ERR(req);
1008 req->timeout = timeout;
1009 cmd_rq = blk_mq_rq_to_pdu(req);
1011 nvme_set_info(cmd_rq, cmdinfo, async_completion);
1012 cmdinfo->status = -EINTR;
1014 cmd->common.command_id = req->tag;
1016 nvme_submit_cmd(nvmeq, cmd);
1020 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1022 struct nvme_command c;
1024 memset(&c, 0, sizeof(c));
1025 c.delete_queue.opcode = opcode;
1026 c.delete_queue.qid = cpu_to_le16(id);
1028 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1031 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1032 struct nvme_queue *nvmeq)
1034 struct nvme_command c;
1035 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1038 * Note: we (ab)use the fact the the prp fields survive if no data
1039 * is attached to the request.
1041 memset(&c, 0, sizeof(c));
1042 c.create_cq.opcode = nvme_admin_create_cq;
1043 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1044 c.create_cq.cqid = cpu_to_le16(qid);
1045 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1046 c.create_cq.cq_flags = cpu_to_le16(flags);
1047 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1049 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1052 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1053 struct nvme_queue *nvmeq)
1055 struct nvme_command c;
1056 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1059 * Note: we (ab)use the fact the the prp fields survive if no data
1060 * is attached to the request.
1062 memset(&c, 0, sizeof(c));
1063 c.create_sq.opcode = nvme_admin_create_sq;
1064 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1065 c.create_sq.sqid = cpu_to_le16(qid);
1066 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1067 c.create_sq.sq_flags = cpu_to_le16(flags);
1068 c.create_sq.cqid = cpu_to_le16(qid);
1070 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1073 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1075 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1078 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1080 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1083 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1085 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1086 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
1087 struct nvme_dev *dev = nvmeq->dev;
1088 struct request *abort_req;
1089 struct nvme_cmd_info *abort_cmd;
1090 struct nvme_command cmd;
1093 * Shutdown immediately if controller times out while starting. The
1094 * reset work will see the pci device disabled when it gets the forced
1095 * cancellation error. All outstanding requests are completed on
1096 * shutdown, so we return BLK_EH_HANDLED.
1098 if (test_bit(NVME_CTRL_RESETTING, &dev->flags)) {
1100 "I/O %d QID %d timeout, disable controller\n",
1101 req->tag, nvmeq->qid);
1102 nvme_dev_shutdown(dev);
1103 req->errors = NVME_SC_CANCELLED;
1104 return BLK_EH_HANDLED;
1108 * Shutdown the controller immediately and schedule a reset if the
1109 * command was already aborted once before and still hasn't been
1110 * returned to the driver, or if this is the admin queue.
1112 if (!nvmeq->qid || cmd_rq->aborted) {
1114 "I/O %d QID %d timeout, reset controller\n",
1115 req->tag, nvmeq->qid);
1116 nvme_dev_shutdown(dev);
1117 queue_work(nvme_workq, &dev->reset_work);
1120 * Mark the request as handled, since the inline shutdown
1121 * forces all outstanding requests to complete.
1123 req->errors = NVME_SC_CANCELLED;
1124 return BLK_EH_HANDLED;
1127 if (atomic_dec_and_test(&dev->ctrl.abort_limit))
1128 return BLK_EH_RESET_TIMER;
1130 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE,
1132 if (IS_ERR(abort_req)) {
1133 atomic_inc(&dev->ctrl.abort_limit);
1134 return BLK_EH_RESET_TIMER;
1137 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1138 nvme_set_info(abort_cmd, abort_req, abort_completion);
1140 memset(&cmd, 0, sizeof(cmd));
1141 cmd.abort.opcode = nvme_admin_abort_cmd;
1142 cmd.abort.cid = req->tag;
1143 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1144 cmd.abort.command_id = abort_req->tag;
1146 cmd_rq->aborted = 1;
1148 dev_warn(nvmeq->q_dmadev, "I/O %d QID %d timeout, aborting\n",
1149 req->tag, nvmeq->qid);
1150 nvme_submit_cmd(dev->queues[0], &cmd);
1153 * The aborted req will be completed on receiving the abort req.
1154 * We enable the timer again. If hit twice, it'll cause a device reset,
1155 * as the device then is in a faulty state.
1157 return BLK_EH_RESET_TIMER;
1160 static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
1162 struct nvme_queue *nvmeq = data;
1164 nvme_completion_fn fn;
1165 struct nvme_cmd_info *cmd;
1166 struct nvme_completion cqe;
1168 if (!blk_mq_request_started(req))
1171 cmd = blk_mq_rq_to_pdu(req);
1173 if (cmd->ctx == CMD_CTX_CANCELLED)
1176 if (blk_queue_dying(req->q))
1177 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1179 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1182 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1183 req->tag, nvmeq->qid);
1184 ctx = cancel_cmd_info(cmd, &fn);
1185 fn(nvmeq, ctx, &cqe);
1188 static void nvme_free_queue(struct nvme_queue *nvmeq)
1190 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1191 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1193 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1194 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1198 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1202 for (i = dev->queue_count - 1; i >= lowest; i--) {
1203 struct nvme_queue *nvmeq = dev->queues[i];
1205 dev->queues[i] = NULL;
1206 nvme_free_queue(nvmeq);
1211 * nvme_suspend_queue - put queue into suspended state
1212 * @nvmeq - queue to suspend
1214 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1218 spin_lock_irq(&nvmeq->q_lock);
1219 if (nvmeq->cq_vector == -1) {
1220 spin_unlock_irq(&nvmeq->q_lock);
1223 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1224 nvmeq->dev->online_queues--;
1225 nvmeq->cq_vector = -1;
1226 spin_unlock_irq(&nvmeq->q_lock);
1228 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1229 blk_mq_freeze_queue_start(nvmeq->dev->ctrl.admin_q);
1231 irq_set_affinity_hint(vector, NULL);
1232 free_irq(vector, nvmeq);
1237 static void nvme_clear_queue(struct nvme_queue *nvmeq)
1239 spin_lock_irq(&nvmeq->q_lock);
1240 if (nvmeq->tags && *nvmeq->tags)
1241 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
1242 spin_unlock_irq(&nvmeq->q_lock);
1245 static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1247 struct nvme_queue *nvmeq = dev->queues[qid];
1251 if (nvme_suspend_queue(nvmeq))
1254 /* Don't tell the adapter to delete the admin queue.
1255 * Don't tell a removed adapter to delete IO queues. */
1256 if (qid && readl(dev->bar + NVME_REG_CSTS) != -1) {
1257 adapter_delete_sq(dev, qid);
1258 adapter_delete_cq(dev, qid);
1261 spin_lock_irq(&nvmeq->q_lock);
1262 nvme_process_cq(nvmeq);
1263 spin_unlock_irq(&nvmeq->q_lock);
1266 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1269 int q_depth = dev->q_depth;
1270 unsigned q_size_aligned = roundup(q_depth * entry_size,
1271 dev->ctrl.page_size);
1273 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1274 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1275 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1276 q_depth = div_u64(mem_per_q, entry_size);
1279 * Ensure the reduced q_depth is above some threshold where it
1280 * would be better to map queues in system memory with the
1290 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1293 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1294 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1295 dev->ctrl.page_size);
1296 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1297 nvmeq->sq_cmds_io = dev->cmb + offset;
1299 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1300 &nvmeq->sq_dma_addr, GFP_KERNEL);
1301 if (!nvmeq->sq_cmds)
1308 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1311 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1315 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1316 &nvmeq->cq_dma_addr, GFP_KERNEL);
1320 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1323 nvmeq->q_dmadev = dev->dev;
1325 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1326 dev->ctrl.instance, qid);
1327 spin_lock_init(&nvmeq->q_lock);
1329 nvmeq->cq_phase = 1;
1330 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1331 nvmeq->q_depth = depth;
1333 nvmeq->cq_vector = -1;
1334 dev->queues[qid] = nvmeq;
1336 /* make sure queue descriptor is set before queue count, for kthread */
1343 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1344 nvmeq->cq_dma_addr);
1350 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1353 if (use_threaded_interrupts)
1354 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1355 nvme_irq_check, nvme_irq, IRQF_SHARED,
1357 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1358 IRQF_SHARED, name, nvmeq);
1361 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1363 struct nvme_dev *dev = nvmeq->dev;
1365 spin_lock_irq(&nvmeq->q_lock);
1368 nvmeq->cq_phase = 1;
1369 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1370 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1371 dev->online_queues++;
1372 spin_unlock_irq(&nvmeq->q_lock);
1375 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1377 struct nvme_dev *dev = nvmeq->dev;
1380 nvmeq->cq_vector = qid - 1;
1381 result = adapter_alloc_cq(dev, qid, nvmeq);
1385 result = adapter_alloc_sq(dev, qid, nvmeq);
1389 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1393 nvme_init_queue(nvmeq, qid);
1397 adapter_delete_sq(dev, qid);
1399 adapter_delete_cq(dev, qid);
1403 static struct blk_mq_ops nvme_mq_admin_ops = {
1404 .queue_rq = nvme_queue_rq,
1405 .map_queue = blk_mq_map_queue,
1406 .init_hctx = nvme_admin_init_hctx,
1407 .exit_hctx = nvme_admin_exit_hctx,
1408 .init_request = nvme_admin_init_request,
1409 .timeout = nvme_timeout,
1412 static struct blk_mq_ops nvme_mq_ops = {
1413 .queue_rq = nvme_queue_rq,
1414 .map_queue = blk_mq_map_queue,
1415 .init_hctx = nvme_init_hctx,
1416 .init_request = nvme_init_request,
1417 .timeout = nvme_timeout,
1421 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1423 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1424 blk_cleanup_queue(dev->ctrl.admin_q);
1425 blk_mq_free_tag_set(&dev->admin_tagset);
1429 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1431 if (!dev->ctrl.admin_q) {
1432 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1433 dev->admin_tagset.nr_hw_queues = 1;
1434 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1435 dev->admin_tagset.reserved_tags = 1;
1436 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1437 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1438 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1439 dev->admin_tagset.driver_data = dev;
1441 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1444 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1445 if (IS_ERR(dev->ctrl.admin_q)) {
1446 blk_mq_free_tag_set(&dev->admin_tagset);
1449 if (!blk_get_queue(dev->ctrl.admin_q)) {
1450 nvme_dev_remove_admin(dev);
1451 dev->ctrl.admin_q = NULL;
1455 blk_mq_unfreeze_queue(dev->ctrl.admin_q);
1460 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1464 u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1465 struct nvme_queue *nvmeq;
1467 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ?
1468 NVME_CAP_NSSRC(cap) : 0;
1470 if (dev->subsystem &&
1471 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1472 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1474 result = nvme_disable_ctrl(&dev->ctrl, cap);
1478 nvmeq = dev->queues[0];
1480 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1485 aqa = nvmeq->q_depth - 1;
1488 writel(aqa, dev->bar + NVME_REG_AQA);
1489 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1490 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1492 result = nvme_enable_ctrl(&dev->ctrl, cap);
1496 nvmeq->cq_vector = 0;
1497 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1499 nvmeq->cq_vector = -1;
1506 nvme_free_queues(dev, 0);
1510 static int nvme_kthread(void *data)
1512 struct nvme_dev *dev, *next;
1514 while (!kthread_should_stop()) {
1515 set_current_state(TASK_INTERRUPTIBLE);
1516 spin_lock(&dev_list_lock);
1517 list_for_each_entry_safe(dev, next, &dev_list, node) {
1519 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1522 * Skip controllers currently under reset.
1524 if (work_pending(&dev->reset_work) || work_busy(&dev->reset_work))
1527 if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) ||
1528 csts & NVME_CSTS_CFS) {
1529 if (queue_work(nvme_workq, &dev->reset_work)) {
1531 "Failed status: %x, reset controller\n",
1532 readl(dev->bar + NVME_REG_CSTS));
1536 for (i = 0; i < dev->queue_count; i++) {
1537 struct nvme_queue *nvmeq = dev->queues[i];
1540 spin_lock_irq(&nvmeq->q_lock);
1541 nvme_process_cq(nvmeq);
1543 while (i == 0 && dev->ctrl.event_limit > 0) {
1544 if (nvme_submit_async_admin_req(dev))
1546 dev->ctrl.event_limit--;
1548 spin_unlock_irq(&nvmeq->q_lock);
1551 spin_unlock(&dev_list_lock);
1552 schedule_timeout(round_jiffies_relative(HZ));
1557 static int nvme_create_io_queues(struct nvme_dev *dev)
1562 for (i = dev->queue_count; i <= dev->max_qid; i++) {
1563 if (!nvme_alloc_queue(dev, i, dev->q_depth)) {
1569 for (i = dev->online_queues; i <= dev->queue_count - 1; i++) {
1570 ret = nvme_create_queue(dev->queues[i], i);
1572 nvme_free_queues(dev, i);
1578 * Ignore failing Create SQ/CQ commands, we can continue with less
1579 * than the desired aount of queues, and even a controller without
1580 * I/O queues an still be used to issue admin commands. This might
1581 * be useful to upgrade a buggy firmware for example.
1583 return ret >= 0 ? 0 : ret;
1586 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1588 u64 szu, size, offset;
1590 resource_size_t bar_size;
1591 struct pci_dev *pdev = to_pci_dev(dev->dev);
1593 dma_addr_t dma_addr;
1598 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1599 if (!(NVME_CMB_SZ(dev->cmbsz)))
1602 cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1604 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1605 size = szu * NVME_CMB_SZ(dev->cmbsz);
1606 offset = szu * NVME_CMB_OFST(cmbloc);
1607 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
1609 if (offset > bar_size)
1613 * Controllers may support a CMB size larger than their BAR,
1614 * for example, due to being behind a bridge. Reduce the CMB to
1615 * the reported size of the BAR
1617 if (size > bar_size - offset)
1618 size = bar_size - offset;
1620 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
1621 cmb = ioremap_wc(dma_addr, size);
1625 dev->cmb_dma_addr = dma_addr;
1626 dev->cmb_size = size;
1630 static inline void nvme_release_cmb(struct nvme_dev *dev)
1638 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1640 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1643 static int nvme_setup_io_queues(struct nvme_dev *dev)
1645 struct nvme_queue *adminq = dev->queues[0];
1646 struct pci_dev *pdev = to_pci_dev(dev->dev);
1647 int result, i, vecs, nr_io_queues, size;
1649 nr_io_queues = num_possible_cpus();
1650 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1655 * Degraded controllers might return an error when setting the queue
1656 * count. We still want to be able to bring them online and offer
1657 * access to the admin queue, as that might be only way to fix them up.
1660 dev_err(dev->dev, "Could not set queue count (%d)\n", result);
1665 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1666 result = nvme_cmb_qdepth(dev, nr_io_queues,
1667 sizeof(struct nvme_command));
1669 dev->q_depth = result;
1671 nvme_release_cmb(dev);
1674 size = db_bar_size(dev, nr_io_queues);
1678 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1681 if (!--nr_io_queues)
1683 size = db_bar_size(dev, nr_io_queues);
1685 dev->dbs = dev->bar + 4096;
1686 adminq->q_db = dev->dbs;
1689 /* Deregister the admin queue's interrupt */
1690 free_irq(dev->entry[0].vector, adminq);
1693 * If we enable msix early due to not intx, disable it again before
1694 * setting up the full range we need.
1697 pci_disable_msix(pdev);
1699 for (i = 0; i < nr_io_queues; i++)
1700 dev->entry[i].entry = i;
1701 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
1703 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
1707 for (i = 0; i < vecs; i++)
1708 dev->entry[i].vector = i + pdev->irq;
1713 * Should investigate if there's a performance win from allocating
1714 * more queues than interrupt vectors; it might allow the submission
1715 * path to scale better, even if the receive path is limited by the
1716 * number of interrupts.
1718 nr_io_queues = vecs;
1719 dev->max_qid = nr_io_queues;
1721 result = queue_request_irq(dev, adminq, adminq->irqname);
1723 adminq->cq_vector = -1;
1727 /* Free previously allocated queues that are no longer usable */
1728 nvme_free_queues(dev, nr_io_queues + 1);
1729 return nvme_create_io_queues(dev);
1732 nvme_free_queues(dev, 1);
1736 static void nvme_set_irq_hints(struct nvme_dev *dev)
1738 struct nvme_queue *nvmeq;
1741 for (i = 0; i < dev->online_queues; i++) {
1742 nvmeq = dev->queues[i];
1744 if (!nvmeq->tags || !(*nvmeq->tags))
1747 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
1748 blk_mq_tags_cpumask(*nvmeq->tags));
1752 static void nvme_dev_scan(struct work_struct *work)
1754 struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
1756 if (!dev->tagset.tags)
1758 nvme_scan_namespaces(&dev->ctrl);
1759 nvme_set_irq_hints(dev);
1763 * Return: error value if an error occurred setting up the queues or calling
1764 * Identify Device. 0 if these succeeded, even if adding some of the
1765 * namespaces failed. At the moment, these failures are silent. TBD which
1766 * failures should be reported.
1768 static int nvme_dev_add(struct nvme_dev *dev)
1770 if (!dev->ctrl.tagset) {
1771 dev->tagset.ops = &nvme_mq_ops;
1772 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1773 dev->tagset.timeout = NVME_IO_TIMEOUT;
1774 dev->tagset.numa_node = dev_to_node(dev->dev);
1775 dev->tagset.queue_depth =
1776 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1777 dev->tagset.cmd_size = nvme_cmd_size(dev);
1778 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1779 dev->tagset.driver_data = dev;
1781 if (blk_mq_alloc_tag_set(&dev->tagset))
1783 dev->ctrl.tagset = &dev->tagset;
1785 queue_work(nvme_workq, &dev->scan_work);
1789 static int nvme_dev_map(struct nvme_dev *dev)
1792 int bars, result = -ENOMEM;
1793 struct pci_dev *pdev = to_pci_dev(dev->dev);
1795 if (pci_enable_device_mem(pdev))
1798 dev->entry[0].vector = pdev->irq;
1799 pci_set_master(pdev);
1800 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1804 if (pci_request_selected_regions(pdev, bars, "nvme"))
1807 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1808 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1811 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1815 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1821 * Some devices don't advertse INTx interrupts, pre-enable a single
1822 * MSIX vec for setup. We'll adjust this later.
1825 result = pci_enable_msix(pdev, dev->entry, 1);
1830 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1832 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1833 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1834 dev->dbs = dev->bar + 4096;
1835 if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2))
1836 dev->cmb = nvme_map_cmb(dev);
1844 pci_release_regions(pdev);
1846 pci_disable_device(pdev);
1850 static void nvme_dev_unmap(struct nvme_dev *dev)
1852 struct pci_dev *pdev = to_pci_dev(dev->dev);
1854 if (pdev->msi_enabled)
1855 pci_disable_msi(pdev);
1856 else if (pdev->msix_enabled)
1857 pci_disable_msix(pdev);
1862 pci_release_regions(pdev);
1865 if (pci_is_enabled(pdev))
1866 pci_disable_device(pdev);
1869 struct nvme_delq_ctx {
1870 struct task_struct *waiter;
1871 struct kthread_worker *worker;
1875 static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
1877 dq->waiter = current;
1881 set_current_state(TASK_KILLABLE);
1882 if (!atomic_read(&dq->refcount))
1884 if (!schedule_timeout(ADMIN_TIMEOUT) ||
1885 fatal_signal_pending(current)) {
1887 * Disable the controller first since we can't trust it
1888 * at this point, but leave the admin queue enabled
1889 * until all queue deletion requests are flushed.
1890 * FIXME: This may take a while if there are more h/w
1891 * queues than admin tags.
1893 set_current_state(TASK_RUNNING);
1894 nvme_disable_ctrl(&dev->ctrl,
1895 lo_hi_readq(dev->bar + NVME_REG_CAP));
1896 nvme_clear_queue(dev->queues[0]);
1897 flush_kthread_worker(dq->worker);
1898 nvme_disable_queue(dev, 0);
1902 set_current_state(TASK_RUNNING);
1905 static void nvme_put_dq(struct nvme_delq_ctx *dq)
1907 atomic_dec(&dq->refcount);
1909 wake_up_process(dq->waiter);
1912 static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
1914 atomic_inc(&dq->refcount);
1918 static void nvme_del_queue_end(struct nvme_queue *nvmeq)
1920 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
1923 spin_lock_irq(&nvmeq->q_lock);
1924 nvme_process_cq(nvmeq);
1925 spin_unlock_irq(&nvmeq->q_lock);
1928 static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
1929 kthread_work_func_t fn)
1931 struct nvme_command c;
1933 memset(&c, 0, sizeof(c));
1934 c.delete_queue.opcode = opcode;
1935 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1937 init_kthread_work(&nvmeq->cmdinfo.work, fn);
1938 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
1942 static void nvme_del_cq_work_handler(struct kthread_work *work)
1944 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
1946 nvme_del_queue_end(nvmeq);
1949 static int nvme_delete_cq(struct nvme_queue *nvmeq)
1951 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
1952 nvme_del_cq_work_handler);
1955 static void nvme_del_sq_work_handler(struct kthread_work *work)
1957 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
1959 int status = nvmeq->cmdinfo.status;
1962 status = nvme_delete_cq(nvmeq);
1964 nvme_del_queue_end(nvmeq);
1967 static int nvme_delete_sq(struct nvme_queue *nvmeq)
1969 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
1970 nvme_del_sq_work_handler);
1973 static void nvme_del_queue_start(struct kthread_work *work)
1975 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
1977 if (nvme_delete_sq(nvmeq))
1978 nvme_del_queue_end(nvmeq);
1981 static void nvme_disable_io_queues(struct nvme_dev *dev)
1984 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
1985 struct nvme_delq_ctx dq;
1986 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
1987 &worker, "nvme%d", dev->ctrl.instance);
1989 if (IS_ERR(kworker_task)) {
1991 "Failed to create queue del task\n");
1992 for (i = dev->queue_count - 1; i > 0; i--)
1993 nvme_disable_queue(dev, i);
1998 atomic_set(&dq.refcount, 0);
1999 dq.worker = &worker;
2000 for (i = dev->queue_count - 1; i > 0; i--) {
2001 struct nvme_queue *nvmeq = dev->queues[i];
2003 if (nvme_suspend_queue(nvmeq))
2005 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2006 nvmeq->cmdinfo.worker = dq.worker;
2007 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2008 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2010 nvme_wait_dq(&dq, dev);
2011 kthread_stop(kworker_task);
2014 static int nvme_dev_list_add(struct nvme_dev *dev)
2016 bool start_thread = false;
2018 spin_lock(&dev_list_lock);
2019 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2020 start_thread = true;
2023 list_add(&dev->node, &dev_list);
2024 spin_unlock(&dev_list_lock);
2027 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2028 wake_up_all(&nvme_kthread_wait);
2030 wait_event_killable(nvme_kthread_wait, nvme_thread);
2032 if (IS_ERR_OR_NULL(nvme_thread))
2033 return nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2039 * Remove the node from the device list and check
2040 * for whether or not we need to stop the nvme_thread.
2042 static void nvme_dev_list_remove(struct nvme_dev *dev)
2044 struct task_struct *tmp = NULL;
2046 spin_lock(&dev_list_lock);
2047 list_del_init(&dev->node);
2048 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2052 spin_unlock(&dev_list_lock);
2058 static void nvme_freeze_queues(struct nvme_dev *dev)
2062 list_for_each_entry(ns, &dev->ctrl.namespaces, list) {
2063 blk_mq_freeze_queue_start(ns->queue);
2065 spin_lock_irq(ns->queue->queue_lock);
2066 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
2067 spin_unlock_irq(ns->queue->queue_lock);
2069 blk_mq_cancel_requeue_work(ns->queue);
2070 blk_mq_stop_hw_queues(ns->queue);
2074 static void nvme_unfreeze_queues(struct nvme_dev *dev)
2078 list_for_each_entry(ns, &dev->ctrl.namespaces, list) {
2079 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2080 blk_mq_unfreeze_queue(ns->queue);
2081 blk_mq_start_stopped_hw_queues(ns->queue, true);
2082 blk_mq_kick_requeue_list(ns->queue);
2086 static void nvme_dev_shutdown(struct nvme_dev *dev)
2091 nvme_dev_list_remove(dev);
2093 mutex_lock(&dev->shutdown_lock);
2095 nvme_freeze_queues(dev);
2096 csts = readl(dev->bar + NVME_REG_CSTS);
2098 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
2099 for (i = dev->queue_count - 1; i >= 0; i--) {
2100 struct nvme_queue *nvmeq = dev->queues[i];
2101 nvme_suspend_queue(nvmeq);
2104 nvme_disable_io_queues(dev);
2105 nvme_shutdown_ctrl(&dev->ctrl);
2106 nvme_disable_queue(dev, 0);
2108 nvme_dev_unmap(dev);
2110 for (i = dev->queue_count - 1; i >= 0; i--)
2111 nvme_clear_queue(dev->queues[i]);
2112 mutex_unlock(&dev->shutdown_lock);
2115 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2117 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2118 PAGE_SIZE, PAGE_SIZE, 0);
2119 if (!dev->prp_page_pool)
2122 /* Optimisation for I/Os between 4k and 128k */
2123 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2125 if (!dev->prp_small_pool) {
2126 dma_pool_destroy(dev->prp_page_pool);
2132 static void nvme_release_prp_pools(struct nvme_dev *dev)
2134 dma_pool_destroy(dev->prp_page_pool);
2135 dma_pool_destroy(dev->prp_small_pool);
2138 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2140 struct nvme_dev *dev = to_nvme_dev(ctrl);
2142 put_device(dev->dev);
2143 if (dev->tagset.tags)
2144 blk_mq_free_tag_set(&dev->tagset);
2145 if (dev->ctrl.admin_q)
2146 blk_put_queue(dev->ctrl.admin_q);
2152 static void nvme_reset_work(struct work_struct *work)
2154 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2157 if (WARN_ON(test_bit(NVME_CTRL_RESETTING, &dev->flags)))
2161 * If we're called to reset a live controller first shut it down before
2165 nvme_dev_shutdown(dev);
2167 set_bit(NVME_CTRL_RESETTING, &dev->flags);
2169 result = nvme_dev_map(dev);
2173 result = nvme_configure_admin_queue(dev);
2177 nvme_init_queue(dev->queues[0], 0);
2178 result = nvme_alloc_admin_tags(dev);
2182 result = nvme_init_identify(&dev->ctrl);
2186 result = nvme_setup_io_queues(dev);
2190 dev->ctrl.event_limit = 1;
2192 result = nvme_dev_list_add(dev);
2197 * Keep the controller around but remove all namespaces if we don't have
2198 * any working I/O queue.
2200 if (dev->online_queues < 2) {
2201 dev_warn(dev->dev, "IO queues not created\n");
2202 nvme_remove_namespaces(&dev->ctrl);
2204 nvme_unfreeze_queues(dev);
2208 clear_bit(NVME_CTRL_RESETTING, &dev->flags);
2212 nvme_dev_list_remove(dev);
2214 nvme_dev_remove_admin(dev);
2215 blk_put_queue(dev->ctrl.admin_q);
2216 dev->ctrl.admin_q = NULL;
2217 dev->queues[0]->tags = NULL;
2219 nvme_disable_queue(dev, 0);
2221 nvme_dev_unmap(dev);
2223 nvme_remove_dead_ctrl(dev);
2226 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2228 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2229 struct pci_dev *pdev = to_pci_dev(dev->dev);
2231 if (pci_get_drvdata(pdev))
2232 pci_stop_and_remove_bus_device_locked(pdev);
2233 nvme_put_ctrl(&dev->ctrl);
2236 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2238 dev_warn(dev->dev, "Removing after probe failure\n");
2239 kref_get(&dev->ctrl.kref);
2240 if (!schedule_work(&dev->remove_work))
2241 nvme_put_ctrl(&dev->ctrl);
2244 static int nvme_reset(struct nvme_dev *dev)
2246 if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
2249 if (!queue_work(nvme_workq, &dev->reset_work))
2252 flush_work(&dev->reset_work);
2256 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2258 *val = readl(to_nvme_dev(ctrl)->bar + off);
2262 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2264 writel(val, to_nvme_dev(ctrl)->bar + off);
2268 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2270 *val = readq(to_nvme_dev(ctrl)->bar + off);
2274 static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl)
2276 struct nvme_dev *dev = to_nvme_dev(ctrl);
2278 return !dev->bar || dev->online_queues < 2;
2281 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
2283 return nvme_reset(to_nvme_dev(ctrl));
2286 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2287 .reg_read32 = nvme_pci_reg_read32,
2288 .reg_write32 = nvme_pci_reg_write32,
2289 .reg_read64 = nvme_pci_reg_read64,
2290 .io_incapable = nvme_pci_io_incapable,
2291 .reset_ctrl = nvme_pci_reset_ctrl,
2292 .free_ctrl = nvme_pci_free_ctrl,
2295 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2297 int node, result = -ENOMEM;
2298 struct nvme_dev *dev;
2300 node = dev_to_node(&pdev->dev);
2301 if (node == NUMA_NO_NODE)
2302 set_dev_node(&pdev->dev, 0);
2304 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2307 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2311 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2316 dev->dev = get_device(&pdev->dev);
2317 pci_set_drvdata(pdev, dev);
2319 INIT_LIST_HEAD(&dev->node);
2320 INIT_WORK(&dev->scan_work, nvme_dev_scan);
2321 INIT_WORK(&dev->reset_work, nvme_reset_work);
2322 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2323 mutex_init(&dev->shutdown_lock);
2325 result = nvme_setup_prp_pools(dev);
2329 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2334 queue_work(nvme_workq, &dev->reset_work);
2338 nvme_release_prp_pools(dev);
2340 put_device(dev->dev);
2348 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2350 struct nvme_dev *dev = pci_get_drvdata(pdev);
2353 nvme_dev_shutdown(dev);
2355 queue_work(nvme_workq, &dev->reset_work);
2358 static void nvme_shutdown(struct pci_dev *pdev)
2360 struct nvme_dev *dev = pci_get_drvdata(pdev);
2361 nvme_dev_shutdown(dev);
2364 static void nvme_remove(struct pci_dev *pdev)
2366 struct nvme_dev *dev = pci_get_drvdata(pdev);
2368 spin_lock(&dev_list_lock);
2369 list_del_init(&dev->node);
2370 spin_unlock(&dev_list_lock);
2372 pci_set_drvdata(pdev, NULL);
2373 flush_work(&dev->reset_work);
2374 flush_work(&dev->scan_work);
2375 nvme_remove_namespaces(&dev->ctrl);
2376 nvme_uninit_ctrl(&dev->ctrl);
2377 nvme_dev_shutdown(dev);
2378 nvme_dev_remove_admin(dev);
2379 nvme_free_queues(dev, 0);
2380 nvme_release_cmb(dev);
2381 nvme_release_prp_pools(dev);
2382 nvme_put_ctrl(&dev->ctrl);
2385 /* These functions are yet to be implemented */
2386 #define nvme_error_detected NULL
2387 #define nvme_dump_registers NULL
2388 #define nvme_link_reset NULL
2389 #define nvme_slot_reset NULL
2390 #define nvme_error_resume NULL
2392 #ifdef CONFIG_PM_SLEEP
2393 static int nvme_suspend(struct device *dev)
2395 struct pci_dev *pdev = to_pci_dev(dev);
2396 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2398 nvme_dev_shutdown(ndev);
2402 static int nvme_resume(struct device *dev)
2404 struct pci_dev *pdev = to_pci_dev(dev);
2405 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2407 queue_work(nvme_workq, &ndev->reset_work);
2412 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2414 static const struct pci_error_handlers nvme_err_handler = {
2415 .error_detected = nvme_error_detected,
2416 .mmio_enabled = nvme_dump_registers,
2417 .link_reset = nvme_link_reset,
2418 .slot_reset = nvme_slot_reset,
2419 .resume = nvme_error_resume,
2420 .reset_notify = nvme_reset_notify,
2423 /* Move to pci_ids.h later */
2424 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
2426 static const struct pci_device_id nvme_id_table[] = {
2427 { PCI_VDEVICE(INTEL, 0x0953),
2428 .driver_data = NVME_QUIRK_STRIPE_SIZE, },
2429 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2430 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2431 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2432 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2435 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2437 static struct pci_driver nvme_driver = {
2439 .id_table = nvme_id_table,
2440 .probe = nvme_probe,
2441 .remove = nvme_remove,
2442 .shutdown = nvme_shutdown,
2444 .pm = &nvme_dev_pm_ops,
2446 .err_handler = &nvme_err_handler,
2449 static int __init nvme_init(void)
2453 init_waitqueue_head(&nvme_kthread_wait);
2455 nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2459 result = nvme_core_init();
2463 result = pci_register_driver(&nvme_driver);
2471 destroy_workqueue(nvme_workq);
2475 static void __exit nvme_exit(void)
2477 pci_unregister_driver(&nvme_driver);
2479 destroy_workqueue(nvme_workq);
2480 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
2484 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2485 MODULE_LICENSE("GPL");
2486 MODULE_VERSION("1.0");
2487 module_init(nvme_init);
2488 module_exit(nvme_exit);